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authorRudolf Marek <r.marek@assembler.cz>2009-09-23 16:59:42 -0400
committerJean Delvare <khali@linux-fr.org>2009-09-23 16:59:42 -0400
commit708a62bcd5f699756bae81491e64648fbf19e2a4 (patch)
tree4d56e0d672bcdfe8b1f46980f9e7374e7e729307 /drivers
parent91f17e02a224dc649eaffc8e0bca6db85efb9cd7 (diff)
hwmon: (coretemp) Fix Atom CPUs support
Fix Atom CPUs support. Intel documents TjMax at 90 degrees C but some Atoms may have 125 degrees C (this is undocumented speculation). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Cc: Huaxu Wan <huaxu.wan@linux.intel.com> Cc: Kent Liu <kent.liu@linux.intel.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/hwmon/Kconfig6
-rw-r--r--drivers/hwmon/coretemp.c29
2 files changed, 22 insertions, 13 deletions
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 9d881f708912..6857560144bd 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -373,12 +373,12 @@ config SENSORS_GL520SM
373 will be called gl520sm. 373 will be called gl520sm.
374 374
375config SENSORS_CORETEMP 375config SENSORS_CORETEMP
376 tristate "Intel Core (2) Duo/Solo temperature sensor" 376 tristate "Intel Core/Core2/Atom temperature sensor"
377 depends on X86 && EXPERIMENTAL 377 depends on X86 && EXPERIMENTAL
378 help 378 help
379 If you say yes here you get support for the temperature 379 If you say yes here you get support for the temperature
380 sensor inside your CPU. Supported all are all known variants 380 sensor inside your CPU. Most of the family 6 CPUs
381 of Intel Core family. 381 are supported. Check documentation/driver for details.
382 382
383config SENSORS_IBMAEM 383config SENSORS_IBMAEM
384 tristate "IBM Active Energy Manager temperature/power sensors and control" 384 tristate "IBM Active Energy Manager temperature/power sensors and control"
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 972cf4ba963c..4c15ed7eb786 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -157,17 +157,24 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
157 /* The 100C is default for both mobile and non mobile CPUs */ 157 /* The 100C is default for both mobile and non mobile CPUs */
158 158
159 int tjmax = 100000; 159 int tjmax = 100000;
160 int ismobile = 1; 160 int usemsr_ee = 1;
161 int err; 161 int err;
162 u32 eax, edx; 162 u32 eax, edx;
163 163
164 /* Early chips have no MSR for TjMax */ 164 /* Early chips have no MSR for TjMax */
165 165
166 if ((c->x86_model == 0xf) && (c->x86_mask < 4)) { 166 if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
167 ismobile = 0; 167 usemsr_ee = 0;
168 } 168 }
169 169
170 if ((c->x86_model > 0xe) && (ismobile)) { 170 /* Atoms seems to have TjMax at 90C */
171
172 if (c->x86_model == 0x1c) {
173 usemsr_ee = 0;
174 tjmax = 90000;
175 }
176
177 if ((c->x86_model > 0xe) && (usemsr_ee)) {
171 178
172 /* Now we can detect the mobile CPU using Intel provided table 179 /* Now we can detect the mobile CPU using Intel provided table
173 http://softwarecommunity.intel.com/Wiki/Mobility/720.htm 180 http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
@@ -179,13 +186,13 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
179 dev_warn(dev, 186 dev_warn(dev,
180 "Unable to access MSR 0x17, assuming desktop" 187 "Unable to access MSR 0x17, assuming desktop"
181 " CPU\n"); 188 " CPU\n");
182 ismobile = 0; 189 usemsr_ee = 0;
183 } else if (!(eax & 0x10000000)) { 190 } else if (!(eax & 0x10000000)) {
184 ismobile = 0; 191 usemsr_ee = 0;
185 } 192 }
186 } 193 }
187 194
188 if (ismobile || c->x86_model == 0x1c) { 195 if (usemsr_ee) {
189 196
190 err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); 197 err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
191 if (err) { 198 if (err) {
@@ -195,7 +202,9 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
195 } else if (eax & 0x40000000) { 202 } else if (eax & 0x40000000) {
196 tjmax = 85000; 203 tjmax = 85000;
197 } 204 }
198 } else { 205 /* if we dont use msr EE it means we are desktop CPU (with exeception
206 of Atom) */
207 } else if (tjmax == 100000) {
199 dev_warn(dev, "Using relative temperature scale!\n"); 208 dev_warn(dev, "Using relative temperature scale!\n");
200 } 209 }
201 210
@@ -248,9 +257,9 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
248 platform_set_drvdata(pdev, data); 257 platform_set_drvdata(pdev, data);
249 258
250 /* read the still undocumented IA32_TEMPERATURE_TARGET it exists 259 /* read the still undocumented IA32_TEMPERATURE_TARGET it exists
251 on older CPUs but not in this register */ 260 on older CPUs but not in this register, Atoms don't have it either */
252 261
253 if (c->x86_model > 0xe) { 262 if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
254 err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx); 263 err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
255 if (err) { 264 if (err) {
256 dev_warn(&pdev->dev, "Unable to read" 265 dev_warn(&pdev->dev, "Unable to read"
@@ -413,7 +422,7 @@ static int __init coretemp_init(void)
413 for_each_online_cpu(i) { 422 for_each_online_cpu(i) {
414 struct cpuinfo_x86 *c = &cpu_data(i); 423 struct cpuinfo_x86 *c = &cpu_data(i);
415 424
416 /* check if family 6, models 0xe, 0xf, 0x16, 0x17, 0x1A */ 425 /* check if family 6, models 0xe, 0xf, 0x16, 0x17, 0x1A, 0x1c */
417 if ((c->cpuid_level < 0) || (c->x86 != 0x6) || 426 if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
418 !((c->x86_model == 0xe) || (c->x86_model == 0xf) || 427 !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
419 (c->x86_model == 0x16) || (c->x86_model == 0x17) || 428 (c->x86_model == 0x16) || (c->x86_model == 0x17) ||