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authorChaoming Li <chaoming_li@realsil.com.cn>2011-05-03 10:48:05 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-05-05 14:59:09 -0400
commit701307a885b13a1790b94e232923de1d199e3cc9 (patch)
tree5e90094c18b74aa4c542fbd6fc697d7b155415eb /drivers
parent9fe255ee3c0dd81c134b354e4b328c51f863ac40 (diff)
rtlwifi: rtl8192se: Merge firmware routines
Merge routines fw.c and fw.h for RTL8192SE. In addition, make changes to rtlwifi/wifi.h to support RTL8192SE. Signed-off-by: Chaoming_Li <chaoming_li@realsil.com.cn> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/fw.c654
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/fw.h375
2 files changed, 1029 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/fw.c b/drivers/net/wireless/rtlwifi/rtl8192se/fw.c
new file mode 100644
index 000000000000..3b5af0113d7f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/fw.c
@@ -0,0 +1,654 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "reg.h"
34#include "def.h"
35#include "fw.h"
36
37static void _rtl92s_fw_set_rqpn(struct ieee80211_hw *hw)
38{
39 struct rtl_priv *rtlpriv = rtl_priv(hw);
40
41 rtl_write_dword(rtlpriv, RQPN, 0xffffffff);
42 rtl_write_dword(rtlpriv, RQPN + 4, 0xffffffff);
43 rtl_write_byte(rtlpriv, RQPN + 8, 0xff);
44 rtl_write_byte(rtlpriv, RQPN + 0xB, 0x80);
45}
46
47static bool _rtl92s_firmware_enable_cpu(struct ieee80211_hw *hw)
48{
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 u32 ichecktime = 200;
51 u16 tmpu2b;
52 u8 tmpu1b, cpustatus = 0;
53
54 _rtl92s_fw_set_rqpn(hw);
55
56 /* Enable CPU. */
57 tmpu1b = rtl_read_byte(rtlpriv, SYS_CLKR);
58 /* AFE source */
59 rtl_write_byte(rtlpriv, SYS_CLKR, (tmpu1b | SYS_CPU_CLKSEL));
60
61 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
62 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | FEN_CPUEN));
63
64 /* Polling IMEM Ready after CPU has refilled. */
65 do {
66 cpustatus = rtl_read_byte(rtlpriv, TCR);
67 if (cpustatus & IMEM_RDY) {
68 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
69 ("IMEM Ready after CPU has refilled.\n"));
70 break;
71 }
72
73 udelay(100);
74 } while (ichecktime--);
75
76 if (!(cpustatus & IMEM_RDY))
77 return false;
78
79 return true;
80}
81
82static enum fw_status _rtl92s_firmware_get_nextstatus(
83 enum fw_status fw_currentstatus)
84{
85 enum fw_status next_fwstatus = 0;
86
87 switch (fw_currentstatus) {
88 case FW_STATUS_INIT:
89 next_fwstatus = FW_STATUS_LOAD_IMEM;
90 break;
91 case FW_STATUS_LOAD_IMEM:
92 next_fwstatus = FW_STATUS_LOAD_EMEM;
93 break;
94 case FW_STATUS_LOAD_EMEM:
95 next_fwstatus = FW_STATUS_LOAD_DMEM;
96 break;
97 case FW_STATUS_LOAD_DMEM:
98 next_fwstatus = FW_STATUS_READY;
99 break;
100 default:
101 break;
102 }
103
104 return next_fwstatus;
105}
106
107static u8 _rtl92s_firmware_header_map_rftype(struct ieee80211_hw *hw)
108{
109 struct rtl_priv *rtlpriv = rtl_priv(hw);
110 struct rtl_phy *rtlphy = &(rtlpriv->phy);
111
112 switch (rtlphy->rf_type) {
113 case RF_1T1R:
114 return 0x11;
115 break;
116 case RF_1T2R:
117 return 0x12;
118 break;
119 case RF_2T2R:
120 return 0x22;
121 break;
122 default:
123 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
124 ("Unknown RF type(%x)\n",
125 rtlphy->rf_type));
126 break;
127 }
128 return 0x22;
129}
130
131static void _rtl92s_firmwareheader_priveupdate(struct ieee80211_hw *hw,
132 struct fw_priv *pfw_priv)
133{
134 /* Update RF types for RATR settings. */
135 pfw_priv->rf_config = _rtl92s_firmware_header_map_rftype(hw);
136}
137
138
139
140static bool _rtl92s_cmd_send_packet(struct ieee80211_hw *hw,
141 struct sk_buff *skb, u8 last)
142{
143 struct rtl_priv *rtlpriv = rtl_priv(hw);
144 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
145 struct rtl8192_tx_ring *ring;
146 struct rtl_tx_desc *pdesc;
147 unsigned long flags;
148 u8 idx = 0;
149
150 ring = &rtlpci->tx_ring[TXCMD_QUEUE];
151
152 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
153
154 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
155 pdesc = &ring->desc[idx];
156 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
157 __skb_queue_tail(&ring->queue, skb);
158
159 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
160
161 return true;
162}
163
164static bool _rtl92s_firmware_downloadcode(struct ieee80211_hw *hw,
165 u8 *code_virtual_address, u32 buffer_len)
166{
167 struct rtl_priv *rtlpriv = rtl_priv(hw);
168 struct sk_buff *skb;
169 struct rtl_tcb_desc *tcb_desc;
170 unsigned char *seg_ptr;
171 u16 frag_threshold = MAX_FIRMWARE_CODE_SIZE;
172 u16 frag_length, frag_offset = 0;
173 u16 extra_descoffset = 0;
174 u8 last_inipkt = 0;
175
176 _rtl92s_fw_set_rqpn(hw);
177
178 if (buffer_len >= MAX_FIRMWARE_CODE_SIZE) {
179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
180 ("Size over FIRMWARE_CODE_SIZE!\n"));
181
182 return false;
183 }
184
185 extra_descoffset = 0;
186
187 do {
188 if ((buffer_len - frag_offset) > frag_threshold) {
189 frag_length = frag_threshold + extra_descoffset;
190 } else {
191 frag_length = (u16)(buffer_len - frag_offset +
192 extra_descoffset);
193 last_inipkt = 1;
194 }
195
196 /* Allocate skb buffer to contain firmware */
197 /* info and tx descriptor info. */
198 skb = dev_alloc_skb(frag_length);
199 skb_reserve(skb, extra_descoffset);
200 seg_ptr = (u8 *)skb_put(skb, (u32)(frag_length -
201 extra_descoffset));
202 memcpy(seg_ptr, code_virtual_address + frag_offset,
203 (u32)(frag_length - extra_descoffset));
204
205 tcb_desc = (struct rtl_tcb_desc *)(skb->cb);
206 tcb_desc->queue_index = TXCMD_QUEUE;
207 tcb_desc->cmd_or_init = DESC_PACKET_TYPE_INIT;
208 tcb_desc->last_inipkt = last_inipkt;
209
210 _rtl92s_cmd_send_packet(hw, skb, last_inipkt);
211
212 frag_offset += (frag_length - extra_descoffset);
213
214 } while (frag_offset < buffer_len);
215
216 rtl_write_byte(rtlpriv, TP_POLL, TPPOLL_CQ);
217
218 return true ;
219}
220
221static bool _rtl92s_firmware_checkready(struct ieee80211_hw *hw,
222 u8 loadfw_status)
223{
224 struct rtl_priv *rtlpriv = rtl_priv(hw);
225 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
226 struct rt_firmware *firmware = (struct rt_firmware *)rtlhal->pfirmware;
227 u32 tmpu4b;
228 u8 cpustatus = 0;
229 short pollingcnt = 1000;
230 bool rtstatus = true;
231
232 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("LoadStaus(%d)\n",
233 loadfw_status));
234
235 firmware->fwstatus = (enum fw_status)loadfw_status;
236
237 switch (loadfw_status) {
238 case FW_STATUS_LOAD_IMEM:
239 /* Polling IMEM code done. */
240 do {
241 cpustatus = rtl_read_byte(rtlpriv, TCR);
242 if (cpustatus & IMEM_CODE_DONE)
243 break;
244 udelay(5);
245 } while (pollingcnt--);
246
247 if (!(cpustatus & IMEM_CHK_RPT) || (pollingcnt <= 0)) {
248 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
249 ("FW_STATUS_LOAD_IMEM"
250 " FAIL CPU, Status=%x\r\n", cpustatus));
251 goto status_check_fail;
252 }
253 break;
254
255 case FW_STATUS_LOAD_EMEM:
256 /* Check Put Code OK and Turn On CPU */
257 /* Polling EMEM code done. */
258 do {
259 cpustatus = rtl_read_byte(rtlpriv, TCR);
260 if (cpustatus & EMEM_CODE_DONE)
261 break;
262 udelay(5);
263 } while (pollingcnt--);
264
265 if (!(cpustatus & EMEM_CHK_RPT) || (pollingcnt <= 0)) {
266 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
267 ("FW_STATUS_LOAD_EMEM"
268 " FAIL CPU, Status=%x\r\n", cpustatus));
269 goto status_check_fail;
270 }
271
272 /* Turn On CPU */
273 rtstatus = _rtl92s_firmware_enable_cpu(hw);
274 if (rtstatus != true) {
275 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
276 ("Enable CPU fail!\n"));
277 goto status_check_fail;
278 }
279 break;
280
281 case FW_STATUS_LOAD_DMEM:
282 /* Polling DMEM code done */
283 do {
284 cpustatus = rtl_read_byte(rtlpriv, TCR);
285 if (cpustatus & DMEM_CODE_DONE)
286 break;
287 udelay(5);
288 } while (pollingcnt--);
289
290 if (!(cpustatus & DMEM_CODE_DONE) || (pollingcnt <= 0)) {
291 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
292 ("Polling DMEM code done"
293 " fail ! cpustatus(%#x)\n", cpustatus));
294 goto status_check_fail;
295 }
296
297 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
298 ("DMEM code download success,"
299 " cpustatus(%#x)\n", cpustatus));
300
301 /* Prevent Delay too much and being scheduled out */
302 /* Polling Load Firmware ready */
303 pollingcnt = 2000;
304 do {
305 cpustatus = rtl_read_byte(rtlpriv, TCR);
306 if (cpustatus & FWRDY)
307 break;
308 udelay(40);
309 } while (pollingcnt--);
310
311 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
312 ("Polling Load Firmware ready,"
313 " cpustatus(%x)\n", cpustatus));
314
315 if (((cpustatus & LOAD_FW_READY) != LOAD_FW_READY) ||
316 (pollingcnt <= 0)) {
317 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
318 ("Polling Load Firmware"
319 " ready fail ! cpustatus(%x)\n", cpustatus));
320 goto status_check_fail;
321 }
322
323 /* If right here, we can set TCR/RCR to desired value */
324 /* and config MAC lookback mode to normal mode */
325 tmpu4b = rtl_read_dword(rtlpriv, TCR);
326 rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV)));
327
328 tmpu4b = rtl_read_dword(rtlpriv, RCR);
329 rtl_write_dword(rtlpriv, RCR, (tmpu4b | RCR_APPFCS |
330 RCR_APP_ICV | RCR_APP_MIC));
331
332 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
333 ("Current RCR settings(%#x)\n", tmpu4b));
334
335 /* Set to normal mode. */
336 rtl_write_byte(rtlpriv, LBKMD_SEL, LBK_NORMAL);
337 break;
338
339 default:
340 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
341 ("Unknown status check!\n"));
342 rtstatus = false;
343 break;
344 }
345
346status_check_fail:
347 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("loadfw_status(%d), "
348 "rtstatus(%x)\n", loadfw_status, rtstatus));
349 return rtstatus;
350}
351
352int rtl92s_download_fw(struct ieee80211_hw *hw)
353{
354 struct rtl_priv *rtlpriv = rtl_priv(hw);
355 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
356 struct rt_firmware *firmware = NULL;
357 struct fw_hdr *pfwheader;
358 struct fw_priv *pfw_priv = NULL;
359 u8 *puc_mappedfile = NULL;
360 u32 ul_filelength = 0;
361 u32 file_length = 0;
362 u8 fwhdr_size = RT_8192S_FIRMWARE_HDR_SIZE;
363 u8 fwstatus = FW_STATUS_INIT;
364 bool rtstatus = true;
365
366 if (!rtlhal->pfirmware)
367 return 1;
368
369 firmware = (struct rt_firmware *)rtlhal->pfirmware;
370 firmware->fwstatus = FW_STATUS_INIT;
371
372 puc_mappedfile = firmware->sz_fw_tmpbuffer;
373 file_length = firmware->sz_fw_tmpbufferlen;
374
375 /* 1. Retrieve FW header. */
376 firmware->pfwheader = (struct fw_hdr *) puc_mappedfile;
377 pfwheader = firmware->pfwheader;
378 firmware->firmwareversion = byte(pfwheader->version, 0);
379 firmware->pfwheader->fwpriv.hci_sel = 1;/* pcie */
380
381 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("signature:%x, version:"
382 "%x, size:%x,"
383 "imemsize:%x, sram size:%x\n", pfwheader->signature,
384 pfwheader->version, pfwheader->dmem_size,
385 pfwheader->img_imem_size, pfwheader->img_sram_size));
386
387 /* 2. Retrieve IMEM image. */
388 if ((pfwheader->img_imem_size == 0) || (pfwheader->img_imem_size >
389 sizeof(firmware->fw_imem))) {
390 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
391 ("memory for data image is less than IMEM required\n"));
392 goto fail;
393 } else {
394 puc_mappedfile += fwhdr_size;
395
396 memcpy(firmware->fw_imem, puc_mappedfile,
397 pfwheader->img_imem_size);
398 firmware->fw_imem_len = pfwheader->img_imem_size;
399 }
400
401 /* 3. Retriecve EMEM image. */
402 if (pfwheader->img_sram_size > sizeof(firmware->fw_emem)) {
403 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
404 ("memory for data image is less than EMEM required\n"));
405 goto fail;
406 } else {
407 puc_mappedfile += firmware->fw_imem_len;
408
409 memcpy(firmware->fw_emem, puc_mappedfile,
410 pfwheader->img_sram_size);
411 firmware->fw_emem_len = pfwheader->img_sram_size;
412 }
413
414 /* 4. download fw now */
415 fwstatus = _rtl92s_firmware_get_nextstatus(firmware->fwstatus);
416 while (fwstatus != FW_STATUS_READY) {
417 /* Image buffer redirection. */
418 switch (fwstatus) {
419 case FW_STATUS_LOAD_IMEM:
420 puc_mappedfile = firmware->fw_imem;
421 ul_filelength = firmware->fw_imem_len;
422 break;
423 case FW_STATUS_LOAD_EMEM:
424 puc_mappedfile = firmware->fw_emem;
425 ul_filelength = firmware->fw_emem_len;
426 break;
427 case FW_STATUS_LOAD_DMEM:
428 /* Partial update the content of header private. */
429 pfwheader = firmware->pfwheader;
430 pfw_priv = &pfwheader->fwpriv;
431 _rtl92s_firmwareheader_priveupdate(hw, pfw_priv);
432 puc_mappedfile = (u8 *)(firmware->pfwheader) +
433 RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
434 ul_filelength = fwhdr_size -
435 RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
436 break;
437 default:
438 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
439 ("Unexpected Download step!!\n"));
440 goto fail;
441 break;
442 }
443
444 /* <2> Download image file */
445 rtstatus = _rtl92s_firmware_downloadcode(hw, puc_mappedfile,
446 ul_filelength);
447
448 if (rtstatus != true) {
449 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("fail!\n"));
450 goto fail;
451 }
452
453 /* <3> Check whether load FW process is ready */
454 rtstatus = _rtl92s_firmware_checkready(hw, fwstatus);
455 if (rtstatus != true) {
456 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("fail!\n"));
457 goto fail;
458 }
459
460 fwstatus = _rtl92s_firmware_get_nextstatus(firmware->fwstatus);
461 }
462
463 return rtstatus;
464fail:
465 return 0;
466}
467
468static u32 _rtl92s_fill_h2c_cmd(struct sk_buff *skb, u32 h2cbufferlen,
469 u32 cmd_num, u32 *pelement_id, u32 *pcmd_len,
470 u8 **pcmb_buffer, u8 *cmd_start_seq)
471{
472 u32 totallen = 0, len = 0, tx_desclen = 0;
473 u32 pre_continueoffset = 0;
474 u8 *ph2c_buffer;
475 u8 i = 0;
476
477 do {
478 /* 8 - Byte aligment */
479 len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pcmd_len[i], 8);
480
481 /* Buffer length is not enough */
482 if (h2cbufferlen < totallen + len + tx_desclen)
483 break;
484
485 /* Clear content */
486 ph2c_buffer = (u8 *)skb_put(skb, (u32)len);
487 memset((ph2c_buffer + totallen + tx_desclen), 0, len);
488
489 /* CMD len */
490 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
491 0, 16, pcmd_len[i]);
492
493 /* CMD ID */
494 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
495 16, 8, pelement_id[i]);
496
497 /* CMD Sequence */
498 *cmd_start_seq = *cmd_start_seq % 0x80;
499 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
500 24, 7, *cmd_start_seq);
501 ++*cmd_start_seq;
502
503 /* Copy memory */
504 memcpy((ph2c_buffer + totallen + tx_desclen +
505 H2C_TX_CMD_HDR_LEN), pcmb_buffer[i], pcmd_len[i]);
506
507 /* CMD continue */
508 /* set the continue in prevoius cmd. */
509 if (i < cmd_num - 1)
510 SET_BITS_TO_LE_4BYTE((ph2c_buffer + pre_continueoffset),
511 31, 1, 1);
512
513 pre_continueoffset = totallen;
514
515 totallen += len;
516 } while (++i < cmd_num);
517
518 return totallen;
519}
520
521static u32 _rtl92s_get_h2c_cmdlen(u32 h2cbufferlen, u32 cmd_num, u32 *pcmd_len)
522{
523 u32 totallen = 0, len = 0, tx_desclen = 0;
524 u8 i = 0;
525
526 do {
527 /* 8 - Byte aligment */
528 len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pcmd_len[i], 8);
529
530 /* Buffer length is not enough */
531 if (h2cbufferlen < totallen + len + tx_desclen)
532 break;
533
534 totallen += len;
535 } while (++i < cmd_num);
536
537 return totallen + tx_desclen;
538}
539
540static bool _rtl92s_firmware_set_h2c_cmd(struct ieee80211_hw *hw, u8 h2c_cmd,
541 u8 *pcmd_buffer)
542{
543 struct rtl_priv *rtlpriv = rtl_priv(hw);
544 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
545 struct rtl_tcb_desc *cb_desc;
546 struct sk_buff *skb;
547 u32 element_id = 0;
548 u32 cmd_len = 0;
549 u32 len;
550
551 switch (h2c_cmd) {
552 case FW_H2C_SETPWRMODE:
553 element_id = H2C_SETPWRMODE_CMD ;
554 cmd_len = sizeof(struct h2c_set_pwrmode_parm);
555 break;
556 case FW_H2C_JOINBSSRPT:
557 element_id = H2C_JOINBSSRPT_CMD;
558 cmd_len = sizeof(struct h2c_joinbss_rpt_parm);
559 break;
560 case FW_H2C_WOWLAN_UPDATE_GTK:
561 element_id = H2C_WOWLAN_UPDATE_GTK_CMD;
562 cmd_len = sizeof(struct h2c_wpa_two_way_parm);
563 break;
564 case FW_H2C_WOWLAN_UPDATE_IV:
565 element_id = H2C_WOWLAN_UPDATE_IV_CMD;
566 cmd_len = sizeof(unsigned long long);
567 break;
568 case FW_H2C_WOWLAN_OFFLOAD:
569 element_id = H2C_WOWLAN_FW_OFFLOAD;
570 cmd_len = sizeof(u8);
571 break;
572 default:
573 break;
574 }
575
576 len = _rtl92s_get_h2c_cmdlen(MAX_TRANSMIT_BUFFER_SIZE, 1, &cmd_len);
577 skb = dev_alloc_skb(len);
578 cb_desc = (struct rtl_tcb_desc *)(skb->cb);
579 cb_desc->queue_index = TXCMD_QUEUE;
580 cb_desc->cmd_or_init = DESC_PACKET_TYPE_NORMAL;
581 cb_desc->last_inipkt = false;
582
583 _rtl92s_fill_h2c_cmd(skb, MAX_TRANSMIT_BUFFER_SIZE, 1, &element_id,
584 &cmd_len, &pcmd_buffer, &rtlhal->h2c_txcmd_seq);
585 _rtl92s_cmd_send_packet(hw, skb, false);
586 rtlpriv->cfg->ops->tx_polling(hw, TXCMD_QUEUE);
587
588 return true;
589}
590
591void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 Mode)
592{
593 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
594 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
595 struct h2c_set_pwrmode_parm pwrmode;
596 u16 max_wakeup_period = 0;
597
598 pwrmode.mode = Mode;
599 pwrmode.flag_low_traffic_en = 0;
600 pwrmode.flag_lpnav_en = 0;
601 pwrmode.flag_rf_low_snr_en = 0;
602 pwrmode.flag_dps_en = 0;
603 pwrmode.bcn_rx_en = 0;
604 pwrmode.bcn_to = 0;
605 SET_BITS_TO_LE_2BYTE((u8 *)(&pwrmode) + 8, 0, 16,
606 mac->vif->bss_conf.beacon_int);
607 pwrmode.app_itv = 0;
608 pwrmode.awake_bcn_itvl = ppsc->reg_max_lps_awakeintvl;
609 pwrmode.smart_ps = 1;
610 pwrmode.bcn_pass_period = 10;
611
612 /* Set beacon pass count */
613 if (pwrmode.mode == FW_PS_MIN_MODE)
614 max_wakeup_period = mac->vif->bss_conf.beacon_int;
615 else if (pwrmode.mode == FW_PS_MAX_MODE)
616 max_wakeup_period = mac->vif->bss_conf.beacon_int *
617 mac->vif->bss_conf.dtim_period;
618
619 if (max_wakeup_period >= 500)
620 pwrmode.bcn_pass_cnt = 1;
621 else if ((max_wakeup_period >= 300) && (max_wakeup_period < 500))
622 pwrmode.bcn_pass_cnt = 2;
623 else if ((max_wakeup_period >= 200) && (max_wakeup_period < 300))
624 pwrmode.bcn_pass_cnt = 3;
625 else if ((max_wakeup_period >= 20) && (max_wakeup_period < 200))
626 pwrmode.bcn_pass_cnt = 5;
627 else
628 pwrmode.bcn_pass_cnt = 1;
629
630 _rtl92s_firmware_set_h2c_cmd(hw, FW_H2C_SETPWRMODE, (u8 *)&pwrmode);
631
632}
633
634void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
635 u8 mstatus, u8 ps_qosinfo)
636{
637 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
638 struct h2c_joinbss_rpt_parm joinbss_rpt;
639
640 joinbss_rpt.opmode = mstatus;
641 joinbss_rpt.ps_qos_info = ps_qosinfo;
642 joinbss_rpt.bssid[0] = mac->bssid[0];
643 joinbss_rpt.bssid[1] = mac->bssid[1];
644 joinbss_rpt.bssid[2] = mac->bssid[2];
645 joinbss_rpt.bssid[3] = mac->bssid[3];
646 joinbss_rpt.bssid[4] = mac->bssid[4];
647 joinbss_rpt.bssid[5] = mac->bssid[5];
648 SET_BITS_TO_LE_2BYTE((u8 *)(&joinbss_rpt) + 8, 0, 16,
649 mac->vif->bss_conf.beacon_int);
650 SET_BITS_TO_LE_2BYTE((u8 *)(&joinbss_rpt) + 10, 0, 16, mac->assoc_id);
651
652 _rtl92s_firmware_set_h2c_cmd(hw, FW_H2C_JOINBSSRPT, (u8 *)&joinbss_rpt);
653}
654
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/fw.h b/drivers/net/wireless/rtlwifi/rtl8192se/fw.h
new file mode 100644
index 000000000000..74cc503efe8a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/fw.h
@@ -0,0 +1,375 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#ifndef __REALTEK_FIRMWARE92S_H__
30#define __REALTEK_FIRMWARE92S_H__
31
32#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
33#define RTL8190_CPU_START_OFFSET 0x80
34/* Firmware Local buffer size. 64k */
35#define MAX_FIRMWARE_CODE_SIZE 0xFF00
36
37#define RT_8192S_FIRMWARE_HDR_SIZE 80
38#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
39
40/* support till 64 bit bus width OS */
41#define MAX_DEV_ADDR_SIZE 8
42#define MAX_FIRMWARE_INFORMATION_SIZE 32
43#define MAX_802_11_HEADER_LENGTH (40 + \
44 MAX_FIRMWARE_INFORMATION_SIZE)
45#define ENCRYPTION_MAX_OVERHEAD 128
46#define MAX_FRAGMENT_COUNT 8
47#define MAX_TRANSMIT_BUFFER_SIZE (1600 + \
48 (MAX_802_11_HEADER_LENGTH + \
49 ENCRYPTION_MAX_OVERHEAD) *\
50 MAX_FRAGMENT_COUNT)
51
52#define H2C_TX_CMD_HDR_LEN 8
53
54/* The following DM control code are for Reg0x364, */
55#define FW_DIG_ENABLE_CTL BIT(0)
56#define FW_HIGH_PWR_ENABLE_CTL BIT(1)
57#define FW_SS_CTL BIT(2)
58#define FW_RA_INIT_CTL BIT(3)
59#define FW_RA_BG_CTL BIT(4)
60#define FW_RA_N_CTL BIT(5)
61#define FW_PWR_TRK_CTL BIT(6)
62#define FW_IQK_CTL BIT(7)
63#define FW_FA_CTL BIT(8)
64#define FW_DRIVER_CTRL_DM_CTL BIT(9)
65#define FW_PAPE_CTL_BY_SW_HW BIT(10)
66#define FW_DISABLE_ALL_DM 0
67#define FW_PWR_TRK_PARAM_CLR 0x0000ffff
68#define FW_RA_PARAM_CLR 0xffff0000
69
70enum desc_packet_type {
71 DESC_PACKET_TYPE_INIT = 0,
72 DESC_PACKET_TYPE_NORMAL = 1,
73};
74
75/* 8-bytes alignment required */
76struct fw_priv {
77 /* --- long word 0 ---- */
78 /* 0x12: CE product, 0x92: IT product */
79 u8 signature_0;
80 /* 0x87: CE product, 0x81: IT product */
81 u8 signature_1;
82 /* 0x81: PCI-AP, 01:PCIe, 02: 92S-U,
83 * 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */
84 u8 hci_sel;
85 /* the same value as reigster value */
86 u8 chip_version;
87 /* customer ID low byte */
88 u8 customer_id_0;
89 /* customer ID high byte */
90 u8 customer_id_1;
91 /* 0x11: 1T1R, 0x12: 1T2R,
92 * 0x92: 1T2R turbo, 0x22: 2T2R */
93 u8 rf_config;
94 /* 4: 4EP, 6: 6EP, 11: 11EP */
95 u8 usb_ep_num;
96
97 /* --- long word 1 ---- */
98 /* regulatory class bit map 0 */
99 u8 regulatory_class_0;
100 /* regulatory class bit map 1 */
101 u8 regulatory_class_1;
102 /* regulatory class bit map 2 */
103 u8 regulatory_class_2;
104 /* regulatory class bit map 3 */
105 u8 regulatory_class_3;
106 /* 0:SWSI, 1:HWSI, 2:HWPI */
107 u8 rfintfs;
108 u8 def_nettype;
109 u8 rsvd010;
110 u8 rsvd011;
111
112 /* --- long word 2 ---- */
113 /* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */
114 u8 lbk_mode;
115 /* 1: for MP use, 0: for normal
116 * driver (to be discussed) */
117 u8 mp_mode;
118 u8 rsvd020;
119 u8 rsvd021;
120 u8 rsvd022;
121 u8 rsvd023;
122 u8 rsvd024;
123 u8 rsvd025;
124
125 /* --- long word 3 ---- */
126 /* QoS enable */
127 u8 qos_en;
128 /* 40MHz BW enable */
129 /* 4181 convert AMSDU to AMPDU, 0: disable */
130 u8 bw_40mhz_en;
131 u8 amsdu2ampdu_en;
132 /* 11n AMPDU enable */
133 u8 ampdu_en;
134 /* FW offloads, 0: driver handles */
135 u8 rate_control_offload;
136 /* FW offloads, 0: driver handles */
137 u8 aggregation_offload;
138 u8 rsvd030;
139 u8 rsvd031;
140
141 /* --- long word 4 ---- */
142 /* 1. FW offloads, 0: driver handles */
143 u8 beacon_offload;
144 /* 2. FW offloads, 0: driver handles */
145 u8 mlme_offload;
146 /* 3. FW offloads, 0: driver handles */
147 u8 hwpc_offload;
148 /* 4. FW offloads, 0: driver handles */
149 u8 tcp_checksum_offload;
150 /* 5. FW offloads, 0: driver handles */
151 u8 tcp_offload;
152 /* 6. FW offloads, 0: driver handles */
153 u8 ps_control_offload;
154 /* 7. FW offloads, 0: driver handles */
155 u8 wwlan_offload;
156 u8 rsvd040;
157
158 /* --- long word 5 ---- */
159 /* tcp tx packet length low byte */
160 u8 tcp_tx_frame_len_L;
161 /* tcp tx packet length high byte */
162 u8 tcp_tx_frame_len_H;
163 /* tcp rx packet length low byte */
164 u8 tcp_rx_frame_len_L;
165 /* tcp rx packet length high byte */
166 u8 tcp_rx_frame_len_H;
167 u8 rsvd050;
168 u8 rsvd051;
169 u8 rsvd052;
170 u8 rsvd053;
171};
172
173/* 8-byte alinment required */
174struct fw_hdr {
175
176 /* --- LONG WORD 0 ---- */
177 u16 signature;
178 /* 0x8000 ~ 0x8FFF for FPGA version,
179 * 0x0000 ~ 0x7FFF for ASIC version, */
180 u16 version;
181 /* define the size of boot loader */
182 u32 dmem_size;
183
184
185 /* --- LONG WORD 1 ---- */
186 /* define the size of FW in IMEM */
187 u32 img_imem_size;
188 /* define the size of FW in SRAM */
189 u32 img_sram_size;
190
191 /* --- LONG WORD 2 ---- */
192 /* define the size of DMEM variable */
193 u32 fw_priv_size;
194 u32 rsvd0;
195
196 /* --- LONG WORD 3 ---- */
197 u32 rsvd1;
198 u32 rsvd2;
199
200 struct fw_priv fwpriv;
201
202} ;
203
204enum fw_status {
205 FW_STATUS_INIT = 0,
206 FW_STATUS_LOAD_IMEM = 1,
207 FW_STATUS_LOAD_EMEM = 2,
208 FW_STATUS_LOAD_DMEM = 3,
209 FW_STATUS_READY = 4,
210};
211
212struct rt_firmware {
213 struct fw_hdr *pfwheader;
214 enum fw_status fwstatus;
215 u16 firmwareversion;
216 u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
217 u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
218 u32 fw_imem_len;
219 u32 fw_emem_len;
220 u8 sz_fw_tmpbuffer[164000];
221 u32 sz_fw_tmpbufferlen;
222 u16 cmdpacket_fragthresold;
223};
224
225struct h2c_set_pwrmode_parm {
226 u8 mode;
227 u8 flag_low_traffic_en;
228 u8 flag_lpnav_en;
229 u8 flag_rf_low_snr_en;
230 /* 1: dps, 0: 32k */
231 u8 flag_dps_en;
232 u8 bcn_rx_en;
233 u8 bcn_pass_cnt;
234 /* beacon TO (ms). ¡§=0¡¨ no limit. */
235 u8 bcn_to;
236 u16 bcn_itv;
237 /* only for VOIP mode. */
238 u8 app_itv;
239 u8 awake_bcn_itvl;
240 u8 smart_ps;
241 /* unit: 100 ms */
242 u8 bcn_pass_period;
243};
244
245struct h2c_joinbss_rpt_parm {
246 u8 opmode;
247 u8 ps_qos_info;
248 u8 bssid[6];
249 u16 bcnitv;
250 u16 aid;
251} ;
252
253struct h2c_wpa_ptk {
254 /* EAPOL-Key Key Confirmation Key (KCK) */
255 u8 kck[16];
256 /* EAPOL-Key Key Encryption Key (KEK) */
257 u8 kek[16];
258 /* Temporal Key 1 (TK1) */
259 u8 tk1[16];
260 union {
261 /* Temporal Key 2 (TK2) */
262 u8 tk2[16];
263 struct {
264 u8 tx_mic_key[8];
265 u8 rx_mic_key[8];
266 } athu;
267 } u;
268};
269
270struct h2c_wpa_two_way_parm {
271 /* algorithm TKIP or AES */
272 u8 pairwise_en_alg;
273 u8 group_en_alg;
274 struct h2c_wpa_ptk wpa_ptk_value;
275} ;
276
277enum h2c_cmd {
278 FW_H2C_SETPWRMODE = 0,
279 FW_H2C_JOINBSSRPT = 1,
280 FW_H2C_WOWLAN_UPDATE_GTK = 2,
281 FW_H2C_WOWLAN_UPDATE_IV = 3,
282 FW_H2C_WOWLAN_OFFLOAD = 4,
283};
284
285enum fw_h2c_cmd {
286 H2C_READ_MACREG_CMD, /*0*/
287 H2C_WRITE_MACREG_CMD,
288 H2C_READBB_CMD,
289 H2C_WRITEBB_CMD,
290 H2C_READRF_CMD,
291 H2C_WRITERF_CMD, /*5*/
292 H2C_READ_EEPROM_CMD,
293 H2C_WRITE_EEPROM_CMD,
294 H2C_READ_EFUSE_CMD,
295 H2C_WRITE_EFUSE_CMD,
296 H2C_READ_CAM_CMD, /*10*/
297 H2C_WRITE_CAM_CMD,
298 H2C_SETBCNITV_CMD,
299 H2C_SETMBIDCFG_CMD,
300 H2C_JOINBSS_CMD,
301 H2C_DISCONNECT_CMD, /*15*/
302 H2C_CREATEBSS_CMD,
303 H2C_SETOPMode_CMD,
304 H2C_SITESURVEY_CMD,
305 H2C_SETAUTH_CMD,
306 H2C_SETKEY_CMD, /*20*/
307 H2C_SETSTAKEY_CMD,
308 H2C_SETASSOCSTA_CMD,
309 H2C_DELASSOCSTA_CMD,
310 H2C_SETSTAPWRSTATE_CMD,
311 H2C_SETBASICRATE_CMD, /*25*/
312 H2C_GETBASICRATE_CMD,
313 H2C_SETDATARATE_CMD,
314 H2C_GETDATARATE_CMD,
315 H2C_SETPHYINFO_CMD,
316 H2C_GETPHYINFO_CMD, /*30*/
317 H2C_SETPHY_CMD,
318 H2C_GETPHY_CMD,
319 H2C_READRSSI_CMD,
320 H2C_READGAIN_CMD,
321 H2C_SETATIM_CMD, /*35*/
322 H2C_SETPWRMODE_CMD,
323 H2C_JOINBSSRPT_CMD,
324 H2C_SETRATABLE_CMD,
325 H2C_GETRATABLE_CMD,
326 H2C_GETCCXREPORT_CMD, /*40*/
327 H2C_GETDTMREPORT_CMD,
328 H2C_GETTXRATESTATICS_CMD,
329 H2C_SETUSBSUSPEND_CMD,
330 H2C_SETH2CLBK_CMD,
331 H2C_TMP1, /*45*/
332 H2C_WOWLAN_UPDATE_GTK_CMD,
333 H2C_WOWLAN_FW_OFFLOAD,
334 H2C_TMP2,
335 H2C_TMP3,
336 H2C_WOWLAN_UPDATE_IV_CMD, /*50*/
337 H2C_TMP4,
338 MAX_H2CCMD /*52*/
339};
340
341/* The following macros are used for FW
342 * CMD map and parameter updated. */
343#define FW_CMD_IO_CLR(rtlpriv, _Bit) \
344 do { \
345 udelay(1000); \
346 rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit); \
347 } while (0);
348
349#define FW_CMD_IO_UPDATE(rtlpriv, _val) \
350 rtlpriv->rtlhal.fwcmd_iomap = _val;
351
352#define FW_CMD_IO_SET(rtlpriv, _val) \
353 do { \
354 rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \
355 FW_CMD_IO_UPDATE(rtlpriv, _val); \
356 } while (0);
357
358#define FW_CMD_PARA_SET(rtlpriv, _val) \
359 do { \
360 rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
361 rtlpriv->rtlhal.fwcmd_ioparam = _val; \
362 } while (0);
363
364#define FW_CMD_IO_QUERY(rtlpriv) \
365 (u16)(rtlpriv->rtlhal.fwcmd_iomap)
366#define FW_CMD_IO_PARA_QUERY(rtlpriv) \
367 ((u32)(rtlpriv->rtlhal.fwcmd_ioparam))
368
369int rtl92s_download_fw(struct ieee80211_hw *hw);
370void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
371void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
372 u8 mstatus, u8 ps_qosinfo);
373
374#endif
375
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 09:23:37 -0500