Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi

Allwinner sunXi SoCs clock changes

This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi:
add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and
mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH
1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu
Tsai, which adds support for output clocks present on A20.

3 files changed, 437 insertions, 77 deletions

diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index f05207a27e5f..9e232644f07e 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -30,14 +30,6 @@
  * parent - fixed parent.  No clk_set_parent support
  */
 
-struct clk_factors {
-        struct clk_hw hw;
-        void __iomem *reg;
-        struct clk_factors_config *config;
-        void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
-        spinlock_t *lock;
-};
-
 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
 
 #define SETMASK(len, pos)               (((1U << (len)) - 1) << (pos))
@@ -120,61 +112,8 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
         return 0;
 }
 
-static const struct clk_ops clk_factors_ops = {
+const struct clk_ops clk_factors_ops = {
         .recalc_rate = clk_factors_recalc_rate,
         .round_rate = clk_factors_round_rate,
         .set_rate = clk_factors_set_rate,
 };
-
-/**
- * clk_register_factors - register a factors clock with
- * the clock framework
- * @dev: device registering this clock
- * @name: name of this clock
- * @parent_name: name of clock's parent
- * @flags: framework-specific flags
- * @reg: register address to adjust factors
- * @config: shift and width of factors n, k, m and p
- * @get_factors: function to calculate the factors for a given frequency
- * @lock: shared register lock for this clock
- */
-struct clk *clk_register_factors(struct device *dev, const char *name,
-                                 const char *parent_name,
-                                 unsigned long flags, void __iomem *reg,
-                                 struct clk_factors_config *config,
-                                 void (*get_factors)(u32 *rate, u32 parent,
-                                                     u8 *n, u8 *k, u8 *m, u8 *p),
-                                 spinlock_t *lock)
-{
-        struct clk_factors *factors;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        /* allocate the factors */
-        factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
-        if (!factors) {
-                pr_err("%s: could not allocate factors clk\n", __func__);
-                return ERR_PTR(-ENOMEM);
-        }
-
-        init.name = name;
-        init.ops = &clk_factors_ops;
-        init.flags = flags;
-        init.parent_names = (parent_name ? &parent_name : NULL);
-        init.num_parents = (parent_name ? 1 : 0);
-
-        /* struct clk_factors assignments */
-        factors->reg = reg;
-        factors->config = config;
-        factors->lock = lock;
-        factors->hw.init = &init;
-        factors->get_factors = get_factors;
-
-        /* register the clock */
-        clk = clk_register(dev, &factors->hw);
-
-        if (IS_ERR(clk))
-                kfree(factors);
-
-        return clk;
-}
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index f49851cc4380..02e1a43ebac7 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -17,11 +17,13 @@ struct clk_factors_config {
         u8 pwidth;
 };
 
-struct clk *clk_register_factors(struct device *dev, const char *name,
-                                 const char *parent_name,
-                                 unsigned long flags, void __iomem *reg,
-                                 struct clk_factors_config *config,
-                                 void (*get_factors) (u32 *rate, u32 parent_rate,
-                                                      u8 *n, u8 *k, u8 *m, u8 *p),
-                                 spinlock_t *lock);
+struct clk_factors {
+        struct clk_hw hw;
+        void __iomem *reg;
+        struct clk_factors_config *config;
+        void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
+        spinlock_t *lock;
+};
+
+extern const struct clk_ops clk_factors_ops;
 #endif
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 98fec4e4baa7..659e4ea31893 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -23,6 +23,9 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
+/* Maximum number of parents our clocks have */
+#define SUNXI_MAX_PARENTS       5
+
 /**
  * sun4i_osc_clk_setup() - Setup function for gatable oscillator
  */
@@ -215,6 +218,40 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
 }
 
 /**
+ * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
+ * PLL5 rate is calculated as follows
+ * rate = parent_rate * n * (k + 1)
+ * parent_rate is always 24Mhz
+ */
+
+static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
+                                   u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u8 div;
+
+        /* Normalize value to a parent_rate multiple (24M) */
+        div = *freq / parent_rate;
+        *freq = parent_rate * div;
+
+        /* we were called to round the frequency, we can now return */
+        if (n == NULL)
+                return;
+
+        if (div < 31)
+                *k = 0;
+        else if (div / 2 < 31)
+                *k = 1;
+        else if (div / 3 < 31)
+                *k = 2;
+        else
+                *k = 3;
+
+        *n = DIV_ROUND_UP(div, (*k+1));
+}
+
+
+
+/**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
  * rate = (parent_rate >> p) / (m + 1);
@@ -258,10 +295,96 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
 
 
 /**
+ * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
+ * MMC rate is calculated as follows
+ * rate = (parent_rate >> p) / (m + 1);
+ */
+
+static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
+                                   u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u8 div, calcm, calcp;
+
+        /* These clocks can only divide, so we will never be able to achieve
+         * frequencies higher than the parent frequency */
+        if (*freq > parent_rate)
+                *freq = parent_rate;
+
+        div = parent_rate / *freq;
+
+        if (div < 16)
+                calcp = 0;
+        else if (div / 2 < 16)
+                calcp = 1;
+        else if (div / 4 < 16)
+                calcp = 2;
+        else
+                calcp = 3;
+
+        calcm = DIV_ROUND_UP(div, 1 << calcp);
+
+        *freq = (parent_rate >> calcp) / calcm;
+
+        /* we were called to round the frequency, we can now return */
+        if (n == NULL)
+                return;
+
+        *m = calcm - 1;
+        *p = calcp;
+}
+
+
+
+/**
+ * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
+ * CLK_OUT rate is calculated as follows
+ * rate = (parent_rate >> p) / (m + 1);
+ */
+
+static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
+                                      u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u8 div, calcm, calcp;
+
+        /* These clocks can only divide, so we will never be able to achieve
+         * frequencies higher than the parent frequency */
+        if (*freq > parent_rate)
+                *freq = parent_rate;
+
+        div = parent_rate / *freq;
+
+        if (div < 32)
+                calcp = 0;
+        else if (div / 2 < 32)
+                calcp = 1;
+        else if (div / 4 < 32)
+                calcp = 2;
+        else
+                calcp = 3;
+
+        calcm = DIV_ROUND_UP(div, 1 << calcp);
+
+        *freq = (parent_rate >> calcp) / calcm;
+
+        /* we were called to round the frequency, we can now return */
+        if (n == NULL)
+                return;
+
+        *m = calcm - 1;
+        *p = calcp;
+}
+
+
+
+/**
  * sunxi_factors_clk_setup() - Setup function for factor clocks
  */
 
+#define SUNXI_FACTORS_MUX_MASK 0x3
+
 struct factors_data {
+        int enable;
+        int mux;
         struct clk_factors_config *table;
         void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
 };
@@ -286,6 +409,13 @@ static struct clk_factors_config sun6i_a31_pll1_config = {
         .mwidth = 2,
 };
 
+static struct clk_factors_config sun4i_pll5_config = {
+        .nshift = 8,
+        .nwidth = 5,
+        .kshift = 4,
+        .kwidth = 2,
+};
+
 static struct clk_factors_config sun4i_apb1_config = {
         .mshift = 0,
         .mwidth = 5,
@@ -293,40 +423,143 @@ static struct clk_factors_config sun4i_apb1_config = {
         .pwidth = 2,
 };
 
+/* user manual says "n" but it's really "p" */
+static struct clk_factors_config sun4i_mod0_config = {
+        .mshift = 0,
+        .mwidth = 4,
+        .pshift = 16,
+        .pwidth = 2,
+};
+
+/* user manual says "n" but it's really "p" */
+static struct clk_factors_config sun7i_a20_out_config = {
+        .mshift = 8,
+        .mwidth = 5,
+        .pshift = 20,
+        .pwidth = 2,
+};
+
 static const struct factors_data sun4i_pll1_data __initconst = {
+        .enable = 31,
         .table = &sun4i_pll1_config,
         .getter = sun4i_get_pll1_factors,
 };
 
 static const struct factors_data sun6i_a31_pll1_data __initconst = {
+        .enable = 31,
         .table = &sun6i_a31_pll1_config,
         .getter = sun6i_a31_get_pll1_factors,
 };
 
+static const struct factors_data sun4i_pll5_data __initconst = {
+        .enable = 31,
+        .table = &sun4i_pll5_config,
+        .getter = sun4i_get_pll5_factors,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
         .table = &sun4i_apb1_config,
         .getter = sun4i_get_apb1_factors,
 };
 
-static void __init sunxi_factors_clk_setup(struct device_node *node,
-                                           struct factors_data *data)
+static const struct factors_data sun4i_mod0_data __initconst = {
+        .enable = 31,
+        .mux = 24,
+        .table = &sun4i_mod0_config,
+        .getter = sun4i_get_mod0_factors,
+};
+
+static const struct factors_data sun7i_a20_out_data __initconst = {
+        .enable = 31,
+        .mux = 24,
+        .table = &sun7i_a20_out_config,
+        .getter = sun7i_a20_get_out_factors,
+};
+
+static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
+                                                const struct factors_data *data)
 {
         struct clk *clk;
+        struct clk_factors *factors;
+        struct clk_gate *gate = NULL;
+        struct clk_mux *mux = NULL;
+        struct clk_hw *gate_hw = NULL;
+        struct clk_hw *mux_hw = NULL;
         const char *clk_name = node->name;
-        const char *parent;
+        const char *parents[SUNXI_MAX_PARENTS];
         void *reg;
+        int i = 0;
 
         reg = of_iomap(node, 0);
 
-        parent = of_clk_get_parent_name(node, 0);
+        /* if we have a mux, we will have >1 parents */
+        while (i < SUNXI_MAX_PARENTS &&
+               (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+                i++;
 
-        clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
-                                   data->table, data->getter, &clk_lock);
+        /* Nodes should be providing the name via clock-output-names
+         * but originally our dts didn't, and so we used node->name.
+         * The new, better nodes look like clk@deadbeef, so we pull the
+         * name just in this case */
+        if (!strcmp("clk", clk_name)) {
+                of_property_read_string_index(node, "clock-output-names",
+                                              0, &clk_name);
+        }
+
+        factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
+        if (!factors)
+                return NULL;
+
+        /* Add a gate if this factor clock can be gated */
+        if (data->enable) {
+                gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+                if (!gate) {
+                        kfree(factors);
+                        return NULL;
+                }
+
+                /* set up gate properties */
+                gate->reg = reg;
+                gate->bit_idx = data->enable;
+                gate->lock = &clk_lock;
+                gate_hw = &gate->hw;
+        }
+
+        /* Add a mux if this factor clock can be muxed */
+        if (data->mux) {
+                mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
+                if (!mux) {
+                        kfree(factors);
+                        kfree(gate);
+                        return NULL;
+                }
+
+                /* set up gate properties */
+                mux->reg = reg;
+                mux->shift = data->mux;
+                mux->mask = SUNXI_FACTORS_MUX_MASK;
+                mux->lock = &clk_lock;
+                mux_hw = &mux->hw;
+        }
+
+        /* set up factors properties */
+        factors->reg = reg;
+        factors->config = data->table;
+        factors->get_factors = data->getter;
+        factors->lock = &clk_lock;
+
+        clk = clk_register_composite(NULL, clk_name,
+                        parents, i,
+                        mux_hw, &clk_mux_ops,
+                        &factors->hw, &clk_factors_ops,
+                        gate_hw, &clk_gate_ops, 0);
 
         if (!IS_ERR(clk)) {
                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
                 clk_register_clkdev(clk, clk_name, NULL);
         }
+
+        return clk;
 }
 
 
@@ -358,13 +591,14 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
 {
         struct clk *clk;
         const char *clk_name = node->name;
-        const char *parents[5];
+        const char *parents[SUNXI_MAX_PARENTS];
         void *reg;
         int i = 0;
 
         reg = of_iomap(node, 0);
 
-        while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+        while (i < SUNXI_MAX_PARENTS &&
+               (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
                 i++;
 
         clk = clk_register_mux(NULL, clk_name, parents, i,
@@ -561,11 +795,186 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 }
 
+
+
+/**
+ * sunxi_divs_clk_setup() helper data
+ */
+
+#define SUNXI_DIVS_MAX_QTY      2
+#define SUNXI_DIVISOR_WIDTH     2
+
+struct divs_data {
+        const struct factors_data *factors; /* data for the factor clock */
+        struct {
+                u8 fixed; /* is it a fixed divisor? if not... */
+                struct clk_div_table *table; /* is it a table based divisor? */
+                u8 shift; /* otherwise it's a normal divisor with this shift */
+                u8 pow;   /* is it power-of-two based? */
+                u8 gate;  /* is it independently gateable? */
+        } div[SUNXI_DIVS_MAX_QTY];
+};
+
+static struct clk_div_table pll6_sata_tbl[] = {
+        { .val = 0, .div = 6, },
+        { .val = 1, .div = 12, },
+        { .val = 2, .div = 18, },
+        { .val = 3, .div = 24, },
+        { } /* sentinel */
+};
+
+static const struct divs_data pll5_divs_data __initconst = {
+        .factors = &sun4i_pll5_data,
+        .div = {
+                { .shift = 0, .pow = 0, }, /* M, DDR */
+                { .shift = 16, .pow = 1, }, /* P, other */
+        }
+};
+
+static const struct divs_data pll6_divs_data __initconst = {
+        .factors = &sun4i_pll5_data,
+        .div = {
+                { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
+                { .fixed = 2 }, /* P, other */
+        }
+};
+
+/**
+ * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
+ *
+ * These clocks look something like this
+ *            ________________________
+ *           |         ___divisor 1---|----> to consumer
+ * parent >--|  pll___/___divisor 2---|----> to consumer
+ *           |        \_______________|____> to consumer
+ *           |________________________|
+ */
+
+static void __init sunxi_divs_clk_setup(struct device_node *node,
+                                        struct divs_data *data)
+{
+        struct clk_onecell_data *clk_data;
+        const char *parent  = node->name;
+        const char *clk_name;
+        struct clk **clks, *pclk;
+        struct clk_hw *gate_hw, *rate_hw;
+        const struct clk_ops *rate_ops;
+        struct clk_gate *gate = NULL;
+        struct clk_fixed_factor *fix_factor;
+        struct clk_divider *divider;
+        void *reg;
+        int i = 0;
+        int flags, clkflags;
+
+        /* Set up factor clock that we will be dividing */
+        pclk = sunxi_factors_clk_setup(node, data->factors);
+
+        reg = of_iomap(node, 0);
+
+        clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+        if (!clk_data)
+                return;
+
+        clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
+        if (!clks)
+                goto free_clkdata;
+
+        clk_data->clks = clks;
+
+        /* It's not a good idea to have automatic reparenting changing
+         * our RAM clock! */
+        clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
+
+        for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
+                if (of_property_read_string_index(node, "clock-output-names",
+                                                  i, &clk_name) != 0)
+                        break;
+
+                gate_hw = NULL;
+                rate_hw = NULL;
+                rate_ops = NULL;
+
+                /* If this leaf clock can be gated, create a gate */
+                if (data->div[i].gate) {
+                        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+                        if (!gate)
+                                goto free_clks;
+
+                        gate->reg = reg;
+                        gate->bit_idx = data->div[i].gate;
+                        gate->lock = &clk_lock;
+
+                        gate_hw = &gate->hw;
+                }
+
+                /* Leaves can be fixed or configurable divisors */
+                if (data->div[i].fixed) {
+                        fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
+                        if (!fix_factor)
+                                goto free_gate;
+
+                        fix_factor->mult = 1;
+                        fix_factor->div = data->div[i].fixed;
+
+                        rate_hw = &fix_factor->hw;
+                        rate_ops = &clk_fixed_factor_ops;
+                } else {
+                        divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+                        if (!divider)
+                                goto free_gate;
+
+                        flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
+
+                        divider->reg = reg;
+                        divider->shift = data->div[i].shift;
+                        divider->width = SUNXI_DIVISOR_WIDTH;
+                        divider->flags = flags;
+                        divider->lock = &clk_lock;
+                        divider->table = data->div[i].table;
+
+                        rate_hw = &divider->hw;
+                        rate_ops = &clk_divider_ops;
+                }
+
+                /* Wrap the (potential) gate and the divisor on a composite
+                 * clock to unify them */
+                clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
+                                                 NULL, NULL,
+                                                 rate_hw, rate_ops,
+                                                 gate_hw, &clk_gate_ops,
+                                                 clkflags);
+
+                WARN_ON(IS_ERR(clk_data->clks[i]));
+                clk_register_clkdev(clks[i], clk_name, NULL);
+        }
+
+        /* The last clock available on the getter is the parent */
+        clks[i++] = pclk;
+
+        /* Adjust to the real max */
+        clk_data->clk_num = i;
+
+        of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+        return;
+
+free_gate:
+        kfree(gate);
+free_clks:
+        kfree(clks);
+free_clkdata:
+        kfree(clk_data);
+}
+
+
+
 /* Matches for factors clocks */
 static const struct of_device_id clk_factors_match[] __initconst = {
         {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
         {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
+        {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
+        {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
         {}
 };
 
@@ -578,6 +987,13 @@ static const struct of_device_id clk_div_match[] __initconst = {
         {}
 };
 
+/* Matches for divided outputs */
+static const struct of_device_id clk_divs_match[] __initconst = {
+        {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
+        {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
+        {}
+};
+
 /* Matches for mux clocks */
 static const struct of_device_id clk_mux_match[] __initconst = {
         {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
@@ -655,6 +1071,9 @@ static void __init sunxi_init_clocks(void)
         /* Register divider clocks */
         of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
 
+        /* Register divided output clocks */
+        of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
+
         /* Register mux clocks */
         of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);