diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2010-09-06 12:13:39 -0400 |
---|---|---|
committer | Borislav Petkov <bp@amd64.org> | 2010-10-21 08:47:58 -0400 |
commit | 6337583d7dc0dced36ab98dd63de2389c95c22d9 (patch) | |
tree | 446bc36e340eb1d264e99b75469632b21ef71a1c /drivers | |
parent | 0ee8efa8f4672ce35ee370291c0f21d7b87b1e3f (diff) |
EDAC, MCE: Sanitize error codes
Clean up error codes names, shorten to mnemonics, add RRRR boundary
checking.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/edac/edac_mce_amd.c | 63 | ||||
-rw-r--r-- | drivers/edac/edac_mce_amd.h | 5 |
2 files changed, 19 insertions, 49 deletions
diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c index 765d7fbfa2d5..d0e850eea50a 100644 --- a/drivers/edac/edac_mce_amd.c +++ b/drivers/edac/edac_mce_amd.c | |||
@@ -30,62 +30,31 @@ EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder); | |||
30 | * string representation for the different MCA reported error types, see F3x48 | 30 | * string representation for the different MCA reported error types, see F3x48 |
31 | * or MSR0000_0411. | 31 | * or MSR0000_0411. |
32 | */ | 32 | */ |
33 | const char *tt_msgs[] = { /* transaction type */ | 33 | |
34 | "instruction", | 34 | /* transaction type */ |
35 | "data", | 35 | const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" }; |
36 | "generic", | ||
37 | "reserved" | ||
38 | }; | ||
39 | EXPORT_SYMBOL_GPL(tt_msgs); | 36 | EXPORT_SYMBOL_GPL(tt_msgs); |
40 | 37 | ||
41 | const char *ll_msgs[] = { /* cache level */ | 38 | /* cache level */ |
42 | "L0", | 39 | const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; |
43 | "L1", | ||
44 | "L2", | ||
45 | "L3/generic" | ||
46 | }; | ||
47 | EXPORT_SYMBOL_GPL(ll_msgs); | 40 | EXPORT_SYMBOL_GPL(ll_msgs); |
48 | 41 | ||
42 | /* memory transaction type */ | ||
49 | const char *rrrr_msgs[] = { | 43 | const char *rrrr_msgs[] = { |
50 | "generic", | 44 | "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP" |
51 | "generic read", | ||
52 | "generic write", | ||
53 | "data read", | ||
54 | "data write", | ||
55 | "inst fetch", | ||
56 | "prefetch", | ||
57 | "evict", | ||
58 | "snoop", | ||
59 | "reserved RRRR= 9", | ||
60 | "reserved RRRR= 10", | ||
61 | "reserved RRRR= 11", | ||
62 | "reserved RRRR= 12", | ||
63 | "reserved RRRR= 13", | ||
64 | "reserved RRRR= 14", | ||
65 | "reserved RRRR= 15" | ||
66 | }; | 45 | }; |
67 | EXPORT_SYMBOL_GPL(rrrr_msgs); | 46 | EXPORT_SYMBOL_GPL(rrrr_msgs); |
68 | 47 | ||
69 | const char *pp_msgs[] = { /* participating processor */ | 48 | /* participating processor */ |
70 | "local node originated (SRC)", | 49 | const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" }; |
71 | "local node responded to request (RES)", | ||
72 | "local node observed as 3rd party (OBS)", | ||
73 | "generic" | ||
74 | }; | ||
75 | EXPORT_SYMBOL_GPL(pp_msgs); | 50 | EXPORT_SYMBOL_GPL(pp_msgs); |
76 | 51 | ||
77 | const char *to_msgs[] = { | 52 | /* request timeout */ |
78 | "no timeout", | 53 | const char *to_msgs[] = { "no timeout", "timed out" }; |
79 | "timed out" | ||
80 | }; | ||
81 | EXPORT_SYMBOL_GPL(to_msgs); | 54 | EXPORT_SYMBOL_GPL(to_msgs); |
82 | 55 | ||
83 | const char *ii_msgs[] = { /* memory or i/o */ | 56 | /* memory or i/o */ |
84 | "mem access", | 57 | const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" }; |
85 | "reserved", | ||
86 | "i/o access", | ||
87 | "generic" | ||
88 | }; | ||
89 | EXPORT_SYMBOL_GPL(ii_msgs); | 58 | EXPORT_SYMBOL_GPL(ii_msgs); |
90 | 59 | ||
91 | /* | 60 | /* |
@@ -336,16 +305,16 @@ static void amd_decode_fr_mce(u64 mc5_status) | |||
336 | pr_emerg(HW_ERR "Corrupted FR MCE info?\n"); | 305 | pr_emerg(HW_ERR "Corrupted FR MCE info?\n"); |
337 | } | 306 | } |
338 | 307 | ||
339 | static inline void amd_decode_err_code(unsigned int ec) | 308 | static inline void amd_decode_err_code(u16 ec) |
340 | { | 309 | { |
341 | if (TLB_ERROR(ec)) { | 310 | if (TLB_ERROR(ec)) { |
342 | pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n", | 311 | pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n", |
343 | TT_MSG(ec), LL_MSG(ec)); | 312 | TT_MSG(ec), LL_MSG(ec)); |
344 | } else if (MEM_ERROR(ec)) { | 313 | } else if (MEM_ERROR(ec)) { |
345 | pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s", | 314 | pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s\n", |
346 | RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec)); | 315 | RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec)); |
347 | } else if (BUS_ERROR(ec)) { | 316 | } else if (BUS_ERROR(ec)) { |
348 | pr_emerg(HW_ERR "Transaction type: %s(%s), %s, Cache Level: %s, " | 317 | pr_emerg(HW_ERR "Transaction: %s (%s), %s, Cache Level: %s, " |
349 | "Participating Processor: %s\n", | 318 | "Participating Processor: %s\n", |
350 | RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), | 319 | RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), |
351 | PP_MSG(ec)); | 320 | PP_MSG(ec)); |
diff --git a/drivers/edac/edac_mce_amd.h b/drivers/edac/edac_mce_amd.h index 8920133075e9..2ee499d7f898 100644 --- a/drivers/edac/edac_mce_amd.h +++ b/drivers/edac/edac_mce_amd.h | |||
@@ -20,13 +20,14 @@ | |||
20 | #define II_MSG(x) ii_msgs[II(x)] | 20 | #define II_MSG(x) ii_msgs[II(x)] |
21 | #define LL(x) (((x) >> 0) & 0x3) | 21 | #define LL(x) (((x) >> 0) & 0x3) |
22 | #define LL_MSG(x) ll_msgs[LL(x)] | 22 | #define LL_MSG(x) ll_msgs[LL(x)] |
23 | #define RRRR(x) (((x) >> 4) & 0xf) | ||
24 | #define RRRR_MSG(x) rrrr_msgs[RRRR(x)] | ||
25 | #define TO(x) (((x) >> 8) & 0x1) | 23 | #define TO(x) (((x) >> 8) & 0x1) |
26 | #define TO_MSG(x) to_msgs[TO(x)] | 24 | #define TO_MSG(x) to_msgs[TO(x)] |
27 | #define PP(x) (((x) >> 9) & 0x3) | 25 | #define PP(x) (((x) >> 9) & 0x3) |
28 | #define PP_MSG(x) pp_msgs[PP(x)] | 26 | #define PP_MSG(x) pp_msgs[PP(x)] |
29 | 27 | ||
28 | #define RRRR(x) (((x) >> 4) & 0xf) | ||
29 | #define RRRR_MSG(x) ((RRRR(x) < 9) ? rrrr_msgs[RRRR(x)] : "Wrong R4!") | ||
30 | |||
30 | #define K8_NBSH 0x4C | 31 | #define K8_NBSH 0x4C |
31 | 32 | ||
32 | #define K8_NBSH_VALID_BIT BIT(31) | 33 | #define K8_NBSH_VALID_BIT BIT(31) |