Merge branch 'drm-intel-fixes' into drm-intel-next

Conflicts:
	drivers/gpu/drm/i915/i915_gem_evict.c
	drivers/gpu/drm/i915/intel_display.c
	drivers/gpu/drm/i915/intel_dp.c

7 files changed, 74 insertions, 59 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a78c97340605..19acf123c1f1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3379,6 +3379,8 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
                                   (int) reloc->offset,
                                   reloc->read_domains,
                                   reloc->write_domain);
+                        drm_gem_object_unreference(target_obj);
+                        i915_gem_object_unpin(obj);
                         return -EINVAL;
                 }
                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index c503c81f4cdf..3d7fbf32bb18 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -93,7 +93,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
         struct list_head eviction_list, unwind_list;
-        struct drm_i915_gem_object *obj_priv, *tmp_obj_priv;
+        struct drm_i915_gem_object *obj_priv;
         struct list_head *render_iter, *bsd_iter;
         int ret = 0;
 
@@ -175,36 +175,34 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen
         return -ENOSPC;
 
 found:
+        /* drm_mm doesn't allow any other other operations while
+         * scanning, therefore store to be evicted objects on a
+         * temporary list. */
         INIT_LIST_HEAD(&eviction_list);
-        list_for_each_entry_safe(obj_priv, tmp_obj_priv,
-                                 &unwind_list, evict_list) {
+        while (!list_empty(&unwind_list)) {
+                obj_priv = list_first_entry(&unwind_list,
+                                            struct drm_i915_gem_object,
+                                            evict_list);
                 if (drm_mm_scan_remove_block(obj_priv->gtt_space)) {
-                        /* drm_mm doesn't allow any other other operations while
-                         * scanning, therefore store to be evicted objects on a
-                         * temporary list. */
                         list_move(&obj_priv->evict_list, &eviction_list);
-                } else
-                        drm_gem_object_unreference(&obj_priv->base);
+                        continue;
+                }
+                list_del(&obj_priv->evict_list);
+                drm_gem_object_unreference(&obj_priv->base);
         }
 
         /* Unbinding will emit any required flushes */
-        list_for_each_entry_safe(obj_priv, tmp_obj_priv,
-                                 &eviction_list, evict_list) {
-                ret = i915_gem_object_unbind(&obj_priv->base);
-                if (ret)
-                        return ret;
-
+        while (!list_empty(&eviction_list)) {
+                obj_priv = list_first_entry(&eviction_list,
+                                            struct drm_i915_gem_object,
+                                            evict_list);
+                if (ret == 0)
+                        ret = i915_gem_object_unbind(&obj_priv->base);
+                list_del(&obj_priv->evict_list);
                 drm_gem_object_unreference(&obj_priv->base);
         }
 
-        /* The just created free hole should be on the top of the free stack
-         * maintained by drm_mm, so this BUG_ON actually executes in O(1).
-         * Furthermore all accessed data has just recently been used, so it
-         * should be really fast, too. */
-        BUG_ON(!drm_mm_search_free(&dev_priv->mm.gtt_space, min_size,
-                                   alignment, 0));
-
-        return 0;
+        return ret;
 }
 
 int
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58cfea25a645..d02de212e6ad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2105,7 +2105,7 @@
 
 /* Pipe A */
 #define PIPEADSL                0x70000
-#define   DSL_LINEMASK          0x00000fff
+#define   DSL_LINEMASK          0x00000fff
 #define PIPEACONF               0x70008
 #define   PIPECONF_ENABLE       (1<<31)
 #define   PIPECONF_DISABLE      0
@@ -2162,13 +2162,14 @@
 #define   PIPE_START_VBLANK_INTERRUPT_STATUS    (1UL<<2) /* 965 or later */
 #define   PIPE_VBLANK_INTERRUPT_STATUS          (1UL<<1)
 #define   PIPE_OVERLAY_UPDATED_STATUS           (1UL<<0)
-#define   PIPE_BPC_MASK                         (7 << 5) /* Ironlake */
+#define   PIPE_BPC_MASK                         (7 << 5) /* Ironlake */
 #define   PIPE_8BPC                             (0 << 5)
 #define   PIPE_10BPC                            (1 << 5)
 #define   PIPE_6BPC                             (2 << 5)
 #define   PIPE_12BPC                            (3 << 5)
 
 #define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF)
+#define PIPEDSL(pipe)  _PIPE(pipe, PIPEADSL, PIPEBDSL)
 
 #define DSPARB                  0x70030
 #define   DSPARB_CSTART_MASK    (0x7f << 7)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 00214c123ec2..a2e8e15b8f5a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1017,8 +1017,8 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
                 DRM_DEBUG_KMS("vblank wait timed out\n");
 }
 
-/**
- * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
+/*
+ * intel_wait_for_pipe_off - wait for pipe to turn off
  * @dev: drm device
  * @pipe: pipe to wait for
  *
@@ -1026,26 +1026,39 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  * spinning on the vblank interrupt status bit, since we won't actually
  * see an interrupt when the pipe is disabled.
  *
- * So this function waits for the display line value to settle (it
- * usually ends up stopping at the start of the next frame).
+ * On Gen4 and above:
+ *   wait for the pipe register state bit to turn off
+ *
+ * Otherwise:
+ *   wait for the display line value to settle (it usually
+ *   ends up stopping at the start of the next frame).
+ *
  */
-void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
+void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
-        unsigned long timeout = jiffies + msecs_to_jiffies(100);
-        u32 last_line, line;
-
-        /* Wait for the display line to settle */
-        line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
-        do {
-                last_line = line;
-                MSLEEP(5);
-                line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
-        } while (line != last_line && time_after(timeout, jiffies));
-
-        if (line != last_line)
-                DRM_DEBUG_KMS("vblank wait timed out\n");
+
+        if (INTEL_INFO(dev)->gen >= 4) {
+                int reg = PIPECONF(pipe);
+
+                /* Wait for the Pipe State to go off */
+                if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
+                             100))
+                        DRM_DEBUG_KMS("pipe_off wait timed out\n");
+        } else {
+                u32 last_line;
+                int reg = PIPEDSL(pipe);
+                unsigned long timeout = jiffies + msecs_to_jiffies(100);
+
+                /* Wait for the display line to settle */
+                do {
+                        last_line = I915_READ(reg) & DSL_LINEMASK;
+                        mdelay(5);
+                } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
+                         time_after(timeout, jiffies));
+                if (time_after(jiffies, timeout))
+                        DRM_DEBUG_KMS("pipe_off wait timed out\n");
+        }
 }
 
 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
@@ -2406,7 +2419,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 
                 /* Wait for vblank for the disable to take effect */
                 if (IS_GEN2(dev))
-                        intel_wait_for_vblank_off(dev, pipe);
+                        intel_wait_for_vblank(dev, pipe);
         }
 
         /* Don't disable pipe A or pipe A PLLs if needed */
@@ -2419,9 +2432,9 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
         if (temp & PIPECONF_ENABLE) {
                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
 
-                /* Wait for vblank for the disable to take effect. */
+                /* Wait for the pipe to turn off */
                 POSTING_READ(reg);
-                intel_wait_for_vblank_off(dev, pipe);
+                intel_wait_for_pipe_off(dev, pipe);
         }
 
         reg = DPLL(pipe);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d19334aa66ad..9e8fe122b0af 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1186,25 +1186,22 @@ intel_channel_eq_ok(struct intel_dp *intel_dp)
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
                         uint32_t dp_reg_value,
-                        uint8_t dp_train_pat,
-                        bool first)
+                        uint8_t dp_train_pat)
 {
         struct drm_device *dev = intel_dp->base.base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
         int ret;
 
         I915_WRITE(intel_dp->output_reg, dp_reg_value);
         POSTING_READ(intel_dp->output_reg);
-        if (first)
-                intel_wait_for_vblank(dev, intel_crtc->pipe);
 
         intel_dp_aux_native_write_1(intel_dp,
                                     DP_TRAINING_PATTERN_SET,
                                     dp_train_pat);
 
         ret = intel_dp_aux_native_write(intel_dp,
-                                        DP_TRAINING_LANE0_SET, intel_dp->train_set, 4);
+                                        DP_TRAINING_LANE0_SET,
+                                        intel_dp->train_set, 4);
         if (ret != 4)
                 return false;
 
@@ -1216,14 +1213,20 @@ static void
 intel_dp_start_link_train(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp->base.base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
         int i;
         uint8_t voltage;
         bool clock_recovery = false;
-        bool first = true;
         int tries;
         u32 reg;
         uint32_t DP = intel_dp->DP;
 
+        /* Enable output, wait for it to become active */
+        I915_WRITE(intel_dp->output_reg, intel_dp->DP);
+        POSTING_READ(intel_dp->output_reg);
+        intel_wait_for_vblank(dev, intel_crtc->pipe);
+
         /* Write the link configuration data */
         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
                                   intel_dp->link_configuration,
@@ -1255,9 +1258,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
                         reg = DP | DP_LINK_TRAIN_PAT_1;
 
                 if (!intel_dp_set_link_train(intel_dp, reg,
-                                             DP_TRAINING_PATTERN_1, first))
+                                             DP_TRAINING_PATTERN_1))
                         break;
-                first = false;
                 /* Set training pattern 1 */
 
                 udelay(100);
@@ -1324,8 +1326,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 
                 /* channel eq pattern */
                 if (!intel_dp_set_link_train(intel_dp, reg,
-                                             DP_TRAINING_PATTERN_2,
-                                             false))
+                                             DP_TRAINING_PATTERN_2))
                         break;
 
                 udelay(400);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 60ce9305e772..40e99bf27ff7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -242,8 +242,8 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
                                                     struct drm_crtc *crtc);
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
                                 struct drm_file *file_priv);
-extern void intel_wait_for_vblank_off(struct drm_device *dev, int pipe);
 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
+extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
                                                    struct drm_connector *connector,
                                                    struct drm_display_mode *mode,
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 106560bc84db..2f7681989316 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1170,7 +1170,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
                 I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
                 /* Wait for vblank for the disable to take effect. */
-                intel_wait_for_vblank_off(dev, intel_crtc->pipe);
+                intel_wait_for_pipe_off(dev, intel_crtc->pipe);
 
                 /* Filter ctl must be set before TV_WIN_SIZE */
                 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);