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authorMauro Carvalho Chehab <mchehab@redhat.com>2009-06-22 21:48:31 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-05-10 10:44:48 -0400
commit5566cb7c91ba4ff4447278bb27896b4a2bb7d18a (patch)
tree24847858d91b2ff12adb8b80787d34660858aa39 /drivers
parent854d3349973a7c47bd989794037f526b74af20c4 (diff)
i7core_edac: Memory info fixes and preparation for properly filling cswrow data
Now, memory size is properly displayed: EDAC i7core: DOD Max limits: DIMMS: 2, 1-ranked, 8-banked EDAC i7core: DOD Max rows x colums = 0x4000 x 0x400 EDAC i7core: Memory channel configuration: EDAC i7core: Ch0 phy rd0, wr0 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: dimm 1 (0x00001288) 1024 Mb offset: 4, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: Ch1 phy rd1, wr1 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: Ch2 phy rd3, wr3 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 Still, as the way to retrieve csrows info is not known, it does a mapping of what's available to csrows basic unit at edac core. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/edac/i7core_edac.c28
1 files changed, 19 insertions, 9 deletions
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 483cca2e543b..772219fa10be 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -113,8 +113,8 @@
113 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7) 113 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
114 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5)) 114 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
115 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5) 115 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
116 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3)) 116 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3)| (1 << 2))
117 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 3) 117 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
118 #define MC_DOD_NUMCOL_MASK 3 118 #define MC_DOD_NUMCOL_MASK 3
119 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK) 119 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
120 120
@@ -361,6 +361,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
361 struct csrow_info *csr; 361 struct csrow_info *csr;
362 struct pci_dev *pdev; 362 struct pci_dev *pdev;
363 int i, j, csrow = 0; 363 int i, j, csrow = 0;
364 unsigned long last_page = 0;
364 enum edac_type mode; 365 enum edac_type mode;
365 enum mem_type mtype; 366 enum mem_type mtype;
366 367
@@ -380,7 +381,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
380 pvt->info.max_dod, pvt->info.ch_map); 381 pvt->info.max_dod, pvt->info.ch_map);
381 382
382 if (ECC_ENABLED(pvt)) { 383 if (ECC_ENABLED(pvt)) {
383 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt)?8:4); 384 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ?8:4);
384 if (ECCx8(pvt)) 385 if (ECCx8(pvt))
385 mode = EDAC_S8ECD8ED; 386 mode = EDAC_S8ECD8ED;
386 else 387 else
@@ -450,6 +451,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
450 451
451 for (j = 0; j < 3; j++) { 452 for (j = 0; j < 3; j++) {
452 u32 banks, ranks, rows, cols; 453 u32 banks, ranks, rows, cols;
454 u32 size, npages;
453 455
454 if (!DIMM_PRESENT(dimm_dod[j])) 456 if (!DIMM_PRESENT(dimm_dod[j]))
455 continue; 457 continue;
@@ -459,19 +461,27 @@ static int get_dimm_config(struct mem_ctl_info *mci)
459 rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); 461 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
460 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j])); 462 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
461 463
464 /* DDR3 has 8 I/O banks */
465 size = (rows * cols * banks * ranks) >> (20 - 3);
466
462 pvt->channel[i].dimms++; 467 pvt->channel[i].dimms++;
463 468
464 debugf0("\tdimm %d offset: %x, numbank: %#x, " 469 debugf0("\tdimm %d (0x%08x) %d Mb offset: %x, "
465 "numrank: %#x, numrow: %#x, numcol: %#x\n", 470 "numbank: %d,\n\t\t"
466 j, 471 "numrank: %d, numrow: %#x, numcol: %#x\n",
472 j, dimm_dod[j], size,
467 RANKOFFSET(dimm_dod[j]), 473 RANKOFFSET(dimm_dod[j]),
468 banks, ranks, rows, cols); 474 banks, ranks, rows, cols);
469 475
476 npages = cols * rows; /* FIXME */
477
470 csr = &mci->csrows[csrow]; 478 csr = &mci->csrows[csrow];
471 csr->first_page = 0; 479 csr->first_page = last_page + 1;
472 csr->last_page = 0; 480 last_page += npages;
481 csr->last_page = last_page;
482 csr->nr_pages = npages;
483
473 csr->page_mask = 0; 484 csr->page_mask = 0;
474 csr->nr_pages = 0;
475 csr->grain = 0; 485 csr->grain = 0;
476 csr->csrow_idx = csrow; 486 csr->csrow_idx = csrow;
477 487