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author | Alex Deucher <alexander.deucher@amd.com> | 2014-08-07 09:57:21 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-08-15 00:58:09 -0400 |
commit | 4fb0bbd5d0f13f39a2fe5e092a64cece3a4afcb9 (patch) | |
tree | c8a939a39a2af6d802c6c37a29bbc01c00a4b4a6 /drivers | |
parent | 6e909f74db2aa9c5b5606b81efcbe18f2749b008 (diff) |
drm/radeon: use pfp for all vm_flush related updates
May fix hangs in some cases.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index b625646bf3e2..e7d99e1547cc 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -5958,14 +5958,14 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5958 | 5958 | ||
5959 | /* update SH_MEM_* regs */ | 5959 | /* update SH_MEM_* regs */ |
5960 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5960 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5961 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5961 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
5962 | WRITE_DATA_DST_SEL(0))); | 5962 | WRITE_DATA_DST_SEL(0))); |
5963 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | 5963 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
5964 | radeon_ring_write(ring, 0); | 5964 | radeon_ring_write(ring, 0); |
5965 | radeon_ring_write(ring, VMID(vm->id)); | 5965 | radeon_ring_write(ring, VMID(vm->id)); |
5966 | 5966 | ||
5967 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); | 5967 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); |
5968 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5968 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
5969 | WRITE_DATA_DST_SEL(0))); | 5969 | WRITE_DATA_DST_SEL(0))); |
5970 | radeon_ring_write(ring, SH_MEM_BASES >> 2); | 5970 | radeon_ring_write(ring, SH_MEM_BASES >> 2); |
5971 | radeon_ring_write(ring, 0); | 5971 | radeon_ring_write(ring, 0); |
@@ -5976,7 +5976,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5976 | radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ | 5976 | radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ |
5977 | 5977 | ||
5978 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5978 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5979 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5979 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
5980 | WRITE_DATA_DST_SEL(0))); | 5980 | WRITE_DATA_DST_SEL(0))); |
5981 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | 5981 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
5982 | radeon_ring_write(ring, 0); | 5982 | radeon_ring_write(ring, 0); |
@@ -5987,7 +5987,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5987 | 5987 | ||
5988 | /* bits 0-15 are the VM contexts0-15 */ | 5988 | /* bits 0-15 are the VM contexts0-15 */ |
5989 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5989 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5990 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5990 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
5991 | WRITE_DATA_DST_SEL(0))); | 5991 | WRITE_DATA_DST_SEL(0))); |
5992 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | 5992 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
5993 | radeon_ring_write(ring, 0); | 5993 | radeon_ring_write(ring, 0); |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 011779bd2b3d..dbd9d8101f05 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -5028,7 +5028,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5028 | 5028 | ||
5029 | /* flush hdp cache */ | 5029 | /* flush hdp cache */ |
5030 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5030 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5031 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5031 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
5032 | WRITE_DATA_DST_SEL(0))); | 5032 | WRITE_DATA_DST_SEL(0))); |
5033 | radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); | 5033 | radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); |
5034 | radeon_ring_write(ring, 0); | 5034 | radeon_ring_write(ring, 0); |
@@ -5036,7 +5036,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5036 | 5036 | ||
5037 | /* bits 0-15 are the VM contexts0-15 */ | 5037 | /* bits 0-15 are the VM contexts0-15 */ |
5038 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5038 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5039 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5039 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
5040 | WRITE_DATA_DST_SEL(0))); | 5040 | WRITE_DATA_DST_SEL(0))); |
5041 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | 5041 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
5042 | radeon_ring_write(ring, 0); | 5042 | radeon_ring_write(ring, 0); |