diff options
| author | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-03-29 11:32:36 -0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-09 12:04:04 -0400 |
| commit | 4dffc4043a392b4a0f13f033330d31833bbf9f35 (patch) | |
| tree | c09663d2e291b26352eae5dec98982c9c4eefe71 /drivers | |
| parent | 90e8d31c53890064962f1154405e1034be7ec9a1 (diff) | |
drm/i915: add WRPLL clocks
The WR PLL can drive the DDI ports at fixed frequencies for HDMI, DVI, DP
and FDI.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8c44fe0b4fa4..fa4d1d303623 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -4157,6 +4157,14 @@ | |||
| 4157 | #define SPLL_PLL_FREQ_810MHz (0<<26) | 4157 | #define SPLL_PLL_FREQ_810MHz (0<<26) |
| 4158 | #define SPLL_PLL_FREQ_1350MHz (1<<26) | 4158 | #define SPLL_PLL_FREQ_1350MHz (1<<26) |
| 4159 | 4159 | ||
| 4160 | /* WRPLL */ | ||
| 4161 | #define WRPLL_CTL1 0x46040 | ||
| 4162 | #define WRPLL_CTL2 0x46060 | ||
| 4163 | #define WRPLL_PLL_ENABLE (1<<31) | ||
| 4164 | #define WRPLL_PLL_SELECT_SSC (0x01<<28) | ||
| 4165 | #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) | ||
| 4166 | #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) | ||
| 4167 | |||
| 4160 | /* Port clock selection */ | 4168 | /* Port clock selection */ |
| 4161 | #define PORT_CLK_SEL_A 0x46100 | 4169 | #define PORT_CLK_SEL_A 0x46100 |
| 4162 | #define PORT_CLK_SEL_B 0x46104 | 4170 | #define PORT_CLK_SEL_B 0x46104 |