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authorRafał Miłecki <zajec5@gmail.com>2011-12-17 07:57:23 -0500
committerJohn W. Linville <linville@tuxdriver.com>2011-12-19 14:40:48 -0500
commit4d9f46ba92b688a5428605101092c2f46955cf6b (patch)
tree6cb178ee7209d604379ad25bde9d59a0318df318 /drivers
parent8be89535e63422858250f90bc77b3f77a19e820b (diff)
b43: N-PHY: reorder functions: collect RSSI selects
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/b43/phy_n.c446
1 files changed, 225 insertions, 221 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 3140b6082d0d..0e4a364b262e 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -913,6 +913,231 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
913} 913}
914 914
915/************************************************** 915/**************************************************
916 * RSSI
917 **************************************************/
918
919/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
920static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
921 s8 offset, u8 core, u8 rail,
922 enum b43_nphy_rssi_type type)
923{
924 u16 tmp;
925 bool core1or5 = (core == 1) || (core == 5);
926 bool core2or5 = (core == 2) || (core == 5);
927
928 offset = clamp_val(offset, -32, 31);
929 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
930
931 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
932 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
933 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
934 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
935 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
936 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
937 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
938 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
939
940 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
941 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
942 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
943 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
944 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
945 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
946 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
947 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
948
949 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
950 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
951 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
952 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
953 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
954 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
955 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
956 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
957
958 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
959 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
960 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
961 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
962 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
963 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
964 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
965 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
966
967 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
968 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
969 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
970 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
971 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
972 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
973 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
974 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
975
976 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
977 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
978 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
979 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
980
981 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
982 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
983 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
984 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
985}
986
987static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
988{
989 u8 i;
990 u16 reg, val;
991
992 if (code == 0) {
993 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
994 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
995 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
996 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
997 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
998 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
999 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1000 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1001 } else {
1002 for (i = 0; i < 2; i++) {
1003 if ((code == 1 && i == 1) || (code == 2 && !i))
1004 continue;
1005
1006 reg = (i == 0) ?
1007 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1008 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1009
1010 if (type < 3) {
1011 reg = (i == 0) ?
1012 B43_NPHY_AFECTL_C1 :
1013 B43_NPHY_AFECTL_C2;
1014 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1015
1016 reg = (i == 0) ?
1017 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1018 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1019 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1020
1021 if (type == 0)
1022 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1023 else if (type == 1)
1024 val = 16;
1025 else
1026 val = 32;
1027 b43_phy_set(dev, reg, val);
1028
1029 reg = (i == 0) ?
1030 B43_NPHY_TXF_40CO_B1S0 :
1031 B43_NPHY_TXF_40CO_B32S1;
1032 b43_phy_set(dev, reg, 0x0020);
1033 } else {
1034 if (type == 6)
1035 val = 0x0100;
1036 else if (type == 3)
1037 val = 0x0200;
1038 else
1039 val = 0x0300;
1040
1041 reg = (i == 0) ?
1042 B43_NPHY_AFECTL_C1 :
1043 B43_NPHY_AFECTL_C2;
1044
1045 b43_phy_maskset(dev, reg, 0xFCFF, val);
1046 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1047
1048 if (type != 3 && type != 6) {
1049 enum ieee80211_band band =
1050 b43_current_band(dev->wl);
1051
1052 if (b43_nphy_ipa(dev))
1053 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1054 else
1055 val = 0x11;
1056 reg = (i == 0) ? 0x2000 : 0x3000;
1057 reg |= B2055_PADDRV;
1058 b43_radio_write16(dev, reg, val);
1059
1060 reg = (i == 0) ?
1061 B43_NPHY_AFECTL_OVER1 :
1062 B43_NPHY_AFECTL_OVER;
1063 b43_phy_set(dev, reg, 0x0200);
1064 }
1065 }
1066 }
1067 }
1068}
1069
1070static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1071{
1072 u16 val;
1073
1074 if (type < 3)
1075 val = 0;
1076 else if (type == 6)
1077 val = 1;
1078 else if (type == 3)
1079 val = 2;
1080 else
1081 val = 3;
1082
1083 val = (val << 12) | (val << 14);
1084 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1085 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1086
1087 if (type < 3) {
1088 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1089 (type + 1) << 4);
1090 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1091 (type + 1) << 4);
1092 }
1093
1094 if (code == 0) {
1095 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1096 if (type < 3) {
1097 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1098 ~(B43_NPHY_RFCTL_CMD_RXEN |
1099 B43_NPHY_RFCTL_CMD_CORESEL));
1100 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1101 ~(0x1 << 12 |
1102 0x1 << 5 |
1103 0x1 << 1 |
1104 0x1));
1105 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1106 ~B43_NPHY_RFCTL_CMD_START);
1107 udelay(20);
1108 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1109 }
1110 } else {
1111 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1112 if (type < 3) {
1113 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1114 ~(B43_NPHY_RFCTL_CMD_RXEN |
1115 B43_NPHY_RFCTL_CMD_CORESEL),
1116 (B43_NPHY_RFCTL_CMD_RXEN |
1117 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1118 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1119 (0x1 << 12 |
1120 0x1 << 5 |
1121 0x1 << 1 |
1122 0x1));
1123 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1124 B43_NPHY_RFCTL_CMD_START);
1125 udelay(20);
1126 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1127 }
1128 }
1129}
1130
1131/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1132static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1133{
1134 if (dev->phy.rev >= 3)
1135 b43_nphy_rev3_rssi_select(dev, code, type);
1136 else
1137 b43_nphy_rev2_rssi_select(dev, code, type);
1138}
1139
1140/**************************************************
916 * Others 1141 * Others
917 **************************************************/ 1142 **************************************************/
918 1143
@@ -2311,227 +2536,6 @@ static void b43_nphy_bphy_init(struct b43_wldev *dev)
2311 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); 2536 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2312} 2537}
2313 2538
2314/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2315static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2316 s8 offset, u8 core, u8 rail,
2317 enum b43_nphy_rssi_type type)
2318{
2319 u16 tmp;
2320 bool core1or5 = (core == 1) || (core == 5);
2321 bool core2or5 = (core == 2) || (core == 5);
2322
2323 offset = clamp_val(offset, -32, 31);
2324 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2325
2326 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2327 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2328 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2329 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2330 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2331 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2332 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2333 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2334
2335 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2336 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2337 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2338 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2339 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2340 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2341 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2342 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2343
2344 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2345 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2346 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2347 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2348 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2349 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2350 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2351 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2352
2353 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2354 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2355 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2356 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2357 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2358 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2359 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2360 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2361
2362 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2363 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2364 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2365 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2366 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2367 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2368 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2369 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2370
2371 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2372 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2373 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2374 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2375
2376 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2377 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2378 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2379 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2380}
2381
2382static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2383{
2384 u16 val;
2385
2386 if (type < 3)
2387 val = 0;
2388 else if (type == 6)
2389 val = 1;
2390 else if (type == 3)
2391 val = 2;
2392 else
2393 val = 3;
2394
2395 val = (val << 12) | (val << 14);
2396 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2397 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2398
2399 if (type < 3) {
2400 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2401 (type + 1) << 4);
2402 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2403 (type + 1) << 4);
2404 }
2405
2406 if (code == 0) {
2407 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2408 if (type < 3) {
2409 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2410 ~(B43_NPHY_RFCTL_CMD_RXEN |
2411 B43_NPHY_RFCTL_CMD_CORESEL));
2412 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2413 ~(0x1 << 12 |
2414 0x1 << 5 |
2415 0x1 << 1 |
2416 0x1));
2417 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2418 ~B43_NPHY_RFCTL_CMD_START);
2419 udelay(20);
2420 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2421 }
2422 } else {
2423 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2424 if (type < 3) {
2425 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2426 ~(B43_NPHY_RFCTL_CMD_RXEN |
2427 B43_NPHY_RFCTL_CMD_CORESEL),
2428 (B43_NPHY_RFCTL_CMD_RXEN |
2429 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2430 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2431 (0x1 << 12 |
2432 0x1 << 5 |
2433 0x1 << 1 |
2434 0x1));
2435 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2436 B43_NPHY_RFCTL_CMD_START);
2437 udelay(20);
2438 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2439 }
2440 }
2441}
2442
2443static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2444{
2445 u8 i;
2446 u16 reg, val;
2447
2448 if (code == 0) {
2449 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2450 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2451 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2452 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2453 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2454 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2455 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2456 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2457 } else {
2458 for (i = 0; i < 2; i++) {
2459 if ((code == 1 && i == 1) || (code == 2 && !i))
2460 continue;
2461
2462 reg = (i == 0) ?
2463 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2464 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2465
2466 if (type < 3) {
2467 reg = (i == 0) ?
2468 B43_NPHY_AFECTL_C1 :
2469 B43_NPHY_AFECTL_C2;
2470 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2471
2472 reg = (i == 0) ?
2473 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2474 B43_NPHY_RFCTL_LUT_TRSW_UP2;
2475 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2476
2477 if (type == 0)
2478 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2479 else if (type == 1)
2480 val = 16;
2481 else
2482 val = 32;
2483 b43_phy_set(dev, reg, val);
2484
2485 reg = (i == 0) ?
2486 B43_NPHY_TXF_40CO_B1S0 :
2487 B43_NPHY_TXF_40CO_B32S1;
2488 b43_phy_set(dev, reg, 0x0020);
2489 } else {
2490 if (type == 6)
2491 val = 0x0100;
2492 else if (type == 3)
2493 val = 0x0200;
2494 else
2495 val = 0x0300;
2496
2497 reg = (i == 0) ?
2498 B43_NPHY_AFECTL_C1 :
2499 B43_NPHY_AFECTL_C2;
2500
2501 b43_phy_maskset(dev, reg, 0xFCFF, val);
2502 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2503
2504 if (type != 3 && type != 6) {
2505 enum ieee80211_band band =
2506 b43_current_band(dev->wl);
2507
2508 if (b43_nphy_ipa(dev))
2509 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2510 else
2511 val = 0x11;
2512 reg = (i == 0) ? 0x2000 : 0x3000;
2513 reg |= B2055_PADDRV;
2514 b43_radio_write16(dev, reg, val);
2515
2516 reg = (i == 0) ?
2517 B43_NPHY_AFECTL_OVER1 :
2518 B43_NPHY_AFECTL_OVER;
2519 b43_phy_set(dev, reg, 0x0200);
2520 }
2521 }
2522 }
2523 }
2524}
2525
2526/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2527static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2528{
2529 if (dev->phy.rev >= 3)
2530 b43_nphy_rev3_rssi_select(dev, code, type);
2531 else
2532 b43_nphy_rev2_rssi_select(dev, code, type);
2533}
2534
2535/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ 2539/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2536static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) 2540static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2537{ 2541{
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 10:31:26 -0400