diff options
| author | Rafał Miłecki <zajec5@gmail.com> | 2010-01-15 07:36:43 -0500 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-01-15 17:05:33 -0500 |
| commit | 4a933c8566da3e2b164ea74b1632bf2f43c8ee9b (patch) | |
| tree | 4b1d475c326a988058653bf11d74cf6763645027 /drivers | |
| parent | 0988a7a1a98300e90a6613b33738e07cdf8ce786 (diff) | |
b43: N-PHY: update CCA reset
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/wireless/b43/phy_n.c | 30 |
1 files changed, 23 insertions, 7 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c index c16c98538f65..c9d2b7738aef 100644 --- a/drivers/net/wireless/b43/phy_n.c +++ b/drivers/net/wireless/b43/phy_n.c | |||
| @@ -343,18 +343,34 @@ static void b43_nphy_workarounds(struct b43_wldev *dev) | |||
| 343 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); | 343 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); |
| 344 | } | 344 | } |
| 345 | 345 | ||
| 346 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ | ||
| 347 | static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force) | ||
| 348 | { | ||
| 349 | u32 tmslow; | ||
| 350 | |||
| 351 | if (dev->phy.type != B43_PHYTYPE_N) | ||
| 352 | return; | ||
| 353 | |||
| 354 | tmslow = ssb_read32(dev->dev, SSB_TMSLOW); | ||
| 355 | if (force) | ||
| 356 | tmslow |= SSB_TMSLOW_FGC; | ||
| 357 | else | ||
| 358 | tmslow &= ~SSB_TMSLOW_FGC; | ||
| 359 | ssb_write32(dev->dev, SSB_TMSLOW, tmslow); | ||
| 360 | } | ||
| 361 | |||
| 362 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ | ||
| 346 | static void b43_nphy_reset_cca(struct b43_wldev *dev) | 363 | static void b43_nphy_reset_cca(struct b43_wldev *dev) |
| 347 | { | 364 | { |
| 348 | u16 bbcfg; | 365 | u16 bbcfg; |
| 349 | 366 | ||
| 350 | ssb_write32(dev->dev, SSB_TMSLOW, | 367 | b43_nphy_bmac_clock_fgc(dev, 1); |
| 351 | ssb_read32(dev->dev, SSB_TMSLOW) | SSB_TMSLOW_FGC); | ||
| 352 | bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); | 368 | bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); |
| 353 | b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA); | 369 | b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); |
| 354 | b43_phy_write(dev, B43_NPHY_BBCFG, | 370 | udelay(1); |
| 355 | bbcfg & ~B43_NPHY_BBCFG_RSTCCA); | 371 | b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); |
| 356 | ssb_write32(dev->dev, SSB_TMSLOW, | 372 | b43_nphy_bmac_clock_fgc(dev, 0); |
| 357 | ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC); | 373 | /* TODO: N PHY Force RF Seq with argument 2 */ |
| 358 | } | 374 | } |
| 359 | 375 | ||
| 360 | enum b43_nphy_rf_sequence { | 376 | enum b43_nphy_rf_sequence { |
