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authorYauheni Kaliuta <yauheni.kaliuta@nokia.com>2011-06-08 10:12:02 -0400
committerFelipe Balbi <balbi@ti.com>2011-06-09 05:01:03 -0400
commit4858f06e7d92ed2ebdb29ccbc079c127e675a89c (patch)
tree6fe442179b78f4968de1a5180d0bad6b439733be /drivers
parent72887c8644384c0cc43b9298ae0659de383f2e9c (diff)
usb: musb: gadget: clear TXPKTRDY flag when set FLUSHFIFO
Fixes mis-use of MUSB's hardware feature where it won't flush FIFOs when TXPKTRDY flag was set before and we are flushing setting both FLUSHFIFO and TXPKTRDY. In other words, we need to ensure that when we try to flush FIFOs, we don't accidentaly set TXPKTRDY bit too due to a read-back of the register. The MUSB Programming Guide says "May be set simultaneously with TxPktRdy to abort the packet that is currently being loaded into the FIFO". This is a situation where TXPKTRDY hasn't been set yet, but some data already loaded into the fifo. It looks, that if TXPKTRDY has been set before, and there is no loading in progress, but we set FLUSHFIFO with the TXPKTRDY, controller tries to use the same logic to abort loading and as the result just does nothing (because there is no packet been loaded currently) Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@nokia.com> [ balbi@ti.com : fixed one whitespace git complained about improved the commit log slightly ] Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/musb/musb_gadget.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 0a50a35e1853..6aeb363e63e7 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -1524,6 +1524,12 @@ static void musb_gadget_fifo_flush(struct usb_ep *ep)
1524 csr = musb_readw(epio, MUSB_TXCSR); 1524 csr = musb_readw(epio, MUSB_TXCSR);
1525 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1525 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1526 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; 1526 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1527 /*
1528 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1529 * to interrupt current FIFO loading, but not flushing
1530 * the already loaded ones.
1531 */
1532 csr &= ~MUSB_TXCSR_TXPKTRDY;
1527 musb_writew(epio, MUSB_TXCSR, csr); 1533 musb_writew(epio, MUSB_TXCSR, csr);
1528 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1534 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1529 musb_writew(epio, MUSB_TXCSR, csr); 1535 musb_writew(epio, MUSB_TXCSR, csr);