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authorJens Taprogge <jens.taprogge@taprogge.org>2012-09-12 08:55:27 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-09-12 12:54:15 -0400
commit459e6d7c93d47af0c0829b97bb17239eae79e3d6 (patch)
tree91051540fbda5bf224d398bfc82a29a7e41861b3 /drivers
parent70a32811e5d1c3a48d99088065ef74367221cde3 (diff)
Staging: ipack/devices/ipoctal: Directly use ioread/iowrite function.
Signed-off-by: Jens Taprogge <jens.taprogge@taprogge.org> Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/ipack/devices/ipoctal.c151
1 files changed, 41 insertions, 110 deletions
diff --git a/drivers/staging/ipack/devices/ipoctal.c b/drivers/staging/ipack/devices/ipoctal.c
index 9ab0e8082565..c963456ad8b7 100644
--- a/drivers/staging/ipack/devices/ipoctal.c
+++ b/drivers/staging/ipack/devices/ipoctal.c
@@ -56,26 +56,6 @@ struct ipoctal {
56/* Linked list to save the registered devices */ 56/* Linked list to save the registered devices */
57static LIST_HEAD(ipoctal_list); 57static LIST_HEAD(ipoctal_list);
58 58
59static inline void ipoctal_write_io_reg(struct ipoctal *ipoctal,
60 u8 __iomem *dest,
61 u8 value)
62{
63 iowrite8(value, dest);
64}
65
66static inline void ipoctal_write_cr_cmd(struct ipoctal *ipoctal,
67 u8 __iomem *dest,
68 u8 value)
69{
70 ipoctal_write_io_reg(ipoctal, dest, value);
71}
72
73static inline unsigned char ipoctal_read_io_reg(struct ipoctal *ipoctal,
74 u8 __iomem *src)
75{
76 return ioread8(src);
77}
78
79static struct ipoctal *ipoctal_find_board(struct tty_struct *tty) 59static struct ipoctal *ipoctal_find_board(struct tty_struct *tty)
80{ 60{
81 struct ipoctal *p; 61 struct ipoctal *p;
@@ -102,8 +82,7 @@ static int ipoctal_port_activate(struct tty_port *port, struct tty_struct *tty)
102 } 82 }
103 channel = &ipoctal->channel[tty->index]; 83 channel = &ipoctal->channel[tty->index];
104 84
105 ipoctal_write_io_reg(ipoctal, &channel->regs->w.cr, 85 iowrite8(CR_ENABLE_RX, &channel->regs->w.cr);
106 CR_ENABLE_RX);
107 return 0; 86 return 0;
108} 87}
109 88
@@ -216,10 +195,8 @@ static int ipoctal_irq_handler(void *arg)
216 * The HW is organized in pair of channels. 195 * The HW is organized in pair of channels.
217 * See which register we need to read from 196 * See which register we need to read from
218 */ 197 */
219 isr = ipoctal_read_io_reg(ipoctal, 198 isr = ioread8(&channel->block_regs->r.isr);
220 &channel->block_regs->r.isr); 199 sr = ioread8(&channel->regs->r.sr);
221 sr = ipoctal_read_io_reg(ipoctal,
222 &channel->regs->r.sr);
223 200
224 if ((ichannel % 2) == 1) { 201 if ((ichannel % 2) == 1) {
225 isr_tx_rdy = isr & ISR_TxRDY_B; 202 isr_tx_rdy = isr & ISR_TxRDY_B;
@@ -235,30 +212,21 @@ static int ipoctal_irq_handler(void *arg)
235 if ((ipoctal->board_id == IPACK1_DEVICE_ID_SBS_OCTAL_485) && 212 if ((ipoctal->board_id == IPACK1_DEVICE_ID_SBS_OCTAL_485) &&
236 (sr & SR_TX_EMPTY) && 213 (sr & SR_TX_EMPTY) &&
237 (channel->nb_bytes == 0)) { 214 (channel->nb_bytes == 0)) {
238 ipoctal_write_io_reg(ipoctal, 215 iowrite8(CR_DISABLE_TX, &channel->regs->w.cr);
239 &channel->regs->w.cr, 216 iowrite8(CR_CMD_NEGATE_RTSN, &channel->regs->w.cr);
240 CR_DISABLE_TX); 217 iowrite8(CR_ENABLE_RX, &channel->regs->w.cr);
241 ipoctal_write_cr_cmd(ipoctal,
242 &channel->regs->w.cr,
243 CR_CMD_NEGATE_RTSN);
244 ipoctal_write_io_reg(ipoctal,
245 &channel->regs->w.cr,
246 CR_ENABLE_RX);
247 ipoctal->write = 1; 218 ipoctal->write = 1;
248 wake_up_interruptible(&channel->queue); 219 wake_up_interruptible(&channel->queue);
249 } 220 }
250 221
251 /* RX data */ 222 /* RX data */
252 if (isr_rx_rdy && (sr & SR_RX_READY)) { 223 if (isr_rx_rdy && (sr & SR_RX_READY)) {
253 value = ipoctal_read_io_reg(ipoctal, 224 value = ioread8(&channel->regs->r.rhr);
254 &channel->regs->r.rhr);
255 flag = TTY_NORMAL; 225 flag = TTY_NORMAL;
256 226
257 /* Error: count statistics */ 227 /* Error: count statistics */
258 if (sr & SR_ERROR) { 228 if (sr & SR_ERROR) {
259 ipoctal_write_cr_cmd(ipoctal, 229 iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr);
260 &channel->regs->w.cr,
261 CR_CMD_RESET_ERR_STATUS);
262 230
263 if (sr & SR_OVERRUN_ERROR) { 231 if (sr & SR_OVERRUN_ERROR) {
264 channel->stats.overrun_err++; 232 channel->stats.overrun_err++;
@@ -292,9 +260,7 @@ static int ipoctal_irq_handler(void *arg)
292 } 260 }
293 261
294 value = channel->tty_port.xmit_buf[*pointer_write]; 262 value = channel->tty_port.xmit_buf[*pointer_write];
295 ipoctal_write_io_reg(ipoctal, 263 iowrite8(value, &channel->regs->w.thr);
296 &channel->regs->w.thr,
297 value);
298 channel->stats.tx++; 264 channel->stats.tx++;
299 channel->count_wr++; 265 channel->count_wr++;
300 (*pointer_write)++; 266 (*pointer_write)++;
@@ -405,37 +371,22 @@ static int ipoctal_inst_slot(struct ipoctal *ipoctal, unsigned int bus_nr,
405 channel->regs = chan_regs + i; 371 channel->regs = chan_regs + i;
406 channel->block_regs = block_regs + (i >> 1); 372 channel->block_regs = block_regs + (i >> 1);
407 373
408 ipoctal_write_io_reg(ipoctal, &channel->regs->w.cr, 374 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr);
409 CR_DISABLE_RX | CR_DISABLE_TX); 375 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr);
410 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr, 376 iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr);
411 CR_CMD_RESET_RX); 377 iowrite8(MR1_CHRL_8_BITS | MR1_ERROR_CHAR | MR1_RxINT_RxRDY,
412 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr, 378 &channel->regs->w.mr); /* mr1 */
413 CR_CMD_RESET_TX); 379 iowrite8(0, &channel->regs->w.mr); /* mr2 */
414 ipoctal_write_io_reg(ipoctal, 380 iowrite8(TX_CLK_9600 | RX_CLK_9600, &channel->regs->w.csr);
415 &channel->regs->w.mr,
416 MR1_CHRL_8_BITS | MR1_ERROR_CHAR |
417 MR1_RxINT_RxRDY); /* mr1 */
418 ipoctal_write_io_reg(ipoctal,
419 &channel->regs->w.mr,
420 0); /* mr2 */
421 ipoctal_write_io_reg(ipoctal,
422 &channel->regs->w.csr,
423 TX_CLK_9600 | RX_CLK_9600);
424 } 381 }
425 382
426 for (i = 0; i < IP_OCTAL_NB_BLOCKS; i++) { 383 for (i = 0; i < IP_OCTAL_NB_BLOCKS; i++) {
427 ipoctal_write_io_reg(ipoctal, 384 iowrite8(ACR_BRG_SET2, &block_regs[i].w.acr);
428 &block_regs[i].w.acr, 385 iowrite8(OPCR_MPP_OUTPUT | OPCR_MPOa_RTSN | OPCR_MPOb_RTSN,
429 ACR_BRG_SET2); 386 &block_regs[i].w.opcr);
430 ipoctal_write_io_reg(ipoctal, 387 iowrite8(IMR_TxRDY_A | IMR_RxRDY_FFULL_A | IMR_DELTA_BREAK_A |
431 &block_regs[i].w.opcr, 388 IMR_TxRDY_B | IMR_RxRDY_FFULL_B | IMR_DELTA_BREAK_B,
432 OPCR_MPP_OUTPUT | OPCR_MPOa_RTSN | 389 &block_regs[i].w.imr);
433 OPCR_MPOb_RTSN);
434 ipoctal_write_io_reg(ipoctal,
435 &block_regs[i].w.imr,
436 IMR_TxRDY_A | IMR_RxRDY_FFULL_A |
437 IMR_DELTA_BREAK_A | IMR_TxRDY_B |
438 IMR_RxRDY_FFULL_B | IMR_DELTA_BREAK_B);
439 } 390 }
440 391
441 /* 392 /*
@@ -504,8 +455,7 @@ static int ipoctal_inst_slot(struct ipoctal *ipoctal, unsigned int bus_nr,
504 * Enable again the RX. TX will be enabled when 455 * Enable again the RX. TX will be enabled when
505 * there is something to send 456 * there is something to send
506 */ 457 */
507 ipoctal_write_io_reg(ipoctal, &channel->regs->w.cr, 458 iowrite8(CR_ENABLE_RX, &channel->regs->w.cr);
508 CR_ENABLE_RX);
509 } 459 }
510 460
511 return 0; 461 return 0;
@@ -553,25 +503,17 @@ static int ipoctal_write(struct ipoctal *ipoctal, unsigned int ichannel,
553 503
554 /* As the IP-OCTAL 485 only supports half duplex, do it manually */ 504 /* As the IP-OCTAL 485 only supports half duplex, do it manually */
555 if (ipoctal->board_id == IPACK1_DEVICE_ID_SBS_OCTAL_485) { 505 if (ipoctal->board_id == IPACK1_DEVICE_ID_SBS_OCTAL_485) {
556 ipoctal_write_io_reg(ipoctal, 506 iowrite8(CR_DISABLE_RX, &channel->regs->w.cr);
557 &channel->regs->w.cr, 507 iowrite8(CR_CMD_ASSERT_RTSN, &channel->regs->w.cr);
558 CR_DISABLE_RX);
559 ipoctal_write_cr_cmd(ipoctal,
560 &channel->regs->w.cr,
561 CR_CMD_ASSERT_RTSN);
562 } 508 }
563 509
564 /* 510 /*
565 * Send a packet and then disable TX to avoid failure after several send 511 * Send a packet and then disable TX to avoid failure after several send
566 * operations 512 * operations
567 */ 513 */
568 ipoctal_write_io_reg(ipoctal, 514 iowrite8(CR_ENABLE_TX, &channel->regs->w.cr);
569 &channel->regs->w.cr,
570 CR_ENABLE_TX);
571 wait_event_interruptible(channel->queue, ipoctal->write); 515 wait_event_interruptible(channel->queue, ipoctal->write);
572 ipoctal_write_io_reg(ipoctal, 516 iowrite8(CR_DISABLE_TX, &channel->regs->w.cr);
573 &channel->regs->w.cr,
574 CR_DISABLE_TX);
575 517
576 ipoctal->write = 0; 518 ipoctal->write = 0;
577 return channel->count_wr; 519 return channel->count_wr;
@@ -615,16 +557,11 @@ static void ipoctal_set_termios(struct tty_struct *tty,
615 cflag = tty->termios->c_cflag; 557 cflag = tty->termios->c_cflag;
616 558
617 /* Disable and reset everything before change the setup */ 559 /* Disable and reset everything before change the setup */
618 ipoctal_write_io_reg(ipoctal, &channel->regs->w.cr, 560 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr);
619 CR_DISABLE_RX | CR_DISABLE_TX); 561 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr);
620 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr, 562 iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr);
621 CR_CMD_RESET_RX); 563 iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr);
622 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr, 564 iowrite8(CR_CMD_RESET_MR, &channel->regs->w.cr);
623 CR_CMD_RESET_TX);
624 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr,
625 CR_CMD_RESET_ERR_STATUS);
626 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr,
627 CR_CMD_RESET_MR);
628 565
629 /* Set Bits per chars */ 566 /* Set Bits per chars */
630 switch (cflag & CSIZE) { 567 switch (cflag & CSIZE) {
@@ -737,13 +674,12 @@ static void ipoctal_set_termios(struct tty_struct *tty,
737 mr1 |= MR1_RxINT_RxRDY; 674 mr1 |= MR1_RxINT_RxRDY;
738 675
739 /* Write the control registers */ 676 /* Write the control registers */
740 ipoctal_write_io_reg(ipoctal, &channel->regs->w.mr, mr1); 677 iowrite8(mr1, &channel->regs->w.mr);
741 ipoctal_write_io_reg(ipoctal, &channel->regs->w.mr, mr2); 678 iowrite8(mr2, &channel->regs->w.mr);
742 ipoctal_write_io_reg(ipoctal, &channel->regs->w.csr, csr); 679 iowrite8(csr, &channel->regs->w.csr);
743 680
744 /* Enable again the RX */ 681 /* Enable again the RX */
745 ipoctal_write_io_reg(ipoctal, &channel->regs->w.cr, 682 iowrite8(CR_ENABLE_RX, &channel->regs->w.cr);
746 CR_ENABLE_RX);
747} 683}
748 684
749static void ipoctal_hangup(struct tty_struct *tty) 685static void ipoctal_hangup(struct tty_struct *tty)
@@ -763,16 +699,11 @@ static void ipoctal_hangup(struct tty_struct *tty)
763 699
764 tty_port_hangup(&channel->tty_port); 700 tty_port_hangup(&channel->tty_port);
765 701
766 ipoctal_write_io_reg(ipoctal, &channel->regs->w.cr, 702 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr);
767 CR_DISABLE_RX | CR_DISABLE_TX); 703 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr);
768 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr, 704 iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr);
769 CR_CMD_RESET_RX); 705 iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr);
770 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr, 706 iowrite8(CR_CMD_RESET_MR, &channel->regs->w.cr);
771 CR_CMD_RESET_TX);
772 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr,
773 CR_CMD_RESET_ERR_STATUS);
774 ipoctal_write_cr_cmd(ipoctal, &channel->regs->w.cr,
775 CR_CMD_RESET_MR);
776 707
777 clear_bit(ASYNCB_INITIALIZED, &channel->tty_port.flags); 708 clear_bit(ASYNCB_INITIALIZED, &channel->tty_port.flags);
778 wake_up_interruptible(&channel->tty_port.open_wait); 709 wake_up_interruptible(&channel->tty_port.open_wait);
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