diff options
| author | Bing Zhao <bzhao@marvell.com> | 2012-04-12 22:00:35 -0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2012-04-13 14:06:59 -0400 |
| commit | 428ca8a7065354877db63ceabfc493107686eebe (patch) | |
| tree | 3cfe306f4aeed323b99e77b3ec7558f34d005317 /drivers | |
| parent | 75600abf1991657580233570400009e85f861787 (diff) | |
mwifiex: update pcie8766 scratch register addresses
The scratch register addresses have been changed for newer chips.
Since the old chip was never shipped and it will not be supported
any more, just update register addresses to support the new chips.
Cc: <stable@vger.kernel.org> # 3.2.y, 3.3.y
Signed-off-by: Bing Zhao <bzhao@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/wireless/mwifiex/pcie.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/net/wireless/mwifiex/pcie.h b/drivers/net/wireless/mwifiex/pcie.h index 445ff21772e2..2f218f9a3fd3 100644 --- a/drivers/net/wireless/mwifiex/pcie.h +++ b/drivers/net/wireless/mwifiex/pcie.h | |||
| @@ -48,15 +48,15 @@ | |||
| 48 | #define PCIE_HOST_INT_STATUS_MASK 0xC3C | 48 | #define PCIE_HOST_INT_STATUS_MASK 0xC3C |
| 49 | #define PCIE_SCRATCH_2_REG 0xC40 | 49 | #define PCIE_SCRATCH_2_REG 0xC40 |
| 50 | #define PCIE_SCRATCH_3_REG 0xC44 | 50 | #define PCIE_SCRATCH_3_REG 0xC44 |
| 51 | #define PCIE_SCRATCH_4_REG 0xCC0 | 51 | #define PCIE_SCRATCH_4_REG 0xCD0 |
| 52 | #define PCIE_SCRATCH_5_REG 0xCC4 | 52 | #define PCIE_SCRATCH_5_REG 0xCD4 |
| 53 | #define PCIE_SCRATCH_6_REG 0xCC8 | 53 | #define PCIE_SCRATCH_6_REG 0xCD8 |
| 54 | #define PCIE_SCRATCH_7_REG 0xCCC | 54 | #define PCIE_SCRATCH_7_REG 0xCDC |
| 55 | #define PCIE_SCRATCH_8_REG 0xCD0 | 55 | #define PCIE_SCRATCH_8_REG 0xCE0 |
| 56 | #define PCIE_SCRATCH_9_REG 0xCD4 | 56 | #define PCIE_SCRATCH_9_REG 0xCE4 |
| 57 | #define PCIE_SCRATCH_10_REG 0xCD8 | 57 | #define PCIE_SCRATCH_10_REG 0xCE8 |
| 58 | #define PCIE_SCRATCH_11_REG 0xCDC | 58 | #define PCIE_SCRATCH_11_REG 0xCEC |
| 59 | #define PCIE_SCRATCH_12_REG 0xCE0 | 59 | #define PCIE_SCRATCH_12_REG 0xCF0 |
| 60 | 60 | ||
| 61 | #define CPU_INTR_DNLD_RDY BIT(0) | 61 | #define CPU_INTR_DNLD_RDY BIT(0) |
| 62 | #define CPU_INTR_DOOR_BELL BIT(1) | 62 | #define CPU_INTR_DOOR_BELL BIT(1) |