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authorGrant Likely <grant.likely@secretlab.ca>2012-03-28 16:55:04 -0400
committerGrant Likely <grant.likely@secretlab.ca>2012-04-10 16:20:55 -0400
commit3ffc9cebb65f6942cd912e33e60e1f09e497e208 (patch)
treebae0fa51490677ab2804b9de3ac9a93c29342020 /drivers
parent0034102808e0dbbf3a2394b82b1bb40b5778de9e (diff)
gpio/sodaville: Convert sodaville driver to new irqdomain API
The irqdomain api changed significantly in v3.4 which caused a build failure for this driver. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Hans J. Koch <hjk@linutronix.de> Cc: Torben Hohn <torbenh@linutronix.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpio/Kconfig2
-rw-r--r--drivers/gpio/gpio-sodaville.c23
2 files changed, 11 insertions, 14 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index edadbdad31d0..e03653d69357 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -430,7 +430,7 @@ config GPIO_ML_IOH
430 430
431config GPIO_SODAVILLE 431config GPIO_SODAVILLE
432 bool "Intel Sodaville GPIO support" 432 bool "Intel Sodaville GPIO support"
433 depends on X86 && PCI && OF && BROKEN 433 depends on X86 && PCI && OF
434 select GPIO_GENERIC 434 select GPIO_GENERIC
435 select GENERIC_IRQ_CHIP 435 select GENERIC_IRQ_CHIP
436 help 436 help
diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c
index 9ba15d31d242..031e5d24837d 100644
--- a/drivers/gpio/gpio-sodaville.c
+++ b/drivers/gpio/gpio-sodaville.c
@@ -41,7 +41,7 @@
41struct sdv_gpio_chip_data { 41struct sdv_gpio_chip_data {
42 int irq_base; 42 int irq_base;
43 void __iomem *gpio_pub_base; 43 void __iomem *gpio_pub_base;
44 struct irq_domain id; 44 struct irq_domain *id;
45 struct irq_chip_generic *gc; 45 struct irq_chip_generic *gc;
46 struct bgpio_chip bgpio; 46 struct bgpio_chip bgpio;
47}; 47};
@@ -51,10 +51,9 @@ static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
52 struct sdv_gpio_chip_data *sd = gc->private; 52 struct sdv_gpio_chip_data *sd = gc->private;
53 void __iomem *type_reg; 53 void __iomem *type_reg;
54 u32 irq_offs = d->irq - sd->irq_base;
55 u32 reg; 54 u32 reg;
56 55
57 if (irq_offs < 8) 56 if (d->hwirq < 8)
58 type_reg = sd->gpio_pub_base + GPIT1R0; 57 type_reg = sd->gpio_pub_base + GPIT1R0;
59 else 58 else
60 type_reg = sd->gpio_pub_base + GPIT1R1; 59 type_reg = sd->gpio_pub_base + GPIT1R1;
@@ -63,11 +62,11 @@ static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
63 62
64 switch (type) { 63 switch (type) {
65 case IRQ_TYPE_LEVEL_HIGH: 64 case IRQ_TYPE_LEVEL_HIGH:
66 reg &= ~BIT(4 * (irq_offs % 8)); 65 reg &= ~BIT(4 * (d->hwirq % 8));
67 break; 66 break;
68 67
69 case IRQ_TYPE_LEVEL_LOW: 68 case IRQ_TYPE_LEVEL_LOW:
70 reg |= BIT(4 * (irq_offs % 8)); 69 reg |= BIT(4 * (d->hwirq % 8));
71 break; 70 break;
72 71
73 default: 72 default:
@@ -91,7 +90,7 @@ static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
91 u32 irq_bit = __fls(irq_stat); 90 u32 irq_bit = __fls(irq_stat);
92 91
93 irq_stat &= ~BIT(irq_bit); 92 irq_stat &= ~BIT(irq_bit);
94 generic_handle_irq(sd->irq_base + irq_bit); 93 generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
95 } 94 }
96 95
97 return IRQ_HANDLED; 96 return IRQ_HANDLED;
@@ -127,7 +126,7 @@ static int sdv_xlate(struct irq_domain *h, struct device_node *node,
127} 126}
128 127
129static struct irq_domain_ops irq_domain_sdv_ops = { 128static struct irq_domain_ops irq_domain_sdv_ops = {
130 .dt_translate = sdv_xlate, 129 .xlate = sdv_xlate,
131}; 130};
132 131
133static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd, 132static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
@@ -149,10 +148,6 @@ static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
149 if (ret) 148 if (ret)
150 goto out_free_desc; 149 goto out_free_desc;
151 150
152 sd->id.irq_base = sd->irq_base;
153 sd->id.of_node = of_node_get(pdev->dev.of_node);
154 sd->id.ops = &irq_domain_sdv_ops;
155
156 /* 151 /*
157 * This gpio irq controller latches level irqs. Testing shows that if 152 * This gpio irq controller latches level irqs. Testing shows that if
158 * we unmask & ACK the IRQ before the source of the interrupt is gone 153 * we unmask & ACK the IRQ before the source of the interrupt is gone
@@ -179,7 +174,10 @@ static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
179 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 174 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
180 IRQ_LEVEL | IRQ_NOPROBE); 175 IRQ_LEVEL | IRQ_NOPROBE);
181 176
182 irq_domain_add(&sd->id); 177 sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
178 sd->irq_base, 0, &irq_domain_sdv_ops, sd);
179 if (!sd->id)
180 goto out_free_irq;
183 return 0; 181 return 0;
184out_free_irq: 182out_free_irq:
185 free_irq(pdev->irq, sd); 183 free_irq(pdev->irq, sd);
@@ -260,7 +258,6 @@ static void sdv_gpio_remove(struct pci_dev *pdev)
260{ 258{
261 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev); 259 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
262 260
263 irq_domain_del(&sd->id);
264 free_irq(pdev->irq, sd); 261 free_irq(pdev->irq, sd);
265 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS); 262 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
266 263