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authorMario Kleiner <mario.kleiner@tuebingen.mpg.de>2010-11-21 10:59:02 -0500
committerDave Airlie <airlied@redhat.com>2010-11-21 20:51:27 -0500
commit3e4ea7421f45966c93c8cbe81569e8dc93a58b87 (patch)
tree9a27cb7455aeed88a1ccaa0ec6d234b606c480f6 /drivers
parent6f34be50bd1bdd2ff3c955940e033a80d05f248a (diff)
drm/kms/radeon: Reorder vblank and pageflip interrupt handling.
In the vblank irq handler, calls to actual vblank handling, or at least drm_handle_vblank(), need to happen before calls to radeon_crtc_handle_flip(). Reason: The high precision pageflip timestamping and some other pageflip optimizations will need the updated vblank count and timestamps for the current vblank interval. These are calculated in drm_handle_vblank(), therefore it must go first. Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c8
-rw-r--r--drivers/gpu/drm/radeon/r100.c8
-rw-r--r--drivers/gpu/drm/radeon/r600.c8
-rw-r--r--drivers/gpu/drm/radeon/rs600.c8
4 files changed, 16 insertions, 16 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index df3f37243222..25e84379e7c6 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2398,13 +2398,13 @@ restart_ih:
2398 switch (src_data) { 2398 switch (src_data) {
2399 case 0: /* D1 vblank */ 2399 case 0: /* D1 vblank */
2400 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 2400 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2401 if (rdev->irq.pflip[0])
2402 radeon_crtc_handle_flip(rdev, 0);
2403 if (rdev->irq.crtc_vblank_int[0]) { 2401 if (rdev->irq.crtc_vblank_int[0]) {
2404 drm_handle_vblank(rdev->ddev, 0); 2402 drm_handle_vblank(rdev->ddev, 0);
2405 rdev->pm.vblank_sync = true; 2403 rdev->pm.vblank_sync = true;
2406 wake_up(&rdev->irq.vblank_queue); 2404 wake_up(&rdev->irq.vblank_queue);
2407 } 2405 }
2406 if (rdev->irq.pflip[0])
2407 radeon_crtc_handle_flip(rdev, 0);
2408 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 2408 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2409 DRM_DEBUG("IH: D1 vblank\n"); 2409 DRM_DEBUG("IH: D1 vblank\n");
2410 } 2410 }
@@ -2424,13 +2424,13 @@ restart_ih:
2424 switch (src_data) { 2424 switch (src_data) {
2425 case 0: /* D2 vblank */ 2425 case 0: /* D2 vblank */
2426 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 2426 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2427 if (rdev->irq.pflip[1])
2428 radeon_crtc_handle_flip(rdev, 1);
2429 if (rdev->irq.crtc_vblank_int[1]) { 2427 if (rdev->irq.crtc_vblank_int[1]) {
2430 drm_handle_vblank(rdev->ddev, 1); 2428 drm_handle_vblank(rdev->ddev, 1);
2431 rdev->pm.vblank_sync = true; 2429 rdev->pm.vblank_sync = true;
2432 wake_up(&rdev->irq.vblank_queue); 2430 wake_up(&rdev->irq.vblank_queue);
2433 } 2431 }
2432 if (rdev->irq.pflip[1])
2433 radeon_crtc_handle_flip(rdev, 1);
2434 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 2434 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2435 DRM_DEBUG("IH: D2 vblank\n"); 2435 DRM_DEBUG("IH: D2 vblank\n");
2436 } 2436 }
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index b2e29798a99d..2316f73db6c0 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -650,22 +650,22 @@ int r100_irq_process(struct radeon_device *rdev)
650 } 650 }
651 /* Vertical blank interrupts */ 651 /* Vertical blank interrupts */
652 if (status & RADEON_CRTC_VBLANK_STAT) { 652 if (status & RADEON_CRTC_VBLANK_STAT) {
653 if (rdev->irq.pflip[0])
654 radeon_crtc_handle_flip(rdev, 0);
655 if (rdev->irq.crtc_vblank_int[0]) { 653 if (rdev->irq.crtc_vblank_int[0]) {
656 drm_handle_vblank(rdev->ddev, 0); 654 drm_handle_vblank(rdev->ddev, 0);
657 rdev->pm.vblank_sync = true; 655 rdev->pm.vblank_sync = true;
658 wake_up(&rdev->irq.vblank_queue); 656 wake_up(&rdev->irq.vblank_queue);
659 } 657 }
658 if (rdev->irq.pflip[0])
659 radeon_crtc_handle_flip(rdev, 0);
660 } 660 }
661 if (status & RADEON_CRTC2_VBLANK_STAT) { 661 if (status & RADEON_CRTC2_VBLANK_STAT) {
662 if (rdev->irq.pflip[1])
663 radeon_crtc_handle_flip(rdev, 1);
664 if (rdev->irq.crtc_vblank_int[1]) { 662 if (rdev->irq.crtc_vblank_int[1]) {
665 drm_handle_vblank(rdev->ddev, 1); 663 drm_handle_vblank(rdev->ddev, 1);
666 rdev->pm.vblank_sync = true; 664 rdev->pm.vblank_sync = true;
667 wake_up(&rdev->irq.vblank_queue); 665 wake_up(&rdev->irq.vblank_queue);
668 } 666 }
667 if (rdev->irq.pflip[1])
668 radeon_crtc_handle_flip(rdev, 1);
669 } 669 }
670 if (status & RADEON_FP_DETECT_STAT) { 670 if (status & RADEON_FP_DETECT_STAT) {
671 queue_hotplug = true; 671 queue_hotplug = true;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 15b95724c408..7057b392e005 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3294,13 +3294,13 @@ restart_ih:
3294 switch (src_data) { 3294 switch (src_data) {
3295 case 0: /* D1 vblank */ 3295 case 0: /* D1 vblank */
3296 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 3296 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3297 if (rdev->irq.pflip[0])
3298 radeon_crtc_handle_flip(rdev, 0);
3299 if (rdev->irq.crtc_vblank_int[0]) { 3297 if (rdev->irq.crtc_vblank_int[0]) {
3300 drm_handle_vblank(rdev->ddev, 0); 3298 drm_handle_vblank(rdev->ddev, 0);
3301 rdev->pm.vblank_sync = true; 3299 rdev->pm.vblank_sync = true;
3302 wake_up(&rdev->irq.vblank_queue); 3300 wake_up(&rdev->irq.vblank_queue);
3303 } 3301 }
3302 if (rdev->irq.pflip[0])
3303 radeon_crtc_handle_flip(rdev, 0);
3304 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3304 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3305 DRM_DEBUG("IH: D1 vblank\n"); 3305 DRM_DEBUG("IH: D1 vblank\n");
3306 } 3306 }
@@ -3320,13 +3320,13 @@ restart_ih:
3320 switch (src_data) { 3320 switch (src_data) {
3321 case 0: /* D2 vblank */ 3321 case 0: /* D2 vblank */
3322 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 3322 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3323 if (rdev->irq.pflip[1])
3324 radeon_crtc_handle_flip(rdev, 1);
3325 if (rdev->irq.crtc_vblank_int[1]) { 3323 if (rdev->irq.crtc_vblank_int[1]) {
3326 drm_handle_vblank(rdev->ddev, 1); 3324 drm_handle_vblank(rdev->ddev, 1);
3327 rdev->pm.vblank_sync = true; 3325 rdev->pm.vblank_sync = true;
3328 wake_up(&rdev->irq.vblank_queue); 3326 wake_up(&rdev->irq.vblank_queue);
3329 } 3327 }
3328 if (rdev->irq.pflip[1])
3329 radeon_crtc_handle_flip(rdev, 1);
3330 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 3330 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3331 DRM_DEBUG("IH: D2 vblank\n"); 3331 DRM_DEBUG("IH: D2 vblank\n");
3332 } 3332 }
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 683652bea17c..9a85b1614c86 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -662,22 +662,22 @@ int rs600_irq_process(struct radeon_device *rdev)
662 } 662 }
663 /* Vertical blank interrupts */ 663 /* Vertical blank interrupts */
664 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 664 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
665 if (rdev->irq.pflip[0])
666 radeon_crtc_handle_flip(rdev, 0);
667 if (rdev->irq.crtc_vblank_int[0]) { 665 if (rdev->irq.crtc_vblank_int[0]) {
668 drm_handle_vblank(rdev->ddev, 0); 666 drm_handle_vblank(rdev->ddev, 0);
669 rdev->pm.vblank_sync = true; 667 rdev->pm.vblank_sync = true;
670 wake_up(&rdev->irq.vblank_queue); 668 wake_up(&rdev->irq.vblank_queue);
671 } 669 }
670 if (rdev->irq.pflip[0])
671 radeon_crtc_handle_flip(rdev, 0);
672 } 672 }
673 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 673 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
674 if (rdev->irq.pflip[1])
675 radeon_crtc_handle_flip(rdev, 1);
676 if (rdev->irq.crtc_vblank_int[1]) { 674 if (rdev->irq.crtc_vblank_int[1]) {
677 drm_handle_vblank(rdev->ddev, 1); 675 drm_handle_vblank(rdev->ddev, 1);
678 rdev->pm.vblank_sync = true; 676 rdev->pm.vblank_sync = true;
679 wake_up(&rdev->irq.vblank_queue); 677 wake_up(&rdev->irq.vblank_queue);
680 } 678 }
679 if (rdev->irq.pflip[1])
680 radeon_crtc_handle_flip(rdev, 1);
681 } 681 }
682 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 682 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
683 queue_hotplug = true; 683 queue_hotplug = true;