drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800

We care about the upper 32 bits here so we have to use 1ULL instead of 1
to avoid a shift wrapping bug.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 64dca260912f..fe67415c3e17 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
                         } while (!tpcnr[gpc]);
                         tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
 
-                        tpc_set |= 1 << ((gpc * 8) + tpc);
+                        tpc_set |= 1ULL << ((gpc * 8) + tpc);
                 }
 
                 nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));