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authorPatrick Boettcher <pb@linuxtv.org>2005-07-07 20:57:48 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-07 21:23:56 -0400
commit2819639b5630cd26d399ee0481be9a752280cf4d (patch)
treee742b0c098755591ae1cf864dbe71c0e7fd9110f /drivers
parent178c6efcd8435644028bf3f079c1e82107e72dfd (diff)
[PATCH] dvb: flexcop: add big endian register definitions
Add big-endian register definitions for running on a PowerPC. (Thanks to Paavo Hartikainen for testing.) Signed-off-by: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Johannes Stezenbach <js@linuxtv.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/dvb/b2c2/flexcop-reg.h548
-rw-r--r--drivers/media/dvb/b2c2/flexcop_ibi_value_be.h451
-rw-r--r--drivers/media/dvb/b2c2/flexcop_ibi_value_le.h451
3 files changed, 909 insertions, 541 deletions
diff --git a/drivers/media/dvb/b2c2/flexcop-reg.h b/drivers/media/dvb/b2c2/flexcop-reg.h
index 75b50f21afe6..4ae1eb5bfe98 100644
--- a/drivers/media/dvb/b2c2/flexcop-reg.h
+++ b/drivers/media/dvb/b2c2/flexcop-reg.h
@@ -36,555 +36,21 @@ typedef enum {
36extern const char *flexcop_device_names[]; 36extern const char *flexcop_device_names[];
37 37
38/* FlexCop IBI Registers */ 38/* FlexCop IBI Registers */
39#if defined(__LITTLE_ENDIAN)
40 #include "flexcop_ibi_value_le.h"
41#elif defined(__BIG_ENDIAN)
42 #include "flexcop_ibi_value_be.h"
43#else
44 #error no endian defined
45#endif
39 46
40/* flexcop_ibi_reg - a huge union representing the register structure */
41typedef union {
42 u32 raw;
43
44/* DMA 0x000 to 0x01c
45 * DMA1 0x000 to 0x00c
46 * DMA2 0x010 to 0x01c
47 */
48 struct {
49 u32 dma_0start : 1; /* set: data will be delivered to dma1_address0 */
50 u32 dma_0No_update : 1; /* set: dma1_cur_address will be updated, unset: no update */
51 u32 dma_address0 :30; /* physical/virtual host memory address0 DMA */
52 } dma_0x0;
53
54 struct {
55 u32 DMA_maxpackets : 8; /* (remapped) PCI DMA1 Packet Count Interrupt. This variable
56 is able to be read and written while bit(1) of register
57 0x00c (remap_enable) is set. This variable represents
58 the number of packets that will be transmitted to the PCI
59 host using PCI DMA1 before an interrupt to the PCI is
60 asserted. This functionality may be enabled using bit(20)
61 of register 0x208. N=0 disables the IRQ. */
62 u32 dma_addr_size :24; /* size of memory buffer in DWORDs (bytesize / 4) for DMA */
63 } dma_0x4_remap;
64
65 struct {
66 u32 dma1timer : 7; /* reading PCI DMA1 timer ... when remap_enable is 0 */
67 u32 unused : 1;
68 u32 dma_addr_size :24;
69 } dma_0x4_read;
70
71 struct {
72 u32 unused : 1;
73 u32 dmatimer : 7; /* writing PCI DMA1 timer ... when remap_enable is 0 */
74 u32 dma_addr_size :24;
75 } dma_0x4_write;
76
77 struct {
78 u32 unused : 2;
79 u32 dma_cur_addr :30; /* current physical host memory address pointer for DMA */
80 } dma_0x8;
81
82 struct {
83 u32 dma_1start : 1; /* set: data will be delivered to dma_address1, when dma_address0 is full */
84 u32 remap_enable : 1; /* remap enable for 0x0x4(7:0) */
85 u32 dma_address1 :30; /* Physical/virtual address 1 on DMA */
86 } dma_0xc;
87
88/* Two-wire Serial Master and Clock 0x100-0x110 */
89 struct {
90// u32 slave_transmitter : 1; /* ???*/
91 u32 chipaddr : 7; /* two-line serial address of the target slave */
92 u32 reserved1 : 1;
93 u32 baseaddr : 8; /* address of the location of the read/write operation */
94 u32 data1_reg : 8; /* first byte in two-line serial read/write operation */
95 u32 working_start : 1; /* when doing a write operation this indicator is 0 when ready
96 * set to 1 when doing a write operation */
97 u32 twoWS_rw : 1; /* read/write indicator (1 = read, 0 write) */
98 u32 total_bytes : 2; /* number of data bytes in each two-line serial transaction (0 = 1 byte, 11 = 4byte)*/
99 u32 twoWS_port_reg : 2; /* port selection: 01 - Front End/Demod, 10 - EEPROM, 11 - Tuner */
100 u32 no_base_addr_ack_error : 1; /* writing: write-req: frame is produced w/o baseaddr, read-req: read-cycles w/o
101 * preceding address assignment write frame
102 * ACK_ERROR = 1 when no ACK from slave in the last transaction */
103 u32 st_done : 1; /* indicator for transaction is done */
104 } tw_sm_c_100;
105
106 struct {
107 u32 data2_reg : 8; /* 2nd data byte */
108 u32 data3_reg : 8; /* 3rd data byte */
109 u32 data4_reg : 8; /* 4th data byte */
110 u32 exlicit_stops : 1; /* when set, transactions are produced w/o trailing STOP flag, then send isolated STOP flags */
111 u32 force_stop : 1; /* isolated stop flag */
112 u32 unused : 6;
113 } tw_sm_c_104;
114
115/* Clock. The register allows the FCIII to convert an incoming Master clock
116 * (MCLK) signal into a lower frequency clock through the use of a LowCounter
117 * (TLO) and a High- Counter (THI). The time counts for THI and TLO are
118 * measured in MCLK; each count represents 4 MCLK input clock cycles.
119 *
120 * The default output for port #1 is set for Front End Demod communication. (0x108)
121 * The default output for port #2 is set for EEPROM communication. (0x10c)
122 * The default output for port #3 is set for Tuner communication. (0x110)
123 */
124 struct {
125 u32 thi1 : 6; /* Thi for port #1 (def: 100110b; 38) */
126 u32 reserved1 : 2;
127 u32 tlo1 : 5; /* Tlo for port #1 (def: 11100b; 28) */
128 u32 reserved2 :19;
129 } tw_sm_c_108;
130
131 struct {
132 u32 thi1 : 6; /* Thi for port #2 (def: 111001b; 57) */
133 u32 reserved1 : 2;
134 u32 tlo1 : 5; /* Tlo for port #2 (def: 11100b; 28) */
135 u32 reserved2 :19;
136 } tw_sm_c_10c;
137
138 struct {
139 u32 thi1 : 6; /* Thi for port #3 (def: 111001b; 57) */
140 u32 reserved1 : 2;
141 u32 tlo1 : 5; /* Tlo for port #3 (def: 11100b; 28) */
142 u32 reserved2 :19;
143 } tw_sm_c_110;
144
145/* LNB Switch Frequency 0x200
146 * Clock that creates the LNB switch tone. The default is set to have a fixed
147 * low output (not oscillating) to the LNB_CTL line.
148 */
149 struct {
150 u32 LNB_CTLHighCount_sig :15; /* It is the number of pre-scaled clock cycles that will be low. */
151 u32 LNB_CTLLowCount_sig :15; /* For example, to obtain a 22KHz output given a 45 Mhz Master
152 Clock signal (MCLK), set PreScalar=01 and LowCounter value to 0x1ff. */
153 u32 LNB_CTLPrescaler_sig : 2; /* pre-scaler divides MCLK: 00 (no division), 01 by 2, 10 by 4, 11 by 12 */
154 } lnb_switch_freq_200;
155
156/* ACPI, Peripheral Reset, LNB Polarity
157 * ACPI power conservation mode, LNB polarity selection (low or high voltage),
158 * and peripheral reset.
159 */
160 struct {
161 u32 ACPI1_sig : 1; /* turn of the power of tuner and LNB, not implemented in FCIII */
162 u32 ACPI3_sig : 1; /* turn of power of the complete satelite receiver board (except FCIII) */
163 u32 LNB_L_H_sig : 1; /* low or high voltage for LNB. (0 = low, 1 = high) */
164 u32 Per_reset_sig : 1; /* misc. init reset (default: 1), to reset set to low and back to high */
165 u32 reserved :20;
166 u32 Rev_N_sig_revision_hi : 4;/* 0xc in case of FCIII */
167 u32 Rev_N_sig_reserved1 : 2;
168 u32 Rev_N_sig_caps : 1; /* if 1, FCIII has 32 PID- and MAC-filters and is capable of IP multicast */
169 u32 Rev_N_sig_reserved2 : 1;
170 } misc_204;
171
172/* Control and Status 0x208 to 0x21c */
173/* Gross enable and disable control */
174 struct {
175 u32 Stream1_filter_sig : 1; /* Stream1 PID filtering */
176 u32 Stream2_filter_sig : 1; /* Stream2 PID filtering */
177 u32 PCR_filter_sig : 1; /* PCR PID filter */
178 u32 PMT_filter_sig : 1; /* PMT PID filter */
179
180 u32 EMM_filter_sig : 1; /* EMM PID filter */
181 u32 ECM_filter_sig : 1; /* ECM PID filter */
182 u32 Null_filter_sig : 1; /* Filters null packets, PID=0x1fff. */
183 u32 Mask_filter_sig : 1; /* mask PID filter */
184
185 u32 WAN_Enable_sig : 1; /* WAN output line through V8 memory space is activated. */
186 u32 WAN_CA_Enable_sig : 1; /* not in FCIII */
187 u32 CA_Enable_sig : 1; /* not in FCIII */
188 u32 SMC_Enable_sig : 1; /* CI stream data (CAI) goes directly to the smart card intf (opposed IBI 0x600 or SC-cmd buf). */
189
190 u32 Per_CA_Enable_sig : 1; /* not in FCIII */
191 u32 Multi2_Enable_sig : 1; /* ? */
192 u32 MAC_filter_Mode_sig : 1; /* (MAC_filter_enable) Globally enables MAC filters for Net PID filteres. */
193 u32 Rcv_Data_sig : 1; /* PID filtering module enable. When this bit is a one, the PID filter will
194 examine and process packets according to all other (individual) PID
195 filtering controls. If it a zero, no packet processing of any kind will
196 take place. All data from the tuner will be thrown away. */
197
198 u32 DMA1_IRQ_Enable_sig : 1; /* When set, a DWORD counter is enabled on PCI DMA1 that asserts the PCI
199 * interrupt after the specified count for filling the buffer. */
200 u32 DMA1_Timer_Enable_sig : 1; /* When set, a timer is enabled on PCI DMA1 that asserts the PCI interrupt
201 after a specified amount of time. */
202 u32 DMA2_IRQ_Enable_sig : 1; /* same as DMA1_IRQ_Enable_sig but for DMA2 */
203 u32 DMA2_Timer_Enable_sig : 1; /* same as DMA1_Timer_Enable_sig but for DMA2 */
204
205 u32 DMA1_Size_IRQ_Enable_sig : 1; /* When set, a packet count detector is enabled on PCI DMA1 that asserts the PCI interrupt. */
206 u32 DMA2_Size_IRQ_Enable_sig : 1; /* When set, a packet count detector is enabled on PCI DMA2 that asserts the PCI interrupt. */
207 u32 Mailbox_from_V8_Enable_sig: 1; /* When set, writes to the mailbox register produce an interrupt to the
208 PCI host to indicate that mailbox data is available. */
209
210 u32 unused : 9;
211 } ctrl_208;
212
213/* General status. When a PCI interrupt occurs, this register is read to
214 * discover the reason for the interrupt.
215 */
216 struct {
217 u32 DMA1_IRQ_Status : 1; /* When set(1) the DMA1 counter had generated an IRQ. Read Only. */
218 u32 DMA1_Timer_Status : 1; /* When set(1) the DMA1 timer had generated an IRQ. Read Only. */
219 u32 DMA2_IRQ_Status : 1; /* When set(1) the DMA2 counter had generated an IRQ. Read Only. */
220 u32 DMA2_Timer_Status : 1; /* When set(1) the DMA2 timer had generated an IRQ. Read Only. */
221 u32 DMA1_Size_IRQ_Status : 1; /* (Read only). This register is read after an interrupt to */
222 u32 DMA2_Size_IRQ_Status : 1; /* find out why we had an IRQ. Reading this register will clear this bit. Packet count*/
223 u32 Mailbox_from_V8_Status_sig: 1; /* Same as above. Reading this register will clear this bit. */
224 u32 Data_receiver_error : 1; /* 1 indicate an error in the receiver Front End (Tuner module) */
225 u32 Continuity_error_flag : 1; /* 1 indicates a continuity error in the TS stream. */
226 u32 LLC_SNAP_FLAG_set : 1; /* 1 indicates that the LCC_SNAP_FLAG was set. */
227 u32 Transport_Error : 1; /* When set indicates that an unexpected packet was received. */
228 u32 reserved :21;
229 } irq_20c;
230
231
232/* Software reset register */
233 struct {
234 u32 reset_blocks : 8; /* Enabled when Block_reset_enable = 0xB2 and 0x208 bits 15:8 = 0x00.
235 Each bit location represents a 0x100 block of registers. Writing
236 a one in a bit location resets that block of registers and the logic
237 that it controls. */
238 u32 Block_reset_enable : 8; /* This variable is set to 0xB2 when the register is written. */
239 u32 Special_controls :16; /* Asserts Reset_V8 => 0xC258; Turns on pci encryption => 0xC25A;
240 Turns off pci encryption => 0xC259 Note: pci_encryption default
241 at power-up is ON. */
242 } sw_reset_210;
243
244 struct {
245 u32 vuart_oe_sig : 1; /* When clear, the V8 processor has sole control of the serial UART
246 (RS-232 Smart Card interface). When set, the IBI interface
247 defined by register 0x600 controls the serial UART. */
248 u32 v2WS_oe_sig : 1; /* When clear, the V8 processor has direct control of the Two-line
249 Serial Master EEPROM target. When set, the Two-line Serial Master
250 EEPROM target interface is controlled by IBI register 0x100. */
251 u32 halt_V8_sig : 1; /* When set, contiguous wait states are applied to the V8-space
252 bus masters. Once this signal is cleared, normal V8-space
253 operations resume. */
254 u32 section_pkg_enable_sig: 1; /* When set, this signal enables the front end translation circuitry
255 to process section packed transport streams. */
256 u32 s2p_sel_sig : 1; /* Serial to parallel conversion. When set, polarized transport data
257 within the FlexCop3 front end circuitry is converted from a serial
258 stream into parallel data before downstream processing otherwise
259 interprets the data. */
260 u32 unused1 : 3;
261 u32 polarity_PS_CLK_sig: 1; /* This signal is used to invert the input polarity of the tranport
262 stream CLOCK signal before any processing occurs on the transport
263 stream within FlexCop3. */
264 u32 polarity_PS_VALID_sig: 1; /* This signal is used to invert the input polarity of the tranport
265 stream VALID signal before any processing occurs on the transport
266 stream within FlexCop3. */
267 u32 polarity_PS_SYNC_sig: 1; /* This signal is used to invert the input polarity of the tranport
268 stream SYNC signal before any processing occurs on the transport
269 stream within FlexCop3. */
270 u32 polarity_PS_ERR_sig: 1; /* This signal is used to invert the input polarity of the tranport
271 stream ERROR signal before any processing occurs on the transport
272 stream within FlexCop3. */
273 u32 unused2 :20;
274 } misc_214;
275
276/* Mailbox from V8 to host */
277 struct {
278 u32 Mailbox_from_V8 :32; /* When this register is written by either the V8 processor or by an
279 end host, an interrupt is generated to the PCI host to indicate
280 that mailbox data is available. Reading register 20c will clear
281 the IRQ. */
282 } mbox_v8_to_host_218;
283
284/* Mailbox from host to v8 Mailbox_to_V8
285 * Mailbox_to_V8 mailbox storage register
286 * used to send messages from PCI to V8. Writing to this register will send an
287 * IRQ to the V8. Then it can read the data from here. Reading this register
288 * will clear the IRQ. If the V8 is halted and bit 31 of this register is set,
289 * then this register is used instead as a direct interface to access the
290 * V8space memory.
291 */
292 struct {
293 u32 sysramaccess_data : 8; /* Data byte written or read from the specified address in V8 SysRAM. */
294 u32 sysramaccess_addr :15; /* 15 bit address used to access V8 Sys-RAM. */
295 u32 unused : 7;
296 u32 sysramaccess_write: 1; /* Write flag used to latch data into the V8 SysRAM. */
297 u32 sysramaccess_busmuster: 1; /* Setting this bit when the V8 is halted at 0x214 Bit(2) allows
298 this IBI register interface to directly drive the V8-space memory. */
299 } mbox_host_to_v8_21c;
300
301
302/* PIDs, Translation Bit, SMC Filter Select 0x300 to 0x31c */
303 struct {
304 u32 Stream1_PID :13; /* Primary use is receiving Net data, so these 13 bits normally
305 hold the PID value for the desired network stream. */
306 u32 Stream1_trans : 1; /* When set, Net translation will take place for Net data ferried in TS packets. */
307 u32 MAC_Multicast_filter : 1; /* When clear, multicast MAC filtering is not allowed for Stream1 and PID_n filters. */
308 u32 debug_flag_pid_saved : 1;
309 u32 Stream2_PID :13; /* 13 bits for Stream 2 PID filter value. General use. */
310 u32 Stream2_trans : 1; /* When set Tables/CAI translation will take place for the data ferried in
311 Stream2_PID TS packets. */
312 u32 debug_flag_write_status00 : 1;
313 u32 debug_fifo_problem : 1;
314 } pid_filter_300;
315
316 struct {
317 u32 PCR_PID :13; /* PCR stream PID filter value. Primary use is Program Clock Reference stream filtering. */
318 u32 PCR_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
319 u32 debug_overrun3 : 1;
320 u32 debug_overrun2 : 1;
321 u32 PMT_PID :13; /* stream PID filter value. Primary use is Program Management Table segment filtering. */
322 u32 PMT_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
323 u32 reserved : 2;
324 } pid_filter_304;
325
326 struct {
327 u32 EMM_PID :13; /* EMM PID filter value. Primary use is Entitlement Management Messaging for
328 conditional access-related data. */
329 u32 EMM_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
330 u32 EMM_filter_4 : 1; /* When set will pass only EMM data possessing the same ID code as the
331 first four bytes (32 bits) of the end-user s 6-byte Smart Card ID number Select */
332 u32 EMM_filter_6 : 1; /* When set will pass only EMM data possessing the same 6-byte code as the end-users
333 complete 6-byte Smart Card ID number. */
334 u32 ECM_PID :13; /* ECM PID filter value. Primary use is Entitlement Control Messaging for conditional
335 access-related data. */
336 u32 ECM_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
337 u32 reserved : 2;
338 } pid_filter_308;
339
340 struct {
341 u32 Group_PID :13; /* PID value for group filtering. */
342 u32 Group_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
343 u32 unused1 : 2;
344 u32 Group_mask :13; /* Mask value used in logical "and" equation that defines group filtering */
345 u32 unused2 : 3;
346 } pid_filter_30c_ext_ind_0_7;
347
348 struct {
349 u32 net_master_read :17;
350 u32 unused :15;
351 } pid_filter_30c_ext_ind_1;
352
353 struct {
354 u32 net_master_write :17;
355 u32 unused :15;
356 } pid_filter_30c_ext_ind_2;
357
358 struct {
359 u32 next_net_master_write :17;
360 u32 unused :15;
361 } pid_filter_30c_ext_ind_3;
362
363 struct {
364 u32 unused1 : 1;
365 u32 state_write :10;
366 u32 reserved1 : 6; /* default: 000100 */
367 u32 stack_read :10;
368 u32 reserved2 : 5; /* default: 00100 */
369 } pid_filter_30c_ext_ind_4;
370
371 struct {
372 u32 stack_cnt :10;
373 u32 unused :22;
374 } pid_filter_30c_ext_ind_5;
375
376 struct {
377 u32 pid_fsm_save_reg0 : 2;
378 u32 pid_fsm_save_reg1 : 2;
379 u32 pid_fsm_save_reg2 : 2;
380 u32 pid_fsm_save_reg3 : 2;
381 u32 pid_fsm_save_reg4 : 2;
382 u32 pid_fsm_save_reg300 : 2;
383 u32 write_status1 : 2;
384 u32 write_status4 : 2;
385 u32 data_size_reg :12;
386 u32 unused : 4;
387 } pid_filter_30c_ext_ind_6;
388
389 struct {
390 u32 index_reg : 5; /* (Index pointer) Points at an internal PIDn register. A binary code
391 representing one of 32 internal PIDn registers as well as its
392 corresponding internal MAC_lown register. */
393 u32 extra_index_reg : 3; /* This vector is used to select between sets of debug signals routed to register 0x30c. */
394 u32 AB_select : 1; /* Used in conjunction with 0x31c. read/write to the MAC_highA or MAC_highB register
395 0=MAC_highB register, 1=MAC_highA */
396 u32 pass_alltables : 1; /* 1=Net packets are not filtered against the Network Table ID found in register 0x400.
397 All types of networks (DVB, ATSC, ISDB) are passed. */
398 u32 unused :22;
399 } index_reg_310;
400
401 struct {
402 u32 PID :13; /* PID value */
403 u32 PID_trans : 1; /* translation will take place for packets filtered */
404 u32 PID_enable_bit : 1; /* When set this PID filter is enabled */
405 u32 reserved :17;
406 } pid_n_reg_314;
407
408 struct {
409 u32 A4_byte : 8;
410 u32 A5_byte : 8;
411 u32 A6_byte : 8;
412 u32 Enable_bit : 1; /* enabled (1) or disabled (1) */
413 u32 HighAB_bit : 1; /* use MAC_highA (1) or MAC_highB (0) as MSB */
414 u32 reserved : 6;
415 } mac_low_reg_318;
416
417 struct {
418 u32 A1_byte : 8;
419 u32 A2_byte : 8;
420 u32 A3_byte : 8;
421 u32 reserved : 8;
422 } mac_high_reg_31c;
423
424/* Table, SMCID,MACDestination Filters 0x400 to 0x41c */
425 struct {
426 u32 reserved :16;
427#define fc_data_Tag_ID_DVB 0x3e 47#define fc_data_Tag_ID_DVB 0x3e
428#define fc_data_Tag_ID_ATSC 0x3f 48#define fc_data_Tag_ID_ATSC 0x3f
429#define fc_data_Tag_ID_IDSB 0x8b 49#define fc_data_Tag_ID_IDSB 0x8b
430 u32 data_Tag_ID :16;
431 } data_tag_400;
432
433 struct {
434 u32 Card_IDbyte6 : 8;
435 u32 Card_IDbyte5 : 8;
436 u32 Card_IDbyte4 : 8;
437 u32 Card_IDbyte3 : 8;
438 } card_id_408;
439
440 struct {
441 u32 Card_IDbyte2 : 8;
442 u32 Card_IDbyte1 : 8;
443 } card_id_40c;
444
445 /* holding the unique mac address of the receiver which houses the FlexCopIII */
446 struct {
447 u32 MAC1 : 8;
448 u32 MAC2 : 8;
449 u32 MAC3 : 8;
450 u32 MAC6 : 8;
451 } mac_address_418;
452
453 struct {
454 u32 MAC7 : 8;
455 u32 MAC8 : 8;
456 u32 reserved : 16;
457 } mac_address_41c;
458
459 struct {
460 u32 transmitter_data_byte : 8;
461 u32 ReceiveDataReady : 1;
462 u32 ReceiveByteFrameError: 1;
463 u32 txbuffempty : 1;
464 u32 reserved :21;
465 } ci_600;
466
467 struct {
468 u32 pi_d : 8;
469 u32 pi_ha :20;
470 u32 pi_rw : 1;
471 u32 pi_component_reg : 3;
472 } pi_604;
473
474 struct {
475 u32 serialReset : 1;
476 u32 oncecycle_read : 1;
477 u32 Timer_Read_req : 1;
478 u32 Timer_Load_req : 1;
479 u32 timer_data : 7;
480 u32 unused : 1; /* ??? not mentioned in data book */
481 u32 Timer_addr : 5;
482 u32 reserved : 3;
483 u32 pcmcia_a_mod_pwr_n : 1;
484 u32 pcmcia_b_mod_pwr_n : 1;
485 u32 config_Done_stat : 1;
486 u32 config_Init_stat : 1;
487 u32 config_Prog_n : 1;
488 u32 config_wr_n : 1;
489 u32 config_cs_n : 1;
490 u32 config_cclk : 1;
491 u32 pi_CiMax_IRQ_n : 1;
492 u32 pi_timeout_status : 1;
493 u32 pi_wait_n : 1;
494 u32 pi_busy_n : 1;
495 } pi_608;
496 50
497 struct {
498 u32 PID :13;
499 u32 key_enable : 1;
500#define fc_key_code_default 0x1 51#define fc_key_code_default 0x1
501#define fc_key_code_even 0x2 52#define fc_key_code_even 0x2
502#define fc_key_code_odd 0x3 53#define fc_key_code_odd 0x3
503 u32 key_code : 2;
504 u32 key_array_col : 3;
505 u32 key_array_row : 5;
506 u32 dvb_en : 1; /* 0=TS bypasses the Descrambler */
507 u32 rw_flag : 1;
508 u32 reserved : 6;
509 } dvb_reg_60c;
510
511/* SRAM and Output Destination 0x700 to 0x714 */
512 struct {
513 u32 sram_addr :15;
514 u32 sram_rw : 1; /* 0=write, 1=read */
515 u32 sram_data : 8;
516 u32 sc_xfer_bit : 1;
517 u32 reserved1 : 3;
518 u32 oe_pin_reg : 1;
519 u32 ce_pin_reg : 1;
520 u32 reserved2 : 1;
521 u32 start_sram_ibi : 1;
522 } sram_ctrl_reg_700;
523
524 struct {
525 u32 net_addr_read :16;
526 u32 net_addr_write :16;
527 } net_buf_reg_704;
528
529 struct {
530 u32 cai_read :11;
531 u32 reserved1 : 5;
532 u32 cai_write :11;
533 u32 reserved2 : 6;
534 u32 cai_cnt : 4;
535 } cai_buf_reg_708;
536
537 struct {
538 u32 cao_read :11;
539 u32 reserved1 : 5;
540 u32 cap_write :11;
541 u32 reserved2 : 6;
542 u32 cao_cnt : 4;
543 } cao_buf_reg_70c;
544
545 struct {
546 u32 media_read :11;
547 u32 reserved1 : 5;
548 u32 media_write :11;
549 u32 reserved2 : 6;
550 u32 media_cnt : 4;
551 } media_buf_reg_710;
552
553 struct {
554 u32 NET_Dest : 2;
555 u32 CAI_Dest : 2;
556 u32 CAO_Dest : 2;
557 u32 MEDIA_Dest : 2;
558 u32 net_ovflow_error : 1;
559 u32 media_ovflow_error : 1;
560 u32 cai_ovflow_error : 1;
561 u32 cao_ovflow_error : 1;
562 u32 ctrl_usb_wan : 1;
563 u32 ctrl_sramdma : 1;
564 u32 ctrl_maximumfill : 1;
565 u32 reserved :17;
566 } sram_dest_reg_714;
567
568 struct {
569 u32 net_cnt :12;
570 u32 reserved1 : 4;
571 u32 net_addr_read : 1;
572 u32 reserved2 : 3;
573 u32 net_addr_write : 1;
574 u32 reserved3 :11;
575 } net_buf_reg_718;
576
577 struct {
578 u32 wan_speed_sig : 2;
579 u32 reserved1 : 6;
580 u32 wan_wait_state : 8;
581 u32 sram_chip : 2;
582 u32 sram_memmap : 2;
583 u32 reserved2 : 4;
584 u32 wan_pkt_frame : 4;
585 u32 reserved3 : 4;
586 } wan_ctrl_reg_71c;
587} flexcop_ibi_value;
588 54
589extern flexcop_ibi_value ibi_zero; 55extern flexcop_ibi_value ibi_zero;
590 56
diff --git a/drivers/media/dvb/b2c2/flexcop_ibi_value_be.h b/drivers/media/dvb/b2c2/flexcop_ibi_value_be.h
new file mode 100644
index 000000000000..bf3cb5a71fb4
--- /dev/null
+++ b/drivers/media/dvb/b2c2/flexcop_ibi_value_be.h
@@ -0,0 +1,451 @@
1/* This file is part of linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
2 *
3 * register descriptions
4 *
5 * see flexcop.c for copyright information.
6 */
7
8/* This file is automatically generated, do not edit things here. */
9#ifndef __FLEXCOP_IBI_VALUE_INCLUDED__
10#define __FLEXCOP_IBI_VALUE_INCLUDED__
11
12typedef union {
13 u32 raw;
14
15 struct {
16 u32 dma_address0 :30;
17 u32 dma_0No_update : 1;
18 u32 dma_0start : 1;
19 } dma_0x0;
20
21 struct {
22 u32 dma_addr_size :24;
23 u32 DMA_maxpackets : 8;
24 } dma_0x4_remap;
25
26 struct {
27 u32 dma_addr_size :24;
28 u32 unused : 1;
29 u32 dma1timer : 7;
30 } dma_0x4_read;
31
32 struct {
33 u32 dma_addr_size :24;
34 u32 dmatimer : 7;
35 u32 unused : 1;
36 } dma_0x4_write;
37
38 struct {
39 u32 dma_cur_addr :30;
40 u32 unused : 2;
41 } dma_0x8;
42
43 struct {
44 u32 dma_address1 :30;
45 u32 remap_enable : 1;
46 u32 dma_1start : 1;
47 } dma_0xc;
48
49 struct {
50 u32 st_done : 1;
51 u32 no_base_addr_ack_error : 1;
52 u32 twoWS_port_reg : 2;
53 u32 total_bytes : 2;
54 u32 twoWS_rw : 1;
55 u32 working_start : 1;
56 u32 data1_reg : 8;
57 u32 baseaddr : 8;
58 u32 reserved1 : 1;
59 u32 chipaddr : 7;
60 } tw_sm_c_100;
61
62 struct {
63 u32 unused : 6;
64 u32 force_stop : 1;
65 u32 exlicit_stops : 1;
66 u32 data4_reg : 8;
67 u32 data3_reg : 8;
68 u32 data2_reg : 8;
69 } tw_sm_c_104;
70
71 struct {
72 u32 reserved2 :19;
73 u32 tlo1 : 5;
74 u32 reserved1 : 2;
75 u32 thi1 : 6;
76 } tw_sm_c_108;
77
78 struct {
79 u32 reserved2 :19;
80 u32 tlo1 : 5;
81 u32 reserved1 : 2;
82 u32 thi1 : 6;
83 } tw_sm_c_10c;
84
85 struct {
86 u32 reserved2 :19;
87 u32 tlo1 : 5;
88 u32 reserved1 : 2;
89 u32 thi1 : 6;
90 } tw_sm_c_110;
91
92 struct {
93 u32 LNB_CTLPrescaler_sig : 2;
94 u32 LNB_CTLLowCount_sig :15;
95 u32 LNB_CTLHighCount_sig :15;
96 } lnb_switch_freq_200;
97
98 struct {
99 u32 Rev_N_sig_reserved2 : 1;
100 u32 Rev_N_sig_caps : 1;
101 u32 Rev_N_sig_reserved1 : 2;
102 u32 Rev_N_sig_revision_hi : 4;
103 u32 reserved :20;
104 u32 Per_reset_sig : 1;
105 u32 LNB_L_H_sig : 1;
106 u32 ACPI3_sig : 1;
107 u32 ACPI1_sig : 1;
108 } misc_204;
109
110 struct {
111 u32 unused : 9;
112 u32 Mailbox_from_V8_Enable_sig : 1;
113 u32 DMA2_Size_IRQ_Enable_sig : 1;
114 u32 DMA1_Size_IRQ_Enable_sig : 1;
115 u32 DMA2_Timer_Enable_sig : 1;
116 u32 DMA2_IRQ_Enable_sig : 1;
117 u32 DMA1_Timer_Enable_sig : 1;
118 u32 DMA1_IRQ_Enable_sig : 1;
119 u32 Rcv_Data_sig : 1;
120 u32 MAC_filter_Mode_sig : 1;
121 u32 Multi2_Enable_sig : 1;
122 u32 Per_CA_Enable_sig : 1;
123 u32 SMC_Enable_sig : 1;
124 u32 CA_Enable_sig : 1;
125 u32 WAN_CA_Enable_sig : 1;
126 u32 WAN_Enable_sig : 1;
127 u32 Mask_filter_sig : 1;
128 u32 Null_filter_sig : 1;
129 u32 ECM_filter_sig : 1;
130 u32 EMM_filter_sig : 1;
131 u32 PMT_filter_sig : 1;
132 u32 PCR_filter_sig : 1;
133 u32 Stream2_filter_sig : 1;
134 u32 Stream1_filter_sig : 1;
135 } ctrl_208;
136
137 struct {
138 u32 reserved :21;
139 u32 Transport_Error : 1;
140 u32 LLC_SNAP_FLAG_set : 1;
141 u32 Continuity_error_flag : 1;
142 u32 Data_receiver_error : 1;
143 u32 Mailbox_from_V8_Status_sig : 1;
144 u32 DMA2_Size_IRQ_Status : 1;
145 u32 DMA1_Size_IRQ_Status : 1;
146 u32 DMA2_Timer_Status : 1;
147 u32 DMA2_IRQ_Status : 1;
148 u32 DMA1_Timer_Status : 1;
149 u32 DMA1_IRQ_Status : 1;
150 } irq_20c;
151
152 struct {
153 u32 Special_controls :16;
154 u32 Block_reset_enable : 8;
155 u32 reset_blocks : 8;
156 } sw_reset_210;
157
158 struct {
159 u32 unused2 :20;
160 u32 polarity_PS_ERR_sig : 1;
161 u32 polarity_PS_SYNC_sig : 1;
162 u32 polarity_PS_VALID_sig : 1;
163 u32 polarity_PS_CLK_sig : 1;
164 u32 unused1 : 3;
165 u32 s2p_sel_sig : 1;
166 u32 section_pkg_enable_sig : 1;
167 u32 halt_V8_sig : 1;
168 u32 v2WS_oe_sig : 1;
169 u32 vuart_oe_sig : 1;
170 } misc_214;
171
172 struct {
173 u32 Mailbox_from_V8 :32;
174 } mbox_v8_to_host_218;
175
176 struct {
177 u32 sysramaccess_busmuster : 1;
178 u32 sysramaccess_write : 1;
179 u32 unused : 7;
180 u32 sysramaccess_addr :15;
181 u32 sysramaccess_data : 8;
182 } mbox_host_to_v8_21c;
183
184 struct {
185 u32 debug_fifo_problem : 1;
186 u32 debug_flag_write_status00 : 1;
187 u32 Stream2_trans : 1;
188 u32 Stream2_PID :13;
189 u32 debug_flag_pid_saved : 1;
190 u32 MAC_Multicast_filter : 1;
191 u32 Stream1_trans : 1;
192 u32 Stream1_PID :13;
193 } pid_filter_300;
194
195 struct {
196 u32 reserved : 2;
197 u32 PMT_trans : 1;
198 u32 PMT_PID :13;
199 u32 debug_overrun2 : 1;
200 u32 debug_overrun3 : 1;
201 u32 PCR_trans : 1;
202 u32 PCR_PID :13;
203 } pid_filter_304;
204
205 struct {
206 u32 reserved : 2;
207 u32 ECM_trans : 1;
208 u32 ECM_PID :13;
209 u32 EMM_filter_6 : 1;
210 u32 EMM_filter_4 : 1;
211 u32 EMM_trans : 1;
212 u32 EMM_PID :13;
213 } pid_filter_308;
214
215 struct {
216 u32 unused2 : 3;
217 u32 Group_mask :13;
218 u32 unused1 : 2;
219 u32 Group_trans : 1;
220 u32 Group_PID :13;
221 } pid_filter_30c_ext_ind_0_7;
222
223 struct {
224 u32 unused :15;
225 u32 net_master_read :17;
226 } pid_filter_30c_ext_ind_1;
227
228 struct {
229 u32 unused :15;
230 u32 net_master_write :17;
231 } pid_filter_30c_ext_ind_2;
232
233 struct {
234 u32 unused :15;
235 u32 next_net_master_write :17;
236 } pid_filter_30c_ext_ind_3;
237
238 struct {
239 u32 reserved2 : 5;
240 u32 stack_read :10;
241 u32 reserved1 : 6;
242 u32 state_write :10;
243 u32 unused1 : 1;
244 } pid_filter_30c_ext_ind_4;
245
246 struct {
247 u32 unused :22;
248 u32 stack_cnt :10;
249 } pid_filter_30c_ext_ind_5;
250
251 struct {
252 u32 unused : 4;
253 u32 data_size_reg :12;
254 u32 write_status4 : 2;
255 u32 write_status1 : 2;
256 u32 pid_fsm_save_reg300 : 2;
257 u32 pid_fsm_save_reg4 : 2;
258 u32 pid_fsm_save_reg3 : 2;
259 u32 pid_fsm_save_reg2 : 2;
260 u32 pid_fsm_save_reg1 : 2;
261 u32 pid_fsm_save_reg0 : 2;
262 } pid_filter_30c_ext_ind_6;
263
264 struct {
265 u32 unused :22;
266 u32 pass_alltables : 1;
267 u32 AB_select : 1;
268 u32 extra_index_reg : 3;
269 u32 index_reg : 5;
270 } index_reg_310;
271
272 struct {
273 u32 reserved :17;
274 u32 PID_enable_bit : 1;
275 u32 PID_trans : 1;
276 u32 PID :13;
277 } pid_n_reg_314;
278
279 struct {
280 u32 reserved : 6;
281 u32 HighAB_bit : 1;
282 u32 Enable_bit : 1;
283 u32 A6_byte : 8;
284 u32 A5_byte : 8;
285 u32 A4_byte : 8;
286 } mac_low_reg_318;
287
288 struct {
289 u32 reserved : 8;
290 u32 A3_byte : 8;
291 u32 A2_byte : 8;
292 u32 A1_byte : 8;
293 } mac_high_reg_31c;
294
295 struct {
296 u32 data_Tag_ID :16;
297 u32 reserved :16;
298 } data_tag_400;
299
300 struct {
301 u32 Card_IDbyte3 : 8;
302 u32 Card_IDbyte4 : 8;
303 u32 Card_IDbyte5 : 8;
304 u32 Card_IDbyte6 : 8;
305 } card_id_408;
306
307 struct {
308 u32 Card_IDbyte1 : 8;
309 u32 Card_IDbyte2 : 8;
310 } card_id_40c;
311
312 struct {
313 u32 MAC6 : 8;
314 u32 MAC3 : 8;
315 u32 MAC2 : 8;
316 u32 MAC1 : 8;
317 } mac_address_418;
318
319 struct {
320 u32 reserved :16;
321 u32 MAC8 : 8;
322 u32 MAC7 : 8;
323 } mac_address_41c;
324
325 struct {
326 u32 reserved :21;
327 u32 txbuffempty : 1;
328 u32 ReceiveByteFrameError : 1;
329 u32 ReceiveDataReady : 1;
330 u32 transmitter_data_byte : 8;
331 } ci_600;
332
333 struct {
334 u32 pi_component_reg : 3;
335 u32 pi_rw : 1;
336 u32 pi_ha :20;
337 u32 pi_d : 8;
338 } pi_604;
339
340 struct {
341 u32 pi_busy_n : 1;
342 u32 pi_wait_n : 1;
343 u32 pi_timeout_status : 1;
344 u32 pi_CiMax_IRQ_n : 1;
345 u32 config_cclk : 1;
346 u32 config_cs_n : 1;
347 u32 config_wr_n : 1;
348 u32 config_Prog_n : 1;
349 u32 config_Init_stat : 1;
350 u32 config_Done_stat : 1;
351 u32 pcmcia_b_mod_pwr_n : 1;
352 u32 pcmcia_a_mod_pwr_n : 1;
353 u32 reserved : 3;
354 u32 Timer_addr : 5;
355 u32 unused : 1;
356 u32 timer_data : 7;
357 u32 Timer_Load_req : 1;
358 u32 Timer_Read_req : 1;
359 u32 oncecycle_read : 1;
360 u32 serialReset : 1;
361 } pi_608;
362
363 struct {
364 u32 reserved : 6;
365 u32 rw_flag : 1;
366 u32 dvb_en : 1;
367 u32 key_array_row : 5;
368 u32 key_array_col : 3;
369 u32 key_code : 2;
370 u32 key_enable : 1;
371 u32 PID :13;
372 } dvb_reg_60c;
373
374 struct {
375 u32 start_sram_ibi : 1;
376 u32 reserved2 : 1;
377 u32 ce_pin_reg : 1;
378 u32 oe_pin_reg : 1;
379 u32 reserved1 : 3;
380 u32 sc_xfer_bit : 1;
381 u32 sram_data : 8;
382 u32 sram_rw : 1;
383 u32 sram_addr :15;
384 } sram_ctrl_reg_700;
385
386 struct {
387 u32 net_addr_write :16;
388 u32 net_addr_read :16;
389 } net_buf_reg_704;
390
391 struct {
392 u32 cai_cnt : 4;
393 u32 reserved2 : 6;
394 u32 cai_write :11;
395 u32 reserved1 : 5;
396 u32 cai_read :11;
397 } cai_buf_reg_708;
398
399 struct {
400 u32 cao_cnt : 4;
401 u32 reserved2 : 6;
402 u32 cap_write :11;
403 u32 reserved1 : 5;
404 u32 cao_read :11;
405 } cao_buf_reg_70c;
406
407 struct {
408 u32 media_cnt : 4;
409 u32 reserved2 : 6;
410 u32 media_write :11;
411 u32 reserved1 : 5;
412 u32 media_read :11;
413 } media_buf_reg_710;
414
415 struct {
416 u32 reserved :17;
417 u32 ctrl_maximumfill : 1;
418 u32 ctrl_sramdma : 1;
419 u32 ctrl_usb_wan : 1;
420 u32 cao_ovflow_error : 1;
421 u32 cai_ovflow_error : 1;
422 u32 media_ovflow_error : 1;
423 u32 net_ovflow_error : 1;
424 u32 MEDIA_Dest : 2;
425 u32 CAO_Dest : 2;
426 u32 CAI_Dest : 2;
427 u32 NET_Dest : 2;
428 } sram_dest_reg_714;
429
430 struct {
431 u32 reserved3 :11;
432 u32 net_addr_write : 1;
433 u32 reserved2 : 3;
434 u32 net_addr_read : 1;
435 u32 reserved1 : 4;
436 u32 net_cnt :12;
437 } net_buf_reg_718;
438
439 struct {
440 u32 reserved3 : 4;
441 u32 wan_pkt_frame : 4;
442 u32 reserved2 : 4;
443 u32 sram_memmap : 2;
444 u32 sram_chip : 2;
445 u32 wan_wait_state : 8;
446 u32 reserved1 : 6;
447 u32 wan_speed_sig : 2;
448 } wan_ctrl_reg_71c;
449} flexcop_ibi_value;
450
451#endif
diff --git a/drivers/media/dvb/b2c2/flexcop_ibi_value_le.h b/drivers/media/dvb/b2c2/flexcop_ibi_value_le.h
new file mode 100644
index 000000000000..bd4528d747d7
--- /dev/null
+++ b/drivers/media/dvb/b2c2/flexcop_ibi_value_le.h
@@ -0,0 +1,451 @@
1/* This file is part of linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
2 *
3 * register descriptions
4 *
5 * see flexcop.c for copyright information.
6 */
7
8/* This file is automatically generated, do not edit things here. */
9#ifndef __FLEXCOP_IBI_VALUE_INCLUDED__
10#define __FLEXCOP_IBI_VALUE_INCLUDED__
11
12typedef union {
13 u32 raw;
14
15 struct {
16 u32 dma_0start : 1;
17 u32 dma_0No_update : 1;
18 u32 dma_address0 :30;
19 } dma_0x0;
20
21 struct {
22 u32 DMA_maxpackets : 8;
23 u32 dma_addr_size :24;
24 } dma_0x4_remap;
25
26 struct {
27 u32 dma1timer : 7;
28 u32 unused : 1;
29 u32 dma_addr_size :24;
30 } dma_0x4_read;
31
32 struct {
33 u32 unused : 1;
34 u32 dmatimer : 7;
35 u32 dma_addr_size :24;
36 } dma_0x4_write;
37
38 struct {
39 u32 unused : 2;
40 u32 dma_cur_addr :30;
41 } dma_0x8;
42
43 struct {
44 u32 dma_1start : 1;
45 u32 remap_enable : 1;
46 u32 dma_address1 :30;
47 } dma_0xc;
48
49 struct {
50 u32 chipaddr : 7;
51 u32 reserved1 : 1;
52 u32 baseaddr : 8;
53 u32 data1_reg : 8;
54 u32 working_start : 1;
55 u32 twoWS_rw : 1;
56 u32 total_bytes : 2;
57 u32 twoWS_port_reg : 2;
58 u32 no_base_addr_ack_error : 1;
59 u32 st_done : 1;
60 } tw_sm_c_100;
61
62 struct {
63 u32 data2_reg : 8;
64 u32 data3_reg : 8;
65 u32 data4_reg : 8;
66 u32 exlicit_stops : 1;
67 u32 force_stop : 1;
68 u32 unused : 6;
69 } tw_sm_c_104;
70
71 struct {
72 u32 thi1 : 6;
73 u32 reserved1 : 2;
74 u32 tlo1 : 5;
75 u32 reserved2 :19;
76 } tw_sm_c_108;
77
78 struct {
79 u32 thi1 : 6;
80 u32 reserved1 : 2;
81 u32 tlo1 : 5;
82 u32 reserved2 :19;
83 } tw_sm_c_10c;
84
85 struct {
86 u32 thi1 : 6;
87 u32 reserved1 : 2;
88 u32 tlo1 : 5;
89 u32 reserved2 :19;
90 } tw_sm_c_110;
91
92 struct {
93 u32 LNB_CTLHighCount_sig :15;
94 u32 LNB_CTLLowCount_sig :15;
95 u32 LNB_CTLPrescaler_sig : 2;
96 } lnb_switch_freq_200;
97
98 struct {
99 u32 ACPI1_sig : 1;
100 u32 ACPI3_sig : 1;
101 u32 LNB_L_H_sig : 1;
102 u32 Per_reset_sig : 1;
103 u32 reserved :20;
104 u32 Rev_N_sig_revision_hi : 4;
105 u32 Rev_N_sig_reserved1 : 2;
106 u32 Rev_N_sig_caps : 1;
107 u32 Rev_N_sig_reserved2 : 1;
108 } misc_204;
109
110 struct {
111 u32 Stream1_filter_sig : 1;
112 u32 Stream2_filter_sig : 1;
113 u32 PCR_filter_sig : 1;
114 u32 PMT_filter_sig : 1;
115 u32 EMM_filter_sig : 1;
116 u32 ECM_filter_sig : 1;
117 u32 Null_filter_sig : 1;
118 u32 Mask_filter_sig : 1;
119 u32 WAN_Enable_sig : 1;
120 u32 WAN_CA_Enable_sig : 1;
121 u32 CA_Enable_sig : 1;
122 u32 SMC_Enable_sig : 1;
123 u32 Per_CA_Enable_sig : 1;
124 u32 Multi2_Enable_sig : 1;
125 u32 MAC_filter_Mode_sig : 1;
126 u32 Rcv_Data_sig : 1;
127 u32 DMA1_IRQ_Enable_sig : 1;
128 u32 DMA1_Timer_Enable_sig : 1;
129 u32 DMA2_IRQ_Enable_sig : 1;
130 u32 DMA2_Timer_Enable_sig : 1;
131 u32 DMA1_Size_IRQ_Enable_sig : 1;
132 u32 DMA2_Size_IRQ_Enable_sig : 1;
133 u32 Mailbox_from_V8_Enable_sig : 1;
134 u32 unused : 9;
135 } ctrl_208;
136
137 struct {
138 u32 DMA1_IRQ_Status : 1;
139 u32 DMA1_Timer_Status : 1;
140 u32 DMA2_IRQ_Status : 1;
141 u32 DMA2_Timer_Status : 1;
142 u32 DMA1_Size_IRQ_Status : 1;
143 u32 DMA2_Size_IRQ_Status : 1;
144 u32 Mailbox_from_V8_Status_sig : 1;
145 u32 Data_receiver_error : 1;
146 u32 Continuity_error_flag : 1;
147 u32 LLC_SNAP_FLAG_set : 1;
148 u32 Transport_Error : 1;
149 u32 reserved :21;
150 } irq_20c;
151
152 struct {
153 u32 reset_blocks : 8;
154 u32 Block_reset_enable : 8;
155 u32 Special_controls :16;
156 } sw_reset_210;
157
158 struct {
159 u32 vuart_oe_sig : 1;
160 u32 v2WS_oe_sig : 1;
161 u32 halt_V8_sig : 1;
162 u32 section_pkg_enable_sig : 1;
163 u32 s2p_sel_sig : 1;
164 u32 unused1 : 3;
165 u32 polarity_PS_CLK_sig : 1;
166 u32 polarity_PS_VALID_sig : 1;
167 u32 polarity_PS_SYNC_sig : 1;
168 u32 polarity_PS_ERR_sig : 1;
169 u32 unused2 :20;
170 } misc_214;
171
172 struct {
173 u32 Mailbox_from_V8 :32;
174 } mbox_v8_to_host_218;
175
176 struct {
177 u32 sysramaccess_data : 8;
178 u32 sysramaccess_addr :15;
179 u32 unused : 7;
180 u32 sysramaccess_write : 1;
181 u32 sysramaccess_busmuster : 1;
182 } mbox_host_to_v8_21c;
183
184 struct {
185 u32 Stream1_PID :13;
186 u32 Stream1_trans : 1;
187 u32 MAC_Multicast_filter : 1;
188 u32 debug_flag_pid_saved : 1;
189 u32 Stream2_PID :13;
190 u32 Stream2_trans : 1;
191 u32 debug_flag_write_status00 : 1;
192 u32 debug_fifo_problem : 1;
193 } pid_filter_300;
194
195 struct {
196 u32 PCR_PID :13;
197 u32 PCR_trans : 1;
198 u32 debug_overrun3 : 1;
199 u32 debug_overrun2 : 1;
200 u32 PMT_PID :13;
201 u32 PMT_trans : 1;
202 u32 reserved : 2;
203 } pid_filter_304;
204
205 struct {
206 u32 EMM_PID :13;
207 u32 EMM_trans : 1;
208 u32 EMM_filter_4 : 1;
209 u32 EMM_filter_6 : 1;
210 u32 ECM_PID :13;
211 u32 ECM_trans : 1;
212 u32 reserved : 2;
213 } pid_filter_308;
214
215 struct {
216 u32 Group_PID :13;
217 u32 Group_trans : 1;
218 u32 unused1 : 2;
219 u32 Group_mask :13;
220 u32 unused2 : 3;
221 } pid_filter_30c_ext_ind_0_7;
222
223 struct {
224 u32 net_master_read :17;
225 u32 unused :15;
226 } pid_filter_30c_ext_ind_1;
227
228 struct {
229 u32 net_master_write :17;
230 u32 unused :15;
231 } pid_filter_30c_ext_ind_2;
232
233 struct {
234 u32 next_net_master_write :17;
235 u32 unused :15;
236 } pid_filter_30c_ext_ind_3;
237
238 struct {
239 u32 unused1 : 1;
240 u32 state_write :10;
241 u32 reserved1 : 6;
242 u32 stack_read :10;
243 u32 reserved2 : 5;
244 } pid_filter_30c_ext_ind_4;
245
246 struct {
247 u32 stack_cnt :10;
248 u32 unused :22;
249 } pid_filter_30c_ext_ind_5;
250
251 struct {
252 u32 pid_fsm_save_reg0 : 2;
253 u32 pid_fsm_save_reg1 : 2;
254 u32 pid_fsm_save_reg2 : 2;
255 u32 pid_fsm_save_reg3 : 2;
256 u32 pid_fsm_save_reg4 : 2;
257 u32 pid_fsm_save_reg300 : 2;
258 u32 write_status1 : 2;
259 u32 write_status4 : 2;
260 u32 data_size_reg :12;
261 u32 unused : 4;
262 } pid_filter_30c_ext_ind_6;
263
264 struct {
265 u32 index_reg : 5;
266 u32 extra_index_reg : 3;
267 u32 AB_select : 1;
268 u32 pass_alltables : 1;
269 u32 unused :22;
270 } index_reg_310;
271
272 struct {
273 u32 PID :13;
274 u32 PID_trans : 1;
275 u32 PID_enable_bit : 1;
276 u32 reserved :17;
277 } pid_n_reg_314;
278
279 struct {
280 u32 A4_byte : 8;
281 u32 A5_byte : 8;
282 u32 A6_byte : 8;
283 u32 Enable_bit : 1;
284 u32 HighAB_bit : 1;
285 u32 reserved : 6;
286 } mac_low_reg_318;
287
288 struct {
289 u32 A1_byte : 8;
290 u32 A2_byte : 8;
291 u32 A3_byte : 8;
292 u32 reserved : 8;
293 } mac_high_reg_31c;
294
295 struct {
296 u32 reserved :16;
297 u32 data_Tag_ID :16;
298 } data_tag_400;
299
300 struct {
301 u32 Card_IDbyte6 : 8;
302 u32 Card_IDbyte5 : 8;
303 u32 Card_IDbyte4 : 8;
304 u32 Card_IDbyte3 : 8;
305 } card_id_408;
306
307 struct {
308 u32 Card_IDbyte2 : 8;
309 u32 Card_IDbyte1 : 8;
310 } card_id_40c;
311
312 struct {
313 u32 MAC1 : 8;
314 u32 MAC2 : 8;
315 u32 MAC3 : 8;
316 u32 MAC6 : 8;
317 } mac_address_418;
318
319 struct {
320 u32 MAC7 : 8;
321 u32 MAC8 : 8;
322 u32 reserved :16;
323 } mac_address_41c;
324
325 struct {
326 u32 transmitter_data_byte : 8;
327 u32 ReceiveDataReady : 1;
328 u32 ReceiveByteFrameError : 1;
329 u32 txbuffempty : 1;
330 u32 reserved :21;
331 } ci_600;
332
333 struct {
334 u32 pi_d : 8;
335 u32 pi_ha :20;
336 u32 pi_rw : 1;
337 u32 pi_component_reg : 3;
338 } pi_604;
339
340 struct {
341 u32 serialReset : 1;
342 u32 oncecycle_read : 1;
343 u32 Timer_Read_req : 1;
344 u32 Timer_Load_req : 1;
345 u32 timer_data : 7;
346 u32 unused : 1;
347 u32 Timer_addr : 5;
348 u32 reserved : 3;
349 u32 pcmcia_a_mod_pwr_n : 1;
350 u32 pcmcia_b_mod_pwr_n : 1;
351 u32 config_Done_stat : 1;
352 u32 config_Init_stat : 1;
353 u32 config_Prog_n : 1;
354 u32 config_wr_n : 1;
355 u32 config_cs_n : 1;
356 u32 config_cclk : 1;
357 u32 pi_CiMax_IRQ_n : 1;
358 u32 pi_timeout_status : 1;
359 u32 pi_wait_n : 1;
360 u32 pi_busy_n : 1;
361 } pi_608;
362
363 struct {
364 u32 PID :13;
365 u32 key_enable : 1;
366 u32 key_code : 2;
367 u32 key_array_col : 3;
368 u32 key_array_row : 5;
369 u32 dvb_en : 1;
370 u32 rw_flag : 1;
371 u32 reserved : 6;
372 } dvb_reg_60c;
373
374 struct {
375 u32 sram_addr :15;
376 u32 sram_rw : 1;
377 u32 sram_data : 8;
378 u32 sc_xfer_bit : 1;
379 u32 reserved1 : 3;
380 u32 oe_pin_reg : 1;
381 u32 ce_pin_reg : 1;
382 u32 reserved2 : 1;
383 u32 start_sram_ibi : 1;
384 } sram_ctrl_reg_700;
385
386 struct {
387 u32 net_addr_read :16;
388 u32 net_addr_write :16;
389 } net_buf_reg_704;
390
391 struct {
392 u32 cai_read :11;
393 u32 reserved1 : 5;
394 u32 cai_write :11;
395 u32 reserved2 : 6;
396 u32 cai_cnt : 4;
397 } cai_buf_reg_708;
398
399 struct {
400 u32 cao_read :11;
401 u32 reserved1 : 5;
402 u32 cap_write :11;
403 u32 reserved2 : 6;
404 u32 cao_cnt : 4;
405 } cao_buf_reg_70c;
406
407 struct {
408 u32 media_read :11;
409 u32 reserved1 : 5;
410 u32 media_write :11;
411 u32 reserved2 : 6;
412 u32 media_cnt : 4;
413 } media_buf_reg_710;
414
415 struct {
416 u32 NET_Dest : 2;
417 u32 CAI_Dest : 2;
418 u32 CAO_Dest : 2;
419 u32 MEDIA_Dest : 2;
420 u32 net_ovflow_error : 1;
421 u32 media_ovflow_error : 1;
422 u32 cai_ovflow_error : 1;
423 u32 cao_ovflow_error : 1;
424 u32 ctrl_usb_wan : 1;
425 u32 ctrl_sramdma : 1;
426 u32 ctrl_maximumfill : 1;
427 u32 reserved :17;
428 } sram_dest_reg_714;
429
430 struct {
431 u32 net_cnt :12;
432 u32 reserved1 : 4;
433 u32 net_addr_read : 1;
434 u32 reserved2 : 3;
435 u32 net_addr_write : 1;
436 u32 reserved3 :11;
437 } net_buf_reg_718;
438
439 struct {
440 u32 wan_speed_sig : 2;
441 u32 reserved1 : 6;
442 u32 wan_wait_state : 8;
443 u32 sram_chip : 2;
444 u32 sram_memmap : 2;
445 u32 reserved2 : 4;
446 u32 wan_pkt_frame : 4;
447 u32 reserved3 : 4;
448 } wan_ctrl_reg_71c;
449} flexcop_ibi_value;
450
451#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-26 02:45:36 -0400