mtd: add bcmring nand driver

Signed-off-by: Leo Hao Chen <leochen@broadcom.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

6 files changed, 1318 insertions, 0 deletions

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 2fda0b615246..34598e9c1a40 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -203,6 +203,22 @@ config MTD_NAND_S3C2410_CLKSTOP
           when the is NAND chip selected or released, but will save
           approximately 5mA of power when there is nothing happening.
 
+config MTD_NAND_BCM_UMI
+        tristate "NAND Flash support for BCM Reference Boards"
+        depends on ARCH_BCMRING && MTD_NAND
+        help
+          This enables the NAND flash controller on the BCM UMI block.
+
+          No board specfic support is done by this driver, each board
+          must advertise a platform_device for the driver to attach.
+
+config MTD_NAND_BCM_UMI_HWCS
+        bool "BCM UMI NAND Hardware CS"
+        depends on MTD_NAND_BCM_UMI
+        help
+          Enable the use of the BCM UMI block's internal CS using NAND.
+          This should only be used if you know the external NAND CS can toggle.
+
 config MTD_NAND_DISKONCHIP
         tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
         depends on EXPERIMENTAL
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6950d3dabf10..460a1f39a8d1 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -42,5 +42,6 @@ obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o
 obj-$(CONFIG_MTD_NAND_TXX9NDFMC)        += txx9ndfmc.o
 obj-$(CONFIG_MTD_NAND_W90P910)          += w90p910_nand.o
 obj-$(CONFIG_MTD_NAND_NOMADIK)          += nomadik_nand.o
+obj-$(CONFIG_MTD_NAND_BCM_UMI)          += bcm_umi_nand.o nand_bcm_umi.o
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c
new file mode 100644
index 000000000000..a930666d0687
--- /dev/null
+++ b/drivers/mtd/nand/bcm_umi_bch.c
@@ -0,0 +1,213 @@
+/*****************************************************************************
+* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+#include "nand_bcm_umi.h"
+
+/* ---- External Variable Declarations ----------------------------------- */
+/* ---- External Function Prototypes ------------------------------------- */
+/* ---- Public Variables ------------------------------------------------- */
+/* ---- Private Constants and Types -------------------------------------- */
+
+/* ---- Private Function Prototypes -------------------------------------- */
+static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
+        struct nand_chip *chip, uint8_t *buf, int page);
+static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
+        struct nand_chip *chip, const uint8_t *buf);
+
+/* ---- Private Variables ------------------------------------------------ */
+
+/*
+** nand_hw_eccoob
+** New oob placement block for use with hardware ecc generation.
+*/
+static struct nand_ecclayout nand_hw_eccoob_512 = {
+        /* Reserve 5 for BI indicator */
+        .oobfree = {
+#if (NAND_ECC_NUM_BYTES > 3)
+                    {.offset = 0, .length = 2}
+#else
+                    {.offset = 0, .length = 5},
+                    {.offset = 6, .length = 7}
+#endif
+                    }
+};
+
+/*
+** We treat the OOB for a 2K page as if it were 4 512 byte oobs,
+** except the BI is at byte 0.
+*/
+static struct nand_ecclayout nand_hw_eccoob_2048 = {
+        /* Reserve 0 as BI indicator */
+        .oobfree = {
+#if (NAND_ECC_NUM_BYTES > 10)
+                    {.offset = 1, .length = 2},
+#elif (NAND_ECC_NUM_BYTES > 7)
+                    {.offset = 1, .length = 5},
+                    {.offset = 16, .length = 6},
+                    {.offset = 32, .length = 6},
+                    {.offset = 48, .length = 6}
+#else
+                    {.offset = 1, .length = 8},
+                    {.offset = 16, .length = 9},
+                    {.offset = 32, .length = 9},
+                    {.offset = 48, .length = 9}
+#endif
+                    }
+};
+
+/* We treat the OOB for a 4K page as if it were 8 512 byte oobs,
+ * except the BI is at byte 0. */
+static struct nand_ecclayout nand_hw_eccoob_4096 = {
+        /* Reserve 0 as BI indicator */
+        .oobfree = {
+#if (NAND_ECC_NUM_BYTES > 10)
+                    {.offset = 1, .length = 2},
+                    {.offset = 16, .length = 3},
+                    {.offset = 32, .length = 3},
+                    {.offset = 48, .length = 3},
+                    {.offset = 64, .length = 3},
+                    {.offset = 80, .length = 3},
+                    {.offset = 96, .length = 3},
+                    {.offset = 112, .length = 3}
+#else
+                    {.offset = 1, .length = 5},
+                    {.offset = 16, .length = 6},
+                    {.offset = 32, .length = 6},
+                    {.offset = 48, .length = 6},
+                    {.offset = 64, .length = 6},
+                    {.offset = 80, .length = 6},
+                    {.offset = 96, .length = 6},
+                    {.offset = 112, .length = 6}
+#endif
+                    }
+};
+
+/* ---- Private Functions ------------------------------------------------ */
+/* ==== Public Functions ================================================= */
+
+/****************************************************************************
+*
+*  bcm_umi_bch_read_page_hwecc - hardware ecc based page read function
+*  @mtd:        mtd info structure
+*  @chip:       nand chip info structure
+*  @buf:        buffer to store read data
+*
+***************************************************************************/
+static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
+                                       struct nand_chip *chip, uint8_t * buf,
+                                                 int page)
+{
+        int sectorIdx = 0;
+        int eccsize = chip->ecc.size;
+        int eccsteps = chip->ecc.steps;
+        uint8_t *datap = buf;
+        uint8_t eccCalc[NAND_ECC_NUM_BYTES];
+        int sectorOobSize = mtd->oobsize / eccsteps;
+        int stat;
+
+        for (sectorIdx = 0; sectorIdx < eccsteps;
+                        sectorIdx++, datap += eccsize) {
+                if (sectorIdx > 0) {
+                        /* Seek to page location within sector */
+                        chip->cmdfunc(mtd, NAND_CMD_RNDOUT, sectorIdx * eccsize,
+                                      -1);
+                }
+
+                /* Enable hardware ECC before reading the buf */
+                nand_bcm_umi_bch_enable_read_hwecc();
+
+                /* Read in data */
+                bcm_umi_nand_read_buf(mtd, datap, eccsize);
+
+                /* Pause hardware ECC after reading the buf */
+                nand_bcm_umi_bch_pause_read_ecc_calc();
+
+                /* Read the OOB ECC */
+                chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
+                              mtd->writesize + sectorIdx * sectorOobSize, -1);
+                nand_bcm_umi_bch_read_oobEcc(mtd->writesize, eccCalc,
+                                             NAND_ECC_NUM_BYTES,
+                                             chip->oob_poi +
+                                             sectorIdx * sectorOobSize);
+
+                /* Correct any ECC detected errors */
+                stat =
+                    nand_bcm_umi_bch_correct_page(datap, eccCalc,
+                                                  NAND_ECC_NUM_BYTES);
+
+                /* Update Stats */
+                if (stat < 0) {
+#if defined(NAND_BCM_UMI_DEBUG)
+                        printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n",
+                               __func__, sectorIdx);
+                        printk(KERN_WARNING
+                               "%s data %02x %02x %02x %02x "
+                                         "%02x %02x %02x %02x\n",
+                               __func__, datap[0], datap[1], datap[2], datap[3],
+                               datap[4], datap[5], datap[6], datap[7]);
+                        printk(KERN_WARNING
+                               "%s ecc  %02x %02x %02x %02x "
+                                         "%02x %02x %02x %02x %02x %02x "
+                                         "%02x %02x %02x\n",
+                               __func__, eccCalc[0], eccCalc[1], eccCalc[2],
+                               eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6],
+                               eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10],
+                               eccCalc[11], eccCalc[12]);
+                        BUG();
+#endif
+                        mtd->ecc_stats.failed++;
+                } else {
+#if defined(NAND_BCM_UMI_DEBUG)
+                        if (stat > 0) {
+                                printk(KERN_INFO
+                                       "%s %d correctable_errors detected\n",
+                                       __func__, stat);
+                        }
+#endif
+                        mtd->ecc_stats.corrected += stat;
+                }
+        }
+        return 0;
+}
+
+/****************************************************************************
+*
+*  bcm_umi_bch_write_page_hwecc - hardware ecc based page write function
+*  @mtd:        mtd info structure
+*  @chip:       nand chip info structure
+*  @buf:        data buffer
+*
+***************************************************************************/
+static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
+        struct nand_chip *chip, const uint8_t *buf)
+{
+        int sectorIdx = 0;
+        int eccsize = chip->ecc.size;
+        int eccsteps = chip->ecc.steps;
+        const uint8_t *datap = buf;
+        uint8_t *oobp = chip->oob_poi;
+        int sectorOobSize = mtd->oobsize / eccsteps;
+
+        for (sectorIdx = 0; sectorIdx < eccsteps;
+             sectorIdx++, datap += eccsize, oobp += sectorOobSize) {
+                /* Enable hardware ECC before writing the buf */
+                nand_bcm_umi_bch_enable_write_hwecc();
+                bcm_umi_nand_write_buf(mtd, datap, eccsize);
+                nand_bcm_umi_bch_write_oobEcc(mtd->writesize, oobp,
+                                              NAND_ECC_NUM_BYTES);
+        }
+
+        bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
new file mode 100644
index 000000000000..087bcd745bb7
--- /dev/null
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -0,0 +1,581 @@
+/*****************************************************************************
+* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-types.h>
+#include <asm/system.h>
+
+#include <mach/reg_nand.h>
+#include <mach/reg_umi.h>
+
+#include "nand_bcm_umi.h"
+
+#include <mach/memory_settings.h>
+
+#define USE_DMA 1
+#include <mach/dma.h>
+#include <linux/dma-mapping.h>
+#include <linux/completion.h>
+
+/* ---- External Variable Declarations ----------------------------------- */
+/* ---- External Function Prototypes ------------------------------------- */
+/* ---- Public Variables ------------------------------------------------- */
+/* ---- Private Constants and Types -------------------------------------- */
+static const __devinitconst char gBanner[] = KERN_INFO \
+        "BCM UMI MTD NAND Driver: 1.00\n";
+
+#ifdef CONFIG_MTD_PARTITIONS
+const char *part_probes[] = { "cmdlinepart", NULL };
+#endif
+
+#if NAND_ECC_BCH
+static uint8_t scan_ff_pattern[] = { 0xff };
+
+static struct nand_bbt_descr largepage_bbt = {
+        .options = 0,
+        .offs = 0,
+        .len = 1,
+        .pattern = scan_ff_pattern
+};
+#endif
+
+/*
+** Preallocate a buffer to avoid having to do this every dma operation.
+** This is the size of the preallocated coherent DMA buffer.
+*/
+#if USE_DMA
+#define DMA_MIN_BUFLEN  512
+#define DMA_MAX_BUFLEN  PAGE_SIZE
+#define USE_DIRECT_IO(len)      (((len) < DMA_MIN_BUFLEN) || \
+        ((len) > DMA_MAX_BUFLEN))
+
+/*
+ * The current NAND data space goes from 0x80001900 to 0x80001FFF,
+ * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
+ * size NAND flash. Need to break the DMA down to multiple 1Ks.
+ *
+ * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
+ */
+#define DMA_MAX_LEN             1024
+
+#else /* !USE_DMA */
+#define DMA_MIN_BUFLEN          0
+#define DMA_MAX_BUFLEN          0
+#define USE_DIRECT_IO(len)      1
+#endif
+/* ---- Private Function Prototypes -------------------------------------- */
+static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);
+static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
+                                   int len);
+
+/* ---- Private Variables ------------------------------------------------ */
+static struct mtd_info *board_mtd;
+static void __iomem *bcm_umi_io_base;
+static void *virtPtr;
+static dma_addr_t physPtr;
+static struct completion nand_comp;
+
+/* ---- Private Functions ------------------------------------------------ */
+#if NAND_ECC_BCH
+#include "bcm_umi_bch.c"
+#else
+#include "bcm_umi_hamming.c"
+#endif
+
+#if USE_DMA
+
+/* Handler called when the DMA finishes. */
+static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
+{
+        complete(&nand_comp);
+}
+
+static int nand_dma_init(void)
+{
+        int rc;
+
+        rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
+                nand_dma_handler, NULL);
+        if (rc != 0) {
+                printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
+                return rc;
+        }
+
+        virtPtr =
+            dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
+        if (virtPtr == NULL) {
+                printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+static void nand_dma_term(void)
+{
+        if (virtPtr != NULL)
+                dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
+}
+
+static void nand_dma_read(void *buf, int len)
+{
+        int offset = 0;
+        int tmp_len = 0;
+        int len_left = len;
+        DMA_Handle_t hndl;
+
+        if (virtPtr == NULL)
+                panic("nand_dma_read: virtPtr == NULL\n");
+
+        if ((void *)physPtr == NULL)
+                panic("nand_dma_read: physPtr == NULL\n");
+
+        hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
+        if (hndl < 0) {
+                printk(KERN_ERR
+                       "nand_dma_read: unable to allocate dma channel: %d\n",
+                       (int)hndl);
+                panic("\n");
+        }
+
+        while (len_left > 0) {
+                if (len_left > DMA_MAX_LEN) {
+                        tmp_len = DMA_MAX_LEN;
+                        len_left -= DMA_MAX_LEN;
+                } else {
+                        tmp_len = len_left;
+                        len_left = 0;
+                }
+
+                init_completion(&nand_comp);
+                dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
+                                        physPtr + offset, tmp_len);
+                wait_for_completion(&nand_comp);
+
+                offset += tmp_len;
+        }
+
+        dma_free_channel(hndl);
+
+        if (buf != NULL)
+                memcpy(buf, virtPtr, len);
+}
+
+static void nand_dma_write(const void *buf, int len)
+{
+        int offset = 0;
+        int tmp_len = 0;
+        int len_left = len;
+        DMA_Handle_t hndl;
+
+        if (buf == NULL)
+                panic("nand_dma_write: buf == NULL\n");
+
+        if (virtPtr == NULL)
+                panic("nand_dma_write: virtPtr == NULL\n");
+
+        if ((void *)physPtr == NULL)
+                panic("nand_dma_write: physPtr == NULL\n");
+
+        memcpy(virtPtr, buf, len);
+
+
+        hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
+        if (hndl < 0) {
+                printk(KERN_ERR
+                       "nand_dma_write: unable to allocate dma channel: %d\n",
+                       (int)hndl);
+                panic("\n");
+        }
+
+        while (len_left > 0) {
+                if (len_left > DMA_MAX_LEN) {
+                        tmp_len = DMA_MAX_LEN;
+                        len_left -= DMA_MAX_LEN;
+                } else {
+                        tmp_len = len_left;
+                        len_left = 0;
+                }
+
+                init_completion(&nand_comp);
+                dma_transfer_mem_to_mem(hndl, physPtr + offset,
+                                        REG_NAND_DATA_PADDR, tmp_len);
+                wait_for_completion(&nand_comp);
+
+                offset += tmp_len;
+        }
+
+        dma_free_channel(hndl);
+}
+
+#endif
+
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+        return nand_bcm_umi_dev_ready();
+}
+
+/****************************************************************************
+*
+*  bcm_umi_nand_inithw
+*
+*   This routine does the necessary hardware (board-specific)
+*   initializations.  This includes setting up the timings, etc.
+*
+***************************************************************************/
+int bcm_umi_nand_inithw(void)
+{
+        /* Configure nand timing parameters */
+        REG_UMI_NAND_TCR &= ~0x7ffff;
+        REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
+
+#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
+        /* enable software control of CS */
+        REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
+#endif
+
+        /* keep NAND chip select asserted */
+        REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
+
+        REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
+        /* enable writes to flash */
+        REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
+
+        writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
+        nand_bcm_umi_wait_till_ready();
+
+#if NAND_ECC_BCH
+        nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
+#endif
+
+        return 0;
+}
+
+/* Used to turn latch the proper register for access. */
+static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+                                   unsigned int ctrl)
+{
+        /* send command to hardware */
+        struct nand_chip *chip = mtd->priv;
+        if (ctrl & NAND_CTRL_CHANGE) {
+                if (ctrl & NAND_CLE) {
+                        chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
+                        goto CMD;
+                }
+                if (ctrl & NAND_ALE) {
+                        chip->IO_ADDR_W =
+                            bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
+                        goto CMD;
+                }
+                chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
+        }
+
+CMD:
+        /* Send command to chip directly */
+        if (cmd != NAND_CMD_NONE)
+                writeb(cmd, chip->IO_ADDR_W);
+}
+
+static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
+                                   int len)
+{
+        if (USE_DIRECT_IO(len)) {
+                /* Do it the old way if the buffer is small or too large.
+                 * Probably quicker than starting and checking dma. */
+                int i;
+                struct nand_chip *this = mtd->priv;
+
+                for (i = 0; i < len; i++)
+                        writeb(buf[i], this->IO_ADDR_W);
+        }
+#if USE_DMA
+        else
+                nand_dma_write(buf, len);
+#endif
+}
+
+static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+        if (USE_DIRECT_IO(len)) {
+                int i;
+                struct nand_chip *this = mtd->priv;
+
+                for (i = 0; i < len; i++)
+                        buf[i] = readb(this->IO_ADDR_R);
+        }
+#if USE_DMA
+        else
+                nand_dma_read(buf, len);
+#endif
+}
+
+static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
+static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
+                                   int len)
+{
+        /*
+         * Try to readback page with ECC correction. This is necessary
+         * for MLC parts which may have permanently stuck bits.
+         */
+        struct nand_chip *chip = mtd->priv;
+        int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0);
+        if (ret < 0)
+                return -EFAULT;
+        else {
+                if (memcmp(readbackbuf, buf, len) == 0)
+                        return 0;
+
+                return -EFAULT;
+        }
+        return 0;
+}
+
+static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
+{
+        struct nand_chip *this;
+        struct resource *r;
+        int err = 0;
+
+        printk(gBanner);
+
+        /* Allocate memory for MTD device structure and private data */
+        board_mtd =
+            kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
+                    GFP_KERNEL);
+        if (!board_mtd) {
+                printk(KERN_WARNING
+                       "Unable to allocate NAND MTD device structure.\n");
+                return -ENOMEM;
+        }
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        if (!r)
+                return -ENXIO;
+
+        /* map physical adress */
+        bcm_umi_io_base = ioremap(r->start, r->end - r->start + 1);
+
+        if (!bcm_umi_io_base) {
+                printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
+                kfree(board_mtd);
+                return -EIO;
+        }
+
+        /* Get pointer to private data */
+        this = (struct nand_chip *)(&board_mtd[1]);
+
+        /* Initialize structures */
+        memset((char *)board_mtd, 0, sizeof(struct mtd_info));
+        memset((char *)this, 0, sizeof(struct nand_chip));
+
+        /* Link the private data with the MTD structure */
+        board_mtd->priv = this;
+
+        /* Initialize the NAND hardware.  */
+        if (bcm_umi_nand_inithw() < 0) {
+                printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
+                iounmap(bcm_umi_io_base);
+                kfree(board_mtd);
+                return -EIO;
+        }
+
+        /* Set address of NAND IO lines */
+        this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
+        this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
+
+        /* Set command delay time, see datasheet for correct value */
+        this->chip_delay = 0;
+        /* Assign the device ready function, if available */
+        this->dev_ready = nand_dev_ready;
+        this->options = 0;
+
+        this->write_buf = bcm_umi_nand_write_buf;
+        this->read_buf = bcm_umi_nand_read_buf;
+        this->verify_buf = bcm_umi_nand_verify_buf;
+
+        this->cmd_ctrl = bcm_umi_nand_hwcontrol;
+        this->ecc.mode = NAND_ECC_HW;
+        this->ecc.size = 512;
+        this->ecc.bytes = NAND_ECC_NUM_BYTES;
+#if NAND_ECC_BCH
+        this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
+        this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
+#else
+        this->ecc.correct = nand_correct_data512;
+        this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
+        this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
+#endif
+
+#if USE_DMA
+        err = nand_dma_init();
+        if (err != 0)
+                return err;
+#endif
+
+        /* Figure out the size of the device that we have.
+         * We need to do this to figure out which ECC
+         * layout we'll be using.
+         */
+
+        err = nand_scan_ident(board_mtd, 1);
+        if (err) {
+                printk(KERN_ERR "nand_scan failed: %d\n", err);
+                iounmap(bcm_umi_io_base);
+                kfree(board_mtd);
+                return err;
+        }
+
+        /* Now that we know the nand size, we can setup the ECC layout */
+
+        switch (board_mtd->writesize) { /* writesize is the pagesize */
+        case 4096:
+                this->ecc.layout = &nand_hw_eccoob_4096;
+                break;
+        case 2048:
+                this->ecc.layout = &nand_hw_eccoob_2048;
+                break;
+        case 512:
+                this->ecc.layout = &nand_hw_eccoob_512;
+                break;
+        default:
+                {
+                        printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
+                                         board_mtd->writesize);
+                        return -EINVAL;
+                }
+        }
+
+#if NAND_ECC_BCH
+        if (board_mtd->writesize > 512) {
+                if (this->options & NAND_USE_FLASH_BBT)
+                        largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
+                this->badblock_pattern = &largepage_bbt;
+        }
+#endif
+
+        /* Now finish off the scan, now that ecc.layout has been initialized. */
+
+        err = nand_scan_tail(board_mtd);
+        if (err) {
+                printk(KERN_ERR "nand_scan failed: %d\n", err);
+                iounmap(bcm_umi_io_base);
+                kfree(board_mtd);
+                return err;
+        }
+
+        /* Register the partitions */
+        {
+                int nr_partitions;
+                struct mtd_partition *partition_info;
+
+                board_mtd->name = "bcm_umi-nand";
+                nr_partitions =
+                    parse_mtd_partitions(board_mtd, part_probes,
+                                         &partition_info, 0);
+
+                if (nr_partitions <= 0) {
+                        printk(KERN_ERR "BCM UMI NAND: Too few partitions - %d\n",
+                               nr_partitions);
+                        iounmap(bcm_umi_io_base);
+                        kfree(board_mtd);
+                        return -EIO;
+                }
+                add_mtd_partitions(board_mtd, partition_info, nr_partitions);
+        }
+
+        /* Return happy */
+        return 0;
+}
+
+static int bcm_umi_nand_remove(struct platform_device *pdev)
+{
+#if USE_DMA
+        nand_dma_term();
+#endif
+
+        /* Release resources, unregister device */
+        nand_release(board_mtd);
+
+        /* unmap physical adress */
+        iounmap(bcm_umi_io_base);
+
+        /* Free the MTD device structure */
+        kfree(board_mtd);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int bcm_umi_nand_suspend(struct platform_device *pdev,
+                                pm_message_t state)
+{
+        printk(KERN_ERR "MTD NAND suspend is being called\n");
+        return 0;
+}
+
+static int bcm_umi_nand_resume(struct platform_device *pdev)
+{
+        printk(KERN_ERR "MTD NAND resume is being called\n");
+        return 0;
+}
+#else
+#define bcm_umi_nand_suspend   NULL
+#define bcm_umi_nand_resume    NULL
+#endif
+
+static struct platform_driver nand_driver = {
+        .driver = {
+                   .name = "bcm-nand",
+                   .owner = THIS_MODULE,
+                   },
+        .probe = bcm_umi_nand_probe,
+        .remove = bcm_umi_nand_remove,
+        .suspend = bcm_umi_nand_suspend,
+        .resume = bcm_umi_nand_resume,
+};
+
+static int __init nand_init(void)
+{
+        return platform_driver_register(&nand_driver);
+}
+
+static void __exit nand_exit(void)
+{
+        platform_driver_unregister(&nand_driver);
+}
+
+module_init(nand_init);
+module_exit(nand_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom");
+MODULE_DESCRIPTION("BCM UMI MTD NAND driver");
diff --git a/drivers/mtd/nand/nand_bcm_umi.c b/drivers/mtd/nand/nand_bcm_umi.c
new file mode 100644
index 000000000000..46a6bc9c4b74
--- /dev/null
+++ b/drivers/mtd/nand/nand_bcm_umi.c
@@ -0,0 +1,149 @@
+/*****************************************************************************
+* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/reg_umi.h>
+#include "nand_bcm_umi.h"
+#ifdef BOOT0_BUILD
+#include <uart.h>
+#endif
+
+/* ---- External Variable Declarations ----------------------------------- */
+/* ---- External Function Prototypes ------------------------------------- */
+/* ---- Public Variables ------------------------------------------------- */
+/* ---- Private Constants and Types -------------------------------------- */
+/* ---- Private Function Prototypes -------------------------------------- */
+/* ---- Private Variables ------------------------------------------------ */
+/* ---- Private Functions ------------------------------------------------ */
+
+#if NAND_ECC_BCH
+/****************************************************************************
+*  nand_bch_ecc_flip_bit - Routine to flip an errored bit
+*
+*  PURPOSE:
+*     This is a helper routine that flips the bit (0 -> 1 or 1 -> 0) of the
+*     errored bit specified
+*
+*  PARAMETERS:
+*     datap - Container that holds the 512 byte data
+*     errorLocation - Location of the bit that needs to be flipped
+*
+*  RETURNS:
+*     None
+****************************************************************************/
+static void nand_bcm_umi_bch_ecc_flip_bit(uint8_t *datap, int errorLocation)
+{
+        int locWithinAByte = (errorLocation & REG_UMI_BCH_ERR_LOC_BYTE) >> 0;
+        int locWithinAWord = (errorLocation & REG_UMI_BCH_ERR_LOC_WORD) >> 3;
+        int locWithinAPage = (errorLocation & REG_UMI_BCH_ERR_LOC_PAGE) >> 5;
+
+        uint8_t errorByte = 0;
+        uint8_t byteMask = 1 << locWithinAByte;
+
+        /* BCH uses big endian, need to change the location
+         * bits to little endian */
+        locWithinAWord = 3 - locWithinAWord;
+
+        errorByte = datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord];
+
+#ifdef BOOT0_BUILD
+        puthexs("\nECC Correct Offset: ",
+                locWithinAPage * sizeof(uint32_t) + locWithinAWord);
+        puthexs(" errorByte:", errorByte);
+        puthex8(" Bit: ", locWithinAByte);
+#endif
+
+        if (errorByte & byteMask) {
+                /* bit needs to be cleared */
+                errorByte &= ~byteMask;
+        } else {
+                /* bit needs to be set */
+                errorByte |= byteMask;
+        }
+
+        /* write back the value with the fixed bit */
+        datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord] = errorByte;
+}
+
+/****************************************************************************
+*  nand_correct_page_bch - Routine to correct bit errors when reading NAND
+*
+*  PURPOSE:
+*     This routine reads the BCH registers to determine if there are any bit
+*     errors during the read of the last 512 bytes of data + ECC bytes.  If
+*     errors exists, the routine fixes it.
+*
+*  PARAMETERS:
+*     datap - Container that holds the 512 byte data
+*
+*  RETURNS:
+*     0 or greater = Number of errors corrected
+*                    (No errors are found or errors have been fixed)
+*    -1 = Error(s) cannot be fixed
+****************************************************************************/
+int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
+                                  int numEccBytes)
+{
+        int numErrors;
+        int errorLocation;
+        int idx;
+        uint32_t regValue;
+
+        /* wait for read ECC to be valid */
+        regValue = nand_bcm_umi_bch_poll_read_ecc_calc();
+
+        /*
+         * read the control status register to determine if there
+         * are error'ed bits
+         * see if errors are correctible
+         */
+        if ((regValue & REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR) > 0) {
+                int i;
+
+                for (i = 0; i < numEccBytes; i++) {
+                        if (readEccData[i] != 0xff) {
+                                /* errors cannot be fixed, return -1 */
+                                return -1;
+                        }
+                }
+                /* If ECC is unprogrammed then we can't correct,
+                 * assume everything OK */
+                return 0;
+        }
+
+        if ((regValue & REG_UMI_BCH_CTRL_STATUS_CORR_ERR) == 0) {
+                /* no errors */
+                return 0;
+        }
+
+        /*
+         * Fix errored bits by doing the following:
+         * 1. Read the number of errors in the control and status register
+         * 2. Read the error location registers that corresponds to the number
+         *    of errors reported
+         * 3. Invert the bit in the data
+         */
+        numErrors = (regValue & REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR) >> 20;
+
+        for (idx = 0; idx < numErrors; idx++) {
+                errorLocation =
+                    REG_UMI_BCH_ERR_LOC_ADDR(idx) & REG_UMI_BCH_ERR_LOC_MASK;
+
+                /* Flip bit */
+                nand_bcm_umi_bch_ecc_flip_bit(datap, errorLocation);
+        }
+        /* Errors corrected */
+        return numErrors;
+}
+#endif
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
new file mode 100644
index 000000000000..7cec2cd97854
--- /dev/null
+++ b/drivers/mtd/nand/nand_bcm_umi.h
@@ -0,0 +1,358 @@
+/*****************************************************************************
+* Copyright 2003 - 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef NAND_BCM_UMI_H
+#define NAND_BCM_UMI_H
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/reg_umi.h>
+#include <mach/reg_nand.h>
+#include <cfg_global.h>
+
+/* ---- Constants and Types ---------------------------------------------- */
+#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
+#define NAND_ECC_BCH (CFG_GLOBAL_CHIP_REV > 0xA0)
+#else
+#define NAND_ECC_BCH 0
+#endif
+
+#define CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES       13
+
+#if NAND_ECC_BCH
+#ifdef BOOT0_BUILD
+#define NAND_ECC_NUM_BYTES 13
+#else
+#define NAND_ECC_NUM_BYTES CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES
+#endif
+#else
+#define NAND_ECC_NUM_BYTES 3
+#endif
+
+#define NAND_DATA_ACCESS_SIZE 512
+
+/* ---- Variable Externs ------------------------------------------ */
+/* ---- Function Prototypes --------------------------------------- */
+int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
+                                  int numEccBytes);
+
+/* Check in device is ready */
+static inline int nand_bcm_umi_dev_ready(void)
+{
+        return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
+}
+
+/* Wait until device is ready */
+static inline void nand_bcm_umi_wait_till_ready(void)
+{
+        while (nand_bcm_umi_dev_ready() == 0)
+                ;
+}
+
+/* Enable Hamming ECC */
+static inline void nand_bcm_umi_hamming_enable_hwecc(void)
+{
+        /* disable and reset ECC, 512 byte page */
+        REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
+                REG_UMI_NAND_ECC_CSR_256BYTE);
+        /* enable ECC */
+        REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
+}
+
+#if NAND_ECC_BCH
+/* BCH ECC specifics */
+#define ECC_BITS_PER_CORRECTABLE_BIT 13
+
+/* Enable BCH Read ECC */
+static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
+{
+        /* disable and reset ECC */
+        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+        /* Turn on ECC */
+        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+}
+
+/* Enable BCH Write ECC */
+static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
+{
+        /* disable and reset ECC */
+        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
+        /* Turn on ECC */
+        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
+}
+
+/* Config number of BCH ECC bytes */
+static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
+{
+        uint32_t nValue;
+        uint32_t tValue;
+        uint32_t kValue;
+        uint32_t numBits = numEccBytes * 8;
+
+        /* disable and reset ECC */
+        REG_UMI_BCH_CTRL_STATUS =
+            REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
+            REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+
+        /* Every correctible bit requires 13 ECC bits */
+        tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
+
+        /* Total data in number of bits for generating and computing BCH ECC */
+        nValue = (NAND_DATA_ACCESS_SIZE + numEccBytes) * 8;
+
+        /* K parameter is used internally.  K = N - (T * 13) */
+        kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
+
+        /* Write the settings */
+        REG_UMI_BCH_N = nValue;
+        REG_UMI_BCH_T = tValue;
+        REG_UMI_BCH_K = kValue;
+}
+
+/* Pause during ECC read calculation to skip bytes in OOB */
+static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
+{
+        REG_UMI_BCH_CTRL_STATUS =
+            REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
+            REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
+}
+
+/* Resume during ECC read calculation after skipping bytes in OOB */
+static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
+{
+        REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+}
+
+/* Poll read ECC calc to check when hardware completes */
+static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
+{
+        uint32_t regVal;
+
+        do {
+                /* wait for ECC to be valid */
+                regVal = REG_UMI_BCH_CTRL_STATUS;
+        } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
+
+        return regVal;
+}
+
+/* Poll write ECC calc to check when hardware completes */
+static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
+{
+        /* wait for ECC to be valid */
+        while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
+               == 0)
+                ;
+}
+
+/* Read the OOB and ECC, for kernel write OOB to a buffer */
+#if defined(__KERNEL__) && !defined(STANDALONE)
+static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
+        uint8_t *eccCalc, int numEccBytes, uint8_t *oobp)
+#else
+static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
+        uint8_t *eccCalc, int numEccBytes)
+#endif
+{
+        int eccPos = 0;
+        int numToRead = 16;     /* There are 16 bytes per sector in the OOB */
+
+        /* ECC is already paused when this function is called */
+
+        if (pageSize == NAND_DATA_ACCESS_SIZE) {
+                while (numToRead > numEccBytes) {
+                        /* skip free oob region */
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                        *oobp++ = REG_NAND_DATA8;
+#else
+                        REG_NAND_DATA8;
+#endif
+                        numToRead--;
+                }
+
+                /* read ECC bytes before BI */
+                nand_bcm_umi_bch_resume_read_ecc_calc();
+
+                while (numToRead > 11) {
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                        *oobp = REG_NAND_DATA8;
+                        eccCalc[eccPos++] = *oobp;
+                        oobp++;
+#else
+                        eccCalc[eccPos++] = REG_NAND_DATA8;
+#endif
+                }
+
+                nand_bcm_umi_bch_pause_read_ecc_calc();
+
+                if (numToRead == 11) {
+                        /* read BI */
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                        *oobp++ = REG_NAND_DATA8;
+#else
+                        REG_NAND_DATA8;
+#endif
+                        numToRead--;
+                }
+
+                /* read ECC bytes */
+                nand_bcm_umi_bch_resume_read_ecc_calc();
+                while (numToRead) {
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                        *oobp = REG_NAND_DATA8;
+                        eccCalc[eccPos++] = *oobp;
+                        oobp++;
+#else
+                        eccCalc[eccPos++] = REG_NAND_DATA8;
+#endif
+                        numToRead--;
+                }
+        } else {
+                /* skip BI */
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                *oobp++ = REG_NAND_DATA8;
+#else
+                REG_NAND_DATA8;
+#endif
+                numToRead--;
+
+                while (numToRead > numEccBytes) {
+                        /* skip free oob region */
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                        *oobp++ = REG_NAND_DATA8;
+#else
+                        REG_NAND_DATA8;
+#endif
+                        numToRead--;
+                }
+
+                /* read ECC bytes */
+                nand_bcm_umi_bch_resume_read_ecc_calc();
+                while (numToRead) {
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                        *oobp = REG_NAND_DATA8;
+                        eccCalc[eccPos++] = *oobp;
+                        oobp++;
+#else
+                        eccCalc[eccPos++] = REG_NAND_DATA8;
+#endif
+                        numToRead--;
+                }
+        }
+}
+
+/* Helper function to write ECC */
+static inline void NAND_BCM_UMI_ECC_WRITE(int numEccBytes, int eccBytePos,
+                                          uint8_t *oobp, uint8_t eccVal)
+{
+        if (eccBytePos <= numEccBytes)
+                *oobp = eccVal;
+}
+
+/* Write OOB with ECC */
+static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
+                                                 uint8_t *oobp, int numEccBytes)
+{
+        uint32_t eccVal = 0xffffffff;
+
+        /* wait for write ECC to be valid */
+        nand_bcm_umi_bch_poll_write_ecc_calc();
+
+        /*
+         ** Get the hardware ecc from the 32-bit result registers.
+         ** Read after 512 byte accesses. Format B3B2B1B0
+         ** where B3 = ecc3, etc.
+         */
+
+        if (pageSize == NAND_DATA_ACCESS_SIZE) {
+                /* Now fill in the ECC bytes */
+                if (numEccBytes >= 13)
+                        eccVal = REG_UMI_BCH_WR_ECC_3;
+
+                /* Usually we skip CM in oob[0,1] */
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
+                        (eccVal >> 16) & 0xff);
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[1],
+                        (eccVal >> 8) & 0xff);
+
+                /* Write ECC in oob[2,3,4] */
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[2],
+                        eccVal & 0xff); /* ECC 12 */
+
+                if (numEccBytes >= 9)
+                        eccVal = REG_UMI_BCH_WR_ECC_2;
+
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
+                        (eccVal >> 24) & 0xff); /* ECC11 */
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[4],
+                        (eccVal >> 16) & 0xff); /* ECC10 */
+
+                /* Always Skip BI in oob[5] */
+        } else {
+                /* Always Skip BI in oob[0] */
+
+                /* Now fill in the ECC bytes */
+                if (numEccBytes >= 13)
+                        eccVal = REG_UMI_BCH_WR_ECC_3;
+
+                /* Usually skip CM in oob[1,2] */
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
+                        (eccVal >> 16) & 0xff);
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[2],
+                        (eccVal >> 8) & 0xff);
+
+                /* Write ECC in oob[3-15] */
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[3],
+                        eccVal & 0xff); /* ECC12 */
+
+                if (numEccBytes >= 9)
+                        eccVal = REG_UMI_BCH_WR_ECC_2;
+
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
+                        (eccVal >> 24) & 0xff); /* ECC11 */
+                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[5],
+                        (eccVal >> 16) & 0xff); /* ECC10 */
+        }
+
+        /* Fill in the remainder of ECC locations */
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 10, &oobp[6],
+                (eccVal >> 8) & 0xff);  /* ECC9 */
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 9, &oobp[7],
+                eccVal & 0xff); /* ECC8 */
+
+        if (numEccBytes >= 5)
+                eccVal = REG_UMI_BCH_WR_ECC_1;
+
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
+                (eccVal >> 24) & 0xff); /* ECC7 */
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 7, &oobp[9],
+                (eccVal >> 16) & 0xff); /* ECC6 */
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 6, &oobp[10],
+                (eccVal >> 8) & 0xff);  /* ECC5 */
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 5, &oobp[11],
+                eccVal & 0xff); /* ECC4 */
+
+        if (numEccBytes >= 1)
+                eccVal = REG_UMI_BCH_WR_ECC_0;
+
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
+                (eccVal >> 24) & 0xff); /* ECC3 */
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 3, &oobp[13],
+                (eccVal >> 16) & 0xff); /* ECC2 */
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 2, &oobp[14],
+                (eccVal >> 8) & 0xff);  /* ECC1 */
+        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 1, &oobp[15],
+                eccVal & 0xff); /* ECC0 */
+}
+#endif
+
+#endif /* NAND_BCM_UMI_H */