drm/i915 invalidate indirect state pointers at end of ring exec

This is required by the spec, and without this some 3D programs will
hang after resume from RC6 we enable that.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

3 files changed, 17 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f19ffe87af3c..44af317731b6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -499,6 +499,13 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
                 }
         }
 
+
+        if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
+                BEGIN_LP_RING(2);
+                OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
+                OUT_RING(MI_NOOP);
+                ADVANCE_LP_RING();
+        }
         i915_emit_breadcrumb(dev);
 
         return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 97a35a42da28..21fd657663aa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -170,6 +170,7 @@
 #define   MI_NO_WRITE_FLUSH     (1 << 2)
 #define   MI_SCENE_COUNT        (1 << 3) /* just increment scene count */
 #define   MI_END_SCENE          (1 << 4) /* flush binner and incr scene count */
+#define   MI_INVALIDATE_ISP     (1 << 5) /* invalidate indirect state pointers */
 #define MI_BATCH_BUFFER_END     MI_INSTR(0x0a, 0)
 #define MI_REPORT_HEAD          MI_INSTR(0x07, 0)
 #define MI_OVERLAY_FLIP         MI_INSTR(0x11,0)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7823b9648176..51e9c9e718c4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -535,7 +535,16 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
                 intel_ring_advance(dev, ring);
         }
 
+        if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
+                intel_ring_begin(dev, ring, 2);
+                intel_ring_emit(dev, ring, MI_FLUSH |
+                                MI_NO_WRITE_FLUSH |
+                                MI_INVALIDATE_ISP );
+                intel_ring_emit(dev, ring, MI_NOOP);
+                intel_ring_advance(dev, ring);
+        }
         /* XXX breadcrumb */
+
         return 0;
 }