aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorArend van Spriel <arend@broadcom.com>2011-12-08 18:06:51 -0500
committerJohn W. Linville <linville@tuxdriver.com>2011-12-13 15:32:36 -0500
commit16d2812e9eaaa47ca952ea81e34b4f400c861dfc (patch)
tree503064675eafaf4d539ba57327532d4e1aa37722 /drivers
parent5204563ab841fbb5d6ef683635682e155a0a9e84 (diff)
brcm80211: smac: use bcma core register access functions for 802.11 core
The driver now uses the bcma register access functions to read and write the registers on the 802.11 core. The dma and phy code need to be modified next and access to the other cores. That will be done in coming patches. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/aiutils.c48
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/ampdu.c7
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/d11.h3
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/main.c479
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/main.h4
5 files changed, 274 insertions, 267 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
index 989dd3ed5b88..ef1441a9a4e0 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
@@ -504,6 +504,17 @@ static void ai_scan(struct si_pub *sih, struct bcma_bus *bus)
504 } 504 }
505} 505}
506 506
507static struct bcma_device *ai_find_bcma_core(struct si_pub *sih, uint coreidx)
508{
509 struct si_info *sii = (struct si_info *)sih;
510 struct bcma_device *core;
511
512 list_for_each_entry(core, &sii->icbus->cores, list) {
513 if (core->core_index == coreidx)
514 return core;
515 }
516 return NULL;
517}
507/* 518/*
508 * This function changes the logical "focus" to the indicated core. 519 * This function changes the logical "focus" to the indicated core.
509 * Return the current core's virtual address. Since each core starts with the 520 * Return the current core's virtual address. Since each core starts with the
@@ -514,18 +525,16 @@ static void ai_scan(struct si_pub *sih, struct bcma_bus *bus)
514void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx) 525void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx)
515{ 526{
516 struct si_info *sii = (struct si_info *)sih; 527 struct si_info *sii = (struct si_info *)sih;
517 u32 addr = sii->coresba[coreidx]; 528 struct bcma_device *core;
518 u32 wrap = sii->wrapba[coreidx];
519
520 if (coreidx >= sii->numcores)
521 return NULL;
522 529
523 /* point bar0 window */ 530 if (sii->curidx != coreidx) {
524 pci_write_config_dword(sii->pcibus, PCI_BAR0_WIN, addr); 531 core = ai_find_bcma_core(sih, coreidx);
525 /* point bar0 2nd 4KB window */ 532 if (core == NULL)
526 pci_write_config_dword(sii->pcibus, PCI_BAR0_WIN2, wrap); 533 return NULL;
527 sii->curidx = coreidx;
528 534
535 (void)bcma_aread32(core, BCMA_IOST);
536 sii->curidx = coreidx;
537 }
529 return sii->curmap; 538 return sii->curmap;
530} 539}
531 540
@@ -811,8 +820,6 @@ static struct si_info *ai_doattach(struct si_info *sii,
811 uint socitype; 820 uint socitype;
812 uint origidx; 821 uint origidx;
813 822
814 /* assume the window is looking at chipcommon */
815 WARN_ON(pbus->mapped_core->id.id != BCMA_CORE_CHIPCOMMON);
816 memset((unsigned char *) sii, 0, sizeof(struct si_info)); 823 memset((unsigned char *) sii, 0, sizeof(struct si_info));
817 824
818 savewin = 0; 825 savewin = 0;
@@ -823,13 +830,10 @@ static struct si_info *ai_doattach(struct si_info *sii,
823 sii->curmap = regs; 830 sii->curmap = regs;
824 sii->curwrap = sii->curmap + SI_CORE_SIZE; 831 sii->curwrap = sii->curmap + SI_CORE_SIZE;
825 832
826 /* find Chipcommon address */ 833 /* switch to Chipcommon core */
827 pci_read_config_dword(sii->pcibus, PCI_BAR0_WIN, &savewin); 834 bcma_read32(pbus->drv_cc.core, 0);
828 if (!GOODCOREADDR(savewin, SI_ENUM_BASE)) 835 savewin = SI_ENUM_BASE;
829 savewin = SI_ENUM_BASE;
830 836
831 pci_write_config_dword(sii->pcibus, PCI_BAR0_WIN,
832 SI_ENUM_BASE);
833 cc = (struct chipcregs __iomem *) regs; 837 cc = (struct chipcregs __iomem *) regs;
834 838
835 /* bus/core/clk setup for register access */ 839 /* bus/core/clk setup for register access */
@@ -1036,18 +1040,18 @@ bool ai_backplane64(struct si_pub *sih)
1036/* return index of coreid or BADIDX if not found */ 1040/* return index of coreid or BADIDX if not found */
1037uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit) 1041uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit)
1038{ 1042{
1043 struct bcma_device *core;
1039 struct si_info *sii; 1044 struct si_info *sii;
1040 uint found; 1045 uint found;
1041 uint i;
1042 1046
1043 sii = (struct si_info *)sih; 1047 sii = (struct si_info *)sih;
1044 1048
1045 found = 0; 1049 found = 0;
1046 1050
1047 for (i = 0; i < sii->numcores; i++) 1051 list_for_each_entry(core, &sii->icbus->cores, list)
1048 if (sii->coreid[i] == coreid) { 1052 if (core->id.id == coreid) {
1049 if (found == coreunit) 1053 if (found == coreunit)
1050 return i; 1054 return core->core_index;
1051 found++; 1055 found++;
1052 } 1056 }
1053 1057
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c b/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c
index 43f7a724dda8..90911eec0cf5 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c
@@ -1118,14 +1118,17 @@ brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
1118 u8 status_delay = 0; 1118 u8 status_delay = 0;
1119 1119
1120 /* wait till the next 8 bytes of txstatus is available */ 1120 /* wait till the next 8 bytes of txstatus is available */
1121 while (((s1 = R_REG(&wlc->regs->frmtxstatus)) & TXS_V) == 0) { 1121 s1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(frmtxstatus));
1122 while ((s1 & TXS_V) == 0) {
1122 udelay(1); 1123 udelay(1);
1123 status_delay++; 1124 status_delay++;
1124 if (status_delay > 10) 1125 if (status_delay > 10)
1125 return; /* error condition */ 1126 return; /* error condition */
1127 s1 = bcma_read32(wlc->hw->d11core,
1128 D11REGOFFS(frmtxstatus));
1126 } 1129 }
1127 1130
1128 s2 = R_REG(&wlc->regs->frmtxstatus2); 1131 s2 = bcma_read32(wlc->hw->d11core, D11REGOFFS(frmtxstatus2));
1129 } 1132 }
1130 1133
1131 if (scb) { 1134 if (scb) {
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/d11.h b/drivers/net/wireless/brcm80211/brcmsmac/d11.h
index ed51616abc85..1948cb2771e9 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/d11.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/d11.h
@@ -430,6 +430,9 @@ struct d11regs {
430 u16 PAD[0x380]; /* 0x800 - 0xEFE */ 430 u16 PAD[0x380]; /* 0x800 - 0xEFE */
431}; 431};
432 432
433/* d11 register field offset */
434#define D11REGOFFS(field) offsetof(struct d11regs, field)
435
433#define PIHR_BASE 0x0400 /* byte address of packed IHR region */ 436#define PIHR_BASE 0x0400 /* byte address of packed IHR region */
434 437
435/* biststatus */ 438/* biststatus */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.c b/drivers/net/wireless/brcm80211/brcmsmac/main.c
index 73bc0ab78320..f4a64652fdab 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
@@ -388,10 +388,13 @@ static u16 get_sifs(struct brcms_band *band)
388 */ 388 */
389static bool brcms_deviceremoved(struct brcms_c_info *wlc) 389static bool brcms_deviceremoved(struct brcms_c_info *wlc)
390{ 390{
391 u32 macctrl;
392
391 if (!wlc->hw->clk) 393 if (!wlc->hw->clk)
392 return ai_deviceremoved(wlc->hw->sih); 394 return ai_deviceremoved(wlc->hw->sih);
393 return (R_REG(&wlc->hw->regs->maccontrol) & 395 macctrl = bcma_read32(wlc->hw->d11core,
394 (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN; 396 D11REGOFFS(maccontrol));
397 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
395} 398}
396 399
397/* sum the individual fifo tx pending packet counts */ 400/* sum the individual fifo tx pending packet counts */
@@ -582,17 +585,15 @@ brcms_c_attach_malloc(uint unit, uint *err, uint devid)
582static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw, 585static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
583 bool shortslot) 586 bool shortslot)
584{ 587{
585 struct d11regs __iomem *regs; 588 struct bcma_device *core = wlc_hw->d11core;
586
587 regs = wlc_hw->regs;
588 589
589 if (shortslot) { 590 if (shortslot) {
590 /* 11g short slot: 11a timing */ 591 /* 11g short slot: 11a timing */
591 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */ 592 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
592 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME); 593 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
593 } else { 594 } else {
594 /* 11g long slot: 11b timing */ 595 /* 11g long slot: 11b timing */
595 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */ 596 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
596 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME); 597 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
597 } 598 }
598} 599}
@@ -672,24 +673,22 @@ static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
672static void brcms_c_write_inits(struct brcms_hardware *wlc_hw, 673static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
673 const struct d11init *inits) 674 const struct d11init *inits)
674{ 675{
676 struct bcma_device *core = wlc_hw->d11core;
675 int i; 677 int i;
676 u8 __iomem *base; 678 uint offset;
677 u8 __iomem *addr;
678 u16 size; 679 u16 size;
679 u32 value; 680 u32 value;
680 681
681 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 682 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
682 683
683 base = (u8 __iomem *)wlc_hw->regs;
684
685 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) { 684 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
686 size = le16_to_cpu(inits[i].size); 685 size = le16_to_cpu(inits[i].size);
687 addr = base + le16_to_cpu(inits[i].addr); 686 offset = le16_to_cpu(inits[i].addr);
688 value = le32_to_cpu(inits[i].value); 687 value = le32_to_cpu(inits[i].value);
689 if (size == 2) 688 if (size == 2)
690 W_REG((u16 __iomem *)addr, value); 689 bcma_write16(core, offset, value);
691 else if (size == 4) 690 else if (size == 4)
692 W_REG((u32 __iomem *)addr, value); 691 bcma_write32(core, offset, value);
693 else 692 else
694 break; 693 break;
695 } 694 }
@@ -788,10 +787,12 @@ static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
788{ 787{
789 struct brcms_hardware *wlc_hw = wlc->hw; 788 struct brcms_hardware *wlc_hw = wlc->hw;
790 u32 macintmask; 789 u32 macintmask;
790 u32 macctrl;
791 791
792 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 792 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
793 793 macctrl = bcma_read32(wlc_hw->d11core,
794 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0); 794 D11REGOFFS(maccontrol));
795 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
795 796
796 /* disable interrupts */ 797 /* disable interrupts */
797 macintmask = brcms_intrsoff(wlc->wl); 798 macintmask = brcms_intrsoff(wlc->wl);
@@ -982,7 +983,7 @@ brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
982{ 983{
983 bool morepending = false; 984 bool morepending = false;
984 struct brcms_c_info *wlc = wlc_hw->wlc; 985 struct brcms_c_info *wlc = wlc_hw->wlc;
985 struct d11regs __iomem *regs; 986 struct bcma_device *core;
986 struct tx_status txstatus, *txs; 987 struct tx_status txstatus, *txs;
987 u32 s1, s2; 988 u32 s1, s2;
988 uint n = 0; 989 uint n = 0;
@@ -995,18 +996,18 @@ brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
995 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 996 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
996 997
997 txs = &txstatus; 998 txs = &txstatus;
998 regs = wlc_hw->regs; 999 core = wlc_hw->d11core;
999 *fatal = false; 1000 *fatal = false;
1001 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1000 while (!(*fatal) 1002 while (!(*fatal)
1001 && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) { 1003 && (s1 & TXS_V)) {
1002 1004
1003 if (s1 == 0xffffffff) { 1005 if (s1 == 0xffffffff) {
1004 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", 1006 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
1005 wlc_hw->unit, __func__); 1007 wlc_hw->unit, __func__);
1006 return morepending; 1008 return morepending;
1007 } 1009 }
1008 1010 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1009 s2 = R_REG(&regs->frmtxstatus2);
1010 1011
1011 txs->status = s1 & TXS_STATUS_MASK; 1012 txs->status = s1 & TXS_STATUS_MASK;
1012 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT; 1013 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
@@ -1019,6 +1020,7 @@ brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1019 /* !give others some time to run! */ 1020 /* !give others some time to run! */
1020 if (++n >= max_tx_num) 1021 if (++n >= max_tx_num)
1021 break; 1022 break;
1023 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1022 } 1024 }
1023 1025
1024 if (*fatal) 1026 if (*fatal)
@@ -1066,9 +1068,11 @@ brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1066static struct dma64regs __iomem * 1068static struct dma64regs __iomem *
1067dmareg(struct brcms_hardware *hw, uint direction, uint fifonum) 1069dmareg(struct brcms_hardware *hw, uint direction, uint fifonum)
1068{ 1070{
1071 struct d11regs __iomem *regs = hw->d11core->bus->mmio;
1072
1069 if (direction == DMA_TX) 1073 if (direction == DMA_TX)
1070 return &(hw->regs->fifo64regs[fifonum].dmaxmt); 1074 return &(regs->fifo64regs[fifonum].dmaxmt);
1071 return &(hw->regs->fifo64regs[fifonum].dmarcv); 1075 return &(regs->fifo64regs[fifonum].dmarcv);
1072} 1076}
1073 1077
1074static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme) 1078static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
@@ -1214,29 +1218,33 @@ static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
1214 1218
1215 if (wlc_hw->clk) { 1219 if (wlc_hw->clk) {
1216 if (mode == CLK_FAST) { 1220 if (mode == CLK_FAST) {
1217 OR_REG(&wlc_hw->regs->clk_ctl_st, 1221 bcma_set32(wlc_hw->d11core,
1218 CCS_FORCEHT); 1222 D11REGOFFS(clk_ctl_st),
1223 CCS_FORCEHT);
1219 1224
1220 udelay(64); 1225 udelay(64);
1221 1226
1222 SPINWAIT(((R_REG 1227 SPINWAIT(
1223 (&wlc_hw->regs-> 1228 ((bcma_read32(wlc_hw->d11core,
1224 clk_ctl_st) & CCS_HTAVAIL) == 0), 1229 D11REGOFFS(clk_ctl_st)) &
1225 PMU_MAX_TRANSITION_DLY); 1230 CCS_HTAVAIL) == 0),
1226 WARN_ON(!(R_REG 1231 PMU_MAX_TRANSITION_DLY);
1227 (&wlc_hw->regs-> 1232 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1228 clk_ctl_st) & CCS_HTAVAIL)); 1233 D11REGOFFS(clk_ctl_st)) &
1234 CCS_HTAVAIL));
1229 } else { 1235 } else {
1230 if ((ai_get_pmurev(wlc_hw->sih) == 0) && 1236 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1231 (R_REG 1237 (bcma_read32(wlc_hw->d11core,
1232 (&wlc_hw->regs-> 1238 D11REGOFFS(clk_ctl_st)) &
1233 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ))) 1239 (CCS_FORCEHT | CCS_HTAREQ)))
1234 SPINWAIT(((R_REG 1240 SPINWAIT(
1235 (&wlc_hw->regs-> 1241 ((bcma_read32(wlc_hw->d11core,
1236 clk_ctl_st) & CCS_HTAVAIL) 1242 offsetof(struct d11regs,
1237 == 0), 1243 clk_ctl_st)) &
1238 PMU_MAX_TRANSITION_DLY); 1244 CCS_HTAVAIL) == 0),
1239 AND_REG(&wlc_hw->regs->clk_ctl_st, 1245 PMU_MAX_TRANSITION_DLY);
1246 bcma_mask32(wlc_hw->d11core,
1247 D11REGOFFS(clk_ctl_st),
1240 ~CCS_FORCEHT); 1248 ~CCS_FORCEHT);
1241 } 1249 }
1242 } 1250 }
@@ -1368,7 +1376,8 @@ static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1368 maccontrol |= MCTL_INFRA; 1376 maccontrol |= MCTL_INFRA;
1369 } 1377 }
1370 1378
1371 W_REG(&wlc_hw->regs->maccontrol, maccontrol); 1379 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1380 maccontrol);
1372} 1381}
1373 1382
1374/* set or clear maccontrol bits */ 1383/* set or clear maccontrol bits */
@@ -1462,7 +1471,7 @@ static void
1462brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset, 1471brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1463 const u8 *addr) 1472 const u8 *addr)
1464{ 1473{
1465 struct d11regs __iomem *regs; 1474 struct bcma_device *core = wlc_hw->d11core;
1466 u16 mac_l; 1475 u16 mac_l;
1467 u16 mac_m; 1476 u16 mac_m;
1468 u16 mac_h; 1477 u16 mac_h;
@@ -1470,38 +1479,36 @@ brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1470 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n", 1479 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1471 wlc_hw->unit); 1480 wlc_hw->unit);
1472 1481
1473 regs = wlc_hw->regs;
1474 mac_l = addr[0] | (addr[1] << 8); 1482 mac_l = addr[0] | (addr[1] << 8);
1475 mac_m = addr[2] | (addr[3] << 8); 1483 mac_m = addr[2] | (addr[3] << 8);
1476 mac_h = addr[4] | (addr[5] << 8); 1484 mac_h = addr[4] | (addr[5] << 8);
1477 1485
1478 /* enter the MAC addr into the RXE match registers */ 1486 /* enter the MAC addr into the RXE match registers */
1479 W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset); 1487 bcma_write16(core, D11REGOFFS(rcm_ctl),
1480 W_REG(&regs->rcm_mat_data, mac_l); 1488 RCM_INC_DATA | match_reg_offset);
1481 W_REG(&regs->rcm_mat_data, mac_m); 1489 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1482 W_REG(&regs->rcm_mat_data, mac_h); 1490 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1483 1491 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1484} 1492}
1485 1493
1486void 1494void
1487brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len, 1495brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1488 void *buf) 1496 void *buf)
1489{ 1497{
1490 struct d11regs __iomem *regs; 1498 struct bcma_device *core = wlc_hw->d11core;
1491 u32 word; 1499 u32 word;
1492 __le32 word_le; 1500 __le32 word_le;
1493 __be32 word_be; 1501 __be32 word_be;
1494 bool be_bit; 1502 bool be_bit;
1495 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1503 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1496 1504
1497 regs = wlc_hw->regs; 1505 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1498 W_REG(&regs->tplatewrptr, offset);
1499 1506
1500 /* if MCTL_BIGEND bit set in mac control register, 1507 /* if MCTL_BIGEND bit set in mac control register,
1501 * the chip swaps data in fifo, as well as data in 1508 * the chip swaps data in fifo, as well as data in
1502 * template ram 1509 * template ram
1503 */ 1510 */
1504 be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0; 1511 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1505 1512
1506 while (len > 0) { 1513 while (len > 0) {
1507 memcpy(&word, buf, sizeof(u32)); 1514 memcpy(&word, buf, sizeof(u32));
@@ -1514,7 +1521,7 @@ brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1514 word = *(u32 *)&word_le; 1521 word = *(u32 *)&word_le;
1515 } 1522 }
1516 1523
1517 W_REG(&regs->tplatewrdata, word); 1524 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1518 1525
1519 buf = (u8 *) buf + sizeof(u32); 1526 buf = (u8 *) buf + sizeof(u32);
1520 len -= sizeof(u32); 1527 len -= sizeof(u32);
@@ -1525,18 +1532,20 @@ static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1525{ 1532{
1526 wlc_hw->band->CWmin = newmin; 1533 wlc_hw->band->CWmin = newmin;
1527 1534
1528 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN); 1535 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1529 (void)R_REG(&wlc_hw->regs->objaddr); 1536 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1530 W_REG(&wlc_hw->regs->objdata, newmin); 1537 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1538 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1531} 1539}
1532 1540
1533static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax) 1541static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1534{ 1542{
1535 wlc_hw->band->CWmax = newmax; 1543 wlc_hw->band->CWmax = newmax;
1536 1544
1537 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX); 1545 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1538 (void)R_REG(&wlc_hw->regs->objaddr); 1546 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1539 W_REG(&wlc_hw->regs->objdata, newmax); 1547 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1548 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1540} 1549}
1541 1550
1542void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw) 1551void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
@@ -1815,7 +1824,8 @@ static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1815 brcms_intrsrestore(wlc->wl, macintmask); 1824 brcms_intrsrestore(wlc->wl, macintmask);
1816 1825
1817 /* ucode should still be suspended.. */ 1826 /* ucode should still be suspended.. */
1818 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0); 1827 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1828 MCTL_EN_MAC) != 0);
1819} 1829}
1820 1830
1821static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw) 1831static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
@@ -1937,13 +1947,14 @@ static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1937 */ 1947 */
1938 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) || 1948 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
1939 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) 1949 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
1940 wlc_hw->regs = (struct d11regs __iomem *) 1950 (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
1941 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 1951
1942 ai_core_reset(wlc_hw->sih, flags, resetbits); 1952 ai_core_reset(wlc_hw->sih, flags, resetbits);
1943 brcms_c_mctrl_reset(wlc_hw); 1953 brcms_c_mctrl_reset(wlc_hw);
1944 } 1954 }
1945 1955
1946 v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0); 1956 v = ((bcma_read32(wlc_hw->d11core,
1957 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1947 1958
1948 /* put core back into reset */ 1959 /* put core back into reset */
1949 if (!clk) 1960 if (!clk)
@@ -1971,7 +1982,6 @@ static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1971 */ 1982 */
1972void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags) 1983void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1973{ 1984{
1974 struct d11regs __iomem *regs;
1975 uint i; 1985 uint i;
1976 bool fastclk; 1986 bool fastclk;
1977 u32 resetbits = 0; 1987 u32 resetbits = 0;
@@ -1981,8 +1991,6 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1981 1991
1982 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1992 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1983 1993
1984 regs = wlc_hw->regs;
1985
1986 /* request FAST clock if not on */ 1994 /* request FAST clock if not on */
1987 fastclk = wlc_hw->forcefastclk; 1995 fastclk = wlc_hw->forcefastclk;
1988 if (!fastclk) 1996 if (!fastclk)
@@ -2055,7 +2063,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2055 */ 2063 */
2056static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw) 2064static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2057{ 2065{
2058 struct d11regs __iomem *regs = wlc_hw->regs; 2066 struct bcma_device *core = wlc_hw->d11core;
2059 u16 fifo_nu; 2067 u16 fifo_nu;
2060 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk; 2068 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2061 u16 txfifo_def, txfifo_def1; 2069 u16 txfifo_def, txfifo_def1;
@@ -2076,11 +2084,11 @@ static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2076 txfifo_cmd = 2084 txfifo_cmd =
2077 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT); 2085 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2078 2086
2079 W_REG(&regs->xmtfifocmd, txfifo_cmd); 2087 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2080 W_REG(&regs->xmtfifodef, txfifo_def); 2088 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2081 W_REG(&regs->xmtfifodef1, txfifo_def1); 2089 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2082 2090
2083 W_REG(&regs->xmtfifocmd, txfifo_cmd); 2091 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2084 2092
2085 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu]; 2093 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2086 } 2094 }
@@ -2115,27 +2123,27 @@ static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2115 2123
2116void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode) 2124void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2117{ 2125{
2118 struct d11regs __iomem *regs = wlc_hw->regs; 2126 struct bcma_device *core = wlc_hw->d11core;
2119 2127
2120 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) || 2128 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
2121 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) { 2129 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) {
2122 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */ 2130 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2123 W_REG(&regs->tsf_clk_frac_l, 0x2082); 2131 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2124 W_REG(&regs->tsf_clk_frac_h, 0x8); 2132 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2125 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */ 2133 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2126 W_REG(&regs->tsf_clk_frac_l, 0x5341); 2134 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2127 W_REG(&regs->tsf_clk_frac_h, 0x8); 2135 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2128 } else { /* 120Mhz */ 2136 } else { /* 120Mhz */
2129 W_REG(&regs->tsf_clk_frac_l, 0x8889); 2137 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2130 W_REG(&regs->tsf_clk_frac_h, 0x8); 2138 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2131 } 2139 }
2132 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2140 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2133 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */ 2141 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2134 W_REG(&regs->tsf_clk_frac_l, 0x7CE0); 2142 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2135 W_REG(&regs->tsf_clk_frac_h, 0xC); 2143 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2136 } else { /* 80Mhz */ 2144 } else { /* 80Mhz */
2137 W_REG(&regs->tsf_clk_frac_l, 0xCCCD); 2145 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2138 W_REG(&regs->tsf_clk_frac_h, 0xC); 2146 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2139 } 2147 }
2140 } 2148 }
2141} 2149}
@@ -2144,11 +2152,8 @@ void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2144static void brcms_c_gpio_init(struct brcms_c_info *wlc) 2152static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2145{ 2153{
2146 struct brcms_hardware *wlc_hw = wlc->hw; 2154 struct brcms_hardware *wlc_hw = wlc->hw;
2147 struct d11regs __iomem *regs;
2148 u32 gc, gm; 2155 u32 gc, gm;
2149 2156
2150 regs = wlc_hw->regs;
2151
2152 /* use GPIO select 0 to get all gpio signals from the gpio out reg */ 2157 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2153 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0); 2158 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2154 2159
@@ -2179,10 +2184,10 @@ static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2179 * The board itself is powered by these GPIOs 2184 * The board itself is powered by these GPIOs
2180 * (when not sending pattern) so set them high 2185 * (when not sending pattern) so set them high
2181 */ 2186 */
2182 OR_REG(&regs->psm_gpio_oe, 2187 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2183 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2188 (BOARD_GPIO_12 | BOARD_GPIO_13));
2184 OR_REG(&regs->psm_gpio_out, 2189 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2185 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2190 (BOARD_GPIO_12 | BOARD_GPIO_13));
2186 2191
2187 /* Enable antenna diversity, use 2x4 mode */ 2192 /* Enable antenna diversity, use 2x4 mode */
2188 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2193 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
@@ -2209,7 +2214,7 @@ static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2209static void brcms_ucode_write(struct brcms_hardware *wlc_hw, 2214static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2210 const __le32 ucode[], const size_t nbytes) 2215 const __le32 ucode[], const size_t nbytes)
2211{ 2216{
2212 struct d11regs __iomem *regs = wlc_hw->regs; 2217 struct bcma_device *core = wlc_hw->d11core;
2213 uint i; 2218 uint i;
2214 uint count; 2219 uint count;
2215 2220
@@ -2217,10 +2222,11 @@ static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2217 2222
2218 count = (nbytes / sizeof(u32)); 2223 count = (nbytes / sizeof(u32));
2219 2224
2220 W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL)); 2225 bcma_write32(core, D11REGOFFS(objaddr),
2221 (void)R_REG(&regs->objaddr); 2226 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2227 (void)bcma_read32(core, D11REGOFFS(objaddr));
2222 for (i = 0; i < count; i++) 2228 for (i = 0; i < count; i++)
2223 W_REG(&regs->objdata, le32_to_cpu(ucode[i])); 2229 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2224 2230
2225} 2231}
2226 2232
@@ -2286,7 +2292,7 @@ static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2286 bool fatal = false; 2292 bool fatal = false;
2287 uint unit; 2293 uint unit;
2288 uint intstatus, idx; 2294 uint intstatus, idx;
2289 struct d11regs __iomem *regs = wlc_hw->regs; 2295 struct bcma_device *core = wlc_hw->d11core;
2290 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 2296 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2291 2297
2292 unit = wlc_hw->unit; 2298 unit = wlc_hw->unit;
@@ -2294,7 +2300,9 @@ static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2294 for (idx = 0; idx < NFIFO; idx++) { 2300 for (idx = 0; idx < NFIFO; idx++) {
2295 /* read intstatus register and ignore any non-error bits */ 2301 /* read intstatus register and ignore any non-error bits */
2296 intstatus = 2302 intstatus =
2297 R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS; 2303 bcma_read32(core,
2304 D11REGOFFS(intctrlregs[idx].intstatus)) &
2305 I_ERRORS;
2298 if (!intstatus) 2306 if (!intstatus)
2299 continue; 2307 continue;
2300 2308
@@ -2339,8 +2347,9 @@ static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2339 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */ 2347 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2340 break; 2348 break;
2341 } else 2349 } else
2342 W_REG(&regs->intctrlregs[idx].intstatus, 2350 bcma_write32(core,
2343 intstatus); 2351 D11REGOFFS(intctrlregs[idx].intstatus),
2352 intstatus);
2344 } 2353 }
2345} 2354}
2346 2355
@@ -2348,7 +2357,7 @@ void brcms_c_intrson(struct brcms_c_info *wlc)
2348{ 2357{
2349 struct brcms_hardware *wlc_hw = wlc->hw; 2358 struct brcms_hardware *wlc_hw = wlc->hw;
2350 wlc->macintmask = wlc->defmacintmask; 2359 wlc->macintmask = wlc->defmacintmask;
2351 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask); 2360 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2352} 2361}
2353 2362
2354/* 2363/*
@@ -2382,8 +2391,8 @@ u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2382 2391
2383 macintmask = wlc->macintmask; /* isr can still happen */ 2392 macintmask = wlc->macintmask; /* isr can still happen */
2384 2393
2385 W_REG(&wlc_hw->regs->macintmask, 0); 2394 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2386 (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */ 2395 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2387 udelay(1); /* ensure int line is no longer driven */ 2396 udelay(1); /* ensure int line is no longer driven */
2388 wlc->macintmask = 0; 2397 wlc->macintmask = 0;
2389 2398
@@ -2398,7 +2407,7 @@ void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2398 return; 2407 return;
2399 2408
2400 wlc->macintmask = macintmask; 2409 wlc->macintmask = macintmask;
2401 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask); 2410 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2402} 2411}
2403 2412
2404/* assumes that the d11 MAC is enabled */ 2413/* assumes that the d11 MAC is enabled */
@@ -2510,11 +2519,11 @@ brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2510static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr) 2519static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2511{ 2520{
2512 struct brcms_hardware *wlc_hw = wlc->hw; 2521 struct brcms_hardware *wlc_hw = wlc->hw;
2513 struct d11regs __iomem *regs = wlc_hw->regs; 2522 struct bcma_device *core = wlc_hw->d11core;
2514 u32 macintstatus; 2523 u32 macintstatus;
2515 2524
2516 /* macintstatus includes a DMA interrupt summary bit */ 2525 /* macintstatus includes a DMA interrupt summary bit */
2517 macintstatus = R_REG(&regs->macintstatus); 2526 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2518 2527
2519 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit, 2528 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2520 macintstatus); 2529 macintstatus);
@@ -2541,12 +2550,12 @@ static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2541 * consequences 2550 * consequences
2542 */ 2551 */
2543 /* turn off the interrupts */ 2552 /* turn off the interrupts */
2544 W_REG(&regs->macintmask, 0); 2553 bcma_write32(core, D11REGOFFS(macintmask), 0);
2545 (void)R_REG(&regs->macintmask); /* sync readback */ 2554 (void)bcma_read32(core, D11REGOFFS(macintmask));
2546 wlc->macintmask = 0; 2555 wlc->macintmask = 0;
2547 2556
2548 /* clear device interrupts */ 2557 /* clear device interrupts */
2549 W_REG(&regs->macintstatus, macintstatus); 2558 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2550 2559
2551 /* MI_DMAINT is indication of non-zero intstatus */ 2560 /* MI_DMAINT is indication of non-zero intstatus */
2552 if (macintstatus & MI_DMAINT) 2561 if (macintstatus & MI_DMAINT)
@@ -2555,8 +2564,8 @@ static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2555 * RX_FIFO. If MI_DMAINT is set, assume it 2564 * RX_FIFO. If MI_DMAINT is set, assume it
2556 * is set and clear the interrupt. 2565 * is set and clear the interrupt.
2557 */ 2566 */
2558 W_REG(&regs->intctrlregs[RX_FIFO].intstatus, 2567 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2559 DEF_RXINTMASK); 2568 DEF_RXINTMASK);
2560 2569
2561 return macintstatus; 2570 return macintstatus;
2562} 2571}
@@ -2619,7 +2628,7 @@ bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2619void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc) 2628void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2620{ 2629{
2621 struct brcms_hardware *wlc_hw = wlc->hw; 2630 struct brcms_hardware *wlc_hw = wlc->hw;
2622 struct d11regs __iomem *regs = wlc_hw->regs; 2631 struct bcma_device *core = wlc_hw->d11core;
2623 u32 mc, mi; 2632 u32 mc, mi;
2624 struct wiphy *wiphy = wlc->wiphy; 2633 struct wiphy *wiphy = wlc->wiphy;
2625 2634
@@ -2636,7 +2645,7 @@ void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2636 /* force the core awake */ 2645 /* force the core awake */
2637 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2646 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2638 2647
2639 mc = R_REG(&regs->maccontrol); 2648 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2640 2649
2641 if (mc == 0xffffffff) { 2650 if (mc == 0xffffffff) {
2642 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2651 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
@@ -2648,7 +2657,7 @@ void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2648 WARN_ON(!(mc & MCTL_PSM_RUN)); 2657 WARN_ON(!(mc & MCTL_PSM_RUN));
2649 WARN_ON(!(mc & MCTL_EN_MAC)); 2658 WARN_ON(!(mc & MCTL_EN_MAC));
2650 2659
2651 mi = R_REG(&regs->macintstatus); 2660 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2652 if (mi == 0xffffffff) { 2661 if (mi == 0xffffffff) {
2653 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2662 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2654 __func__); 2663 __func__);
@@ -2659,21 +2668,21 @@ void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2659 2668
2660 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0); 2669 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2661 2670
2662 SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD), 2671 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2663 BRCMS_MAX_MAC_SUSPEND); 2672 BRCMS_MAX_MAC_SUSPEND);
2664 2673
2665 if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) { 2674 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2666 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS" 2675 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2667 " and MI_MACSSPNDD is still not on.\n", 2676 " and MI_MACSSPNDD is still not on.\n",
2668 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND); 2677 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2669 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, " 2678 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2670 "psm_brc 0x%04x\n", wlc_hw->unit, 2679 "psm_brc 0x%04x\n", wlc_hw->unit,
2671 R_REG(&regs->psmdebug), 2680 bcma_read32(core, D11REGOFFS(psmdebug)),
2672 R_REG(&regs->phydebug), 2681 bcma_read32(core, D11REGOFFS(phydebug)),
2673 R_REG(&regs->psm_brc)); 2682 bcma_read16(core, D11REGOFFS(psm_brc)));
2674 } 2683 }
2675 2684
2676 mc = R_REG(&regs->maccontrol); 2685 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2677 if (mc == 0xffffffff) { 2686 if (mc == 0xffffffff) {
2678 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2687 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2679 __func__); 2688 __func__);
@@ -2688,7 +2697,7 @@ void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2688void brcms_c_enable_mac(struct brcms_c_info *wlc) 2697void brcms_c_enable_mac(struct brcms_c_info *wlc)
2689{ 2698{
2690 struct brcms_hardware *wlc_hw = wlc->hw; 2699 struct brcms_hardware *wlc_hw = wlc->hw;
2691 struct d11regs __iomem *regs = wlc_hw->regs; 2700 struct bcma_device *core = wlc_hw->d11core;
2692 u32 mc, mi; 2701 u32 mc, mi;
2693 2702
2694 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 2703 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
@@ -2701,20 +2710,20 @@ void brcms_c_enable_mac(struct brcms_c_info *wlc)
2701 if (wlc_hw->mac_suspend_depth > 0) 2710 if (wlc_hw->mac_suspend_depth > 0)
2702 return; 2711 return;
2703 2712
2704 mc = R_REG(&regs->maccontrol); 2713 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2705 WARN_ON(mc & MCTL_PSM_JMP_0); 2714 WARN_ON(mc & MCTL_PSM_JMP_0);
2706 WARN_ON(mc & MCTL_EN_MAC); 2715 WARN_ON(mc & MCTL_EN_MAC);
2707 WARN_ON(!(mc & MCTL_PSM_RUN)); 2716 WARN_ON(!(mc & MCTL_PSM_RUN));
2708 2717
2709 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC); 2718 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2710 W_REG(&regs->macintstatus, MI_MACSSPNDD); 2719 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2711 2720
2712 mc = R_REG(&regs->maccontrol); 2721 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2713 WARN_ON(mc & MCTL_PSM_JMP_0); 2722 WARN_ON(mc & MCTL_PSM_JMP_0);
2714 WARN_ON(!(mc & MCTL_EN_MAC)); 2723 WARN_ON(!(mc & MCTL_EN_MAC));
2715 WARN_ON(!(mc & MCTL_PSM_RUN)); 2724 WARN_ON(!(mc & MCTL_PSM_RUN));
2716 2725
2717 mi = R_REG(&regs->macintstatus); 2726 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2718 WARN_ON(mi & MI_MACSSPNDD); 2727 WARN_ON(mi & MI_MACSSPNDD);
2719 2728
2720 brcms_c_ucode_wake_override_clear(wlc_hw, 2729 brcms_c_ucode_wake_override_clear(wlc_hw,
@@ -2731,55 +2740,53 @@ void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2731 2740
2732static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw) 2741static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2733{ 2742{
2734 struct d11regs __iomem *regs; 2743 struct bcma_device *core = wlc_hw->d11core;
2735 u32 w, val; 2744 u32 w, val;
2736 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 2745 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2737 2746
2738 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit); 2747 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
2739 2748
2740 regs = wlc_hw->regs;
2741
2742 /* Validate dchip register access */ 2749 /* Validate dchip register access */
2743 2750
2744 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0); 2751 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2745 (void)R_REG(&regs->objaddr); 2752 (void)bcma_read32(core, D11REGOFFS(objaddr));
2746 w = R_REG(&regs->objdata); 2753 w = bcma_read32(core, D11REGOFFS(objdata));
2747 2754
2748 /* Can we write and read back a 32bit register? */ 2755 /* Can we write and read back a 32bit register? */
2749 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0); 2756 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2750 (void)R_REG(&regs->objaddr); 2757 (void)bcma_read32(core, D11REGOFFS(objaddr));
2751 W_REG(&regs->objdata, (u32) 0xaa5555aa); 2758 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2752 2759
2753 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0); 2760 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2754 (void)R_REG(&regs->objaddr); 2761 (void)bcma_read32(core, D11REGOFFS(objaddr));
2755 val = R_REG(&regs->objdata); 2762 val = bcma_read32(core, D11REGOFFS(objdata));
2756 if (val != (u32) 0xaa5555aa) { 2763 if (val != (u32) 0xaa5555aa) {
2757 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2764 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2758 "expected 0xaa5555aa\n", wlc_hw->unit, val); 2765 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2759 return false; 2766 return false;
2760 } 2767 }
2761 2768
2762 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0); 2769 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2763 (void)R_REG(&regs->objaddr); 2770 (void)bcma_read32(core, D11REGOFFS(objaddr));
2764 W_REG(&regs->objdata, (u32) 0x55aaaa55); 2771 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2765 2772
2766 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0); 2773 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2767 (void)R_REG(&regs->objaddr); 2774 (void)bcma_read32(core, D11REGOFFS(objaddr));
2768 val = R_REG(&regs->objdata); 2775 val = bcma_read32(core, D11REGOFFS(objdata));
2769 if (val != (u32) 0x55aaaa55) { 2776 if (val != (u32) 0x55aaaa55) {
2770 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2777 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2771 "expected 0x55aaaa55\n", wlc_hw->unit, val); 2778 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2772 return false; 2779 return false;
2773 } 2780 }
2774 2781
2775 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0); 2782 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2776 (void)R_REG(&regs->objaddr); 2783 (void)bcma_read32(core, D11REGOFFS(objaddr));
2777 W_REG(&regs->objdata, w); 2784 bcma_write32(core, D11REGOFFS(objdata), w);
2778 2785
2779 /* clear CFPStart */ 2786 /* clear CFPStart */
2780 W_REG(&regs->tsf_cfpstart, 0); 2787 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2781 2788
2782 w = R_REG(&regs->maccontrol); 2789 w = bcma_read32(core, D11REGOFFS(maccontrol));
2783 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) && 2790 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2784 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) { 2791 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2785 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = " 2792 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
@@ -2796,38 +2803,38 @@ static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2796 2803
2797void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on) 2804void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2798{ 2805{
2799 struct d11regs __iomem *regs; 2806 struct bcma_device *core = wlc_hw->d11core;
2800 u32 tmp; 2807 u32 tmp;
2801 2808
2802 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 2809 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2803 2810
2804 tmp = 0; 2811 tmp = 0;
2805 regs = wlc_hw->regs;
2806 2812
2807 if (on) { 2813 if (on) {
2808 if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) { 2814 if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
2809 OR_REG(&regs->clk_ctl_st, 2815 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2810 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL | 2816 CCS_ERSRC_REQ_HT |
2811 CCS_ERSRC_REQ_PHYPLL)); 2817 CCS_ERSRC_REQ_D11PLL |
2812 SPINWAIT((R_REG(&regs->clk_ctl_st) & 2818 CCS_ERSRC_REQ_PHYPLL);
2813 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT), 2819 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2820 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2814 PHYPLL_WAIT_US); 2821 PHYPLL_WAIT_US);
2815 2822
2816 tmp = R_REG(&regs->clk_ctl_st); 2823 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2817 if ((tmp & (CCS_ERSRC_AVAIL_HT)) != 2824 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2818 (CCS_ERSRC_AVAIL_HT))
2819 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY" 2825 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
2820 " PLL failed\n", __func__); 2826 " PLL failed\n", __func__);
2821 } else { 2827 } else {
2822 OR_REG(&regs->clk_ctl_st, 2828 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2823 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL)); 2829 tmp | CCS_ERSRC_REQ_D11PLL |
2824 SPINWAIT((R_REG(&regs->clk_ctl_st) & 2830 CCS_ERSRC_REQ_PHYPLL);
2831 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2825 (CCS_ERSRC_AVAIL_D11PLL | 2832 (CCS_ERSRC_AVAIL_D11PLL |
2826 CCS_ERSRC_AVAIL_PHYPLL)) != 2833 CCS_ERSRC_AVAIL_PHYPLL)) !=
2827 (CCS_ERSRC_AVAIL_D11PLL | 2834 (CCS_ERSRC_AVAIL_D11PLL |
2828 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US); 2835 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2829 2836
2830 tmp = R_REG(&regs->clk_ctl_st); 2837 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2831 if ((tmp & 2838 if ((tmp &
2832 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2839 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2833 != 2840 !=
@@ -2841,8 +2848,9 @@ void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2841 * be requesting it; so we'll deassert the request but 2848 * be requesting it; so we'll deassert the request but
2842 * not wait for status to comply. 2849 * not wait for status to comply.
2843 */ 2850 */
2844 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL); 2851 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2845 tmp = R_REG(&regs->clk_ctl_st); 2852 ~CCS_ERSRC_REQ_PHYPLL);
2853 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2846 } 2854 }
2847} 2855}
2848 2856
@@ -2894,35 +2902,31 @@ static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2894static u16 2902static u16
2895brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel) 2903brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2896{ 2904{
2897 struct d11regs __iomem *regs = wlc_hw->regs; 2905 struct bcma_device *core = wlc_hw->d11core;
2898 u16 __iomem *objdata_lo = (u16 __iomem *)&regs->objdata; 2906 u16 objoff = D11REGOFFS(objdata);
2899 u16 __iomem *objdata_hi = objdata_lo + 1;
2900 u16 v;
2901 2907
2902 W_REG(&regs->objaddr, sel | (offset >> 2)); 2908 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2903 (void)R_REG(&regs->objaddr); 2909 (void)bcma_read32(core, D11REGOFFS(objaddr));
2904 if (offset & 2) 2910 if (offset & 2)
2905 v = R_REG(objdata_hi); 2911 objoff += 2;
2906 else
2907 v = R_REG(objdata_lo);
2908 2912
2909 return v; 2913 return bcma_read16(core, objoff);
2914;
2910} 2915}
2911 2916
2912static void 2917static void
2913brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v, 2918brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2914 u32 sel) 2919 u32 sel)
2915{ 2920{
2916 struct d11regs __iomem *regs = wlc_hw->regs; 2921 struct bcma_device *core = wlc_hw->d11core;
2917 u16 __iomem *objdata_lo = (u16 __iomem *)&regs->objdata; 2922 u16 objoff = D11REGOFFS(objdata);
2918 u16 __iomem *objdata_hi = objdata_lo + 1;
2919 2923
2920 W_REG(&regs->objaddr, sel | (offset >> 2)); 2924 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2921 (void)R_REG(&regs->objaddr); 2925 (void)bcma_read32(core, D11REGOFFS(objaddr));
2922 if (offset & 2) 2926 if (offset & 2)
2923 W_REG(objdata_hi, v); 2927 objoff += 2;
2924 else 2928
2925 W_REG(objdata_lo, v); 2929 bcma_write16(core, objoff, v);
2926} 2930}
2927 2931
2928/* 2932/*
@@ -3008,14 +3012,14 @@ static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3008 3012
3009 /* write retry limit to SCR, shouldn't need to suspend */ 3013 /* write retry limit to SCR, shouldn't need to suspend */
3010 if (wlc_hw->up) { 3014 if (wlc_hw->up) {
3011 W_REG(&wlc_hw->regs->objaddr, 3015 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3012 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3016 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3013 (void)R_REG(&wlc_hw->regs->objaddr); 3017 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3014 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL); 3018 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3015 W_REG(&wlc_hw->regs->objaddr, 3019 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3016 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3020 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3017 (void)R_REG(&wlc_hw->regs->objaddr); 3021 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3018 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL); 3022 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3019 } 3023 }
3020} 3024}
3021 3025
@@ -3197,9 +3201,9 @@ void brcms_c_init_scb(struct scb *scb)
3197static void brcms_b_coreinit(struct brcms_c_info *wlc) 3201static void brcms_b_coreinit(struct brcms_c_info *wlc)
3198{ 3202{
3199 struct brcms_hardware *wlc_hw = wlc->hw; 3203 struct brcms_hardware *wlc_hw = wlc->hw;
3200 struct d11regs __iomem *regs; 3204 struct bcma_device *core = wlc_hw->d11core;
3201 u32 sflags; 3205 u32 sflags;
3202 uint bcnint_us; 3206 u32 bcnint_us;
3203 uint i = 0; 3207 uint i = 0;
3204 bool fifosz_fixup = false; 3208 bool fifosz_fixup = false;
3205 int err = 0; 3209 int err = 0;
@@ -3207,8 +3211,6 @@ static void brcms_b_coreinit(struct brcms_c_info *wlc)
3207 struct wiphy *wiphy = wlc->wiphy; 3211 struct wiphy *wiphy = wlc->wiphy;
3208 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 3212 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3209 3213
3210 regs = wlc_hw->regs;
3211
3212 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 3214 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3213 3215
3214 /* reset PSM */ 3216 /* reset PSM */
@@ -3221,14 +3223,14 @@ static void brcms_b_coreinit(struct brcms_c_info *wlc)
3221 fifosz_fixup = true; 3223 fifosz_fixup = true;
3222 3224
3223 /* let the PSM run to the suspended state, set mode to BSS STA */ 3225 /* let the PSM run to the suspended state, set mode to BSS STA */
3224 W_REG(&regs->macintstatus, -1); 3226 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3225 brcms_b_mctrl(wlc_hw, ~0, 3227 brcms_b_mctrl(wlc_hw, ~0,
3226 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE)); 3228 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3227 3229
3228 /* wait for ucode to self-suspend after auto-init */ 3230 /* wait for ucode to self-suspend after auto-init */
3229 SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0), 3231 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3230 1000 * 1000); 3232 MI_MACSSPNDD) == 0), 1000 * 1000);
3231 if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0) 3233 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3232 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-" 3234 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
3233 "suspend!\n", wlc_hw->unit); 3235 "suspend!\n", wlc_hw->unit);
3234 3236
@@ -3298,7 +3300,7 @@ static void brcms_b_coreinit(struct brcms_c_info *wlc)
3298 wlc_hw->xmtfifo_sz[i], i); 3300 wlc_hw->xmtfifo_sz[i], i);
3299 3301
3300 /* make sure we can still talk to the mac */ 3302 /* make sure we can still talk to the mac */
3301 WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff); 3303 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3302 3304
3303 /* band-specific inits done by wlc_bsinit() */ 3305 /* band-specific inits done by wlc_bsinit() */
3304 3306
@@ -3307,7 +3309,7 @@ static void brcms_b_coreinit(struct brcms_c_info *wlc)
3307 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT); 3309 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3308 3310
3309 /* enable one rx interrupt per received frame */ 3311 /* enable one rx interrupt per received frame */
3310 W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT)); 3312 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3311 3313
3312 /* set the station mode (BSS STA) */ 3314 /* set the station mode (BSS STA) */
3313 brcms_b_mctrl(wlc_hw, 3315 brcms_b_mctrl(wlc_hw,
@@ -3316,19 +3318,21 @@ static void brcms_b_coreinit(struct brcms_c_info *wlc)
3316 3318
3317 /* set up Beacon interval */ 3319 /* set up Beacon interval */
3318 bcnint_us = 0x8000 << 10; 3320 bcnint_us = 0x8000 << 10;
3319 W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT)); 3321 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3320 W_REG(&regs->tsf_cfpstart, bcnint_us); 3322 (bcnint_us << CFPREP_CBI_SHIFT));
3321 W_REG(&regs->macintstatus, MI_GP1); 3323 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3324 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3322 3325
3323 /* write interrupt mask */ 3326 /* write interrupt mask */
3324 W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK); 3327 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3328 DEF_RXINTMASK);
3325 3329
3326 /* allow the MAC to control the PHY clock (dynamic on/off) */ 3330 /* allow the MAC to control the PHY clock (dynamic on/off) */
3327 brcms_b_macphyclk_set(wlc_hw, ON); 3331 brcms_b_macphyclk_set(wlc_hw, ON);
3328 3332
3329 /* program dynamic clock control fast powerup delay register */ 3333 /* program dynamic clock control fast powerup delay register */
3330 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih); 3334 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3331 W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly); 3335 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3332 3336
3333 /* tell the ucode the corerev */ 3337 /* tell the ucode the corerev */
3334 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev); 3338 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
@@ -3341,19 +3345,21 @@ static void brcms_b_coreinit(struct brcms_c_info *wlc)
3341 machwcap >> 16) & 0xffff)); 3345 machwcap >> 16) & 0xffff));
3342 3346
3343 /* write retry limits to SCR, this done after PSM init */ 3347 /* write retry limits to SCR, this done after PSM init */
3344 W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3348 bcma_write32(core, D11REGOFFS(objaddr),
3345 (void)R_REG(&regs->objaddr); 3349 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3346 W_REG(&regs->objdata, wlc_hw->SRL); 3350 (void)bcma_read32(core, D11REGOFFS(objaddr));
3347 W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3351 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3348 (void)R_REG(&regs->objaddr); 3352 bcma_write32(core, D11REGOFFS(objaddr),
3349 W_REG(&regs->objdata, wlc_hw->LRL); 3353 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3354 (void)bcma_read32(core, D11REGOFFS(objaddr));
3355 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3350 3356
3351 /* write rate fallback retry limits */ 3357 /* write rate fallback retry limits */
3352 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL); 3358 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3353 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL); 3359 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3354 3360
3355 AND_REG(&regs->ifs_ctl, 0x0FFF); 3361 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3356 W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN); 3362 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3357 3363
3358 /* init the tx dma engines */ 3364 /* init the tx dma engines */
3359 for (i = 0; i < NFIFO; i++) { 3365 for (i = 0; i < NFIFO; i++) {
@@ -3810,7 +3816,7 @@ static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3810 3816
3811 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps); 3817 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
3812 3818
3813 v1 = R_REG(&wlc->regs->maccontrol); 3819 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3814 v2 = MCTL_WAKE; 3820 v2 = MCTL_WAKE;
3815 if (hps) 3821 if (hps)
3816 v2 |= MCTL_HPS; 3822 v2 |= MCTL_HPS;
@@ -4129,7 +4135,8 @@ void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4129 acp_shm.cwmax = params->cw_max; 4135 acp_shm.cwmax = params->cw_max;
4130 acp_shm.cwcur = acp_shm.cwmin; 4136 acp_shm.cwcur = acp_shm.cwmin;
4131 acp_shm.bslots = 4137 acp_shm.bslots =
4132 R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur; 4138 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4139 acp_shm.cwcur;
4133 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs; 4140 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4134 /* Indicate the new params to the ucode */ 4141 /* Indicate the new params to the ucode */
4135 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO + 4142 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
@@ -4441,7 +4448,6 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4441 uint unit, bool piomode) 4448 uint unit, bool piomode)
4442{ 4449{
4443 struct brcms_hardware *wlc_hw; 4450 struct brcms_hardware *wlc_hw;
4444 struct d11regs __iomem *regs;
4445 char *macaddr = NULL; 4451 char *macaddr = NULL;
4446 uint err = 0; 4452 uint err = 0;
4447 uint j; 4453 uint j;
@@ -4490,13 +4496,9 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4490 wlc_hw->deviceid = pcidev->device; 4496 wlc_hw->deviceid = pcidev->device;
4491 4497
4492 /* set bar0 window to point at D11 core */ 4498 /* set bar0 window to point at D11 core */
4493 wlc_hw->regs = (struct d11regs __iomem *) 4499 (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
4494 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 4500 wlc_hw->d11core = core;
4495 wlc_hw->corerev = ai_corerev(wlc_hw->sih); 4501 wlc_hw->corerev = core->id.rev;
4496
4497 regs = wlc_hw->regs;
4498
4499 wlc->regs = wlc_hw->regs;
4500 4502
4501 /* validate chip, chiprev and corerev */ 4503 /* validate chip, chiprev and corerev */
4502 if (!brcms_c_isgoodchip(wlc_hw)) { 4504 if (!brcms_c_isgoodchip(wlc_hw)) {
@@ -4617,7 +4619,7 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4617 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4619 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4618 wlc->core->coreidx = ai_coreidx(wlc_hw->sih); 4620 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
4619 4621
4620 wlc_hw->machwcap = R_REG(&regs->machwcap); 4622 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4621 wlc_hw->machwcap_backup = wlc_hw->machwcap; 4623 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4622 4624
4623 /* init tx fifo size */ 4625 /* init tx fifo size */
@@ -4626,7 +4628,7 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4626 4628
4627 /* Get a phy for this band */ 4629 /* Get a phy for this band */
4628 wlc_hw->band->pi = 4630 wlc_hw->band->pi =
4629 wlc_phy_attach(wlc_hw->phy_sh, regs, 4631 wlc_phy_attach(wlc_hw->phy_sh, core->bus->mmio,
4630 wlc_hw->band->bandtype, 4632 wlc_hw->band->bandtype,
4631 wlc->wiphy); 4633 wlc->wiphy);
4632 if (wlc_hw->band->pi == NULL) { 4634 if (wlc_hw->band->pi == NULL) {
@@ -5074,8 +5076,7 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5074 */ 5076 */
5075 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) || 5077 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
5076 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) 5078 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
5077 wlc_hw->regs = (struct d11regs __iomem *) 5079 (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
5078 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
5079 5080
5080 /* 5081 /*
5081 * Inform phy that a POR reset has occurred so 5082 * Inform phy that a POR reset has occurred so
@@ -5320,8 +5321,8 @@ static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5320 5321
5321 /* Reset and disable the core */ 5322 /* Reset and disable the core */
5322 if (ai_iscoreup(wlc_hw->sih)) { 5323 if (ai_iscoreup(wlc_hw->sih)) {
5323 if (R_REG(&wlc_hw->regs->maccontrol) & 5324 if (bcma_read32(wlc_hw->d11core,
5324 MCTL_EN_MAC) 5325 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5325 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 5326 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5326 callbacks += brcms_reset(wlc_hw->wlc->wl); 5327 callbacks += brcms_reset(wlc_hw->wlc->wl);
5327 brcms_c_coredisable(wlc_hw); 5328 brcms_c_coredisable(wlc_hw);
@@ -7478,11 +7479,11 @@ static void
7478brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr, 7479brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7479 u32 *tsf_h_ptr) 7480 u32 *tsf_h_ptr)
7480{ 7481{
7481 struct d11regs __iomem *regs = wlc_hw->regs; 7482 struct bcma_device *core = wlc_hw->d11core;
7482 7483
7483 /* read the tsf timer low, then high to get an atomic read */ 7484 /* read the tsf timer low, then high to get an atomic read */
7484 *tsf_l_ptr = R_REG(&regs->tsf_timerlow); 7485 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7485 *tsf_h_ptr = R_REG(&regs->tsf_timerhigh); 7486 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7486} 7487}
7487 7488
7488/* 7489/*
@@ -8155,7 +8156,7 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8155{ 8156{
8156 u32 macintstatus; 8157 u32 macintstatus;
8157 struct brcms_hardware *wlc_hw = wlc->hw; 8158 struct brcms_hardware *wlc_hw = wlc->hw;
8158 struct d11regs __iomem *regs = wlc_hw->regs; 8159 struct bcma_device *core = wlc_hw->d11core;
8159 struct wiphy *wiphy = wlc->wiphy; 8160 struct wiphy *wiphy = wlc->wiphy;
8160 8161
8161 if (brcms_deviceremoved(wlc)) { 8162 if (brcms_deviceremoved(wlc)) {
@@ -8191,7 +8192,7 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8191 /* ATIM window end */ 8192 /* ATIM window end */
8192 if (macintstatus & MI_ATIMWINEND) { 8193 if (macintstatus & MI_ATIMWINEND) {
8193 BCMMSG(wlc->wiphy, "end of ATIM window\n"); 8194 BCMMSG(wlc->wiphy, "end of ATIM window\n");
8194 OR_REG(&regs->maccommand, wlc->qvalid); 8195 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
8195 wlc->qvalid = 0; 8196 wlc->qvalid = 0;
8196 } 8197 }
8197 8198
@@ -8219,7 +8220,7 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8219 8220
8220 /* gptimer timeout */ 8221 /* gptimer timeout */
8221 if (macintstatus & MI_TO) 8222 if (macintstatus & MI_TO)
8222 W_REG(&regs->gptimer, 0); 8223 bcma_write32(core, D11REGOFFS(gptimer), 0);
8223 8224
8224 if (macintstatus & MI_RFDISABLE) { 8225 if (macintstatus & MI_RFDISABLE) {
8225 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the" 8226 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
@@ -8241,13 +8242,11 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8241 8242
8242void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx) 8243void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8243{ 8244{
8244 struct d11regs __iomem *regs; 8245 struct bcma_device *core = wlc->hw->d11core;
8245 u16 chanspec; 8246 u16 chanspec;
8246 8247
8247 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 8248 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8248 8249
8249 regs = wlc->regs;
8250
8251 /* 8250 /*
8252 * This will happen if a big-hammer was executed. In 8251 * This will happen if a big-hammer was executed. In
8253 * that case, we want to go back to the channel that 8252 * that case, we want to go back to the channel that
@@ -8277,8 +8276,8 @@ void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8277 * update since init path would reset 8276 * update since init path would reset
8278 * to default value 8277 * to default value
8279 */ 8278 */
8280 W_REG(&regs->tsf_cfprep, 8279 bcma_write32(core, D11REGOFFS(tsf_cfprep),
8281 (bi << CFPREP_CBI_SHIFT)); 8280 bi << CFPREP_CBI_SHIFT);
8282 8281
8283 /* Update maccontrol PM related bits */ 8282 /* Update maccontrol PM related bits */
8284 brcms_c_set_ps_ctrl(wlc); 8283 brcms_c_set_ps_ctrl(wlc);
@@ -8308,7 +8307,7 @@ void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8308 brcms_c_bsinit(wlc); 8307 brcms_c_bsinit(wlc);
8309 8308
8310 /* Enable EDCF mode (while the MAC is suspended) */ 8309 /* Enable EDCF mode (while the MAC is suspended) */
8311 OR_REG(&regs->ifs_ctl, IFS_USEEDCF); 8310 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
8312 brcms_c_edcf_setparams(wlc, false); 8311 brcms_c_edcf_setparams(wlc, false);
8313 8312
8314 /* Init precedence maps for empty FIFOs */ 8313 /* Init precedence maps for empty FIFOs */
@@ -8332,7 +8331,7 @@ void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8332 brcms_c_txflowcontrol_reset(wlc); 8331 brcms_c_txflowcontrol_reset(wlc);
8333 8332
8334 /* enable the RF Disable Delay timer */ 8333 /* enable the RF Disable Delay timer */
8335 W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT); 8334 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
8336 8335
8337 /* 8336 /*
8338 * Initialize WME parameters; if they haven't been set by some other 8337 * Initialize WME parameters; if they haven't been set by some other
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.h b/drivers/net/wireless/brcm80211/brcmsmac/main.h
index e2de97d93635..adb136ec1f04 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.h
@@ -334,7 +334,7 @@ struct brcms_hardware {
334 u32 machwcap_backup; /* backup of machwcap */ 334 u32 machwcap_backup; /* backup of machwcap */
335 335
336 struct si_pub *sih; /* SI handle (cookie for siutils calls) */ 336 struct si_pub *sih; /* SI handle (cookie for siutils calls) */
337 struct d11regs __iomem *regs; /* pointer to device registers */ 337 struct bcma_device *d11core; /* pointer to 802.11 core */
338 struct phy_shim_info *physhim; /* phy shim layer handler */ 338 struct phy_shim_info *physhim; /* phy shim layer handler */
339 struct shared_phy *phy_sh; /* pointer to shared phy state */ 339 struct shared_phy *phy_sh; /* pointer to shared phy state */
340 struct brcms_hw_band *band;/* pointer to active per-band state */ 340 struct brcms_hw_band *band;/* pointer to active per-band state */
@@ -400,7 +400,6 @@ struct brcms_txq_info {
400 * 400 *
401 * pub: pointer to driver public state. 401 * pub: pointer to driver public state.
402 * wl: pointer to specific private state. 402 * wl: pointer to specific private state.
403 * regs: pointer to device registers.
404 * hw: HW related state. 403 * hw: HW related state.
405 * clkreq_override: setting for clkreq for PCIE : Auto, 0, 1. 404 * clkreq_override: setting for clkreq for PCIE : Auto, 0, 1.
406 * fastpwrup_dly: time in us needed to bring up d11 fast clock. 405 * fastpwrup_dly: time in us needed to bring up d11 fast clock.
@@ -477,7 +476,6 @@ struct brcms_txq_info {
477struct brcms_c_info { 476struct brcms_c_info {
478 struct brcms_pub *pub; 477 struct brcms_pub *pub;
479 struct brcms_info *wl; 478 struct brcms_info *wl;
480 struct d11regs __iomem *regs;
481 struct brcms_hardware *hw; 479 struct brcms_hardware *hw;
482 480
483 /* clock */ 481 /* clock */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 23:20:37 -0400