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authorRong Wang <Rong.Wang@csr.com>2011-11-17 10:17:04 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-11-17 14:46:04 -0500
commit161e773cbd0c3d1b5b8cc00602e1f72de61ed4f7 (patch)
treec31ed7e2197786518060938d1d01d64f78125356 /drivers
parent8b3ffa173ffa13ac47c1d7524af92d4b2c95abfc (diff)
UART: add CSR SiRFprimaII SoC on-chip uart drivers
SiRFprimaII is the latest generation application processor from CSR’s multi-function SoC product family. The SoC support codes are in arch/arm/mach-prima2 from Linux mainline 3.0. There are three dedicated UARTs in system. This patch adds basic driver support for them. It has used the newest pinmux subsystem from Linus Walleij. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rong Wang <Rong.Wang@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/tty/serial/Kconfig21
-rw-r--r--drivers/tty/serial/Makefile1
-rw-r--r--drivers/tty/serial/sirfsoc_uart.c783
-rw-r--r--drivers/tty/serial/sirfsoc_uart.h185
4 files changed, 990 insertions, 0 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 3d86bdaee047..45c5758f7690 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -535,6 +535,27 @@ config SERIAL_S5PV210
535 help 535 help
536 Serial port support for Samsung's S5P Family of SoC's 536 Serial port support for Samsung's S5P Family of SoC's
537 537
538config SERIAL_SIRFSOC
539 tristate "SiRF SoC Platform Serial port support"
540 depends on ARM && ARCH_PRIMA2
541 select SERIAL_CORE
542 help
543 Support for the on-chip UART on the CSR SiRFprimaII series,
544 providing /dev/ttySiRF0, 1 and 2 (note, some machines may not
545 provide all of these ports, depending on how the serial port
546 pins are configured).
547
548config SERIAL_SIRFSOC_CONSOLE
549 bool "Support for console on SiRF SoC serial port"
550 depends on SERIAL_SIRFSOC=y
551 select SERIAL_CORE_CONSOLE
552 help
553 Even if you say Y here, the currently visible virtual console
554 (/dev/tty0) will still be used as the system console by default, but
555 you can alter that using a kernel command line option such as
556 "console=ttySiRFx". (Try "man bootparam" or see the documentation of
557 your boot loader about how to pass options to the kernel at
558 boot time.)
538 559
539config SERIAL_MAX3100 560config SERIAL_MAX3100
540 tristate "MAX3100 support" 561 tristate "MAX3100 support"
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index e10cf5b54b6d..af57089ddb67 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o
94obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o 94obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
95obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o 95obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
96obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o 96obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
97obj-$(CONFIG_SERIAL_SIRFSOC) += sirfsoc_uart.o
diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c
new file mode 100644
index 000000000000..a60523fee11b
--- /dev/null
+++ b/drivers/tty/serial/sirfsoc_uart.c
@@ -0,0 +1,783 @@
1/*
2 * Driver for CSR SiRFprimaII onboard UARTs.
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/ioport.h>
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/sysrq.h>
14#include <linux/console.h>
15#include <linux/tty.h>
16#include <linux/tty_flip.h>
17#include <linux/serial_core.h>
18#include <linux/serial.h>
19#include <linux/clk.h>
20#include <linux/of.h>
21#include <linux/slab.h>
22#include <linux/io.h>
23#include <asm/irq.h>
24#include <asm/mach/irq.h>
25#include <linux/pinctrl/pinmux.h>
26
27#include "sirfsoc_uart.h"
28
29static unsigned int
30sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
31static unsigned int
32sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
33static struct uart_driver sirfsoc_uart_drv;
34
35static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
36 {4000000, 2359296},
37 {3500000, 1310721},
38 {3000000, 1572865},
39 {2500000, 1245186},
40 {2000000, 1572866},
41 {1500000, 1245188},
42 {1152000, 1638404},
43 {1000000, 1572869},
44 {921600, 1114120},
45 {576000, 1245196},
46 {500000, 1245198},
47 {460800, 1572876},
48 {230400, 1310750},
49 {115200, 1310781},
50 {57600, 1310843},
51 {38400, 1114328},
52 {19200, 1114545},
53 {9600, 1114979},
54};
55
56static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
57 [0] = {
58 .port = {
59 .iotype = UPIO_MEM,
60 .flags = UPF_BOOT_AUTOCONF,
61 .line = 0,
62 },
63 },
64 [1] = {
65 .port = {
66 .iotype = UPIO_MEM,
67 .flags = UPF_BOOT_AUTOCONF,
68 .line = 1,
69 },
70 },
71 [2] = {
72 .port = {
73 .iotype = UPIO_MEM,
74 .flags = UPF_BOOT_AUTOCONF,
75 .line = 2,
76 },
77 },
78};
79
80static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
81{
82 return container_of(port, struct sirfsoc_uart_port, port);
83}
84
85static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
86{
87 unsigned long reg;
88 reg = rd_regl(port, SIRFUART_TX_FIFO_STATUS);
89 if (reg & SIRFUART_FIFOEMPTY_MASK(port))
90 return TIOCSER_TEMT;
91 else
92 return 0;
93}
94
95static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
96{
97 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
98 if (!(sirfport->ms_enabled)) {
99 goto cts_asserted;
100 } else if (sirfport->hw_flow_ctrl) {
101 if (!(rd_regl(port, SIRFUART_AFC_CTRL) &
102 SIRFUART_CTS_IN_STATUS))
103 goto cts_asserted;
104 else
105 goto cts_deasserted;
106 }
107cts_deasserted:
108 return TIOCM_CAR | TIOCM_DSR;
109cts_asserted:
110 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
111}
112
113static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
114{
115 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
116 unsigned int assert = mctrl & TIOCM_RTS;
117 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
118 unsigned int current_val;
119 if (sirfport->hw_flow_ctrl) {
120 current_val = rd_regl(port, SIRFUART_AFC_CTRL) & ~0xFF;
121 val |= current_val;
122 wr_regl(port, SIRFUART_AFC_CTRL, val);
123 }
124}
125
126static void sirfsoc_uart_stop_tx(struct uart_port *port)
127{
128 unsigned int regv;
129 regv = rd_regl(port, SIRFUART_INT_EN);
130 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_TX_INT_EN);
131}
132
133void sirfsoc_uart_start_tx(struct uart_port *port)
134{
135 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
136 unsigned long regv;
137 sirfsoc_uart_pio_tx_chars(sirfport, 1);
138 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_START);
139 regv = rd_regl(port, SIRFUART_INT_EN);
140 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_TX_INT_EN);
141}
142
143static void sirfsoc_uart_stop_rx(struct uart_port *port)
144{
145 unsigned long regv;
146 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
147 regv = rd_regl(port, SIRFUART_INT_EN);
148 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_RX_IO_INT_EN);
149}
150
151static void sirfsoc_uart_disable_ms(struct uart_port *port)
152{
153 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
154 unsigned long reg;
155 sirfport->ms_enabled = 0;
156 if (!sirfport->hw_flow_ctrl)
157 return;
158 reg = rd_regl(port, SIRFUART_AFC_CTRL);
159 wr_regl(port, SIRFUART_AFC_CTRL, reg & ~0x3FF);
160 reg = rd_regl(port, SIRFUART_INT_EN);
161 wr_regl(port, SIRFUART_INT_EN, reg & ~SIRFUART_CTS_INT_EN);
162}
163
164static void sirfsoc_uart_enable_ms(struct uart_port *port)
165{
166 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
167 unsigned long reg;
168 unsigned long flg;
169 if (!sirfport->hw_flow_ctrl)
170 return;
171 flg = SIRFUART_AFC_RX_EN | SIRFUART_AFC_TX_EN;
172 reg = rd_regl(port, SIRFUART_AFC_CTRL);
173 wr_regl(port, SIRFUART_AFC_CTRL, reg | flg);
174 reg = rd_regl(port, SIRFUART_INT_EN);
175 wr_regl(port, SIRFUART_INT_EN, reg | SIRFUART_CTS_INT_EN);
176 uart_handle_cts_change(port,
177 !(rd_regl(port, SIRFUART_AFC_CTRL) & SIRFUART_CTS_IN_STATUS));
178 sirfport->ms_enabled = 1;
179}
180
181static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
182{
183 unsigned long ulcon = rd_regl(port, SIRFUART_LINE_CTRL);
184 if (break_state)
185 ulcon |= SIRFUART_SET_BREAK;
186 else
187 ulcon &= ~SIRFUART_SET_BREAK;
188 wr_regl(port, SIRFUART_LINE_CTRL, ulcon);
189}
190
191static unsigned int
192sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
193{
194 unsigned int ch, rx_count = 0;
195 struct tty_struct *tty;
196
197 tty = tty_port_tty_get(&port->state->port);
198 if (!tty)
199 return -ENODEV;
200
201 while (!(rd_regl(port, SIRFUART_RX_FIFO_STATUS) &
202 SIRFUART_FIFOEMPTY_MASK(port))) {
203 ch = rd_regl(port, SIRFUART_RX_FIFO_DATA) | SIRFUART_DUMMY_READ;
204 if (unlikely(uart_handle_sysrq_char(port, ch)))
205 continue;
206 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
207 rx_count++;
208 if (rx_count >= max_rx_count)
209 break;
210 }
211
212 port->icount.rx += rx_count;
213 tty_flip_buffer_push(tty);
214 tty_kref_put(tty);
215
216 return rx_count;
217}
218
219static unsigned int
220sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
221{
222 struct uart_port *port = &sirfport->port;
223 struct circ_buf *xmit = &port->state->xmit;
224 unsigned int num_tx = 0;
225 while (!uart_circ_empty(xmit) &&
226 !(rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
227 SIRFUART_FIFOFULL_MASK(port)) &&
228 count--) {
229 wr_regl(port, SIRFUART_TX_FIFO_DATA, xmit->buf[xmit->tail]);
230 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
231 port->icount.tx++;
232 num_tx++;
233 }
234 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
235 uart_write_wakeup(port);
236 return num_tx;
237}
238
239static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
240{
241 unsigned long intr_status;
242 unsigned long cts_status;
243 unsigned long flag = TTY_NORMAL;
244 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
245 struct uart_port *port = &sirfport->port;
246 struct uart_state *state = port->state;
247 struct circ_buf *xmit = &port->state->xmit;
248 intr_status = rd_regl(port, SIRFUART_INT_STATUS);
249 wr_regl(port, SIRFUART_INT_STATUS, intr_status);
250 intr_status &= rd_regl(port, SIRFUART_INT_EN);
251 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT))) {
252 if (intr_status & SIRFUART_RXD_BREAK) {
253 if (uart_handle_break(port))
254 goto recv_char;
255 uart_insert_char(port, intr_status,
256 SIRFUART_RX_OFLOW, 0, TTY_BREAK);
257 return IRQ_HANDLED;
258 }
259 if (intr_status & SIRFUART_RX_OFLOW)
260 port->icount.overrun++;
261 if (intr_status & SIRFUART_FRM_ERR) {
262 port->icount.frame++;
263 flag = TTY_FRAME;
264 }
265 if (intr_status & SIRFUART_PARITY_ERR)
266 flag = TTY_PARITY;
267 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
268 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
269 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
270 intr_status &= port->read_status_mask;
271 uart_insert_char(port, intr_status,
272 SIRFUART_RX_OFLOW_INT, 0, flag);
273 }
274recv_char:
275 if (intr_status & SIRFUART_CTS_INT_EN) {
276 cts_status = !(rd_regl(port, SIRFUART_AFC_CTRL) &
277 SIRFUART_CTS_IN_STATUS);
278 if (cts_status != 0) {
279 uart_handle_cts_change(port, 1);
280 } else {
281 uart_handle_cts_change(port, 0);
282 wake_up_interruptible(&state->port.delta_msr_wait);
283 }
284 }
285 if (intr_status & SIRFUART_RX_IO_INT_EN)
286 sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
287 if (intr_status & SIRFUART_TX_INT_EN) {
288 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
289 return IRQ_HANDLED;
290 } else {
291 sirfsoc_uart_pio_tx_chars(sirfport,
292 SIRFSOC_UART_IO_TX_REASONABLE_CNT);
293 if ((uart_circ_empty(xmit)) &&
294 (rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
295 SIRFUART_FIFOEMPTY_MASK(port)))
296 sirfsoc_uart_stop_tx(port);
297 }
298 }
299 return IRQ_HANDLED;
300}
301
302static void sirfsoc_uart_start_rx(struct uart_port *port)
303{
304 unsigned long regv;
305 regv = rd_regl(port, SIRFUART_INT_EN);
306 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_RX_IO_INT_EN);
307 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
308 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
309 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
310}
311
312static unsigned int
313sirfsoc_calc_sample_div(unsigned long baud_rate,
314 unsigned long ioclk_rate, unsigned long *setted_baud)
315{
316 unsigned long min_delta = ~0UL;
317 unsigned short sample_div;
318 unsigned int regv = 0;
319 unsigned long ioclk_div;
320 unsigned long baud_tmp;
321 int temp_delta;
322
323 for (sample_div = SIRF_MIN_SAMPLE_DIV;
324 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
325 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
326 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
327 continue;
328 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
329 temp_delta = baud_tmp - baud_rate;
330 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
331 if (temp_delta < min_delta) {
332 regv = regv & (~SIRF_IOCLK_DIV_MASK);
333 regv = regv | ioclk_div;
334 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
335 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
336 min_delta = temp_delta;
337 *setted_baud = baud_tmp;
338 }
339 }
340 return regv;
341}
342
343static void sirfsoc_uart_set_termios(struct uart_port *port,
344 struct ktermios *termios,
345 struct ktermios *old)
346{
347 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
348 unsigned long ioclk_rate;
349 unsigned long config_reg = 0;
350 unsigned long baud_rate;
351 unsigned long setted_baud;
352 unsigned long flags;
353 unsigned long ic;
354 unsigned int clk_div_reg = 0;
355 unsigned long temp_reg_val;
356 unsigned long rx_time_out;
357 int threshold_div;
358 int temp;
359
360 ioclk_rate = 150000000;
361 switch (termios->c_cflag & CSIZE) {
362 default:
363 case CS8:
364 config_reg |= SIRFUART_DATA_BIT_LEN_8;
365 break;
366 case CS7:
367 config_reg |= SIRFUART_DATA_BIT_LEN_7;
368 break;
369 case CS6:
370 config_reg |= SIRFUART_DATA_BIT_LEN_6;
371 break;
372 case CS5:
373 config_reg |= SIRFUART_DATA_BIT_LEN_5;
374 break;
375 }
376 if (termios->c_cflag & CSTOPB)
377 config_reg |= SIRFUART_STOP_BIT_LEN_2;
378 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
379 spin_lock_irqsave(&port->lock, flags);
380 port->read_status_mask = SIRFUART_RX_OFLOW_INT;
381 port->ignore_status_mask = 0;
382 /* read flags */
383 if (termios->c_iflag & INPCK)
384 port->read_status_mask |=
385 SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
386 if (termios->c_iflag & (BRKINT | PARMRK))
387 port->read_status_mask |= SIRFUART_RXD_BREAK_INT;
388 /* ignore flags */
389 if (termios->c_iflag & IGNPAR)
390 port->ignore_status_mask |=
391 SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
392 if ((termios->c_cflag & CREAD) == 0)
393 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
394 /* enable parity if PARENB is set*/
395 if (termios->c_cflag & PARENB) {
396 if (termios->c_cflag & CMSPAR) {
397 if (termios->c_cflag & PARODD)
398 config_reg |= SIRFUART_STICK_BIT_MARK;
399 else
400 config_reg |= SIRFUART_STICK_BIT_SPACE;
401 } else if (termios->c_cflag & PARODD) {
402 config_reg |= SIRFUART_STICK_BIT_ODD;
403 } else {
404 config_reg |= SIRFUART_STICK_BIT_EVEN;
405 }
406 }
407 /* Hardware Flow Control Settings */
408 if (UART_ENABLE_MS(port, termios->c_cflag)) {
409 if (!sirfport->ms_enabled)
410 sirfsoc_uart_enable_ms(port);
411 } else {
412 if (sirfport->ms_enabled)
413 sirfsoc_uart_disable_ms(port);
414 }
415
416 /* common rate: fast calculation */
417 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
418 if (baud_rate == baudrate_to_regv[ic].baud_rate)
419 clk_div_reg = baudrate_to_regv[ic].reg_val;
420 setted_baud = baud_rate;
421 /* arbitary rate setting */
422 if (unlikely(clk_div_reg == 0))
423 clk_div_reg = sirfsoc_calc_sample_div(baud_rate, ioclk_rate,
424 &setted_baud);
425 wr_regl(port, SIRFUART_DIVISOR, clk_div_reg);
426
427 if (tty_termios_baud_rate(termios))
428 tty_termios_encode_baud_rate(termios, setted_baud, setted_baud);
429
430 /* set receive timeout */
431 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(baud_rate, 20000);
432 rx_time_out = (rx_time_out > 0xFFFF) ? 0xFFFF : rx_time_out;
433 config_reg |= SIRFUART_RECV_TIMEOUT(rx_time_out);
434 temp_reg_val = rd_regl(port, SIRFUART_TX_FIFO_OP);
435 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
436 wr_regl(port, SIRFUART_TX_FIFO_OP,
437 temp_reg_val & ~SIRFUART_TX_FIFO_START);
438 wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, SIRFUART_TX_MODE_IO);
439 wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, SIRFUART_RX_MODE_IO);
440 wr_regl(port, SIRFUART_LINE_CTRL, config_reg);
441
442 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
443 if (baud_rate < 1000000)
444 threshold_div = 1;
445 else
446 threshold_div = 2;
447 temp = port->line == 1 ? 16 : 64;
448 wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp / threshold_div);
449 wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp / threshold_div);
450 temp_reg_val |= SIRFUART_TX_FIFO_START;
451 wr_regl(port, SIRFUART_TX_FIFO_OP, temp_reg_val);
452 uart_update_timeout(port, termios->c_cflag, baud_rate);
453 sirfsoc_uart_start_rx(port);
454 wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_TX_EN | SIRFUART_RX_EN);
455 spin_unlock_irqrestore(&port->lock, flags);
456}
457
458static void startup_uart_controller(struct uart_port *port)
459{
460 unsigned long temp_regv;
461 int temp;
462 temp_regv = rd_regl(port, SIRFUART_TX_DMA_IO_CTRL);
463 wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, temp_regv | SIRFUART_TX_MODE_IO);
464 temp_regv = rd_regl(port, SIRFUART_RX_DMA_IO_CTRL);
465 wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, temp_regv | SIRFUART_RX_MODE_IO);
466 wr_regl(port, SIRFUART_TX_DMA_IO_LEN, 0);
467 wr_regl(port, SIRFUART_RX_DMA_IO_LEN, 0);
468 wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_RX_EN | SIRFUART_TX_EN);
469 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_RESET);
470 wr_regl(port, SIRFUART_TX_FIFO_OP, 0);
471 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
472 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
473 temp = port->line == 1 ? 16 : 64;
474 wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp);
475 wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp);
476}
477
478static int sirfsoc_uart_startup(struct uart_port *port)
479{
480 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
481 unsigned int index = port->line;
482 int ret;
483 set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
484 ret = request_irq(port->irq,
485 sirfsoc_uart_isr,
486 0,
487 SIRFUART_PORT_NAME,
488 sirfport);
489 if (ret != 0) {
490 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
491 index, port->irq);
492 goto irq_err;
493 }
494 startup_uart_controller(port);
495 enable_irq(port->irq);
496irq_err:
497 return ret;
498}
499
500static void sirfsoc_uart_shutdown(struct uart_port *port)
501{
502 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
503 wr_regl(port, SIRFUART_INT_EN, 0);
504 free_irq(port->irq, sirfport);
505 if (sirfport->ms_enabled) {
506 sirfsoc_uart_disable_ms(port);
507 sirfport->ms_enabled = 0;
508 }
509}
510
511static const char *sirfsoc_uart_type(struct uart_port *port)
512{
513 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
514}
515
516static int sirfsoc_uart_request_port(struct uart_port *port)
517{
518 void *ret;
519 ret = request_mem_region(port->mapbase,
520 SIRFUART_MAP_SIZE, SIRFUART_PORT_NAME);
521 return ret ? 0 : -EBUSY;
522}
523
524static void sirfsoc_uart_release_port(struct uart_port *port)
525{
526 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
527}
528
529static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
530{
531 if (flags & UART_CONFIG_TYPE) {
532 port->type = SIRFSOC_PORT_TYPE;
533 sirfsoc_uart_request_port(port);
534 }
535}
536
537static struct uart_ops sirfsoc_uart_ops = {
538 .tx_empty = sirfsoc_uart_tx_empty,
539 .get_mctrl = sirfsoc_uart_get_mctrl,
540 .set_mctrl = sirfsoc_uart_set_mctrl,
541 .stop_tx = sirfsoc_uart_stop_tx,
542 .start_tx = sirfsoc_uart_start_tx,
543 .stop_rx = sirfsoc_uart_stop_rx,
544 .enable_ms = sirfsoc_uart_enable_ms,
545 .break_ctl = sirfsoc_uart_break_ctl,
546 .startup = sirfsoc_uart_startup,
547 .shutdown = sirfsoc_uart_shutdown,
548 .set_termios = sirfsoc_uart_set_termios,
549 .type = sirfsoc_uart_type,
550 .release_port = sirfsoc_uart_release_port,
551 .request_port = sirfsoc_uart_request_port,
552 .config_port = sirfsoc_uart_config_port,
553};
554
555#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
556static int __init sirfsoc_uart_console_setup(struct console *co, char *options)
557{
558 unsigned int baud = 115200;
559 unsigned int bits = 8;
560 unsigned int parity = 'n';
561 unsigned int flow = 'n';
562 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
563
564 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
565 return -EINVAL;
566
567 if (!port->mapbase)
568 return -ENODEV;
569
570 if (options)
571 uart_parse_options(options, &baud, &parity, &bits, &flow);
572 port->cons = co;
573 return uart_set_options(port, co, baud, parity, bits, flow);
574}
575
576static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
577{
578 while (rd_regl(port,
579 SIRFUART_TX_FIFO_STATUS) & SIRFUART_FIFOFULL_MASK(port))
580 cpu_relax();
581 wr_regb(port, SIRFUART_TX_FIFO_DATA, ch);
582}
583
584static void sirfsoc_uart_console_write(struct console *co, const char *s,
585 unsigned int count)
586{
587 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
588 uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
589}
590
591static struct console sirfsoc_uart_console = {
592 .name = SIRFSOC_UART_NAME,
593 .device = uart_console_device,
594 .flags = CON_PRINTBUFFER,
595 .index = -1,
596 .write = sirfsoc_uart_console_write,
597 .setup = sirfsoc_uart_console_setup,
598 .data = &sirfsoc_uart_drv,
599};
600
601static int __init sirfsoc_uart_console_init(void)
602{
603 register_console(&sirfsoc_uart_console);
604 return 0;
605}
606console_initcall(sirfsoc_uart_console_init);
607#endif
608
609static struct uart_driver sirfsoc_uart_drv = {
610 .owner = THIS_MODULE,
611 .driver_name = SIRFUART_PORT_NAME,
612 .nr = SIRFSOC_UART_NR,
613 .dev_name = SIRFSOC_UART_NAME,
614 .major = SIRFSOC_UART_MAJOR,
615 .minor = SIRFSOC_UART_MINOR,
616#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
617 .cons = &sirfsoc_uart_console,
618#else
619 .cons = NULL,
620#endif
621};
622
623int sirfsoc_uart_probe(struct platform_device *pdev)
624{
625 struct sirfsoc_uart_port *sirfport;
626 struct uart_port *port;
627 struct resource *res;
628 int ret;
629
630 if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
631 dev_err(&pdev->dev,
632 "Unable to find cell-index in uart node.\n");
633 ret = -EFAULT;
634 goto err;
635 }
636
637 sirfport = &sirfsoc_uart_ports[pdev->id];
638 port = &sirfport->port;
639 port->dev = &pdev->dev;
640 port->private_data = sirfport;
641
642 if (of_find_property(pdev->dev.of_node, "hw_flow_ctrl", NULL))
643 sirfport->hw_flow_ctrl = 1;
644
645 if (of_property_read_u32(pdev->dev.of_node,
646 "fifosize",
647 &port->fifosize)) {
648 dev_err(&pdev->dev,
649 "Unable to find fifosize in uart node.\n");
650 ret = -EFAULT;
651 goto err;
652 }
653
654 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
655 if (res == NULL) {
656 dev_err(&pdev->dev, "Insufficient resources.\n");
657 ret = -EFAULT;
658 goto err;
659 }
660 port->mapbase = res->start;
661 port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
662 if (!port->membase) {
663 dev_err(&pdev->dev, "Cannot remap resource.\n");
664 ret = -ENOMEM;
665 goto err;
666 }
667 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
668 if (res == NULL) {
669 dev_err(&pdev->dev, "Insufficient resources.\n");
670 ret = -EFAULT;
671 goto irq_err;
672 }
673 port->irq = res->start;
674
675 if (sirfport->hw_flow_ctrl) {
676 sirfport->pmx = pinmux_get(&pdev->dev, NULL);
677 ret = IS_ERR(sirfport->pmx);
678 if (ret)
679 goto pmx_err;
680
681 pinmux_enable(sirfport->pmx);
682 }
683
684 port->ops = &sirfsoc_uart_ops;
685 spin_lock_init(&port->lock);
686
687 platform_set_drvdata(pdev, sirfport);
688 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
689 if (ret != 0) {
690 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
691 goto port_err;
692 }
693
694 return 0;
695
696port_err:
697 platform_set_drvdata(pdev, NULL);
698 if (sirfport->hw_flow_ctrl) {
699 pinmux_disable(sirfport->pmx);
700 pinmux_put(sirfport->pmx);
701 }
702pmx_err:
703irq_err:
704 devm_iounmap(&pdev->dev, port->membase);
705err:
706 return ret;
707}
708
709static int sirfsoc_uart_remove(struct platform_device *pdev)
710{
711 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
712 struct uart_port *port = &sirfport->port;
713 platform_set_drvdata(pdev, NULL);
714 if (sirfport->hw_flow_ctrl) {
715 pinmux_disable(sirfport->pmx);
716 pinmux_put(sirfport->pmx);
717 }
718 devm_iounmap(&pdev->dev, port->membase);
719 uart_remove_one_port(&sirfsoc_uart_drv, port);
720 return 0;
721}
722
723static int
724sirfsoc_uart_suspend(struct platform_device *pdev, pm_message_t state)
725{
726 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
727 struct uart_port *port = &sirfport->port;
728 uart_suspend_port(&sirfsoc_uart_drv, port);
729 return 0;
730}
731
732static int sirfsoc_uart_resume(struct platform_device *pdev)
733{
734 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
735 struct uart_port *port = &sirfport->port;
736 uart_resume_port(&sirfsoc_uart_drv, port);
737 return 0;
738}
739
740static struct of_device_id sirfsoc_uart_ids[] __devinitdata = {
741 { .compatible = "sirf,prima2-uart", },
742 {}
743};
744MODULE_DEVICE_TABLE(of, sirfsoc_serial_of_match);
745
746static struct platform_driver sirfsoc_uart_driver = {
747 .probe = sirfsoc_uart_probe,
748 .remove = __devexit_p(sirfsoc_uart_remove),
749 .suspend = sirfsoc_uart_suspend,
750 .resume = sirfsoc_uart_resume,
751 .driver = {
752 .name = SIRFUART_PORT_NAME,
753 .owner = THIS_MODULE,
754 .of_match_table = sirfsoc_uart_ids,
755 },
756};
757
758static int __init sirfsoc_uart_init(void)
759{
760 int ret = 0;
761
762 ret = uart_register_driver(&sirfsoc_uart_drv);
763 if (ret)
764 goto out;
765
766 ret = platform_driver_register(&sirfsoc_uart_driver);
767 if (ret)
768 uart_unregister_driver(&sirfsoc_uart_drv);
769out:
770 return ret;
771}
772module_init(sirfsoc_uart_init);
773
774static void __exit sirfsoc_uart_exit(void)
775{
776 platform_driver_unregister(&sirfsoc_uart_driver);
777 uart_unregister_driver(&sirfsoc_uart_drv);
778}
779module_exit(sirfsoc_uart_exit);
780
781MODULE_LICENSE("GPL v2");
782MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
783MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");
diff --git a/drivers/tty/serial/sirfsoc_uart.h b/drivers/tty/serial/sirfsoc_uart.h
new file mode 100644
index 000000000000..fc64260fa93c
--- /dev/null
+++ b/drivers/tty/serial/sirfsoc_uart.h
@@ -0,0 +1,185 @@
1/*
2 * Drivers for CSR SiRFprimaII onboard UARTs.
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8#include <linux/bitops.h>
9
10/* UART Register Offset Define */
11#define SIRFUART_LINE_CTRL 0x0040
12#define SIRFUART_TX_RX_EN 0x004c
13#define SIRFUART_DIVISOR 0x0050
14#define SIRFUART_INT_EN 0x0054
15#define SIRFUART_INT_STATUS 0x0058
16#define SIRFUART_TX_DMA_IO_CTRL 0x0100
17#define SIRFUART_TX_DMA_IO_LEN 0x0104
18#define SIRFUART_TX_FIFO_CTRL 0x0108
19#define SIRFUART_TX_FIFO_LEVEL_CHK 0x010C
20#define SIRFUART_TX_FIFO_OP 0x0110
21#define SIRFUART_TX_FIFO_STATUS 0x0114
22#define SIRFUART_TX_FIFO_DATA 0x0118
23#define SIRFUART_RX_DMA_IO_CTRL 0x0120
24#define SIRFUART_RX_DMA_IO_LEN 0x0124
25#define SIRFUART_RX_FIFO_CTRL 0x0128
26#define SIRFUART_RX_FIFO_LEVEL_CHK 0x012C
27#define SIRFUART_RX_FIFO_OP 0x0130
28#define SIRFUART_RX_FIFO_STATUS 0x0134
29#define SIRFUART_RX_FIFO_DATA 0x0138
30#define SIRFUART_AFC_CTRL 0x0140
31#define SIRFUART_SWH_DMA_IO 0x0148
32
33/* UART Line Control Register */
34#define SIRFUART_DATA_BIT_LEN_MASK 0x3
35#define SIRFUART_DATA_BIT_LEN_5 BIT(0)
36#define SIRFUART_DATA_BIT_LEN_6 1
37#define SIRFUART_DATA_BIT_LEN_7 2
38#define SIRFUART_DATA_BIT_LEN_8 3
39#define SIRFUART_STOP_BIT_LEN_1 0
40#define SIRFUART_STOP_BIT_LEN_2 BIT(2)
41#define SIRFUART_PARITY_EN BIT(3)
42#define SIRFUART_EVEN_BIT BIT(4)
43#define SIRFUART_STICK_BIT_MASK (7 << 3)
44#define SIRFUART_STICK_BIT_NONE (0 << 3)
45#define SIRFUART_STICK_BIT_EVEN BIT(3)
46#define SIRFUART_STICK_BIT_ODD (3 << 3)
47#define SIRFUART_STICK_BIT_MARK (5 << 3)
48#define SIRFUART_STICK_BIT_SPACE (7 << 3)
49#define SIRFUART_SET_BREAK BIT(6)
50#define SIRFUART_LOOP_BACK BIT(7)
51#define SIRFUART_PARITY_MASK (7 << 3)
52#define SIRFUART_DUMMY_READ BIT(16)
53
54#define SIRFSOC_UART_RX_TIMEOUT(br, to) (((br) * (((to) + 999) / 1000)) / 1000)
55#define SIRFUART_RECV_TIMEOUT_MASK (0xFFFF << 16)
56#define SIRFUART_RECV_TIMEOUT(x) (((x) & 0xFFFF) << 16)
57
58/* UART Auto Flow Control */
59#define SIRFUART_AFC_RX_THD_MASK 0x000000FF
60#define SIRFUART_AFC_RX_EN BIT(8)
61#define SIRFUART_AFC_TX_EN BIT(9)
62#define SIRFUART_CTS_CTRL BIT(10)
63#define SIRFUART_RTS_CTRL BIT(11)
64#define SIRFUART_CTS_IN_STATUS BIT(12)
65#define SIRFUART_RTS_OUT_STATUS BIT(13)
66
67/* UART Interrupt Enable Register */
68#define SIRFUART_RX_DONE_INT BIT(0)
69#define SIRFUART_TX_DONE_INT BIT(1)
70#define SIRFUART_RX_OFLOW_INT BIT(2)
71#define SIRFUART_TX_ALLOUT_INT BIT(3)
72#define SIRFUART_RX_IO_DMA_INT BIT(4)
73#define SIRFUART_TX_IO_DMA_INT BIT(5)
74#define SIRFUART_RXFIFO_FULL_INT BIT(6)
75#define SIRFUART_TXFIFO_EMPTY_INT BIT(7)
76#define SIRFUART_RXFIFO_THD_INT BIT(8)
77#define SIRFUART_TXFIFO_THD_INT BIT(9)
78#define SIRFUART_FRM_ERR_INT BIT(10)
79#define SIRFUART_RXD_BREAK_INT BIT(11)
80#define SIRFUART_RX_TIMEOUT_INT BIT(12)
81#define SIRFUART_PARITY_ERR_INT BIT(13)
82#define SIRFUART_CTS_INT_EN BIT(14)
83#define SIRFUART_RTS_INT_EN BIT(15)
84
85/* UART Interrupt Status Register */
86#define SIRFUART_RX_DONE BIT(0)
87#define SIRFUART_TX_DONE BIT(1)
88#define SIRFUART_RX_OFLOW BIT(2)
89#define SIRFUART_TX_ALL_EMPTY BIT(3)
90#define SIRFUART_DMA_IO_RX_DONE BIT(4)
91#define SIRFUART_DMA_IO_TX_DONE BIT(5)
92#define SIRFUART_RXFIFO_FULL BIT(6)
93#define SIRFUART_TXFIFO_EMPTY BIT(7)
94#define SIRFUART_RXFIFO_THD_REACH BIT(8)
95#define SIRFUART_TXFIFO_THD_REACH BIT(9)
96#define SIRFUART_FRM_ERR BIT(10)
97#define SIRFUART_RXD_BREAK BIT(11)
98#define SIRFUART_RX_TIMEOUT BIT(12)
99#define SIRFUART_PARITY_ERR BIT(13)
100#define SIRFUART_CTS_CHANGE BIT(14)
101#define SIRFUART_RTS_CHANGE BIT(15)
102#define SIRFUART_PLUG_IN BIT(16)
103
104#define SIRFUART_ERR_INT_STAT \
105 (SIRFUART_RX_OFLOW | \
106 SIRFUART_FRM_ERR | \
107 SIRFUART_RXD_BREAK | \
108 SIRFUART_PARITY_ERR)
109#define SIRFUART_ERR_INT_EN \
110 (SIRFUART_RX_OFLOW_INT | \
111 SIRFUART_FRM_ERR_INT | \
112 SIRFUART_RXD_BREAK_INT | \
113 SIRFUART_PARITY_ERR_INT)
114#define SIRFUART_TX_INT_EN SIRFUART_TXFIFO_EMPTY_INT
115#define SIRFUART_RX_IO_INT_EN \
116 (SIRFUART_RX_TIMEOUT_INT | \
117 SIRFUART_RXFIFO_THD_INT | \
118 SIRFUART_RXFIFO_FULL_INT | \
119 SIRFUART_ERR_INT_EN)
120
121/* UART FIFO Register */
122#define SIRFUART_TX_FIFO_STOP 0x0
123#define SIRFUART_TX_FIFO_RESET 0x1
124#define SIRFUART_TX_FIFO_START 0x2
125#define SIRFUART_RX_FIFO_STOP 0x0
126#define SIRFUART_RX_FIFO_RESET 0x1
127#define SIRFUART_RX_FIFO_START 0x2
128#define SIRFUART_TX_MODE_DMA 0
129#define SIRFUART_TX_MODE_IO 1
130#define SIRFUART_RX_MODE_DMA 0
131#define SIRFUART_RX_MODE_IO 1
132
133#define SIRFUART_RX_EN 0x1
134#define SIRFUART_TX_EN 0x2
135
136/* Generic Definitions */
137#define SIRFSOC_UART_NAME "ttySiRF"
138#define SIRFSOC_UART_MAJOR 0
139#define SIRFSOC_UART_MINOR 0
140#define SIRFUART_PORT_NAME "sirfsoc-uart"
141#define SIRFUART_MAP_SIZE 0x200
142#define SIRFSOC_UART_NR 3
143#define SIRFSOC_PORT_TYPE 0xa5
144
145/* Baud Rate Calculation */
146#define SIRF_MIN_SAMPLE_DIV 0xf
147#define SIRF_MAX_SAMPLE_DIV 0x3f
148#define SIRF_IOCLK_DIV_MAX 0xffff
149#define SIRF_SAMPLE_DIV_SHIFT 16
150#define SIRF_IOCLK_DIV_MASK 0xffff
151#define SIRF_SAMPLE_DIV_MASK 0x3f0000
152#define SIRF_BAUD_RATE_SUPPORT_NR 18
153
154/* For Fast Baud Rate Calculation */
155struct sirfsoc_baudrate_to_regv {
156 unsigned int baud_rate;
157 unsigned int reg_val;
158};
159
160struct sirfsoc_uart_port {
161 unsigned char hw_flow_ctrl;
162 unsigned char ms_enabled;
163
164 struct uart_port port;
165 struct pinmux *pmx;
166};
167
168/* Hardware Flow Control */
169#define SIRFUART_AFC_CTRL_RX_THD 0x70
170
171/* Register Access Control */
172#define portaddr(port, reg) ((port)->membase + (reg))
173#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
174#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
175#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
176#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
177
178/* UART Port Mask */
179#define SIRFUART_FIFOLEVEL_MASK(port) ((port->line == 1) ? (0x1f) : (0x7f))
180#define SIRFUART_FIFOFULL_MASK(port) ((port->line == 1) ? (0x20) : (0x80))
181#define SIRFUART_FIFOEMPTY_MASK(port) ((port->line == 1) ? (0x40) : (0x100))
182
183/* I/O Mode */
184#define SIRFSOC_UART_IO_RX_MAX_CNT 256
185#define SIRFSOC_UART_IO_TX_REASONABLE_CNT 6
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-01 18:46:51 -0400