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authorKristina Martšenko <kristina.martsenko@gmail.com>2014-07-01 11:54:43 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-07-01 12:05:33 -0400
commit14b596c9d80bf63da3f0fcbddfd67eb62197afb4 (patch)
tree2dfafe8a96a5f687767f36dd582bbb4d40bc6e9d /drivers
parent19b1e7695be8cbdf14e85ddefc9c5a9d3e88bdfd (diff)
staging: cxt1e1: remove driver
Remove the driver as it hasn't been cleaned up and it doesn't look like anyone is going to work on it anymore. This can be reverted if someone wants to work to fix the remaining issues the driver has. Signed-off-by: Kristina Martšenko <kristina.martsenko@gmail.com> Cc: Bob Beers <bob.beers@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile1
-rw-r--r--drivers/staging/cxt1e1/Kconfig21
-rw-r--r--drivers/staging/cxt1e1/Makefile18
-rw-r--r--drivers/staging/cxt1e1/comet.c596
-rw-r--r--drivers/staging/cxt1e1/comet.h353
-rw-r--r--drivers/staging/cxt1e1/comet_tables.c538
-rw-r--r--drivers/staging/cxt1e1/comet_tables.h61
-rw-r--r--drivers/staging/cxt1e1/functions.c318
-rw-r--r--drivers/staging/cxt1e1/hwprobe.c382
-rw-r--r--drivers/staging/cxt1e1/libsbew.h549
-rw-r--r--drivers/staging/cxt1e1/linux.c1142
-rw-r--r--drivers/staging/cxt1e1/musycc.c1736
-rw-r--r--drivers/staging/cxt1e1/musycc.h427
-rw-r--r--drivers/staging/cxt1e1/pmc93x6_eeprom.c532
-rw-r--r--drivers/staging/cxt1e1/pmc93x6_eeprom.h39
-rw-r--r--drivers/staging/cxt1e1/pmcc4.h108
-rw-r--r--drivers/staging/cxt1e1/pmcc4_cpld.h91
-rw-r--r--drivers/staging/cxt1e1/pmcc4_defs.h68
-rw-r--r--drivers/staging/cxt1e1/pmcc4_drv.c1613
-rw-r--r--drivers/staging/cxt1e1/pmcc4_ioctls.h65
-rw-r--r--drivers/staging/cxt1e1/pmcc4_private.h296
-rw-r--r--drivers/staging/cxt1e1/pmcc4_sysdep.h63
-rw-r--r--drivers/staging/cxt1e1/sbe_bid.h47
-rw-r--r--drivers/staging/cxt1e1/sbe_promformat.h130
-rw-r--r--drivers/staging/cxt1e1/sbecom_inline_linux.h193
-rw-r--r--drivers/staging/cxt1e1/sbecrc.c134
-rw-r--r--drivers/staging/cxt1e1/sbeid.c205
-rw-r--r--drivers/staging/cxt1e1/sbeproc.c219
-rw-r--r--drivers/staging/cxt1e1/sbeproc.h42
-rw-r--r--drivers/staging/cxt1e1/sbew_ioc.h81
31 files changed, 0 insertions, 10070 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 91ebf62497bc..0fd87443412a 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -72,8 +72,6 @@ source "drivers/staging/sep/Kconfig"
72 72
73source "drivers/staging/iio/Kconfig" 73source "drivers/staging/iio/Kconfig"
74 74
75source "drivers/staging/cxt1e1/Kconfig"
76
77source "drivers/staging/xgifb/Kconfig" 75source "drivers/staging/xgifb/Kconfig"
78 76
79source "drivers/staging/tidspbridge/Kconfig" 77source "drivers/staging/tidspbridge/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index a1e0b1c5f72f..9aeecc9b07e0 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -30,7 +30,6 @@ obj-$(CONFIG_VT6656) += vt6656/
30obj-$(CONFIG_VME_BUS) += vme/ 30obj-$(CONFIG_VME_BUS) += vme/
31obj-$(CONFIG_DX_SEP) += sep/ 31obj-$(CONFIG_DX_SEP) += sep/
32obj-$(CONFIG_IIO) += iio/ 32obj-$(CONFIG_IIO) += iio/
33obj-$(CONFIG_CXT1E1) += cxt1e1/
34obj-$(CONFIG_FB_XGI) += xgifb/ 33obj-$(CONFIG_FB_XGI) += xgifb/
35obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/ 34obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/
36obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/ 35obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/
diff --git a/drivers/staging/cxt1e1/Kconfig b/drivers/staging/cxt1e1/Kconfig
deleted file mode 100644
index 947f42a65c59..000000000000
--- a/drivers/staging/cxt1e1/Kconfig
+++ /dev/null
@@ -1,21 +0,0 @@
1config CXT1E1
2 tristate "SBE wanPMC-C[421]E1T1 hardware support"
3 depends on HDLC && PCI
4 ---help---
5 This driver supports the SBE wanPMC-CxT1E1 1, 2 and 4 port T3
6 channelized stream WAN adapter card which contains a HDLC/Transparent
7 mode controller.
8
9 If you want to compile this driver as a module say M here.
10 The module will be called 'cxt1e1'.
11
12 If unsure, say N.
13
14config SBE_PMCC4_NCOMM
15 bool "SBE PMCC4 NCOMM support"
16 depends on CXT1E1
17 ---help---
18 SBE supplies optional support for NCOMM products.
19
20 If you have purchased this optional support you must say Y
21 here to allow the driver to operate with the NCOMM product.
diff --git a/drivers/staging/cxt1e1/Makefile b/drivers/staging/cxt1e1/Makefile
deleted file mode 100644
index b879e7b553c2..000000000000
--- a/drivers/staging/cxt1e1/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
1obj-$(CONFIG_CXT1E1) += cxt1e1.o
2
3ccflags-y := -DSBE_PMCC4_ENABLE
4ccflags-y += -DSBE_ISR_TASKLET
5
6cxt1e1-y := \
7 musycc.o \
8 pmcc4_drv.o \
9 comet.o \
10 linux.o \
11 functions.o \
12 hwprobe.o \
13 pmc93x6_eeprom.o \
14 sbecrc.o \
15 comet_tables.o \
16 sbeid.o
17
18cxt1e1-$(CONFIG_PROC_FS) += sbeproc.o
diff --git a/drivers/staging/cxt1e1/comet.c b/drivers/staging/cxt1e1/comet.c
deleted file mode 100644
index 7005ad022339..000000000000
--- a/drivers/staging/cxt1e1/comet.c
+++ /dev/null
@@ -1,596 +0,0 @@
1/* Copyright (C) 2003-2005 SBE, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/io.h>
17#include <linux/hdlc.h>
18#include "pmcc4_sysdep.h"
19#include "sbecom_inline_linux.h"
20#include "libsbew.h"
21#include "pmcc4.h"
22#include "comet.h"
23#include "comet_tables.h"
24
25
26#define COMET_NUM_SAMPLES 24 /* Number of entries in the waveform table */
27#define COMET_NUM_UNITS 5 /* Number of points per entry in table */
28
29/* forward references */
30static void SetPwrLevel(struct s_comet_reg *comet);
31static void WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet,
32 u_int32_t *table);
33static void WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
34 u_int8_t table[COMET_NUM_SAMPLES]
35 [COMET_NUM_UNITS]);
36
37
38static void *TWV_table[12] = {
39 TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
40 TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
41 TWVShortHaul4, TWVShortHaul5,
42 /** PORT POINT - 75 Ohm not supported **/
43 TWV_E1_75Ohm,
44 TWV_E1_120Ohm
45};
46
47
48static int
49lbo_tbl_lkup(int t1, int lbo) {
50 /* error switches to default */
51 if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
52 if (t1)
53 /* default T1 waveform table */
54 lbo = CFG_LBO_LH0;
55
56 else
57 /* default E1 waveform table */
58 lbo = CFG_LBO_E120;
59 }
60 /* make index ZERO relative */
61 return lbo - 1;
62}
63
64void init_comet(void *ci, struct s_comet_reg *comet, u_int32_t port_mode,
65 int clockmaster, u_int8_t moreParams)
66{
67 u_int8_t isT1mode;
68 /* T1 default */
69 u_int8_t tix = CFG_LBO_LH0;
70 isT1mode = IS_FRAME_ANY_T1(port_mode);
71 /* T1 or E1 */
72 if (isT1mode) {
73 /* Select T1 Mode & PIO output enabled */
74 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
75 /* default T1 waveform table */
76 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
77 } else {
78 /* Select E1 Mode & PIO output enabled */
79 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
80 /* default E1 waveform table */
81 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
82 }
83
84 if (moreParams & CFG_LBO_MASK)
85 /* dial-in requested waveform table */
86 tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
87 /* Tx line Intfc cfg Set for analog & no special patterns */
88 /* Transmit Line Interface Config. */
89 pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
90 /* master test Ignore Test settings for now */
91 /* making sure it's Default value */
92 pci_write_32((u_int32_t *) &comet->mtest, 0x00);
93 /* Turn on Center (CENT) and everything else off */
94 /* RJAT cfg */
95 pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
96 /* Set Jitter Attenuation to recommend T1 values */
97 if (isT1mode) {
98 /* RJAT Divider N1 Control */
99 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
100 /* RJAT Divider N2 Control */
101 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
102 } else {
103 /* RJAT Divider N1 Control */
104 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
105 /* RJAT Divider N2 Control */
106 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
107 }
108
109 /* Turn on Center (CENT) and everything else off */
110 /* TJAT Config. */
111 pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
112
113 /* Do not bypass jitter attenuation and bypass elastic store */
114 /* rx opts */
115 pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
116
117 /* TJAT ctrl & TJAT divider ctrl */
118 /* Set Jitter Attenuation to recommended T1 values */
119 if (isT1mode) {
120 /* TJAT Divider N1 Control */
121 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
122 /* TJAT Divider N2 Control */
123 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
124 } else {
125 /* TJAT Divider N1 Control */
126 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
127 /* TJAT Divider N2 Control */
128 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
129 }
130
131 /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
132
133 /* Select 193-bit frame format */
134 if (isT1mode) {
135 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
136 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
137 } else {
138 /* Select 256-bit frame format */
139 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
140 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
141 /* disable T1 data link receive */
142 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
143 /* disable T1 data link transmit */
144 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
145 }
146
147 /* the following is a default value */
148 /* Enable 8 out of 10 validation */
149 /* t1RBOC enable(BOC:BitOriented Code) */
150 pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
151 if (isT1mode) {
152 /* IBCD cfg: aka Inband Code Detection ** loopback code length
153 * set to
154 */
155 /* 6 bit down, 5 bit up (assert) */
156 pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
157 /* line loopback activate pattern */
158 pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
159 /* deactivate code pattern (i.e.001) */
160 pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
161 }
162 /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */
163 /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */
164 /* 60: t1 ALMI cfg */
165 /* Configure Line Coding */
166
167 switch (port_mode) {
168 /* 1 - T1 B8ZS */
169 case CFG_FRAME_SF:
170 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
171 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
172 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
173 /* 5:B8ZS */
174 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
175 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
176 break;
177 /* 2 - T1 B8ZS */
178 case CFG_FRAME_ESF:
179 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
180 /* Bit 5: T1 DataLink Enable */
181 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
182 /* 5: T1 DataLink Enable */
183 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
184 /* 4:ESF 5:ESFFA */
185 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
186 /* 2:ESF */
187 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
188 /* 4:ESF 5:B8ZS */
189 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
190 /* 4:ESF */
191 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
192 break;
193 /* 3 - HDB3 */
194 case CFG_FRAME_E1PLAIN:
195 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
196 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
197 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
198 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
199 break;
200 /* 4 - HDB3 */
201 case CFG_FRAME_E1CAS:
202 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
203 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
204 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
205 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
206 break;
207 /* 5 - HDB3 */
208 case CFG_FRAME_E1CRC:
209 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
210 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
211 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
212 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
213 break;
214 /* 6 - HDB3 */
215 case CFG_FRAME_E1CRC_CAS:
216 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
217 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
218 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
219 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
220 break;
221 /* 7 - T1 AMI */
222 case CFG_FRAME_SF_AMI:
223 /* Enable AMI Line Decoding */
224 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
225 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
226 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
227 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
228 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
229 break;
230 /* 8 - T1 AMI */
231 case CFG_FRAME_ESF_AMI:
232 /* Enable AMI Line Decoding */
233 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
234 /* 5: T1 DataLink Enable */
235 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
236 /* 5: T1 DataLink Enable */
237 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
238 /* Bit 4:ESF 5:ESFFA */
239 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
240 /* 2:ESF */
241 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
242 /* 4:ESF */
243 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
244 /* 4:ESF */
245 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
246 break;
247 /* 9 - AMI */
248 case CFG_FRAME_E1PLAIN_AMI:
249 /* Enable AMI Line Decoding */
250 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
251 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
252 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
253 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
254 break;
255 /* 10 - AMI */
256 case CFG_FRAME_E1CAS_AMI:
257 /* Enable AMI Line Decoding */
258 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
259 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
260 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
261 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
262 break;
263 /* 11 - AMI */
264 case CFG_FRAME_E1CRC_AMI:
265 /* Enable AMI Line Decoding */
266 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
267 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
268 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
269 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
270 break;
271 /* 12 - AMI */
272 case CFG_FRAME_E1CRC_CAS_AMI:
273 /* Enable AMI Line Decoding */
274 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
275 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
276 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
277 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
278 break;
279 } /* end switch */
280
281 /***
282 * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
283 * CMODE=1: Clock slave mode with BRCLK as an input,
284 * DE=0: Use falling edge of BRCLK for data,
285 * FE=0: Use falling edge of BRCLK for frame,
286 * CMS=0: Use backplane freq,
287 * RATE[1:0]=0,0: T1
288 ***/
289
290
291 /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
292 /* note "rate bits can only be set once after reset" */
293 if (clockmaster) {
294 /* CMODE == clockMode, 0=clock master
295 * (so all 3 others should be slave)
296 */
297 /* rate = 1.544 Mb/s */
298 if (isT1mode)
299 /* Comet 0 Master Mode(CMODE=0) */
300 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
301 /* rate = 2.048 Mb/s */
302 else
303 /* Comet 0 Master Mode(CMODE=0) */
304 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
305
306 /* 31: BRIF frame pulse cfg 06: tx timing options */
307
308 /* Master Mode i.e.FPMODE=0 (@0x20) */
309 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
310 if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
311 if (cxt1e1_log_level >= LOG_SBEBUG12)
312 pr_info(">> %s: clockmaster internal clock\n",
313 __func__);
314 /* internal oscillator */
315 pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
316 } else {
317 /* external clock source */
318 if (cxt1e1_log_level >= LOG_SBEBUG12)
319 pr_info(">> %s: clockmaster external clock\n",
320 __func__);
321 /* loop timing(external) */
322 pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
323 }
324
325 } else {
326 /* slave */
327 if (isT1mode)
328 /* Slave Mode(CMODE=1, see above) */
329 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
330 else
331 /* Slave Mode(CMODE=1)*/
332 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
333 /* Slave Mode i.e. FPMODE=1 (@0x20) */
334 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
335 if (cxt1e1_log_level >= LOG_SBEBUG12)
336 pr_info(">> %s: clockslave internal clock\n", __func__);
337 /* oscillator timing */
338 pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
339 }
340
341 /* 32: BRIF parity F-bit cfg */
342 /* Totem-pole operation */
343 /* Receive Backplane Parity/F-bit */
344 pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
345
346 /* dc: RLPS equalizer V ref */
347 /* Configuration */
348 if (isT1mode)
349 /* RLPS Equalizer Voltage */
350 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
351 else
352 /* RLPS Equalizer Voltage */
353 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
354
355 /* Reserved bit set and SQUELCH enabled */
356 /* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */
357 /* RLPS Configuration Status */
358 pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
359 if (isT1mode)
360 /* ? */
361 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
362 else
363 /* ? */
364 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
365
366
367 /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
368 /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
369 /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
370 /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
371 /*** Transmit side is always an Input, Slave Clock*/
372 /* 40: BTIF cfg 41: loop timing(external) */
373 /*BTIF frame pulse cfg */
374 if (isT1mode)
375 /* BTIF Configuration Reg. */
376 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
377 else
378 /* BTIF Configuration Reg. */
379 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
380 /* BTIF Frame Pulse Config. */
381 pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
382
383 /* 0a: master diag 06: tx timing options */
384 /* if set Comet to loop back */
385
386 /* Comets set to normal */
387 pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
388
389 /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */
390 /* Store is enabled. */
391
392 WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
393 if (isT1mode)
394 WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
395 else
396 WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
397 SetPwrLevel(comet);
398}
399
400/*
401** Name: WrtXmtWaveform
402** Description: Formulate the Data for the Pulse Waveform Storage
403** Write register, (F2), from the sample and unit inputs.
404** Write the data to the Pulse Waveform Storage Data register.
405** Returns: Nothing
406*/
407static void
408WrtXmtWaveform(ci_t *ci, struct s_comet_reg *comet, u_int32_t sample,
409 u_int32_t unit, u_int8_t data)
410{
411 u_int8_t WaveformAddr;
412
413 WaveformAddr = (sample << 3) + (unit & 7);
414 pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
415 /* for write order preservation when Optimizing driver */
416 pci_flush_write(ci);
417 pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
418}
419
420/*
421** Name: WrtXmtWaveformTbl
422** Description: Fill in the Transmit Waveform Values
423** for driving the transmitter DAC.
424** Returns: Nothing
425*/
426static void
427WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
428 u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
429{
430 u_int32_t sample, unit;
431
432 for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
433 for (unit = 0; unit < COMET_NUM_UNITS; unit++)
434 WrtXmtWaveform(ci, comet, sample, unit,
435 table[sample][unit]);
436 }
437
438 /* Enable transmitter and set output amplitude */
439 pci_write_32((u_int32_t *) &comet->xlpg_cfg,
440 table[COMET_NUM_SAMPLES][0]);
441}
442
443
444/*
445** Name: WrtXmtWaveform
446** Description: Fill in the Receive Equalizer RAM from the desired
447** table.
448** Returns: Nothing
449**
450** Remarks: Per PM4351 Device Errata, Receive Equalizer RAM Initialization
451** is coded with early setup of indirect address.
452*/
453
454static void
455WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
456{
457 u_int32_t ramaddr;
458 u_int32_t value;
459
460 for (ramaddr = 0; ramaddr < 256; ramaddr++) {
461 /*** the following lines are per Errata 7, 2.5 ***/
462 {
463 /* Set up for a read operation */
464 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
465 /* for write order preservation when Optimizing driver */
466 pci_flush_write(ci);
467 /* write the addr, initiate a read */
468 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
469 (u_int8_t) ramaddr);
470 /* for write order preservation when Optimizing driver */
471 pci_flush_write(ci);
472 /*
473 * wait 3 line rate clock cycles to ensure address bits are
474 * captured by T1/E1 clock
475 */
476
477 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
478 OS_uwait(4, "wret");
479 }
480
481 value = *table++;
482 pci_write_32((u_int32_t *) &comet->rlps_idata3,
483 (u_int8_t) (value >> 24));
484 pci_write_32((u_int32_t *) &comet->rlps_idata2,
485 (u_int8_t) (value >> 16));
486 pci_write_32((u_int32_t *) &comet->rlps_idata1,
487 (u_int8_t) (value >> 8));
488 pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
489 /* for write order preservation when Optimizing driver */
490 pci_flush_write(ci);
491
492 /* Storing RAM address, causes RAM to be updated */
493
494 /* Set up for a write operation */
495 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
496 /* for write order preservation when optimizing driver */
497 pci_flush_write(ci);
498 /* write the addr, initiate a read */
499 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
500 (u_int8_t) ramaddr);
501 /* for write order preservation when optimizing driver */
502 pci_flush_write(ci);
503
504 /*
505 * wait 3 line rate clock cycles to ensure address bits are captured
506 * by T1/E1 clock
507 */
508 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
509 OS_uwait(4, "wret");
510 }
511
512 /* Enable Equalizer & set it to use 256 periods */
513 pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
514}
515
516
517/*
518** Name: SetPwrLevel
519** Description: Implement power level setting algorithm described below
520** Returns: Nothing
521*/
522
523static void
524SetPwrLevel(struct s_comet_reg *comet)
525{
526 u_int32_t temp;
527
528/*
529** Algorithm to Balance the Power Distribution of Ttip Tring
530**
531** Zero register F6
532** Write 0x01 to register F4
533** Write another 0x01 to register F4
534** Read register F4
535** Remove the 0x01 bit by Anding register F4 with 0xFE
536** Write the resultant value to register F4
537** Repeat these steps for register F5
538** Write 0x01 to register F6
539*/
540 /* XLPG Fuse Data Select */
541 pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
542 /* XLPG Analog Test Positive control */
543 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
544 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
545 temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
546 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
547 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
548 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
549 /* XLPG Analog Test Negative control */
550 temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
551 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
552 /* XLPG */
553 pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
554}
555
556
557/*
558** Name: SetCometOps
559** Description: Set up the selected Comet's clock edge drive for both
560** the transmit out the analog side and receive to the
561** backplane side.
562** Returns: Nothing
563*/
564#if 0
565static void
566SetCometOps(struct s_comet_reg *comet)
567{
568 u_int8_t rd_value;
569
570 if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
571 /* read the BRIF Configuration */
572 rd_value = (u_int8_t) pci_read_32((u_int32_t *)
573 &comet->brif_cfg);
574 rd_value &= ~0x20;
575 pci_write_32((u_int32_t *) &comet->brif_cfg,
576 (u_int32_t) rd_value);
577 /* read the BRIF Frame Pulse Configuration */
578 rd_value = (u_int8_t) pci_read_32((u_int32_t *)
579 &comet->brif_fpcfg);
580 rd_value &= ~0x20;
581 pci_write_32((u_int32_t *) &comet->brif_fpcfg,
582 (u_int8_t) rd_value);
583 } else {
584 /* read the BRIF Configuration */
585 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
586 rd_value |= 0x20;
587 pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
588 /* read the BRIF Frame Pulse Configuration */
589 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
590 rd_value |= 0x20;
591 pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
592 }
593}
594#endif
595
596/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/comet.h b/drivers/staging/cxt1e1/comet.h
deleted file mode 100644
index d5d286e47a4b..000000000000
--- a/drivers/staging/cxt1e1/comet.h
+++ /dev/null
@@ -1,353 +0,0 @@
1#ifndef _INC_COMET_H_
2#define _INC_COMET_H_
3
4/*-----------------------------------------------------------------------------
5 * comet.h -
6 *
7 * Copyright (C) 2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *-----------------------------------------------------------------------------
22 */
23
24#include <linux/types.h>
25
26#define VINT32 volatile u_int32_t
27
28struct s_comet_reg {
29 VINT32 gbl_cfg; /* 00 Global Cfg */
30 VINT32 clkmon; /* 01 Clk Monitor */
31 VINT32 rx_opt; /* 02 RX Options */
32 VINT32 rx_line_cfg; /* 03 RX Line Interface Cfg */
33 VINT32 tx_line_cfg; /* 04 TX Line Interface Cfg */
34 VINT32 tx_frpass; /* 05 TX Framing & Bypass Options */
35 VINT32 tx_time; /* 06 TX Timing Options */
36 VINT32 intr_1; /* 07 Intr Source #1 */
37 VINT32 intr_2; /* 08 Intr Source #2 */
38 VINT32 intr_3; /* 09 Intr Source #3 */
39 VINT32 mdiag; /* 0A Master Diagnostics */
40 VINT32 mtest; /* 0B Master Test */
41 VINT32 adiag; /* 0C Analog Diagnostics */
42 VINT32 rev_id; /* 0D Rev/Chip Id/Global PMON Update */
43#define pmon rev_id
44 VINT32 reset; /* 0E Reset */
45 VINT32 prgd_phctl; /* 0F PRGD Positioning/Ctl & HDLC Ctl */
46 VINT32 cdrc_cfg; /* 10 CDRC Cfg */
47 VINT32 cdrc_ien; /* 11 CDRC Intr Enable */
48 VINT32 cdrc_ists; /* 12 CDRC Intr Sts */
49 VINT32 cdrc_alos; /* 13 CDRC Alternate Loss of Signal */
50
51 VINT32 rjat_ists; /* 14 RJAT Intr Sts */
52 VINT32 rjat_n1clk; /* 15 RJAT Reference Clk Divisor (N1) Ctl */
53 VINT32 rjat_n2clk; /* 16 RJAT Output Clk Divisor (N2) Ctl */
54 VINT32 rjat_cfg; /* 17 RJAT Cfg */
55
56 VINT32 tjat_ists; /* 18 TJAT Intr Sts */
57 VINT32 tjat_n1clk; /* 19 TJAT Reference Clk Divisor (N1) Ctl */
58 VINT32 tjat_n2clk; /* 1A TJAT Output Clk Divisor (N2) Ctl */
59 VINT32 tjat_cfg; /* 1B TJAT Cfg */
60
61 VINT32 rx_elst_cfg; /* 1C RX-ELST Cfg */
62 VINT32 rx_elst_ists; /* 1D RX-ELST Intr Sts */
63 VINT32 rx_elst_idle; /* 1E RX-ELST Idle Code */
64 VINT32 _rx_elst_res1f; /* 1F RX-ELST Reserved */
65
66 VINT32 tx_elst_cfg; /* 20 TX-ELST Cfg */
67 VINT32 tx_elst_ists; /* 21 TX-ELST Intr Sts */
68 VINT32 _tx_elst_res22; /* 22 TX-ELST Reserved */
69 VINT32 _tx_elst_res23; /* 23 TX-ELST Reserved */
70 VINT32 __res24; /* 24 Reserved */
71 VINT32 __res25; /* 25 Reserved */
72 VINT32 __res26; /* 26 Reserved */
73 VINT32 __res27; /* 27 Reserved */
74
75 VINT32 rxce1_ctl; /* 28 RXCE RX Data Link 1 Ctl */
76 VINT32 rxce1_bits; /* 29 RXCE RX Data Link 1 Bit Select */
77 VINT32 rxce2_ctl; /* 2A RXCE RX Data Link 2 Ctl */
78 VINT32 rxce2_bits; /* 2B RXCE RX Data Link 2 Bit Select */
79 VINT32 rxce3_ctl; /* 2C RXCE RX Data Link 3 Ctl */
80 VINT32 rxce3_bits; /* 2D RXCE RX Data Link 3 Bit Select */
81 VINT32 _rxce_res2E; /* 2E RXCE Reserved */
82 VINT32 _rxce_res2F; /* 2F RXCE Reserved */
83
84 VINT32 brif_cfg; /* 30 BRIF RX Backplane Cfg */
85 VINT32 brif_fpcfg; /* 31 BRIF RX Backplane Frame Pulse Cfg */
86 VINT32 brif_pfcfg; /* 32 BRIF RX Backplane Parity/F-Bit Cfg */
87 VINT32 brif_tsoff; /* 33 BRIF RX Backplane Time Slot Offset */
88 VINT32 brif_boff; /* 34 BRIF RX Backplane Bit Offset */
89 VINT32 _brif_res35; /* 35 BRIF RX Backplane Reserved */
90 VINT32 _brif_res36; /* 36 BRIF RX Backplane Reserved */
91 VINT32 _brif_res37; /* 37 BRIF RX Backplane Reserved */
92
93 VINT32 txci1_ctl; /* 38 TXCI TX Data Link 1 Ctl */
94 VINT32 txci1_bits; /* 39 TXCI TX Data Link 2 Bit Select */
95 VINT32 txci2_ctl; /* 3A TXCI TX Data Link 1 Ctl */
96 VINT32 txci2_bits; /* 3B TXCI TX Data Link 2 Bit Select */
97 VINT32 txci3_ctl; /* 3C TXCI TX Data Link 1 Ctl */
98 VINT32 txci3_bits; /* 3D TXCI TX Data Link 2 Bit Select */
99 VINT32 _txci_res3E; /* 3E TXCI Reserved */
100 VINT32 _txci_res3F; /* 3F TXCI Reserved */
101
102 VINT32 btif_cfg; /* 40 BTIF TX Backplane Cfg */
103 VINT32 btif_fpcfg; /* 41 BTIF TX Backplane Frame Pulse Cfg */
104 VINT32 btif_pcfgsts; /* 42 BTIF TX Backplane Parity Cfg & Sts */
105 VINT32 btif_tsoff; /* 43 BTIF TX Backplane Time Slot Offset */
106 VINT32 btif_boff; /* 44 BTIF TX Backplane Bit Offset */
107 VINT32 _btif_res45; /* 45 BTIF TX Backplane Reserved */
108 VINT32 _btif_res46; /* 46 BTIF TX Backplane Reserved */
109 VINT32 _btif_res47; /* 47 BTIF TX Backplane Reserved */
110 VINT32 t1_frmr_cfg; /* 48 T1 FRMR Cfg */
111 VINT32 t1_frmr_ien; /* 49 T1 FRMR Intr Enable */
112 VINT32 t1_frmr_ists; /* 4A T1 FRMR Intr Sts */
113 VINT32 __res_4B; /* 4B Reserved */
114 VINT32 ibcd_cfg; /* 4C IBCD Cfg */
115 VINT32 ibcd_ies; /* 4D IBCD Intr Enable/Sts */
116 VINT32 ibcd_act; /* 4E IBCD Activate Code */
117 VINT32 ibcd_deact; /* 4F IBCD Deactivate Code */
118
119 VINT32 sigx_cfg; /* 50 SIGX Cfg/Change of Signaling State */
120 VINT32 sigx_acc_cos; /* 51 SIGX
121 * uP Access Sts/Change of Signaling State */
122 VINT32 sigx_iac_cos; /* 52 SIGX Channel Indirect
123 * Addr/Ctl/Change of Signaling State */
124 VINT32 sigx_idb_cos; /* 53 SIGX Channel Indirect Data
125 * Buffer/Change of Signaling State */
126
127 VINT32 t1_xbas_cfg; /* 54 T1 XBAS Cfg */
128 VINT32 t1_xbas_altx; /* 55 T1 XBAS Alarm TX */
129 VINT32 t1_xibc_ctl; /* 56 T1 XIBC Ctl */
130 VINT32 t1_xibc_lbcode; /* 57 T1 XIBC Loopback Code */
131
132 VINT32 pmon_ies; /* 58 PMON Intr Enable/Sts */
133 VINT32 pmon_fberr; /* 59 PMON Framing Bit Err Cnt */
134 VINT32 pmon_feb_lsb; /* 5A PMON
135 * OFF/COFA/Far End Block Err Cnt (LSB) */
136 VINT32 pmon_feb_msb; /* 5B PMON
137 * OFF/COFA/Far End Block Err Cnt (MSB) */
138 VINT32 pmon_bed_lsb; /* 5C PMON Bit/Err/CRCE Cnt (LSB) */
139 VINT32 pmon_bed_msb; /* 5D PMON Bit/Err/CRCE Cnt (MSB) */
140 VINT32 pmon_lvc_lsb; /* 5E PMON LVC Cnt (LSB) */
141 VINT32 pmon_lvc_msb; /* 5F PMON LVC Cnt (MSB) */
142
143 VINT32 t1_almi_cfg; /* 60 T1 ALMI Cfg */
144 VINT32 t1_almi_ien; /* 61 T1 ALMI Intr Enable */
145 VINT32 t1_almi_ists; /* 62 T1 ALMI Intr Sts */
146 VINT32 t1_almi_detsts; /* 63 T1 ALMI Alarm Detection Sts */
147
148 VINT32 _t1_pdvd_res64; /* 64 T1 PDVD Reserved */
149 VINT32 t1_pdvd_ies; /* 65 T1 PDVD Intr Enable/Sts */
150 VINT32 _t1_xboc_res66; /* 66 T1 XBOC Reserved */
151 VINT32 t1_xboc_code; /* 67 T1 XBOC Code */
152 VINT32 _t1_xpde_res68; /* 68 T1 XPDE Reserved */
153 VINT32 t1_xpde_ies; /* 69 T1 XPDE Intr Enable/Sts */
154
155 VINT32 t1_rboc_ena; /* 6A T1 RBOC Enable */
156 VINT32 t1_rboc_sts; /* 6B T1 RBOC Code Sts */
157
158 VINT32 t1_tpsc_cfg; /* 6C TPSC Cfg */
159 VINT32 t1_tpsc_sts; /* 6D TPSC uP Access Sts */
160 VINT32 t1_tpsc_ciaddr; /* 6E TPSC Channel Indirect
161 * Addr/Ctl */
162 VINT32 t1_tpsc_cidata; /* 6F TPSC Channel Indirect Data
163 * Buffer */
164 VINT32 t1_rpsc_cfg; /* 70 RPSC Cfg */
165 VINT32 t1_rpsc_sts; /* 71 RPSC uP Access Sts */
166 VINT32 t1_rpsc_ciaddr; /* 72 RPSC Channel Indirect
167 * Addr/Ctl */
168 VINT32 t1_rpsc_cidata; /* 73 RPSC Channel Indirect Data
169 * Buffer */
170 VINT32 __res74; /* 74 Reserved */
171 VINT32 __res75; /* 75 Reserved */
172 VINT32 __res76; /* 76 Reserved */
173 VINT32 __res77; /* 77 Reserved */
174
175 VINT32 t1_aprm_cfg; /* 78 T1 APRM Cfg/Ctl */
176 VINT32 t1_aprm_load; /* 79 T1 APRM Manual Load */
177 VINT32 t1_aprm_ists; /* 7A T1 APRM Intr Sts */
178 VINT32 t1_aprm_1sec_2; /* 7B T1 APRM One Second Content Octet 2 */
179 VINT32 t1_aprm_1sec_3; /* 7C T1 APRM One Second Content Octet 3 */
180 VINT32 t1_aprm_1sec_4; /* 7D T1 APRM One Second Content Octet 4 */
181 VINT32 t1_aprm_1sec_5; /* 7E T1 APRM
182 * One Second Content MSB (Octect 5) */
183 VINT32 t1_aprm_1sec_6; /* 7F T1 APRM
184 * One Second Content MSB (Octect 6) */
185
186 VINT32 e1_tran_cfg; /* 80 E1 TRAN Cfg */
187 VINT32 e1_tran_txalarm; /* 81 E1 TRAN TX Alarm/Diagnostic Ctl */
188 VINT32 e1_tran_intctl; /* 82 E1 TRAN International Ctl */
189 VINT32 e1_tran_extrab; /* 83 E1 TRAN Extra Bits Ctl */
190 VINT32 e1_tran_ien; /* 84 E1 TRAN Intr Enable */
191 VINT32 e1_tran_ists; /* 85 E1 TRAN Intr Sts */
192 VINT32 e1_tran_nats; /* 86 E1 TRAN National Bit Codeword
193 * Select */
194 VINT32 e1_tran_nat; /* 87 E1 TRAN National Bit Codeword */
195 VINT32 __res88; /* 88 Reserved */
196 VINT32 __res89; /* 89 Reserved */
197 VINT32 __res8A; /* 8A Reserved */
198 VINT32 __res8B; /* 8B Reserved */
199
200 VINT32 _t1_frmr_res8C; /* 8C T1 FRMR Reserved */
201 VINT32 _t1_frmr_res8D; /* 8D T1 FRMR Reserved */
202 VINT32 __res8E; /* 8E Reserved */
203 VINT32 __res8F; /* 8F Reserved */
204
205 VINT32 e1_frmr_aopts; /* 90 E1 FRMR Frame Alignment Options */
206 VINT32 e1_frmr_mopts; /* 91 E1 FRMR Maintenance Mode Options */
207 VINT32 e1_frmr_ien; /* 92 E1 FRMR Framing Sts Intr Enable */
208 VINT32 e1_frmr_mien; /* 93 E1 FRMR
209 * Maintenance/Alarm Sts Intr Enable */
210 VINT32 e1_frmr_ists; /* 94 E1 FRMR Framing Sts Intr Indication */
211 VINT32 e1_frmr_mists; /* 95 E1 FRMR
212 * Maintenance/Alarm Sts Indication Enable */
213 VINT32 e1_frmr_sts; /* 96 E1 FRMR Framing Sts */
214 VINT32 e1_frmr_masts; /* 97 E1 FRMR Maintenance/Alarm Sts */
215 VINT32 e1_frmr_nat_bits; /* 98 E1 FRMR International/National Bits */
216 VINT32 e1_frmr_crc_lsb; /* 99 E1 FRMR CRC Err Cnt - LSB */
217 VINT32 e1_frmr_crc_msb; /* 9A E1 FRMR CRC Err Cnt - MSB */
218 VINT32 e1_frmr_nat_ien; /* 9B E1 FRMR
219 * National Bit Codeword Intr Enables */
220 VINT32 e1_frmr_nat_ists; /* 9C E1 FRMR
221 * National Bit Codeword Intr/Sts */
222 VINT32 e1_frmr_nat; /* 9D E1 FRMR National Bit Codewords */
223 VINT32 e1_frmr_fp_ien; /* 9E E1 FRMR
224 * Frame Pulse/Alarm Intr Enables */
225 VINT32 e1_frmr_fp_ists; /* 9F E1 FRMR Frame Pulse/Alarm Intr/Sts */
226
227 VINT32 __resA0; /* A0 Reserved */
228 VINT32 __resA1; /* A1 Reserved */
229 VINT32 __resA2; /* A2 Reserved */
230 VINT32 __resA3; /* A3 Reserved */
231 VINT32 __resA4; /* A4 Reserved */
232 VINT32 __resA5; /* A5 Reserved */
233 VINT32 __resA6; /* A6 Reserved */
234 VINT32 __resA7; /* A7 Reserved */
235
236 VINT32 tdpr1_cfg; /* A8 TDPR #1 Cfg */
237 VINT32 tdpr1_utl; /* A9 TDPR #1 Upper TX Threshold */
238 VINT32 tdpr1_ltl; /* AA TDPR #1 Lower TX Threshold */
239 VINT32 tdpr1_ien; /* AB TDPR #1 Intr Enable */
240 VINT32 tdpr1_ists; /* AC TDPR #1 Intr Sts/UDR Clear */
241 VINT32 tdpr1_data; /* AD TDPR #1 TX Data */
242 VINT32 __resAE; /* AE Reserved */
243 VINT32 __resAF; /* AF Reserved */
244 VINT32 tdpr2_cfg; /* B0 TDPR #2 Cfg */
245 VINT32 tdpr2_utl; /* B1 TDPR #2 Upper TX Threshold */
246 VINT32 tdpr2_ltl; /* B2 TDPR #2 Lower TX Threshold */
247 VINT32 tdpr2_ien; /* B3 TDPR #2 Intr Enable */
248 VINT32 tdpr2_ists; /* B4 TDPR #2 Intr Sts/UDR Clear */
249 VINT32 tdpr2_data; /* B5 TDPR #2 TX Data */
250 VINT32 __resB6; /* B6 Reserved */
251 VINT32 __resB7; /* B7 Reserved1 */
252 VINT32 tdpr3_cfg; /* B8 TDPR #3 Cfg */
253 VINT32 tdpr3_utl; /* B9 TDPR #3 Upper TX Threshold */
254 VINT32 tdpr3_ltl; /* BA TDPR #3 Lower TX Threshold */
255 VINT32 tdpr3_ien; /* BB TDPR #3 Intr Enable */
256 VINT32 tdpr3_ists; /* BC TDPR #3 Intr Sts/UDR Clear */
257 VINT32 tdpr3_data; /* BD TDPR #3 TX Data */
258 VINT32 __resBE; /* BE Reserved */
259 VINT32 __resBF; /* BF Reserved */
260
261 VINT32 rdlc1_cfg; /* C0 RDLC #1 Cfg */
262 VINT32 rdlc1_intctl; /* C1 RDLC #1 Intr Ctl */
263 VINT32 rdlc1_sts; /* C2 RDLC #1 Sts */
264 VINT32 rdlc1_data; /* C3 RDLC #1 Data */
265 VINT32 rdlc1_paddr; /* C4 RDLC #1 Primary Addr Match */
266 VINT32 rdlc1_saddr; /* C5 RDLC #1 Secondary Addr Match */
267 VINT32 __resC6; /* C6 Reserved */
268 VINT32 __resC7; /* C7 Reserved */
269 VINT32 rdlc2_cfg; /* C8 RDLC #2 Cfg */
270 VINT32 rdlc2_intctl; /* C9 RDLC #2 Intr Ctl */
271 VINT32 rdlc2_sts; /* CA RDLC #2 Sts */
272 VINT32 rdlc2_data; /* CB RDLC #2 Data */
273 VINT32 rdlc2_paddr; /* CC RDLC #2 Primary Addr Match */
274 VINT32 rdlc2_saddr; /* CD RDLC #2 Secondary Addr Match */
275 VINT32 __resCE; /* CE Reserved */
276 VINT32 __resCF; /* CF Reserved */
277 VINT32 rdlc3_cfg; /* D0 RDLC #3 Cfg */
278 VINT32 rdlc3_intctl; /* D1 RDLC #3 Intr Ctl */
279 VINT32 rdlc3_sts; /* D2 RDLC #3 Sts */
280 VINT32 rdlc3_data; /* D3 RDLC #3 Data */
281 VINT32 rdlc3_paddr; /* D4 RDLC #3 Primary Addr Match */
282 VINT32 rdlc3_saddr; /* D5 RDLC #3 Secondary Addr Match */
283
284 VINT32 csu_cfg; /* D6 CSU Cfg */
285 VINT32 _csu_resD7; /* D7 CSU Reserved */
286
287 VINT32 rlps_idata3; /* D8 RLPS Indirect Data, 24-31 */
288 VINT32 rlps_idata2; /* D9 RLPS Indirect Data, 16-23 */
289 VINT32 rlps_idata1; /* DA RLPS Indirect Data, 8-15 */
290 VINT32 rlps_idata0; /* DB RLPS Indirect Data, 0-7 */
291 VINT32 rlps_eqvr; /* DC RLPS Equalizer Voltage Reference
292 * (E1 missing) */
293 VINT32 _rlps_resDD; /* DD RLPS Reserved */
294 VINT32 _rlps_resDE; /* DE RLPS Reserved */
295 VINT32 _rlps_resDF; /* DF RLPS Reserved */
296
297 VINT32 prgd_ctl; /* E0 PRGD Ctl */
298 VINT32 prgd_ies; /* E1 PRGD Intr Enable/Sts */
299 VINT32 prgd_shift_len; /* E2 PRGD Shift Length */
300 VINT32 prgd_tap; /* E3 PRGD Tap */
301 VINT32 prgd_errin; /* E4 PRGD Err Insertion */
302 VINT32 _prgd_resE5; /* E5 PRGD Reserved */
303 VINT32 _prgd_resE6; /* E6 PRGD Reserved */
304 VINT32 _prgd_resE7; /* E7 PRGD Reserved */
305 VINT32 prgd_patin1; /* E8 PRGD Pattern Insertion #1 */
306 VINT32 prgd_patin2; /* E9 PRGD Pattern Insertion #2 */
307 VINT32 prgd_patin3; /* EA PRGD Pattern Insertion #3 */
308 VINT32 prgd_patin4; /* EB PRGD Pattern Insertion #4 */
309 VINT32 prgd_patdet1; /* EC PRGD Pattern Detector #1 */
310 VINT32 prgd_patdet2; /* ED PRGD Pattern Detector #2 */
311 VINT32 prgd_patdet3; /* EE PRGD Pattern Detector #3 */
312 VINT32 prgd_patdet4; /* EF PRGD Pattern Detector #4 */
313
314 VINT32 xlpg_cfg; /* F0 XLPG Line Driver Cfg */
315 VINT32 xlpg_ctlsts; /* F1 XLPG Ctl/Sts */
316 VINT32 xlpg_pwave_addr; /* F2 XLPG
317 * Pulse Waveform Storage Write Addr */
318 VINT32 xlpg_pwave_data; /* F3 XLPG Pulse Waveform Storage Data */
319 VINT32 xlpg_atest_pctl; /* F4 XLPG Analog Test Positive Ctl */
320 VINT32 xlpg_atest_nctl; /* F5 XLPG Analog Test Negative Ctl */
321 VINT32 xlpg_fdata_sel; /* F6 XLPG Fuse Data Select */
322 VINT32 _xlpg_resF7; /* F7 XLPG Reserved */
323
324 VINT32 rlps_cfgsts; /* F8 RLPS Cfg & Sts */
325 VINT32 rlps_alos_thresh; /* F9 RLPS
326 * ALOS Detection/Clearance Threshold */
327 VINT32 rlps_alos_dper; /* FA RLPS ALOS Detection Period */
328 VINT32 rlps_alos_cper; /* FB RLPS ALOS Clearance Period */
329 VINT32 rlps_eq_iaddr; /* FC RLPS Equalization Indirect Addr */
330 VINT32 rlps_eq_rwsel; /* FD RLPS Equalization Read/WriteB Select */
331 VINT32 rlps_eq_ctlsts; /* FE RLPS Equalizer Loop Sts & Ctl */
332 VINT32 rlps_eq_cfg; /* FF RLPS Equalizer Cfg */
333};
334
335/* 00AH: MDIAG Register bit definitions */
336#define COMET_MDIAG_ID5 0x40
337#define COMET_MDIAG_LBMASK 0x3F
338#define COMET_MDIAG_PAYLB 0x20
339#define COMET_MDIAG_LINELB 0x10
340#define COMET_MDIAG_RAIS 0x08
341#define COMET_MDIAG_DDLB 0x04
342#define COMET_MDIAG_TXMFP 0x02
343#define COMET_MDIAG_TXLOS 0x01
344#define COMET_MDIAG_LBOFF 0x00
345
346#undef VINT32
347
348#ifdef __KERNEL__
349extern void
350init_comet(void *, struct s_comet_reg *, u_int32_t, int, u_int8_t);
351#endif
352
353#endif /* _INC_COMET_H_ */
diff --git a/drivers/staging/cxt1e1/comet_tables.c b/drivers/staging/cxt1e1/comet_tables.c
deleted file mode 100644
index e96665ea3662..000000000000
--- a/drivers/staging/cxt1e1/comet_tables.c
+++ /dev/null
@@ -1,538 +0,0 @@
1/*-----------------------------------------------------------------------------
2 * comet_tables.c - waveform tables for the PM4351 'COMET'
3 *
4 * Copyright (C) 2003-2005 SBE, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * For further information, contact via email: support@sbei.com
17 * SBE, Inc. San Ramon, California U.S.A.
18 *-----------------------------------------------------------------------------
19 */
20
21#include <linux/types.h>
22#include "comet_tables.h"
23
24/*****************************************************************************
25*
26* Array names:
27*
28* TWVLongHaul0DB
29* TWVLongHaul7_5DB
30* TWVLongHaul15DB
31* TWVLongHaul22_5DB
32* TWVShortHaul0
33* TWVShortHaul1
34* TWVShortHaul2
35* TWVShortHaul3
36* TWVShortHaul4
37* TWVShortHaul5
38* TWV_E1_120Ohm
39* TWV_E1_75Ohm <not supported>
40* T1_Equalizer
41* E1_Equalizer
42*
43*****************************************************************************/
44
45u_int8_t TWVLongHaul0DB[25][5] =/* T1 Long Haul 0 DB */
46{
47 {0x00, 0x44, 0x00, 0x00, 0x00}, /* Sample 0 */
48 {0x0A, 0x44, 0x00, 0x00, 0x00}, /* Sample 1 */
49 {0x20, 0x43, 0x00, 0x00, 0x00}, /* Sample 2 */
50 {0x32, 0x43, 0x00, 0x00, 0x00}, /* Sample 3 */
51 {0x3E, 0x42, 0x00, 0x00, 0x00}, /* Sample 4 */
52 {0x3D, 0x42, 0x00, 0x00, 0x00}, /* Sample 5 */
53 {0x3C, 0x41, 0x00, 0x00, 0x00}, /* Sample 6 */
54 {0x3B, 0x41, 0x00, 0x00, 0x00}, /* Sample 7 */
55 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
56 {0x39, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
57 {0x39, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
58 {0x38, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
59 {0x37, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
60 {0x36, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
61 {0x34, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
62 {0x29, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
63 {0x4F, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
64 {0x4C, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
65 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
66 {0x49, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
67 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
68 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
69 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
70 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
71 {0x0C} /* PMC's suggested value */
72/* {0x14} Output Amplitude */
73};
74
75u_int8_t TWVLongHaul7_5DB[25][5] = /* T1 Long Haul 7.5 DB */
76{
77 {0x00, 0x10, 0x00, 0x00, 0x00}, /* Sample 0 */
78 {0x01, 0x0E, 0x00, 0x00, 0x00}, /* Sample 1 */
79 {0x02, 0x0C, 0x00, 0x00, 0x00}, /* Sample 2 */
80 {0x04, 0x0A, 0x00, 0x00, 0x00}, /* Sample 3 */
81 {0x08, 0x08, 0x00, 0x00, 0x00}, /* Sample 4 */
82 {0x0C, 0x06, 0x00, 0x00, 0x00}, /* Sample 5 */
83 {0x10, 0x04, 0x00, 0x00, 0x00}, /* Sample 6 */
84 {0x16, 0x02, 0x00, 0x00, 0x00}, /* Sample 7 */
85 {0x1A, 0x01, 0x00, 0x00, 0x00}, /* Sample 8 */
86 {0x1E, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
87 {0x22, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
88 {0x26, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
89 {0x2A, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
90 {0x2B, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
91 {0x2C, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
92 {0x2D, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
93 {0x2C, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
94 {0x28, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
95 {0x24, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
96 {0x20, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
97 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
98 {0x18, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
99 {0x14, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
100 {0x12, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
101 {0x07} /* PMC's suggested value */
102/* { 0x0A } Output Amplitude */
103};
104
105u_int8_t TWVLongHaul15DB[25][5] = /* T1 Long Haul 15 DB */
106{
107 {0x00, 0x2A, 0x09, 0x01, 0x00}, /* Sample 0 */
108 {0x00, 0x28, 0x08, 0x01, 0x00}, /* Sample 1 */
109 {0x00, 0x26, 0x08, 0x01, 0x00}, /* Sample 2 */
110 {0x00, 0x24, 0x07, 0x01, 0x00}, /* Sample 3 */
111 {0x01, 0x22, 0x07, 0x01, 0x00}, /* Sample 4 */
112 {0x02, 0x20, 0x06, 0x01, 0x00}, /* Sample 5 */
113 {0x04, 0x1E, 0x06, 0x01, 0x00}, /* Sample 6 */
114 {0x07, 0x1C, 0x05, 0x00, 0x00}, /* Sample 7 */
115 {0x0A, 0x1B, 0x05, 0x00, 0x00}, /* Sample 8 */
116 {0x0D, 0x19, 0x05, 0x00, 0x00}, /* Sample 9 */
117 {0x10, 0x18, 0x04, 0x00, 0x00}, /* Sample 10 */
118 {0x14, 0x16, 0x04, 0x00, 0x00}, /* Sample 11 */
119 {0x18, 0x15, 0x04, 0x00, 0x00}, /* Sample 12 */
120 {0x1B, 0x13, 0x03, 0x00, 0x00}, /* Sample 13 */
121 {0x1E, 0x12, 0x03, 0x00, 0x00}, /* Sample 14 */
122 {0x21, 0x10, 0x03, 0x00, 0x00}, /* Sample 15 */
123 {0x24, 0x0F, 0x03, 0x00, 0x00}, /* Sample 16 */
124 {0x27, 0x0D, 0x03, 0x00, 0x00}, /* Sample 17 */
125 {0x2A, 0x0D, 0x02, 0x00, 0x00}, /* Sample 18 */
126 {0x2D, 0x0B, 0x02, 0x00, 0x00}, /* Sample 19 */
127 {0x30, 0x0B, 0x02, 0x00, 0x00}, /* Sample 20 */
128 {0x30, 0x0A, 0x02, 0x00, 0x00}, /* Sample 21 */
129 {0x2E, 0x0A, 0x02, 0x00, 0x00}, /* Sample 22 */
130 {0x2C, 0x09, 0x02, 0x00, 0x00}, /* Sample 23 */
131 {0x03} /* Output Amplitude */
132};
133
134u_int8_t TWVLongHaul22_5DB[25][5] = /* T1 Long Haul 22.5 DB */
135{
136 {0x00, 0x1F, 0x16, 0x06, 0x01}, /* Sample 0 */
137 {0x00, 0x20, 0x15, 0x05, 0x01}, /* Sample 1 */
138 {0x00, 0x21, 0x15, 0x05, 0x01}, /* Sample 2 */
139 {0x00, 0x22, 0x14, 0x05, 0x01}, /* Sample 3 */
140 {0x00, 0x22, 0x13, 0x04, 0x00}, /* Sample 4 */
141 {0x00, 0x23, 0x12, 0x04, 0x00}, /* Sample 5 */
142 {0x01, 0x23, 0x12, 0x04, 0x00}, /* Sample 6 */
143 {0x01, 0x24, 0x11, 0x03, 0x00}, /* Sample 7 */
144 {0x01, 0x23, 0x10, 0x03, 0x00}, /* Sample 8 */
145 {0x02, 0x23, 0x10, 0x03, 0x00}, /* Sample 9 */
146 {0x03, 0x22, 0x0F, 0x03, 0x00}, /* Sample 10 */
147 {0x05, 0x22, 0x0E, 0x03, 0x00}, /* Sample 11 */
148 {0x07, 0x21, 0x0E, 0x02, 0x00}, /* Sample 12 */
149 {0x09, 0x20, 0x0D, 0x02, 0x00}, /* Sample 13 */
150 {0x0B, 0x1E, 0x0C, 0x02, 0x00}, /* Sample 14 */
151 {0x0E, 0x1D, 0x0C, 0x02, 0x00}, /* Sample 15 */
152 {0x10, 0x1B, 0x0B, 0x02, 0x00}, /* Sample 16 */
153 {0x13, 0x1B, 0x0A, 0x02, 0x00}, /* Sample 17 */
154 {0x15, 0x1A, 0x0A, 0x02, 0x00}, /* Sample 18 */
155 {0x17, 0x19, 0x09, 0x01, 0x00}, /* Sample 19 */
156 {0x19, 0x19, 0x08, 0x01, 0x00}, /* Sample 20 */
157 {0x1B, 0x18, 0x08, 0x01, 0x00}, /* Sample 21 */
158 {0x1D, 0x17, 0x07, 0x01, 0x00}, /* Sample 22 */
159 {0x1E, 0x17, 0x06, 0x01, 0x00}, /* Sample 23 */
160 {0x02} /* Output Amplitude */
161};
162
163u_int8_t TWVShortHaul0[25][5] = /* T1 Short Haul 0 - 110 ft */
164{
165 {0x00, 0x45, 0x00, 0x00, 0x00}, /* Sample 0 */
166 {0x0A, 0x44, 0x00, 0x00, 0x00}, /* Sample 1 */
167 {0x20, 0x43, 0x00, 0x00, 0x00}, /* Sample 2 */
168 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 3 */
169 {0x3F, 0x42, 0x00, 0x00, 0x00}, /* Sample 4 */
170 {0x3F, 0x42, 0x00, 0x00, 0x00}, /* Sample 5 */
171 {0x3C, 0x41, 0x00, 0x00, 0x00}, /* Sample 6 */
172 {0x3B, 0x41, 0x00, 0x00, 0x00}, /* Sample 7 */
173 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
174 {0x39, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
175 {0x39, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
176 {0x38, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
177 {0x37, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
178 {0x36, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
179 {0x34, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
180 {0x29, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
181 {0x59, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
182 {0x55, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
183 {0x50, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
184 {0x4D, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
185 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
186 {0x48, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
187 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
188 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
189 {0x0C} /* Output Amplitude */
190};
191
192u_int8_t TWVShortHaul1[25][5] = /* T1 Short Haul 110 - 220 ft */
193{
194 {0x00, 0x44, 0x00, 0x00, 0x00}, /* Sample 0 */
195 {0x0A, 0x44, 0x00, 0x00, 0x00}, /* Sample 1 */
196 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 2 */
197 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 3 */
198 {0x36, 0x42, 0x00, 0x00, 0x00}, /* Sample 4 */
199 {0x34, 0x42, 0x00, 0x00, 0x00}, /* Sample 5 */
200 {0x30, 0x41, 0x00, 0x00, 0x00}, /* Sample 6 */
201 {0x2F, 0x41, 0x00, 0x00, 0x00}, /* Sample 7 */
202 {0x2E, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
203 {0x2D, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
204 {0x2C, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
205 {0x2B, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
206 {0x2A, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
207 {0x28, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
208 {0x26, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
209 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
210 {0x68, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
211 {0x54, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
212 {0x4F, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
213 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
214 {0x49, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
215 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
216 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
217 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
218 {0x10} /* Output Amplitude */
219};
220
221u_int8_t TWVShortHaul2[25][5] = /* T1 Short Haul 220 - 330 ft */
222{
223 {0x00, 0x44, 0x00, 0x00, 0x00}, /* Sample 0 */
224 {0x0A, 0x44, 0x00, 0x00, 0x00}, /* Sample 1 */
225 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 2 */
226 {0x3A, 0x43, 0x00, 0x00, 0x00}, /* Sample 3 */
227 {0x3A, 0x42, 0x00, 0x00, 0x00}, /* Sample 4 */
228 {0x38, 0x42, 0x00, 0x00, 0x00}, /* Sample 5 */
229 {0x30, 0x41, 0x00, 0x00, 0x00}, /* Sample 6 */
230 {0x2F, 0x41, 0x00, 0x00, 0x00}, /* Sample 7 */
231 {0x2E, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
232 {0x2D, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
233 {0x2C, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
234 {0x2B, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
235 {0x2A, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
236 {0x29, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
237 {0x23, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
238 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
239 {0x6C, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
240 {0x60, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
241 {0x4F, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
242 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
243 {0x49, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
244 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
245 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
246 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
247 {0x11} /* Output Amplitude */
248};
249
250u_int8_t TWVShortHaul3[25][5] = /* T1 Short Haul 330 - 440 ft */
251{
252 {0x00, 0x44, 0x00, 0x00, 0x00}, /* Sample 0 */
253 {0x0A, 0x44, 0x00, 0x00, 0x00}, /* Sample 1 */
254 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 2 */
255 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 3 */
256 {0x3F, 0x42, 0x00, 0x00, 0x00}, /* Sample 4 */
257 {0x3F, 0x42, 0x00, 0x00, 0x00}, /* Sample 5 */
258 {0x2F, 0x41, 0x00, 0x00, 0x00}, /* Sample 6 */
259 {0x2E, 0x41, 0x00, 0x00, 0x00}, /* Sample 7 */
260 {0x2D, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
261 {0x2C, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
262 {0x2B, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
263 {0x2A, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
264 {0x29, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
265 {0x28, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
266 {0x19, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
267 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
268 {0x7F, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
269 {0x60, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
270 {0x4F, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
271 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
272 {0x49, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
273 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
274 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
275 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
276 {0x12} /* Output Amplitude */
277};
278
279u_int8_t TWVShortHaul4[25][5] = /* T1 Short Haul 440 - 550 ft */
280{
281 {0x00, 0x44, 0x00, 0x00, 0x00}, /* Sample 0 */
282 {0x0A, 0x44, 0x00, 0x00, 0x00}, /* Sample 1 */
283 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 2 */
284 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 3 */
285 {0x3F, 0x42, 0x00, 0x00, 0x00}, /* Sample 4 */
286 {0x3F, 0x42, 0x00, 0x00, 0x00}, /* Sample 5 */
287 {0x30, 0x41, 0x00, 0x00, 0x00}, /* Sample 6 */
288 {0x2B, 0x41, 0x00, 0x00, 0x00}, /* Sample 7 */
289 {0x2A, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
290 {0x29, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
291 {0x28, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
292 {0x27, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
293 {0x26, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
294 {0x26, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
295 {0x24, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
296 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
297 {0x7F, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
298 {0x7F, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
299 {0x4F, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
300 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
301 {0x49, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
302 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
303 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
304 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
305 {0x14} /* Output Amplitude */
306};
307
308u_int8_t TWVShortHaul5[25][5] = /* T1 Short Haul 550 - 660 ft */
309{
310 {0x00, 0x44, 0x00, 0x00, 0x00}, /* Sample 0 */
311 {0x0A, 0x44, 0x00, 0x00, 0x00}, /* Sample 1 */
312 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 2 */
313 {0x3F, 0x43, 0x00, 0x00, 0x00}, /* Sample 3 */
314 {0x3F, 0x42, 0x00, 0x00, 0x00}, /* Sample 4 */
315 {0x3F, 0x42, 0x00, 0x00, 0x00}, /* Sample 5 */
316 {0x3F, 0x41, 0x00, 0x00, 0x00}, /* Sample 6 */
317 {0x30, 0x41, 0x00, 0x00, 0x00}, /* Sample 7 */
318 {0x2A, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
319 {0x29, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
320 {0x28, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
321 {0x27, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
322 {0x26, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
323 {0x25, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
324 {0x24, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
325 {0x4A, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
326 {0x7F, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
327 {0x7F, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
328 {0x5F, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
329 {0x50, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
330 {0x49, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
331 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
332 {0x47, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
333 {0x46, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
334 {0x15} /* Output Amplitude */
335};
336
337u_int8_t TWV_E1_120Ohm[25][5] = /* E1 120 Ohm */
338{
339 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 0 */
340 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 1 */
341 {0x0A, 0x00, 0x00, 0x00, 0x00}, /* Sample 2 */
342 {0x3F, 0x00, 0x00, 0x00, 0x00}, /* Sample 3 */
343 {0x3F, 0x00, 0x00, 0x00, 0x00}, /* Sample 4 */
344 {0x39, 0x00, 0x00, 0x00, 0x00}, /* Sample 5 */
345 {0x38, 0x00, 0x00, 0x00, 0x00}, /* Sample 6 */
346 {0x36, 0x00, 0x00, 0x00, 0x00}, /* Sample 7 */
347 {0x36, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
348 {0x35, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
349 {0x35, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
350 {0x35, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
351 {0x35, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
352 {0x35, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
353 {0x35, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
354 {0x2D, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
355 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
356 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
357 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
358 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
359 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
360 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
361 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
362 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
363 {0x0C} /* PMC's suggested value */
364/* { 0x10 } Output Amplitude */
365};
366
367
368
369u_int8_t TWV_E1_75Ohm[25][5] = /* E1 75 Ohm */
370{
371#ifdef PMCC4_DOES_NOT_SUPPORT
372 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 0 */
373 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 1 */
374 {0x0A, 0x00, 0x00, 0x00, 0x00}, /* Sample 2 */
375 {0x28, 0x00, 0x00, 0x00, 0x00}, /* Sample 3 */
376 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 4 */
377 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 5 */
378 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 6 */
379 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 7 */
380 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 8 */
381 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 9 */
382 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 10 */
383 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 11 */
384 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 12 */
385 {0x3A, 0x00, 0x00, 0x00, 0x00}, /* Sample 13 */
386 {0x32, 0x00, 0x00, 0x00, 0x00}, /* Sample 14 */
387 {0x14, 0x00, 0x00, 0x00, 0x00}, /* Sample 15 */
388 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 16 */
389 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 17 */
390 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 18 */
391 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 19 */
392 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 20 */
393 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 21 */
394 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 22 */
395 {0x00, 0x00, 0x00, 0x00, 0x00}, /* Sample 23 */
396#endif
397 {0x0C} /* Output Amplitude */
398};
399
400
401u_int32_t T1_Equalizer[256] = /* T1 Receiver Equalizer */
402{
403 0x03FE1840, 0x03F61840, 0x03EE1840, 0x03E61840, /* 000 - 003 */
404 0x03DE1840, 0x03D61840, 0x03D61840, 0x03D61840, /* 004 - 007 */
405 0x03CE1840, 0x03CE1840, 0x03CE1840, 0x03CE1840, /* 008 - 011 */
406 0x03C61840, 0x03C61840, 0x03C61840, 0x0BBE1840, /* 012 - 015 */
407 0x0BBE1840, 0x0BBE1840, 0x0BBE1840, 0x0BB61840, /* 016 - 019 */
408 0x0BB61840, 0x0BB61840, 0x0BB61840, 0x13AE1838, /* 020 - 023 */
409 0x13AE183C, 0x13AE1840, 0x13AE1840, 0x13AE1840, /* 024 - 027 */
410 0x13AE1840, 0x1BB618B8, 0x1BAE18B8, 0x1BAE18BC, /* 028 - 031 */
411 0x1BAE18C0, 0x1BAE18C0, 0x23A618C0, 0x23A618C0, /* 032 - 035 */
412 0x23A618C0, 0x23A618C0, 0x23A618C0, 0x239E18C0, /* 036 - 039 */
413 0x239E18C0, 0x239E18C0, 0x239E18C0, 0x239E18C0, /* 040 - 043 */
414 0x2B9618C0, 0x2B9618C0, 0x2B9618C0, 0x33961940, /* 044 - 047 */
415 0x37961940, 0x37961940, 0x37961940, 0x3F9E19C0, /* 048 - 051 */
416 0x3F9E19C0, 0x3F9E19C0, 0x3FA61A40, 0x3FA61A40, /* 052 - 055 */
417 0x3FA61A40, 0x3FA61A40, 0x3F9619C0, 0x3F9619C0, /* 056 - 059 */
418 0x3F9619C0, 0x3F9619C0, 0x479E1A40, 0x479E1A40, /* 060 - 063 */
419 0x479E1A40, 0x47961A40, 0x47961A40, 0x47961A40, /* 064 - 067 */
420 0x47961A40, 0x4F8E1A40, 0x4F8E1A40, 0x4F8E1A40, /* 068 - 071 */
421 0x4F8E1A40, 0x4F8E1A40, 0x57861A40, 0x57861A40, /* 072 - 075 */
422 0x57861A40, 0x57861A40, 0x57861A40, 0x5F861AC0, /* 076 - 079 */
423 0x5F861AC0, 0x5F861AC0, 0x5F861AC0, 0x5F861AC0, /* 080 - 083 */
424 0x5F861AC0, 0x5F7E1AC0, 0x5F7E1AC0, 0x5F7E1AC0, /* 084 - 087 */
425 0x5F7E1AC0, 0x5F7E1AC0, 0x677E2AC0, 0x677E2AC0, /* 088 - 091 */
426 0x677E2AC0, 0x677E2AC0, 0x67762AC0, 0x67762AC0, /* 092 - 095 */
427 0x67762AC0, 0x67762AC0, 0x67762AC0, 0x6F6E2AC0, /* 096 - 099 */
428 0x6F6E2AC0, 0x6F6E2AC0, 0x6F6E2AC0, 0x776E3AC0, /* 100 - 103 */
429 0x776E3AC0, 0x776E3AC0, 0x776E3AC0, 0x7F663AC0, /* 104 - 107 */
430 0x7F663AC0, 0x7F664AC0, 0x7F664AC0, 0x7F664AC0, /* 108 - 111 */
431 0x7F664AC0, 0x87665AC0, 0x87665AC0, 0x87665AC0, /* 112 - 115 */
432 0x87665AC0, 0x87665AC0, 0x875E5AC0, 0x875E5AC0, /* 116 - 119 */
433 0x875E5AC0, 0x875E5AC0, 0x875E5AC0, 0x8F5E6AC0, /* 120 - 123 */
434 0x8F5E6AC0, 0x8F5E6AC0, 0x8F5E6AC0, 0x975E7AC0, /* 124 - 127 */
435 0x975E7AC0, 0x975E7AC0, 0x975E7AC0, 0x9F5E8AC0, /* 128 - 131 */
436 0x9F5E8AC0, 0x9F5E8AC0, 0x9F5E8AC0, 0x9F5E8AC0, /* 132 - 135 */
437 0xA7569AC0, 0xA7569AC0, 0xA7569AC0, 0xA7569AC0, /* 136 - 139 */
438 0xA756AAC0, 0xA756AAC0, 0xA756AAC0, 0xAF4EAAC0, /* 140 - 143 */
439 0xAF4EAAC0, 0xAF4EAAC0, 0xAF4EAAC0, 0xAF4EAAC0, /* 144 - 147 */
440 0xB746AAC0, 0xB746AAC0, 0xB746AAC0, 0xB746AAC0, /* 148 - 151 */
441 0xB746AAC0, 0xB746AAC0, 0xB746AAC0, 0xB746BAC0, /* 152 - 155 */
442 0xB746BAC0, 0xB746BAC0, 0xBF4EBB40, 0xBF4EBB40, /* 156 - 159 */
443 0xBF4EBB40, 0xBF4EBB40, 0xBF4EBB40, 0xBF4EBB40, /* 160 - 163 */
444 0xBF4EBB40, 0xBF4EBB40, 0xBF4EBB40, 0xBE46CB40, /* 164 - 167 */
445 0xBE46CB40, 0xBE46CB40, 0xBE46CB40, 0xBE46CB40, /* 168 - 171 */
446 0xBE46CB40, 0xBE46DB40, 0xBE46DB40, 0xBE46DB40, /* 172 - 175 */
447 0xC63ECB40, 0xC63ECB40, 0xC63EDB40, 0xC63EDB40, /* 176 - 179 */
448 0xC63EDB40, 0xC644DB40, 0xC644DB40, 0xC644DB40, /* 180 - 183 */
449 0xC644DB40, 0xC63CDB40, 0xC63CDB40, 0xC63CDB40, /* 184 - 187 */
450 0xC63CDB40, 0xD634DB40, 0xD634DB40, 0xD634DB40, /* 188 - 191 */
451 0xD634DB40, 0xD634DB40, 0xDE2CDB3C, 0xDE2CDB3C, /* 192 - 195 */
452 0xDE2CDB3C, 0xE62CDB40, 0xE62CDB40, 0xE62CDB40, /* 196 - 199 */
453 0xE62CDB40, 0xE62CDB40, 0xE62CEB40, 0xE62CEB40, /* 200 - 203 */
454 0xE62CEB40, 0xEE2CFB40, 0xEE2CFB40, 0xEE2CFB40, /* 204 - 207 */
455 0xEE2D0B40, 0xEE2D0B40, 0xEE2D0B40, 0xEE2D0B40, /* 208 - 211 */
456 0xEE2D0B40, 0xF5250B38, 0xF5250B3C, 0xF5250B40, /* 212 - 215 */
457 0xF5251B40, 0xF5251B40, 0xF5251B40, 0xF5251B40, /* 216 - 219 */
458 0xF5251B40, 0xFD252B40, 0xFD252B40, 0xFD252B40, /* 220 - 223 */
459 0xFD252B40, 0xFD252740, 0xFD252740, 0xFD252740, /* 224 - 227 */
460 0xFD252340, 0xFD252340, 0xFD252340, 0xFD253340, /* 228 - 231 */
461 0xFD253340, 0xFD253340, 0xFD253340, 0xFD253340, /* 232 - 235 */
462 0xFD253340, 0xFD253340, 0xFD253340, 0xFC254340, /* 236 - 239 */
463 0xFD254340, 0xFD254340, 0xFD254344, 0xFC254348, /* 240 - 243 */
464 0xFC25434C, 0xFD2543BC, 0xFD2543C0, 0xFC2543C0, /* 244 - 247 */
465 0xFC2343C0, 0xFC2343C0, 0xFD2343C0, 0xFC2143C0, /* 248 - 251 */
466 0xFC2143C0, 0xFC2153C0, 0xFD2153C0, 0xFC2153C0 /* 252 - 255 */
467};
468
469
470u_int32_t E1_Equalizer[256] = /* E1 Receiver Equalizer */
471{
472 0x07DE182C, 0x07DE182C, 0x07D6182C, 0x07D6182C, /* 000 - 003 */
473 0x07D6182C, 0x07CE182C, 0x07CE182C, 0x07CE182C, /* 004 - 007 */
474 0x07C6182C, 0x07C6182C, 0x07C6182C, 0x07BE182C, /* 008 - 011 */
475 0x07BE182C, 0x07BE182C, 0x07BE182C, 0x07BE182C, /* 012 - 015 */
476 0x07B6182C, 0x07B6182C, 0x07B6182C, 0x07B6182C, /* 016 - 019 */
477 0x07B6182C, 0x07AE182C, 0x07AE182C, 0x07AE182C, /* 020 - 023 */
478 0x07AE182C, 0x07AE182C, 0x07B618AC, 0x07AE18AC, /* 024 - 027 */
479 0x07AE18AC, 0x07AE18AC, 0x07AE18AC, 0x07A618AC, /* 028 - 031 */
480 0x07A618AC, 0x07A618AC, 0x07A618AC, 0x079E18AC, /* 032 - 035 */
481 0x07A6192C, 0x07A6192C, 0x07A6192C, 0x0FA6192C, /* 036 - 039 */
482 0x0FA6192C, 0x0F9E192C, 0x0F9E192C, 0x0F9E192C, /* 040 - 043 */
483 0x179E192C, 0x17A619AC, 0x179E19AC, 0x179E19AC, /* 044 - 047 */
484 0x179619AC, 0x1F9619AC, 0x1F9619AC, 0x1F8E19AC, /* 048 - 051 */
485 0x1F8E19AC, 0x1F8E19AC, 0x278E19AC, 0x278E1A2C, /* 052 - 055 */
486 0x278E1A2C, 0x278E1A2C, 0x278E1A2C, 0x2F861A2C, /* 056 - 059 */
487 0x2F861A2C, 0x2F861A2C, 0x2F7E1A2C, 0x2F7E1A2C, /* 060 - 063 */
488 0x2F7E1A2C, 0x377E1A2C, 0x377E1AAC, 0x377E1AAC, /* 064 - 067 */
489 0x377E1AAC, 0x377E1AAC, 0x3F7E2AAC, 0x3F7E2AAC, /* 068 - 071 */
490 0x3F762AAC, 0x3F862B2C, 0x3F7E2B2C, 0x477E2B2C, /* 072 - 075 */
491 0x477E2F2C, 0x477E2F2C, 0x477E2F2C, 0x47762F2C, /* 076 - 079 */
492 0x4F762F2C, 0x4F762F2C, 0x4F6E2F2C, 0x4F6E2F2C, /* 080 - 083 */
493 0x4F6E2F2C, 0x576E2F2C, 0x576E2F2C, 0x576E3F2C, /* 084 - 087 */
494 0x576E3F2C, 0x576E3F2C, 0x5F6E3F2C, 0x5F6E4F2C, /* 088 - 091 */
495 0x5F6E4F2C, 0x5F6E4F2C, 0x5F664F2C, 0x67664F2C, /* 092 - 095 */
496 0x67664F2C, 0x675E4F2C, 0x675E4F2C, 0x67664F2C, /* 096 - 099 */
497 0x67664F2C, 0x67665F2C, 0x6F6E5F2C, 0x6F6E6F2C, /* 100 - 103 */
498 0x6F6E6F2C, 0x6F6E7F2C, 0x6F6E7F2C, 0x6F6E7F2C, /* 104 - 107 */
499 0x77667F2C, 0x77667F2C, 0x775E6F2C, 0x775E7F2C, /* 108 - 111 */
500 0x775E7F2C, 0x7F5E7F2C, 0x7F5E8F2C, 0x7F5E8F2C, /* 112 - 115 */
501 0x7F5E8F2C, 0x87568F2C, 0x87568F2C, 0x87568F2C, /* 116 - 119 */
502 0x874E8F2C, 0x874E8F2C, 0x874E8F2C, 0x8F4E9F2C, /* 120 - 123 */
503 0x8F4E9F2C, 0x8F4EAF2C, 0x8F4EAF2C, 0x8F4EAF2C, /* 124 - 127 */
504 0x974EAF2C, 0x974EAF2C, 0x974EAB2C, 0x974EAB2C, /* 128 - 131 */
505 0x974EAB2C, 0x9F4EAB2C, 0x9F4EBB2C, 0x9F4EBB2C, /* 132 - 135 */
506 0x9F4EBB2C, 0x9F4ECB2C, 0xA74ECB2C, 0xA74ECB2C, /* 136 - 139 */
507 0xA746CB2C, 0xA746CB2C, 0xA746CB2C, 0xA746DB2C, /* 140 - 143 */
508 0xAF46DB2C, 0xAF46EB2C, 0xAF46EB2C, 0xAF4EEB2C, /* 144 - 147 */
509 0xAE4EEB2C, 0xAE4EEB2C, 0xB546FB2C, 0xB554FB2C, /* 148 - 151 */
510 0xB54CEB2C, 0xB554FB2C, 0xB554FB2C, 0xBD54FB2C, /* 152 - 155 */
511 0xBD4CFB2C, 0xBD4CFB2C, 0xBD4CFB2C, 0xBD44EB2C, /* 156 - 159 */
512 0xC544FB2C, 0xC544FB2C, 0xC544FB2C, 0xC5450B2C, /* 160 - 163 */
513 0xC5450B2C, 0xC5450B2C, 0xCD450B2C, 0xCD450B2C, /* 164 - 167 */
514 0xCD3D0B2C, 0xCD3D0B2C, 0xCD3D0B2C, 0xD53D0B2C, /* 168 - 171 */
515 0xD53D0B2C, 0xD53D1B2C, 0xD53D1B2C, 0xD53D1B2C, /* 172 - 175 */
516 0xDD3D1B2C, 0xDD3D1B2C, 0xDD351B2C, 0xDD351B2C, /* 176 - 179 */
517 0xDD351B2C, 0xE5351B2C, 0xE5351B2C, 0xE52D1B2C, /* 180 - 183 */
518 0xE52D1B2C, 0xE52D3B2C, 0xED2D4B2C, 0xED2D1BA8, /* 184 - 187 */
519 0xED2D1BAC, 0xED2D17AC, 0xED2D17AC, 0xED2D27AC, /* 188 - 191 */
520 0xF52D27AC, 0xF52D27AC, 0xF52D2BAC, 0xF52D2BAC, /* 192 - 195 */
521 0xF52D2BAC, 0xFD2D2BAC, 0xFD2B2BAC, 0xFD2B2BAC, /* 196 - 199 */
522 0xFD2B2BAC, 0xFD2B2BAC, 0xFD232BAC, 0xFD232BAC, /* 200 - 203 */
523 0xFD232BAC, 0xFD212BAC, 0xFD212BAC, 0xFD292BAC, /* 204 - 207 */
524 0xFD292BAC, 0xFD2927AC, 0xFD2937AC, 0xFD2923AC, /* 208 - 211 */
525 0xFD2923AC, 0xFD2923AC, 0xFD2923AC, 0xFD2123AC, /* 212 - 215 */
526 0xFD2123AC, 0xFD2123AC, 0xFD2133AC, 0xFD2133AC, /* 216 - 219 */
527 0xFD2133AC, 0xFD2143AC, 0xFD2143AC, 0xFD2143AC, /* 220 - 223 */
528 0xFC2143AC, 0xFC2143AC, 0xFC1943AC, 0xFC1943AC, /* 224 - 227 */
529 0xFC1943AC, 0xFC1943AC, 0xFC1953AC, 0xFC1953AC, /* 228 - 231 */
530 0xFC1953AC, 0xFC1953AC, 0xFC1963AC, 0xFC1963AC, /* 232 - 235 */
531 0xFC1963AC, 0xFC1973AC, 0xFC1973AC, 0xFC1973AC, /* 236 - 239 */
532 0xFC1973AC, 0xFC1973AC, 0xFC1983AC, 0xFC1983AC, /* 240 - 243 */
533 0xFC1983AC, 0xFC1983AC, 0xFC1983AC, 0xFC1993AC, /* 244 - 247 */
534 0xFC1993AC, 0xFC1993AC, 0xFC19A3AC, 0xFC19A3AC, /* 248 - 251 */
535 0xFC19B3AC, 0xFC19B3AC, 0xFC19B3AC, 0xFC19B3AC /* 252 - 255 */
536};
537
538/*** End-of-Files ***/
diff --git a/drivers/staging/cxt1e1/comet_tables.h b/drivers/staging/cxt1e1/comet_tables.h
deleted file mode 100644
index 3e2e5badf787..000000000000
--- a/drivers/staging/cxt1e1/comet_tables.h
+++ /dev/null
@@ -1,61 +0,0 @@
1#ifndef _INC_COMET_TBLS_H_
2#define _INC_COMET_TBLS_H_
3
4/*-----------------------------------------------------------------------------
5 * comet_tables.h - Waveform Tables for the PM4351 'COMET'
6 *
7 * Copyright (C) 2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *-----------------------------------------------------------------------------
22 */
23
24
25/*****************************************************************************
26*
27* Array names:
28*
29* TWVLongHaul0DB
30* TWVLongHaul7_5DB
31* TWVLongHaul15DB
32* TWVLongHaul22_5DB
33* TWVShortHaul0
34* TWVShortHaul1
35* TWVShortHaul2
36* TWVShortHaul3
37* TWVShortHaul4
38* TWVShortHaul5
39* TWV_E1_120Ohm
40* TWV_E1_75Ohm <not supported>
41* T1_Equalizer
42* E1_Equalizer
43*
44*****************************************************************************/
45
46extern u_int8_t TWVLongHaul0DB[25][5]; /* T1 Long Haul 0 DB */
47extern u_int8_t TWVLongHaul7_5DB[25][5]; /* T1 Long Haul 7.5 DB */
48extern u_int8_t TWVLongHaul15DB[25][5]; /* T1 Long Haul 15 DB */
49extern u_int8_t TWVLongHaul22_5DB[25][5]; /* T1 Long Haul 22.5 DB */
50extern u_int8_t TWVShortHaul0[25][5]; /* T1 Short Haul 0-110 ft */
51extern u_int8_t TWVShortHaul1[25][5]; /* T1 Short Haul 110-220 ft */
52extern u_int8_t TWVShortHaul2[25][5]; /* T1 Short Haul 220-330 ft */
53extern u_int8_t TWVShortHaul3[25][5]; /* T1 Short Haul 330-440 ft */
54extern u_int8_t TWVShortHaul4[25][5]; /* T1 Short Haul 440-550 ft */
55extern u_int8_t TWVShortHaul5[25][5]; /* T1 Short Haul 550-660 ft */
56extern u_int8_t TWV_E1_75Ohm[25][5]; /* E1 75 Ohm */
57extern u_int8_t TWV_E1_120Ohm[25][5]; /* E1 120 Ohm */
58extern u_int32_t T1_Equalizer[256]; /* T1 Receiver Equalizer */
59extern u_int32_t E1_Equalizer[256]; /* E1 Receiver Equalizer */
60
61#endif /* _INC_COMET_TBLS_H_ */
diff --git a/drivers/staging/cxt1e1/functions.c b/drivers/staging/cxt1e1/functions.c
deleted file mode 100644
index 65b6fc36edf6..000000000000
--- a/drivers/staging/cxt1e1/functions.c
+++ /dev/null
@@ -1,318 +0,0 @@
1/* Copyright (C) 2003-2005 SBE, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/slab.h>
17#include <linux/io.h>
18#include <asm/byteorder.h>
19#include <linux/netdevice.h>
20#include <linux/delay.h>
21#include <linux/hdlc.h>
22#include "pmcc4_sysdep.h"
23#include "sbecom_inline_linux.h"
24#include "libsbew.h"
25#include "pmcc4.h"
26
27
28#ifndef USE_MAX_INT_DELAY
29static int dummy = 0;
30
31#endif
32
33extern int drvr_state;
34
35
36#if 1
37u_int32_t
38pci_read_32(u_int32_t *p)
39{
40#ifdef FLOW_DEBUG
41 u_int32_t v;
42
43 FLUSH_PCI_READ();
44 v = le32_to_cpu(*p);
45 if (cxt1e1_log_level >= LOG_DEBUG)
46 pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
47 return v;
48#else
49 FLUSH_PCI_READ(); /* */
50 return le32_to_cpu(*p);
51#endif
52}
53
54void
55pci_write_32(u_int32_t *p, u_int32_t v)
56{
57#ifdef FLOW_DEBUG
58 if (cxt1e1_log_level >= LOG_DEBUG)
59 pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
60#endif
61 *p = cpu_to_le32 (v);
62 FLUSH_PCI_WRITE(); /* This routine is called from routines
63 * which do multiple register writes
64 * which themselves need flushing between
65 * writes in order to guarantee write
66 * ordering. It is less code-cumbersome
67 * to flush here-in then to investigate
68 * and code the many other register
69 * writing routines. */
70}
71#endif
72
73
74void
75pci_flush_write(ci_t *ci)
76{
77 volatile u_int32_t v;
78
79 /* issue a PCI read to flush PCI write thru bridge */
80 v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */
81
82 /*
83 * return nothing, this just reads PCI bridge interface to flush
84 * previously written data
85 */
86}
87
88
89static void
90watchdog_func(unsigned long arg)
91{
92 struct watchdog *wd = (void *) arg;
93
94 if (drvr_state != SBE_DRVR_AVAILABLE) {
95 if (cxt1e1_log_level >= LOG_MONITOR)
96 pr_warning("%s: drvr not available (%x)\n",
97 __func__, drvr_state);
98 return;
99 }
100 schedule_work(&wd->work);
101 mod_timer(&wd->h, jiffies + wd->ticks);
102}
103
104int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *),
105 void *c, int usec)
106{
107 wdp->func = f;
108 wdp->softc = c;
109 wdp->ticks = (HZ) * (usec / 1000) / 1000;
110 INIT_WORK(&wdp->work, (void *)f);
111 init_timer(&wdp->h);
112 {
113 ci_t *ci = (ci_t *) c;
114
115 wdp->h.data = (unsigned long) &ci->wd;
116 }
117 wdp->h.function = watchdog_func;
118 return 0;
119}
120
121void
122OS_uwait(int usec, char *description)
123{
124 int tmp;
125
126 if (usec >= 1000) {
127 mdelay(usec / 1000);
128 /* now delay residual */
129 tmp = (usec / 1000) * 1000; /* round */
130 tmp = usec - tmp; /* residual */
131 if (tmp) { /* wait on residual */
132 udelay(tmp);
133 }
134 } else {
135 udelay(usec);
136 }
137}
138
139/* dummy short delay routine called as a subroutine so that compiler
140 * does not optimize/remove its intent (a short delay)
141 */
142
143void
144OS_uwait_dummy(void)
145{
146#ifndef USE_MAX_INT_DELAY
147 dummy++;
148#else
149 udelay(1);
150#endif
151}
152
153
154void
155OS_sem_init(void *sem, int state)
156{
157 switch (state) {
158 case SEM_TAKEN:
159 sema_init((struct semaphore *) sem, 0);
160 break;
161 case SEM_AVAILABLE:
162 sema_init((struct semaphore *) sem, 1);
163 break;
164 default: /* otherwise, set sem.count to state's
165 * value */
166 sema_init(sem, state);
167 break;
168 }
169}
170
171
172int
173sd_line_is_ok(void *user)
174{
175 struct net_device *ndev = (struct net_device *) user;
176
177 return netif_carrier_ok(ndev);
178}
179
180void
181sd_line_is_up(void *user)
182{
183 struct net_device *ndev = (struct net_device *) user;
184
185 netif_carrier_on(ndev);
186 return;
187}
188
189void
190sd_line_is_down(void *user)
191{
192 struct net_device *ndev = (struct net_device *) user;
193
194 netif_carrier_off(ndev);
195 return;
196}
197
198void
199sd_disable_xmit(void *user)
200{
201 struct net_device *dev = (struct net_device *) user;
202
203 netif_stop_queue(dev);
204 return;
205}
206
207void
208sd_enable_xmit(void *user)
209{
210 struct net_device *dev = (struct net_device *) user;
211
212 netif_wake_queue(dev);
213 return;
214}
215
216int
217sd_queue_stopped(void *user)
218{
219 struct net_device *ndev = (struct net_device *) user;
220
221 return netif_queue_stopped(ndev);
222}
223
224void sd_recv_consume(void *token, size_t len, void *user)
225{
226 struct net_device *ndev = user;
227 struct sk_buff *skb = token;
228
229 skb->dev = ndev;
230 skb_put(skb, len);
231 skb->protocol = hdlc_type_trans(skb, ndev);
232 netif_rx(skb);
233}
234
235
236/**
237 ** Read some reserved location w/in the COMET chip as a usable
238 ** VMETRO trigger point or other trace marking event.
239 **/
240
241#include "comet.h"
242
243extern ci_t *CI; /* dummy pointer to board ZERO's data */
244void
245VMETRO_TRIGGER(ci_t *ci, int x)
246{
247 struct s_comet_reg *comet;
248 volatile u_int32_t data;
249
250 comet = ci->port[0].cometbase; /* default to COMET # 0 */
251
252 switch (x) {
253 default:
254 case 0:
255 data = pci_read_32((u_int32_t *) &comet->__res24); /* 0x90 */
256 break;
257 case 1:
258 data = pci_read_32((u_int32_t *) &comet->__res25); /* 0x94 */
259 break;
260 case 2:
261 data = pci_read_32((u_int32_t *) &comet->__res26); /* 0x98 */
262 break;
263 case 3:
264 data = pci_read_32((u_int32_t *) &comet->__res27); /* 0x9C */
265 break;
266 case 4:
267 data = pci_read_32((u_int32_t *) &comet->__res88); /* 0x220 */
268 break;
269 case 5:
270 data = pci_read_32((u_int32_t *) &comet->__res89); /* 0x224 */
271 break;
272 case 6:
273 data = pci_read_32((u_int32_t *) &comet->__res8A); /* 0x228 */
274 break;
275 case 7:
276 data = pci_read_32((u_int32_t *) &comet->__res8B); /* 0x22C */
277 break;
278 case 8:
279 data = pci_read_32((u_int32_t *) &comet->__resA0); /* 0x280 */
280 break;
281 case 9:
282 data = pci_read_32((u_int32_t *) &comet->__resA1); /* 0x284 */
283 break;
284 case 10:
285 data = pci_read_32((u_int32_t *) &comet->__resA2); /* 0x288 */
286 break;
287 case 11:
288 data = pci_read_32((u_int32_t *) &comet->__resA3); /* 0x28C */
289 break;
290 case 12:
291 data = pci_read_32((u_int32_t *) &comet->__resA4); /* 0x290 */
292 break;
293 case 13:
294 data = pci_read_32((u_int32_t *) &comet->__resA5); /* 0x294 */
295 break;
296 case 14:
297 data = pci_read_32((u_int32_t *) &comet->__resA6); /* 0x298 */
298 break;
299 case 15:
300 data = pci_read_32((u_int32_t *) &comet->__resA7); /* 0x29C */
301 break;
302 case 16:
303 data = pci_read_32((u_int32_t *) &comet->__res74); /* 0x1D0 */
304 break;
305 case 17:
306 data = pci_read_32((u_int32_t *) &comet->__res75); /* 0x1D4 */
307 break;
308 case 18:
309 data = pci_read_32((u_int32_t *) &comet->__res76); /* 0x1D8 */
310 break;
311 case 19:
312 data = pci_read_32((u_int32_t *) &comet->__res77); /* 0x1DC */
313 break;
314 }
315}
316
317
318/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/hwprobe.c b/drivers/staging/cxt1e1/hwprobe.c
deleted file mode 100644
index 4fa27c8931b1..000000000000
--- a/drivers/staging/cxt1e1/hwprobe.c
+++ /dev/null
@@ -1,382 +0,0 @@
1/* Copyright (C) 2007 One Stop Systems
2 * Copyright (C) 2003-2005 SBE, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/netdevice.h>
18#include <linux/hdlc.h>
19#include <linux/if_arp.h>
20#include <asm/uaccess.h>
21#include <linux/rtnetlink.h>
22#include <linux/pci.h>
23#include "pmcc4_sysdep.h"
24#include "sbecom_inline_linux.h"
25#include "libsbew.h"
26#include "pmcc4_private.h"
27#include "pmcc4.h"
28#include "pmcc4_ioctls.h"
29#include "pmc93x6_eeprom.h"
30#ifdef CONFIG_PROC_FS
31#include "sbeproc.h"
32#endif
33
34extern int error_flag;
35extern int drvr_state;
36
37/* forward references */
38void c4_stopwd(ci_t *);
39struct net_device * __init c4_add_dev(hdw_info_t *, int, unsigned long,
40 unsigned long, int, int);
41
42
43struct s_hdw_info hdw_info[MAX_BOARDS];
44
45
46void __init
47show_two(hdw_info_t *hi, int brdno)
48{
49 ci_t *ci;
50 struct pci_dev *pdev;
51 char *bid;
52 char banner[80];
53 char sn[6] = {0,};
54
55 ci = (ci_t *)(netdev_priv(hi->ndev));
56 bid = sbeid_get_bdname(ci);
57 switch (hi->promfmt) {
58 case PROM_FORMAT_TYPE1:
59 memcpy(sn, hi->mfg_info.pft1.Serial, 6);
60 break;
61 case PROM_FORMAT_TYPE2:
62 memcpy(sn, hi->mfg_info.pft2.Serial, 6);
63 break;
64 }
65
66 sprintf(banner, "%s: %s S/N %06X, MUSYCC Rev %02X",
67 hi->devname, bid,
68 ((sn[3] << 16) & 0xff0000) |
69 ((sn[4] << 8) & 0x00ff00) |
70 (sn[5] & 0x0000ff),
71 (u_int8_t) hi->revid[0]);
72
73 pr_info("%s\n", banner);
74
75 pdev = hi->pdev[0];
76 pr_info("%s: %s at v/p=%lx/%lx (%02x:%02x.%x) irq %d\n",
77 hi->devname, "MUSYCC",
78 (unsigned long) hi->addr_mapped[0], hi->addr[0],
79 hi->pci_busno, (u_int8_t) PCI_SLOT(pdev->devfn),
80 (u_int8_t) PCI_FUNC(pdev->devfn), pdev->irq);
81
82 pdev = hi->pdev[1];
83 pr_info("%s: %s at v/p=%lx/%lx (%02x:%02x.%x) irq %d\n",
84 hi->devname, "EBUS ",
85 (unsigned long) hi->addr_mapped[1], hi->addr[1],
86 hi->pci_busno, (u_int8_t) PCI_SLOT(pdev->devfn),
87 (u_int8_t) PCI_FUNC(pdev->devfn), pdev->irq);
88}
89
90
91void __init
92hdw_sn_get(hdw_info_t *hi, int brdno)
93{
94 /* obtain hardware EEPROM information */
95 long addr;
96
97 addr = (long) hi->addr_mapped[1] + EEPROM_OFFSET;
98
99 /* read EEPROM with largest known format size... */
100 pmc_eeprom_read_buffer(addr, 0, (char *)hi->mfg_info.data,
101 sizeof(FLD_TYPE2));
102
103#if 0
104 {
105 unsigned char *ucp = (unsigned char *) &hi->mfg_info.data;
106
107 pr_info("eeprom[00]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
108 *(ucp + 0), *(ucp + 1), *(ucp + 2), *(ucp + 3),
109 *(ucp + 4), *(ucp + 5), *(ucp + 6), *(ucp + 7));
110 pr_info("eeprom[08]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
111 *(ucp + 8), *(ucp + 9), *(ucp + 10), *(ucp + 11),
112 *(ucp + 12), *(ucp + 13), *(ucp + 14), *(ucp + 15));
113 pr_info("eeprom[16]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
114 *(ucp + 16), *(ucp + 17), *(ucp + 18), *(ucp + 19),
115 *(ucp + 20), *(ucp + 21), *(ucp + 22), *(ucp + 23));
116 pr_info("eeprom[24]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
117 *(ucp + 24), *(ucp + 25), *(ucp + 26), *(ucp + 27),
118 *(ucp + 28), *(ucp + 29), *(ucp + 30), *(ucp + 31));
119 pr_info("eeprom[32]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
120 *(ucp + 32), *(ucp + 33), *(ucp + 34), *(ucp + 35),
121 *(ucp + 36), *(ucp + 37), *(ucp + 38), *(ucp + 39));
122 pr_info("eeprom[40]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
123 *(ucp + 40), *(ucp + 41), *(ucp + 42), *(ucp + 43),
124 *(ucp + 44), *(ucp + 45), *(ucp + 46), *(ucp + 47));
125 }
126#endif
127#if 0
128 pr_info("sn: %x %x %x %x %x %x\n",
129 hi->mfg_info.Serial[0],
130 hi->mfg_info.Serial[1],
131 hi->mfg_info.Serial[2],
132 hi->mfg_info.Serial[3],
133 hi->mfg_info.Serial[4],
134 hi->mfg_info.Serial[5]);
135#endif
136
137 hi->promfmt = pmc_verify_cksum(&hi->mfg_info.data);
138 if (hi->promfmt == PROM_FORMAT_Unk) {
139 /* bad crc, data is suspect */
140 if (cxt1e1_log_level >= LOG_WARN)
141 pr_info("%s: EEPROM cksum error\n", hi->devname);
142 hi->mfg_info_sts = EEPROM_CRCERR;
143 } else
144 hi->mfg_info_sts = EEPROM_OK;
145}
146
147
148 void __init
149prep_hdw_info(void)
150{
151 hdw_info_t *hi;
152 int i;
153
154 for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
155 hi->pci_busno = 0xff;
156 hi->pci_slot = 0xff;
157 hi->pci_pin[0] = 0;
158 hi->pci_pin[1] = 0;
159 hi->ndev = NULL;
160 hi->addr[0] = 0L;
161 hi->addr[1] = 0L;
162 hi->addr_mapped[0] = NULL;
163 hi->addr_mapped[1] = NULL;
164 }
165}
166
167void
168cleanup_ioremap(void)
169{
170 hdw_info_t *hi;
171 int i;
172
173 for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
174 if (hi->pci_slot == 0xff)
175 break;
176 if (hi->addr_mapped[0]) {
177 iounmap(hi->addr_mapped[0]);
178 release_mem_region((long) hi->addr[0], hi->len[0]);
179 hi->addr_mapped[0] = NULL;
180 }
181 if (hi->addr_mapped[1]) {
182 iounmap(hi->addr_mapped[1]);
183 release_mem_region((long) hi->addr[1], hi->len[1]);
184 hi->addr_mapped[1] = NULL;
185 }
186 }
187}
188
189
190void
191cleanup_devs(void)
192{
193 hdw_info_t *hi;
194 int i;
195
196 for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
197 if (hi->pci_slot == 0xff || !hi->ndev)
198 break;
199 c4_stopwd(netdev_priv(hi->ndev));
200#ifdef CONFIG_PROC_FS
201 sbecom_proc_brd_cleanup(netdev_priv(hi->ndev));
202#endif
203 unregister_netdev(hi->ndev);
204 free_irq(hi->pdev[0]->irq, hi->ndev);
205#ifdef CONFIG_SBE_PMCC4_NCOMM
206 free_irq(hi->pdev[1]->irq, hi->ndev);
207#endif
208 kfree(hi->ndev);
209 }
210}
211
212
213static int __init
214c4_hdw_init(struct pci_dev *pdev, int found)
215{
216 hdw_info_t *hi;
217 int i;
218 int fun, slot;
219 unsigned char busno = 0xff;
220
221 /* our MUSYCC chip supports two functions, 0 & 1 */
222 fun = PCI_FUNC(pdev->devfn);
223 if (fun > 1) {
224 pr_warning("unexpected devfun: 0x%x\n", pdev->devfn);
225 return 0;
226 }
227
228 /* obtain bus number */
229 if (pdev->bus)
230 busno = pdev->bus->number;
231 else
232 busno = 0; /* default for system PCI inconsistency */
233 slot = pdev->devfn & ~0x07;
234
235 /*
236 * Functions 0 & 1 for a given board (identified by same bus(busno) and
237 * slot(slot)) are placed into the same 'hardware' structure. The first
238 * part of the board's functionality will be placed into an unpopulated
239 * element, identified by "slot==(0xff)". The second part of a board's
240 * functionality will match the previously loaded slot/busno.
241 */
242 for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
243 /*
244 * match with board's first found interface, otherwise this is
245 * fisrt found
246 */
247 if ((hi->pci_slot == 0xff) || /* new board */
248 ((hi->pci_slot == slot) && (hi->bus == pdev->bus)))
249 break; /* found for-loop exit */
250 }
251
252 /* no match in above loop means MAX exceeded */
253 if (i == MAX_BOARDS) {
254 pr_warning("exceeded number of allowed devices (>%d)?\n",
255 MAX_BOARDS);
256 return 0;
257 }
258
259 if (pdev->bus)
260 hi->pci_busno = pdev->bus->number;
261 else
262 hi->pci_busno = 0; /* default for system PCI inconsistency */
263
264 hi->pci_slot = slot;
265 pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &hi->pci_pin[fun]);
266 pci_read_config_byte(pdev, PCI_REVISION_ID, &hi->revid[fun]);
267 hi->bus = pdev->bus;
268 hi->addr[fun] = pci_resource_start(pdev, 0);
269 hi->len[fun] = pci_resource_end(pdev, 0) - hi->addr[fun] + 1;
270 hi->pdev[fun] = pdev;
271
272 {
273 /*
274 * create device name from module name, plus add the appropriate
275 * board number
276 */
277 char *cp = hi->devname;
278
279 strcpy(cp, KBUILD_MODNAME);
280 cp += strlen(cp); /* reposition */
281 *cp++ = '-';
282 *cp++ = '0' + (found / 2); /* there are two found interfaces per
283 * board */
284 *cp = 0; /* termination */
285 }
286
287 return 1;
288}
289
290status_t __init
291c4hw_attach_all(void)
292{
293 hdw_info_t *hi;
294 struct pci_dev *pdev = NULL;
295 int found = 0, i, j;
296
297 error_flag = 0;
298 prep_hdw_info();
299 /*** scan PCI bus for all possible boards */
300 while ((pdev = pci_get_device(PCI_VENDOR_ID_CONEXANT,
301 PCI_DEVICE_ID_CN8474,
302 pdev))) {
303 if (c4_hdw_init(pdev, found))
304 found++;
305 }
306
307 if (!found) {
308 pr_warning("No boards found\n");
309 return -ENODEV;
310 }
311
312 /* sanity check for consistent hardware found */
313 for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
314 if (hi->pci_slot != 0xff && (!hi->addr[0] || !hi->addr[1])) {
315 pr_warning("%s: something very wrong with pci_get_device\n",
316 hi->devname);
317 return -EIO;
318 }
319 }
320 /* bring board's memory regions on/line */
321 for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
322 if (hi->pci_slot == 0xff)
323 break;
324 for (j = 0; j < 2; j++) {
325 if (!request_mem_region(hi->addr[j], hi->len[j], hi->devname)) {
326 pr_warning("%s: memory in use, addr=0x%lx, len=0x%lx ?\n",
327 hi->devname, hi->addr[j], hi->len[j]);
328 cleanup_ioremap();
329 return -ENOMEM;
330 }
331
332 hi->addr_mapped[j] = ioremap(hi->addr[j], hi->len[j]);
333 if (!hi->addr_mapped[j]) {
334 pr_warning("%s: ioremap fails, addr=0x%lx, len=0x%lx ?\n",
335 hi->devname, hi->addr[j], hi->len[j]);
336 cleanup_ioremap();
337 return -ENOMEM;
338 }
339#ifdef SBE_MAP_DEBUG
340 pr_warning("%s: io remapped from phys %x to virt %x\n",
341 hi->devname, (u_int32_t) hi->addr[j],
342 (u_int32_t) hi->addr_mapped[j]);
343#endif
344 }
345 }
346
347 drvr_state = SBE_DRVR_AVAILABLE;
348
349 /* Have now memory mapped all boards. Now allow board's access to system */
350 for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
351 if (hi->pci_slot == 0xff)
352 break;
353 if (pci_enable_device(hi->pdev[0]) ||
354 pci_enable_device(hi->pdev[1])) {
355 drvr_state = SBE_DRVR_DOWN;
356 pr_warning("%s: failed to enable card %d slot %d\n",
357 hi->devname, i, hi->pci_slot);
358 cleanup_devs();
359 cleanup_ioremap();
360 return -EIO;
361 }
362 pci_set_master(hi->pdev[0]);
363 pci_set_master(hi->pdev[1]);
364 hi->ndev = c4_add_dev(hi, i, (long) hi->addr_mapped[0],
365 (long) hi->addr_mapped[1],
366 hi->pdev[0]->irq,
367 hi->pdev[1]->irq);
368 if (!hi->ndev) {
369 drvr_state = SBE_DRVR_DOWN;
370 cleanup_ioremap();
371 /* NOTE: c4_add_dev() does its own device cleanup */
372#if 0
373 cleanup_devs();
374#endif
375 return error_flag; /* error_flag set w/in add_dev() */
376 }
377 show_two(hi, i); /* displays found information */
378 }
379 return 0;
380}
381
382/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/libsbew.h b/drivers/staging/cxt1e1/libsbew.h
deleted file mode 100644
index bd2bfba604b3..000000000000
--- a/drivers/staging/cxt1e1/libsbew.h
+++ /dev/null
@@ -1,549 +0,0 @@
1#ifndef _INC_LIBSBEW_H_
2#define _INC_LIBSBEW_H_
3
4/*-----------------------------------------------------------------------------
5 * libsbew.h - common library elements, charge across mulitple boards
6 *
7 * This file contains common Ioctl structures and contents definitions.
8 *
9 * Copyright (C) 2004-2005 SBE, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * For further information, contact via email: support@sbei.com
22 * SBE, Inc. San Ramon, California U.S.A.
23 *-----------------------------------------------------------------------------
24 */
25
26/********************************/
27/** set driver logging level **/
28/********************************/
29
30/* routine/ioctl: wancfg_set_loglevel() - SBE_IOC_SET_LOGLEVEL */
31
32#define LOG_NONE 0
33#define LOG_ERROR 1
34#define LOG_SBEBUG3 3 /* hidden, for development/debug usage */
35#define LOG_LSCHANGE 5 /* line state change logging */
36#define LOG_LSIMMEDIATE 6 /* line state change logging w/o hysterisis */
37#define LOG_WARN 8
38#define LOG_MONITOR 10
39#define LOG_SBEBUG12 12 /* hidden, for development/debug usage */
40#define LOG_MONITOR2 14 /* hidden, for development/debug usage */
41#define LOG_DEBUG 16
42
43 /* TEMPORARY DEFINES *//* RLD DEBUG */
44#define c4_LOG_NONE LOG_NONE
45#define c4_LOG_ERROR LOG_ERROR
46#define c4_LOG_WARN LOG_WARN
47#define c4_LOG_sTrace LOG_MONITOR /* do some trace logging into
48 * functions */
49#define c4_LOG_DEBUG LOG_DEBUG
50#define c4_LOG_MAX LOG_DEBUG
51
52
53
54/******************************/
55/** get driver information **/
56/******************************/
57
58/* routine/ioctl: wancfg_get_drvinfo() - SBE_IOC_GET_DRVINFO */
59
60#define REL_STRLEN 80
61 struct sbe_drv_info
62 {
63 int rel_strlen;
64 char release[REL_STRLEN];
65 };
66
67
68/*****************************/
69/** get board information **/
70/*****************************/
71
72/* routine/ioctl: wancfg_get_brdinfo() - SBE_IOC_GET_BRDINFO */
73
74#define CHNM_STRLEN 16
75 struct sbe_brd_info
76 {
77 u_int32_t brd_id; /* SBE's unique PCI VENDOR/DEVID */
78 u_int32_t brd_sn;
79 int brd_chan_cnt; /* number of channels being used */
80 int brd_port_cnt; /* number of ports being used */
81 unsigned char brdno; /* our board number */
82 unsigned char brd_pci_speed; /* PCI speed, 33/66Mhz */
83 u_int8_t brd_mac_addr[6];
84 char first_iname[CHNM_STRLEN]; /* first assigned channel's
85 * interface name */
86 char last_iname[CHNM_STRLEN]; /* last assigned channel's
87 * interface name */
88 u_int8_t brd_hdw_id; /* on/board unique hdw ID */
89 u_int8_t reserved8[3]; /* alignment preservation */
90 u_int32_t reserved32[3]; /* size preservation */
91 };
92
93/* These IDs are sometimes available thru pci_ids.h, but not currently. */
94
95#define PCI_VENDOR_ID_SBE 0x1176
96#define PCI_DEVICE_ID_WANPMC_C4T1E1 0x0701 /* BID 0x0X, BTYP 0x0X */
97#define PCI_DEVICE_ID_WANPTMC_C4T1E1 0x0702 /* BID 0x41 */
98#define PCI_DEVICE_ID_WANADAPT_HC4T1E1 0x0703 /* BID 0x44 */
99#define PCI_DEVICE_ID_WANPTMC_256T3_T1 0x0704 /* BID 0x42 (T1 Version) */
100#define PCI_DEVICE_ID_WANPCI_C4T1E1 0x0705 /* BID 0x1X, BTYP 0x0X */
101#define PCI_DEVICE_ID_WANPMC_C1T3 0x0706 /* BID 0x45 */
102#define PCI_DEVICE_ID_WANPCI_C2T1E1 0x0707 /* BID 0x1X, BTYP 0x2X */
103#define PCI_DEVICE_ID_WANPCI_C1T1E1 0x0708 /* BID 0x1X, BTYP 0x1X */
104#define PCI_DEVICE_ID_WANPMC_C2T1E1 0x0709 /* BID 0x0X, BTYP 0x2X */
105#define PCI_DEVICE_ID_WANPMC_C1T1E1 0x070A /* BID 0x0X, BTYP 0x1X */
106#define PCI_DEVICE_ID_WANPTMC_256T3_E1 0x070B /* BID 0x46 (E1 Version) */
107#define PCI_DEVICE_ID_WANPTMC_C24TE1 0x070C /* BID 0x47 */
108#define PCI_DEVICE_ID_WANPMC_C4T1E1_L 0x070D /* BID 0x2X, BTYPE 0x0X w/FP
109 * LEDs */
110#define PCI_DEVICE_ID_WANPMC_C2T1E1_L 0x070E /* BID 0x2X, BTYPE 0x2X w/FP
111 * LEDs */
112#define PCI_DEVICE_ID_WANPMC_C1T1E1_L 0x070F /* BID 0x2X, BTYPE 0x1X w/FP
113 * LEDs */
114#define PCI_DEVICE_ID_WANPMC_2SSI 0x0801
115#define PCI_DEVICE_ID_WANPCI_4SSI 0x0802
116#define PCI_DEVICE_ID_WANPMC_2T3E3 0x0900 /* BID 0x43 */
117#define SBE_BOARD_ID(v,id) ((v<<16) | id)
118
119#define BINFO_PCI_SPEED_unk 0
120#define BINFO_PCI_SPEED_33 1
121#define BINFO_PCI_SPEED_66 2
122
123/***************************/
124/** obtain interface ID **/
125/***************************/
126
127/* routine/ioctl: wancfg_get_iid() - SBE_IOC_IID_GET */
128
129 struct sbe_iid_info
130 {
131 u_int32_t channum; /* channel requested */
132 char iname[CHNM_STRLEN]; /* channel's interface name */
133 };
134
135/**************************************/
136/** get board address information **/
137/**************************************/
138
139/* routine/ioctl: wancfg_get_brdaddr() - SBE_IOC_BRDADDR_GET */
140
141 struct sbe_brd_addr
142 {
143 unsigned char func; /* select PCI address space function */
144 unsigned char brdno; /* returns brdno requested */
145 unsigned char irq;
146 unsigned char size; /* returns size of address */
147#define BRDADDR_SIZE_64 1
148#define BRDADDR_SIZE_32 2
149 int reserved1; /* mod64 align, reserved for future use */
150
151 union
152 {
153 unsigned long virt64; /* virtual/mapped address */
154 u_int32_t virt32[2];
155 } v;
156 union
157 {
158 unsigned long phys64; /* physical bus address */
159 u_int32_t phys32[2];
160 } p;
161 int reserved2[4]; /* reserved for future use */
162 };
163
164/**********************************/
165/** read/write board registers **/
166/**********************************/
167
168/* routine/ioctl: wancfg_read_vec() - SBE_IOC_READ_VEC */
169/* routine/ioctl: wancfg_write_vec() - SBE_IOC_WRITE_VEC */
170
171 struct sbecom_wrt_vec
172 {
173 u_int32_t reg;
174 u_int32_t data;
175 };
176
177#define C1T3_CHIP_MSCC_32 0x01000000
178#define C1T3_CHIP_TECT3_8 0x02000000
179#define C1T3_CHIP_CPLD_8 0x03000000
180#define C1T3_CHIP_EEPROM_8 0x04000000
181
182#define W256T3_CHIP_MUSYCC_32 0x02000000
183#define W256T3_CHIP_TEMUX_8 0x10000000
184#define W256T3_CHIP_T8110_8 0x20000000
185#define W256T3_CHIP_T8110_32 0x22000000
186#define W256T3_CHIP_CPLD_8 0x30000000
187#define W256T3_CHIP_EEPROM_8 0x40000000
188
189
190/**********************************/
191/** read write port parameters **/
192/**********************************/
193
194/* routine/ioctl: wancfg_getset_port_param() - SBE_IOC_PORT_GET */
195/* routine/ioctl: wancfg_set_port_param() - SBE_IOC_PORT_SET */
196
197/* NOTE: this structure supports hardware which supports individual per/port control */
198
199struct sbecom_port_param
200{
201 u_int8_t portnum;
202 u_int8_t port_mode; /* variations of T1 or E1 mode */
203 u_int8_t portStatus;
204 u_int8_t portP; /* more port parameters (clock source - 0x80;
205 * and LBO - 0xf; */
206 /* bits 0x70 are reserved for future use ) */
207#ifdef SBE_PMCC4_ENABLE
208 u_int32_t hypersize; /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
209#endif
210 int reserved[3-1]; /* reserved for future use */
211 int _res[4];
212};
213
214#define CFG_CLK_PORT_MASK 0x80 /* Loop timing */
215#define CFG_CLK_PORT_INTERNAL 0x80 /* Loop timing */
216#define CFG_CLK_PORT_EXTERNAL 0x00 /* Loop timing */
217
218#define CFG_LBO_MASK 0x0F
219#define CFG_LBO_unk 0 /* <not defined> */
220#define CFG_LBO_LH0 1 /* T1 Long Haul (default) */
221#define CFG_LBO_LH7_5 2 /* T1 Long Haul */
222#define CFG_LBO_LH15 3 /* T1 Long Haul */
223#define CFG_LBO_LH22_5 4 /* T1 Long Haul */
224#define CFG_LBO_SH110 5 /* T1 Short Haul */
225#define CFG_LBO_SH220 6 /* T1 Short Haul */
226#define CFG_LBO_SH330 7 /* T1 Short Haul */
227#define CFG_LBO_SH440 8 /* T1 Short Haul */
228#define CFG_LBO_SH550 9 /* T1 Short Haul */
229#define CFG_LBO_SH660 10 /* T1 Short Haul */
230#define CFG_LBO_E75 11 /* E1 75 Ohm */
231#define CFG_LBO_E120 12 /* E1 120 Ohm (default) */
232
233
234/*************************************/
235/** read write channel parameters **/
236/*************************************/
237
238/* routine/ioctl: wancfg_getset_chan_param() - SBE_IOC_CHAN_GET */
239/* routine/ioctl: wancfg_set_chan_param() - SBE_IOC_CHAN_SET */
240
241/* NOTE: this structure supports hardware which supports individual per/channel control */
242
243 struct sbecom_chan_param
244 {
245 u_int32_t channum; /* 0: */
246#ifdef SBE_PMCC4_ENABLE
247 u_int32_t card; /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
248 u_int32_t port; /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
249 u_int8_t bitmask[32];
250#endif
251 u_int32_t intr_mask; /* 4: interrupt mask, specify ored
252 * (SS7_)INTR_* to disable */
253 u_int8_t status; /* 8: channel transceiver status (TX_ENABLED,
254 * RX_ENABLED) */
255 u_int8_t chan_mode; /* 9: protocol mode */
256 u_int8_t idlecode; /* A: idle code, in (FLAG_7E, FLAG_FF,
257 * FLAG_00) */
258 u_int8_t pad_fill_count; /* B: pad fill count (1-127), 0 - pad
259 * fill disabled */
260 u_int8_t data_inv; /* C: channel data inversion selection */
261 u_int8_t mode_56k; /* D: 56kbps mode */
262 u_int8_t reserved[2 + 8]; /* E: */
263 };
264
265/* SS7 interrupt signals <intr_mask> */
266#define SS7_INTR_SFILT 0x00000020
267#define SS7_INTR_SDEC 0x00000040
268#define SS7_INTR_SINC 0x00000080
269#define SS7_INTR_SUERR 0x00000100
270/* Other interrupts that can be masked */
271#define INTR_BUFF 0x00000002
272#define INTR_EOM 0x00000004
273#define INTR_MSG 0x00000008
274#define INTR_IDLE 0x00000010
275
276/* transceiver status flags <status> */
277#define TX_ENABLED 0x01
278#define RX_ENABLED 0x02
279
280/* Protocol modes <mode> */
281#define CFG_CH_PROTO_TRANS 0
282#define CFG_CH_PROTO_SS7 1
283#define CFG_CH_PROTO_HDLC_FCS16 2
284#define CFG_CH_PROTO_HDLC_FCS32 3
285#define CFG_CH_PROTO_ISLP_MODE 4
286
287/* Possible idle code assignments <idlecode> */
288#define CFG_CH_FLAG_7E 0
289#define CFG_CH_FLAG_FF 1
290#define CFG_CH_FLAG_00 2
291
292/* data inversion selection <data_inv> */
293#define CFG_CH_DINV_NONE 0x00
294#define CFG_CH_DINV_RX 0x01
295#define CFG_CH_DINV_TX 0x02
296
297
298/* Possible resettable chipsets/functions */
299#define RESET_DEV_TEMUX 1
300#define RESET_DEV_TECT3 RESET_DEV_TEMUX
301#define RESET_DEV_PLL 2
302
303
304/*********************************************/
305/** read reset channel thruput statistics **/
306/*********************************************/
307
308/* routine/ioctl: wancfg_get_chan_stats() - SBE_IOC_CHAN_GET_STAT */
309/* routine/ioctl: wancfg_del_chan_stats() - SBE_IOC_CHAN_DEL_STAT */
310/* routine/ioctl: wancfg_get_card_chan_stats() - SBE_IOC_CARD_CHAN_STAT */
311
312 struct sbecom_chan_stats
313 {
314 unsigned long rx_packets; /* total packets received */
315 unsigned long tx_packets; /* total packets transmitted */
316 unsigned long rx_bytes; /* total bytes received */
317 unsigned long tx_bytes; /* total bytes transmitted */
318 unsigned long rx_errors;/* bad packets received */
319 unsigned long tx_errors;/* packet transmit problems */
320 unsigned long rx_dropped; /* no space in linux buffers */
321 unsigned long tx_dropped; /* no space available in linux */
322
323 /* detailed rx_errors: */
324 unsigned long rx_length_errors;
325 unsigned long rx_over_errors; /* receiver ring buff overflow */
326 unsigned long rx_crc_errors; /* recved pkt with crc error */
327 unsigned long rx_frame_errors; /* recv'd frame alignment error */
328 unsigned long rx_fifo_errors; /* recv'r fifo overrun */
329 unsigned long rx_missed_errors; /* receiver missed packet */
330
331 /* detailed tx_errors */
332 unsigned long tx_aborted_errors;
333 unsigned long tx_fifo_errors;
334 unsigned long tx_pending;
335 };
336
337
338/****************************************/
339/** read write card level parameters **/
340/****************************************/
341
342 /* NOTE: this structure supports hardware which supports per/card control */
343
344 struct sbecom_card_param
345 {
346 u_int8_t framing_type; /* 0: CBP or M13 */
347 u_int8_t loopback; /* 1: one of LOOPBACK_* */
348 u_int8_t line_build_out; /* 2: boolean */
349 u_int8_t receive_eq; /* 3: boolean */
350 u_int8_t transmit_ones; /* 4: boolean */
351 u_int8_t clock; /* 5: 0 - internal, i>0 - external (recovered
352 * from framer i) */
353 u_int8_t h110enable; /* 6: */
354 u_int8_t disable_leds; /* 7: */
355 u_int8_t reserved1; /* 8: available - old 256t3 hypersized, but
356 * never used */
357 u_int8_t rear_io; /* 9: rear I/O off/on */
358 u_int8_t disable_tx; /* A: disable TX off/on */
359 u_int8_t mute_los; /* B: mute LOS off/on */
360 u_int8_t los_threshold; /* C: LOS threshold norm/low
361 * (default: norm) */
362 u_int8_t ds1_mode; /* D: DS1 mode T1/E1 (default: T1) */
363 u_int8_t ds3_unchan; /* E: DS3 unchannelized mode off/on */
364 u_int8_t reserved[1 + 16]; /* reserved for expansion - must be
365 * ZERO filled */
366 };
367
368/* framing types <framing_type> */
369#define FRAMING_M13 0
370#define FRAMING_CBP 1
371
372/* card level loopback options <loopback> */
373#define CFG_CARD_LOOPBACK_NONE 0x00
374#define CFG_CARD_LOOPBACK_DIAG 0x01
375#define CFG_CARD_LOOPBACK_LINE 0x02
376#define CFG_CARD_LOOPBACK_PAYLOAD 0x03
377
378/* line level loopback options <loopback> */
379#define CFG_LIU_LOOPBACK_NONE 0x00
380#define CFG_LIU_LOOPBACK_ANALOG 0x10
381#define CFG_LIU_LOOPBACK_DIGITAL 0x11
382#define CFG_LIU_LOOPBACK_REMOTE 0x12
383
384/* card level clock options <clock> */
385#define CFG_CLK_INTERNAL 0x00
386#define CFG_CLK_EXTERNAL 0x01
387
388/* legacy 256T3 loopback values */
389#define LOOPBACK_NONE 0
390#define LOOPBACK_LIU_ANALOG 1
391#define LOOPBACK_LIU_DIGITAL 2
392#define LOOPBACK_FRAMER_DS3 3
393#define LOOPBACK_FRAMER_T1 4
394#define LOOPBACK_LIU_REMOTE 5
395
396/* DS1 mode <ds1_mode> */
397#define CFG_DS1_MODE_MASK 0x0f
398#define CFG_DS1_MODE_T1 0x00
399#define CFG_DS1_MODE_E1 0x01
400#define CFG_DS1_MODE_CHANGE 0x80
401
402/* DS3 unchannelized values <ds1_unchan> */
403#define CFG_DS3_UNCHAN_MASK 0x01
404#define CFG_DS3_UNCHAN_OFF 0x00
405#define CFG_DS3_UNCHAN_ON 0x01
406
407
408/************************************/
409/** read write framer parameters **/
410/************************************/
411
412/* routine/ioctl: wancfg_get_framer() - SBE_IOC_FRAMER_GET */
413/* routine/ioctl: wancfg_set_framer() - SBE_IOC_FRAMER_SET */
414
415 struct sbecom_framer_param
416 {
417 u_int8_t framer_num;
418 u_int8_t frame_type; /* SF, ESF, E1PLAIN, E1CAS, E1CRC, E1CRC+CAS */
419 u_int8_t loopback_type; /* DIGITAL, LINE, PAYLOAD */
420 u_int8_t auto_alarms;/* auto alarms */
421 u_int8_t reserved[12]; /* reserved for expansion - must be
422 * ZERO filled */
423 };
424
425/* frame types <frame_type> */
426#define CFG_FRAME_NONE 0
427#define CFG_FRAME_SF 1 /* T1 B8ZS */
428#define CFG_FRAME_ESF 2 /* T1 B8ZS */
429#define CFG_FRAME_E1PLAIN 3 /* HDB3 w/o CAS,CRC */
430#define CFG_FRAME_E1CAS 4 /* HDB3 */
431#define CFG_FRAME_E1CRC 5 /* HDB3 */
432#define CFG_FRAME_E1CRC_CAS 6 /* HDB3 */
433#define CFG_FRAME_SF_AMI 7 /* T1 AMI */
434#define CFG_FRAME_ESF_AMI 8 /* T1 AMI */
435#define CFG_FRAME_E1PLAIN_AMI 9 /* E1 AMI w/o CAS,CRC */
436#define CFG_FRAME_E1CAS_AMI 10 /* E1 AMI */
437#define CFG_FRAME_E1CRC_AMI 11 /* E1 AMI */
438#define CFG_FRAME_E1CRC_CAS_AMI 12 /* E1 AMI */
439
440#define IS_FRAME_ANY_T1(field) \
441 (((field) == CFG_FRAME_NONE) || \
442 ((field) == CFG_FRAME_SF) || \
443 ((field) == CFG_FRAME_ESF) || \
444 ((field) == CFG_FRAME_SF_AMI) || \
445 ((field) == CFG_FRAME_ESF_AMI))
446
447#define IS_FRAME_ANY_T1ESF(field) \
448 (((field) == CFG_FRAME_ESF) || \
449 ((field) == CFG_FRAME_ESF_AMI))
450
451#define IS_FRAME_ANY_E1(field) \
452 (((field) == CFG_FRAME_E1PLAIN) || \
453 ((field) == CFG_FRAME_E1CAS) || \
454 ((field) == CFG_FRAME_E1CRC) || \
455 ((field) == CFG_FRAME_E1CRC_CAS) || \
456 ((field) == CFG_FRAME_E1PLAIN_AMI) || \
457 ((field) == CFG_FRAME_E1CAS_AMI) || \
458 ((field) == CFG_FRAME_E1CRC_AMI) || \
459 ((field) == CFG_FRAME_E1CRC_CAS_AMI))
460
461#define IS_FRAME_ANY_AMI(field) \
462 (((field) == CFG_FRAME_SF_AMI) || \
463 ((field) == CFG_FRAME_ESF_AMI) || \
464 ((field) == CFG_FRAME_E1PLAIN_AMI) || \
465 ((field) == CFG_FRAME_E1CAS_AMI) || \
466 ((field) == CFG_FRAME_E1CRC_AMI) || \
467 ((field) == CFG_FRAME_E1CRC_CAS_AMI))
468
469/* frame level loopback options <loopback_type> */
470#define CFG_FRMR_LOOPBACK_NONE 0
471#define CFG_FRMR_LOOPBACK_DIAG 1
472#define CFG_FRMR_LOOPBACK_LINE 2
473#define CFG_FRMR_LOOPBACK_PAYLOAD 3
474
475
476/****************************************/
477/** read reset card error statistics **/
478/****************************************/
479
480/* routine/ioctl: wancfg_get_card_stats() - SBE_IOC_CARD_GET_STAT */
481/* routine/ioctl: wancfg_del_card_stats() - SBE_IOC_CARD_DEL_STAT */
482
483 struct temux_card_stats
484 {
485 struct temux_stats
486 {
487 /* TEMUX DS3 PMON counters */
488 u_int32_t lcv;
489 u_int32_t err_framing;
490 u_int32_t febe;
491 u_int32_t err_cpbit;
492 u_int32_t err_parity;
493 /* TEMUX DS3 FRMR status */
494 u_int8_t los;
495 u_int8_t oof;
496 u_int8_t red;
497 u_int8_t yellow;
498 u_int8_t idle;
499 u_int8_t ais;
500 u_int8_t cbit;
501 /* TEMUX DS3 FEAC receiver */
502 u_int8_t feac;
503 u_int8_t feac_last;
504 } t;
505 u_int32_t tx_pending; /* total */
506 };
507
508/**************************************************************/
509
510 struct wancfg
511 {
512 int cs, ds;
513 char *p;
514 };
515 typedef struct wancfg wcfg_t;
516
517 extern wcfg_t *wancfg_init(char *, char *);
518 extern int wancfg_card_blink(wcfg_t *, int);
519 extern int wancfg_ctl(wcfg_t *, int, void *, int, void *, int);
520 extern int wancfg_del_card_stats(wcfg_t *);
521 extern int wancfg_del_chan_stats(wcfg_t *, int);
522 extern int wancfg_enable_ports(wcfg_t *, int);
523 extern int wancfg_free(wcfg_t *);
524 extern int wancfg_get_brdaddr(wcfg_t *, struct sbe_brd_addr *);
525 extern int wancfg_get_brdinfo(wcfg_t *, struct sbe_brd_info *);
526 extern int wancfg_get_card(wcfg_t *, struct sbecom_card_param *);
527 extern int wancfg_get_card_chan_stats(wcfg_t *, struct sbecom_chan_stats *);
528 extern int wancfg_get_card_sn(wcfg_t *);
529 extern int wancfg_get_card_stats(wcfg_t *, struct temux_card_stats *);
530 extern int wancfg_get_chan(wcfg_t *, int, struct sbecom_chan_param *);
531 extern int wancfg_get_chan_stats(wcfg_t *, int, struct sbecom_chan_stats *);
532 extern int wancfg_get_drvinfo(wcfg_t *, int, struct sbe_drv_info *);
533 extern int wancfg_get_framer(wcfg_t *, int, struct sbecom_framer_param *);
534 extern int wancfg_get_iid(wcfg_t *, int, struct sbe_iid_info *);
535 extern int wancfg_get_sn(wcfg_t *, unsigned int *);
536 extern int wancfg_read(wcfg_t *, int, struct sbecom_wrt_vec *);
537 extern int wancfg_reset_device(wcfg_t *, int);
538 extern int wancfg_set_card(wcfg_t *, struct sbecom_card_param *);
539 extern int wancfg_set_chan(wcfg_t *, int, struct sbecom_chan_param *);
540 extern int wancfg_set_framer(wcfg_t *, int, struct sbecom_framer_param *);
541 extern int wancfg_set_loglevel(wcfg_t *, uint);
542 extern int wancfg_write(wcfg_t *, int, struct sbecom_wrt_vec *);
543
544#ifdef NOT_YET_COMMON
545 extern int wancfg_get_tsioc(wcfg_t *, struct wanc1t3_ts_hdr *, struct wanc1t3_ts_param *);
546 extern int wancfg_set_tsioc(wcfg_t *, struct wanc1t3_ts_param *);
547#endif
548
549#endif /*** _INC_LIBSBEW_H_ ***/
diff --git a/drivers/staging/cxt1e1/linux.c b/drivers/staging/cxt1e1/linux.c
deleted file mode 100644
index 09f3d5ca75ac..000000000000
--- a/drivers/staging/cxt1e1/linux.c
+++ /dev/null
@@ -1,1142 +0,0 @@
1/* Copyright (C) 2007-2008 One Stop Systems
2 * Copyright (C) 2003-2006 SBE, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/types.h>
18#include <linux/netdevice.h>
19#include <linux/module.h>
20#include <linux/hdlc.h>
21#include <linux/if_arp.h>
22#include <linux/init.h>
23#include <asm/uaccess.h>
24#include <linux/rtnetlink.h>
25#include <linux/skbuff.h>
26#include "pmcc4_sysdep.h"
27#include "sbecom_inline_linux.h"
28#include "libsbew.h"
29#include "pmcc4.h"
30#include "pmcc4_ioctls.h"
31#include "pmcc4_private.h"
32#include "sbeproc.h"
33
34/*******************************************************************************
35 * Error out early if we have compiler trouble.
36 *
37 * (This section is included from the kernel's init/main.c as a friendly
38 * spiderman recommendation...)
39 *
40 * Versions of gcc older than that listed below may actually compile and link
41 * okay, but the end product can have subtle run time bugs. To avoid associated
42 * bogus bug reports, we flatly refuse to compile with a gcc that is known to be
43 * too old from the very beginning.
44 */
45#if (__GNUC__ < 3) || (__GNUC__ == 3 && __GNUC_MINOR__ < 2)
46#error Sorry, your GCC is too old. It builds incorrect kernels.
47#endif
48
49#if __GNUC__ == 4 && __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ == 0
50#warning gcc-4.1.0 is known to miscompile the kernel. A different compiler version is recommended.
51#endif
52
53/*******************************************************************************/
54
55#define CHANNAME "hdlc"
56
57/*******************************************************************/
58/* forward references */
59status_t c4_chan_work_init(mpi_t *, mch_t *);
60void musycc_wq_chan_restart(void *);
61status_t __init c4_init(ci_t *, u_char *, u_char *);
62status_t __init c4_init2(ci_t *);
63int __init c4hw_attach_all(void);
64void __init hdw_sn_get(hdw_info_t *, int);
65
66#ifdef CONFIG_SBE_PMCC4_NCOMM
67irqreturn_t c4_ebus_intr_th_handler(void *);
68
69#endif
70int c4_frame_rw(ci_t *, struct sbecom_port_param *);
71status_t c4_get_port(ci_t *, int);
72int c4_loop_port(ci_t *, int, u_int8_t);
73int c4_musycc_rw(ci_t *, struct c4_musycc_param *);
74int c4_new_chan(ci_t *, int, int, void *);
75status_t c4_set_port(ci_t *, int);
76int c4_pld_rw(ci_t *, struct sbecom_port_param *);
77void cleanup_devs(void);
78void cleanup_ioremap(void);
79status_t musycc_chan_down(ci_t *, int);
80irqreturn_t musycc_intr_th_handler(void *);
81int musycc_start_xmit(ci_t *, int, void *);
82
83extern ci_t *CI;
84extern struct s_hdw_info hdw_info[];
85
86int error_flag; /* module load error reporting */
87int cxt1e1_log_level = LOG_ERROR;
88static int log_level_default = LOG_ERROR;
89module_param(cxt1e1_log_level, int, 0444);
90
91int cxt1e1_max_mru = MUSYCC_MRU;
92static int max_mru_default = MUSYCC_MRU;
93module_param(cxt1e1_max_mru, int, 0444);
94
95int cxt1e1_max_mtu = MUSYCC_MTU;
96int max_mtu_default = MUSYCC_MTU;
97module_param(cxt1e1_max_mtu, int, 0444);
98
99int max_txdesc_used = MUSYCC_TXDESC_MIN;
100int max_txdesc_default = MUSYCC_TXDESC_MIN;
101module_param(max_txdesc_used, int, 0444);
102
103int max_rxdesc_used = MUSYCC_RXDESC_MIN;
104int max_rxdesc_default = MUSYCC_RXDESC_MIN;
105module_param(max_rxdesc_used, int, 0444);
106
107/****************************************************************************/
108/****************************************************************************/
109/****************************************************************************/
110
111void *
112getuserbychan(int channum)
113{
114 mch_t *ch;
115
116 ch = c4_find_chan(channum);
117 return ch ? ch->user : NULL;
118}
119
120
121char *
122get_hdlc_name(hdlc_device *hdlc)
123{
124 struct c4_priv *priv = hdlc->priv;
125 struct net_device *dev = getuserbychan(priv->channum);
126
127 return dev->name;
128}
129
130/***************************************************************************/
131#include <linux/workqueue.h>
132
133/***
134 * One workqueue (wq) per port (since musycc allows simultaneous group
135 * commands), with individual data for each channel:
136 *
137 * mpi_t -> struct workqueue_struct *wq_port; (dynamically allocated using
138 * create_workqueue())
139 *
140 * With work structure (work) statically allocated for each channel:
141 *
142 * mch_t -> struct work_struct ch_work; (statically allocated using ???)
143 *
144 ***/
145
146
147/*
148 * Called by the start transmit routine when a channel TX_ENABLE is to be
149 * issued. This queues the transmission start request among other channels
150 * within a port's group.
151 */
152void
153c4_wk_chan_restart(mch_t *ch)
154{
155 mpi_t *pi = ch->up;
156
157#ifdef RLD_RESTART_DEBUG
158 pr_info(">> %s: queueing Port %d Chan %d, mch_t @ %p\n",
159 __func__, pi->portnum, ch->channum, ch);
160#endif
161
162 /* create new entry w/in workqueue for this channel and let'er rip */
163
164 /** queue_work(struct workqueue_struct *queue,
165 ** struct work_struct *work);
166 **/
167 queue_work(pi->wq_port, &ch->ch_work);
168}
169
170status_t
171c4_wk_chan_init(mpi_t *pi, mch_t *ch)
172{
173 /*
174 * this will be used to restart a stopped channel
175 */
176
177 /** INIT_WORK(struct work_struct *work,
178 ** void (*function)(void *),
179 ** void *data);
180 **/
181 INIT_WORK(&ch->ch_work, (void *)musycc_wq_chan_restart);
182 return 0; /* success */
183}
184
185status_t
186c4_wq_port_init(mpi_t *pi)
187{
188
189 char name[16]; /* NOTE: name of the queue limited by system
190 * to 10 characters */
191 if (pi->wq_port)
192 return 0; /* already initialized */
193
194 /* IE pmcc4-01 */
195 snprintf(name, sizeof(name), "%s%d", pi->up->devname, pi->portnum);
196
197#ifdef RLD_RESTART_DEBUG
198 pr_info(">> %s: creating workqueue <%s> for Port %d.\n",
199 __func__, name, pi->portnum); /* RLD DEBUG */
200#endif
201 pi->wq_port = create_singlethread_workqueue(name);
202 if (!pi->wq_port)
203 return -ENOMEM;
204 return 0; /* success */
205}
206
207void
208c4_wq_port_cleanup(mpi_t *pi)
209{
210 /*
211 * PORT POINT: cannot call this if WQ is statically allocated w/in
212 * structure since it calls kfree(wq);
213 */
214 if (pi->wq_port) {
215 destroy_workqueue(pi->wq_port); /* this also calls
216 * flush_workqueue() */
217 pi->wq_port = NULL;
218 }
219}
220
221/***************************************************************************/
222
223static irqreturn_t
224c4_linux_interrupt(int irq, void *dev_instance)
225{
226 struct net_device *ndev = dev_instance;
227
228 return musycc_intr_th_handler(netdev_priv(ndev));
229}
230
231
232#ifdef CONFIG_SBE_PMCC4_NCOMM
233static irqreturn_t
234c4_ebus_interrupt(int irq, void *dev_instance)
235{
236 struct net_device *ndev = dev_instance;
237
238 return c4_ebus_intr_th_handler(netdev_priv(ndev));
239}
240#endif
241
242
243static int
244void_open(struct net_device *ndev)
245{
246 pr_info("%s: trying to open master device !\n", ndev->name);
247 return -1;
248}
249
250
251static int
252chan_open(struct net_device *ndev)
253{
254 hdlc_device *hdlc = dev_to_hdlc(ndev);
255 const struct c4_priv *priv = hdlc->priv;
256 int ret;
257
258 ret = hdlc_open(ndev);
259 if (ret) {
260 pr_info("hdlc_open failure, err %d.\n", ret);
261 return ret;
262 }
263
264 ret = c4_chan_up(priv->ci, priv->channum);
265 if (ret < 0)
266 return ret;
267 try_module_get(THIS_MODULE);
268 netif_start_queue(ndev);
269 return 0; /* no error = success */
270}
271
272
273static int
274chan_close(struct net_device *ndev)
275{
276 hdlc_device *hdlc = dev_to_hdlc(ndev);
277 const struct c4_priv *priv = hdlc->priv;
278
279 netif_stop_queue(ndev);
280 musycc_chan_down((ci_t *) 0, priv->channum);
281 hdlc_close(ndev);
282 module_put(THIS_MODULE);
283 return 0;
284}
285
286
287static int
288chan_dev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
289{
290 return hdlc_ioctl(dev, ifr, cmd);
291}
292
293
294static int
295chan_attach_noop(struct net_device *ndev, unsigned short foo_1,
296 unsigned short foo_2)
297{
298 /* our driver has nothing to do here, show's
299 * over, go home
300 */
301 return 0;
302}
303
304
305static struct net_device_stats *
306chan_get_stats(struct net_device *ndev)
307{
308 mch_t *ch;
309 struct net_device_stats *nstats;
310 struct sbecom_chan_stats *stats;
311 int channum;
312
313 {
314 struct c4_priv *priv;
315
316 priv = (struct c4_priv *)dev_to_hdlc(ndev)->priv;
317 channum = priv->channum;
318 }
319
320 ch = c4_find_chan(channum);
321 if (ch == NULL)
322 return NULL;
323
324 nstats = &ndev->stats;
325 stats = &ch->s;
326
327 memset(nstats, 0, sizeof(struct net_device_stats));
328 nstats->rx_packets = stats->rx_packets;
329 nstats->tx_packets = stats->tx_packets;
330 nstats->rx_bytes = stats->rx_bytes;
331 nstats->tx_bytes = stats->tx_bytes;
332 nstats->rx_errors = stats->rx_length_errors +
333 stats->rx_over_errors +
334 stats->rx_crc_errors +
335 stats->rx_frame_errors +
336 stats->rx_fifo_errors +
337 stats->rx_missed_errors;
338 nstats->tx_errors = stats->tx_dropped +
339 stats->tx_aborted_errors +
340 stats->tx_fifo_errors;
341 nstats->rx_dropped = stats->rx_dropped;
342 nstats->tx_dropped = stats->tx_dropped;
343
344 nstats->rx_length_errors = stats->rx_length_errors;
345 nstats->rx_over_errors = stats->rx_over_errors;
346 nstats->rx_crc_errors = stats->rx_crc_errors;
347 nstats->rx_frame_errors = stats->rx_frame_errors;
348 nstats->rx_fifo_errors = stats->rx_fifo_errors;
349 nstats->rx_missed_errors = stats->rx_missed_errors;
350
351 nstats->tx_aborted_errors = stats->tx_aborted_errors;
352 nstats->tx_fifo_errors = stats->tx_fifo_errors;
353
354 return nstats;
355}
356
357
358static ci_t *
359get_ci_by_dev(struct net_device *ndev)
360{
361 return (ci_t *)(netdev_priv(ndev));
362}
363
364
365static int
366c4_linux_xmit(struct sk_buff *skb, struct net_device *ndev)
367{
368 const struct c4_priv *priv;
369 int rval;
370
371 hdlc_device *hdlc = dev_to_hdlc(ndev);
372
373 priv = hdlc->priv;
374
375 rval = musycc_start_xmit(priv->ci, priv->channum, skb);
376 return rval;
377}
378
379static const struct net_device_ops chan_ops = {
380 .ndo_open = chan_open,
381 .ndo_stop = chan_close,
382 .ndo_start_xmit = c4_linux_xmit,
383 .ndo_do_ioctl = chan_dev_ioctl,
384 .ndo_get_stats = chan_get_stats,
385};
386
387static struct net_device *
388create_chan(struct net_device *ndev, ci_t *ci,
389 struct sbecom_chan_param *cp)
390{
391 hdlc_device *hdlc;
392 struct net_device *dev;
393 hdw_info_t *hi;
394 int ret;
395
396 if (c4_find_chan(cp->channum))
397 return NULL; /* channel already exists */
398
399 {
400 struct c4_priv *priv;
401
402 /* allocate then fill in private data structure */
403 priv = kzalloc(sizeof(struct c4_priv), GFP_KERNEL);
404 if (!priv) {
405 pr_warning("%s: no memory for net_device !\n",
406 ci->devname);
407 return NULL;
408 }
409 dev = alloc_hdlcdev(priv);
410 if (!dev) {
411 pr_warning("%s: no memory for hdlc_device !\n",
412 ci->devname);
413 kfree(priv);
414 return NULL;
415 }
416 priv->ci = ci;
417 priv->channum = cp->channum;
418 }
419
420 hdlc = dev_to_hdlc(dev);
421
422 dev->base_addr = 0; /* not I/O mapped */
423 dev->irq = ndev->irq;
424 dev->type = ARPHRD_RAWHDLC;
425 *dev->name = 0; /* default ifconfig name = "hdlc" */
426
427 hi = (hdw_info_t *)ci->hdw_info;
428 if (hi->mfg_info_sts == EEPROM_OK) {
429 switch (hi->promfmt) {
430 case PROM_FORMAT_TYPE1:
431 memcpy(dev->dev_addr,
432 (FLD_TYPE1 *) (hi->mfg_info.pft1.Serial), 6);
433 break;
434 case PROM_FORMAT_TYPE2:
435 memcpy(dev->dev_addr,
436 (FLD_TYPE2 *) (hi->mfg_info.pft2.Serial), 6);
437 break;
438 default:
439 memset(dev->dev_addr, 0, 6);
440 break;
441 }
442 } else
443 memset(dev->dev_addr, 0, 6);
444
445 hdlc->xmit = c4_linux_xmit;
446
447 dev->netdev_ops = &chan_ops;
448 /*
449 * The native hdlc stack calls this 'attach' routine during
450 * hdlc_raw_ioctl(), passing parameters for line encoding and parity.
451 * Since hdlc_raw_ioctl() stack does not interrogate whether an 'attach'
452 * routine is actually registered or not, we supply a dummy routine which
453 * does nothing (since encoding and parity are setup for our driver via a
454 * special configuration application).
455 */
456
457 hdlc->attach = chan_attach_noop;
458
459 /* needed due to Ioctl calling sequence */
460 rtnl_unlock();
461 ret = register_hdlc_device(dev);
462 /* NOTE: <stats> setting must occur AFTER registration in order to "take" */
463 dev->tx_queue_len = MAX_DEFAULT_IFQLEN;
464
465 /* needed due to Ioctl calling sequence */
466 rtnl_lock();
467 if (ret) {
468 if (cxt1e1_log_level >= LOG_WARN)
469 pr_info("%s: create_chan[%d] registration error = %d.\n",
470 ci->devname, cp->channum, ret);
471 /* cleanup */
472 free_netdev(dev);
473 /* failed to register */
474 return NULL;
475 }
476 return dev;
477}
478
479
480/* the idea here is to get port information and pass it back (using pointer) */
481static status_t
482do_get_port(struct net_device *ndev, void *data)
483{
484 int ret;
485 ci_t *ci; /* ci stands for card information */
486 struct sbecom_port_param pp;/* copy data to kernel land */
487
488 if (copy_from_user(&pp, data, sizeof(struct sbecom_port_param)))
489 return -EFAULT;
490 if (pp.portnum >= MUSYCC_NPORTS)
491 return -EFAULT;
492 ci = get_ci_by_dev(ndev);
493 if (!ci)
494 return -EINVAL; /* get card info */
495
496 ret = c4_get_port(ci, pp.portnum);
497 if (ret < 0)
498 return ret;
499 if (copy_to_user(data, &ci->port[pp.portnum].p,
500 sizeof(struct sbecom_port_param)))
501 return -EFAULT;
502 return 0;
503}
504
505/* this function copys the user data and then calls the real action function */
506static status_t
507do_set_port(struct net_device *ndev, void *data)
508{
509 ci_t *ci; /* ci stands for card information */
510 struct sbecom_port_param pp;/* copy data to kernel land */
511
512 if (copy_from_user(&pp, data, sizeof(struct sbecom_port_param)))
513 return -EFAULT;
514 if (pp.portnum >= MUSYCC_NPORTS)
515 return -EFAULT;
516 ci = get_ci_by_dev(ndev);
517 if (!ci)
518 return -EINVAL; /* get card info */
519
520 if (pp.portnum >= ci->max_port) /* sanity check */
521 return -ENXIO;
522
523 memcpy(&ci->port[pp.portnum].p, &pp, sizeof(struct sbecom_port_param));
524 return c4_set_port(ci, pp.portnum);
525}
526
527/* work the port loopback mode as per directed */
528static status_t
529do_port_loop(struct net_device *ndev, void *data)
530{
531 struct sbecom_port_param pp;
532 ci_t *ci;
533
534 if (copy_from_user(&pp, data, sizeof(struct sbecom_port_param)))
535 return -EFAULT;
536 ci = get_ci_by_dev(ndev);
537 if (!ci)
538 return -EINVAL;
539 return c4_loop_port(ci, pp.portnum, pp.port_mode);
540}
541
542/* set the specified register with the given value / or just read it */
543static status_t
544do_framer_rw(struct net_device *ndev, void *data)
545{
546 struct sbecom_port_param pp;
547 ci_t *ci;
548 int ret;
549
550 if (copy_from_user(&pp, data, sizeof(struct sbecom_port_param)))
551 return -EFAULT;
552 ci = get_ci_by_dev(ndev);
553 if (!ci)
554 return -EINVAL;
555 ret = c4_frame_rw(ci, &pp);
556 if (ret < 0)
557 return ret;
558 if (copy_to_user(data, &pp, sizeof(struct sbecom_port_param)))
559 return -EFAULT;
560 return 0;
561}
562
563/* set the specified register with the given value / or just read it */
564static status_t
565do_pld_rw(struct net_device *ndev, void *data)
566{
567 struct sbecom_port_param pp;
568 ci_t *ci;
569 int ret;
570
571 if (copy_from_user(&pp, data, sizeof(struct sbecom_port_param)))
572 return -EFAULT;
573 ci = get_ci_by_dev(ndev);
574 if (!ci)
575 return -EINVAL;
576
577 ret = c4_pld_rw(ci, &pp);
578 if (ret)
579 return ret;
580 if (copy_to_user(data, &pp, sizeof(struct sbecom_port_param)))
581 return -EFAULT;
582 return 0;
583}
584
585/* set the specified register with the given value / or just read it */
586static status_t
587do_musycc_rw(struct net_device *ndev, void *data)
588{
589 struct c4_musycc_param mp;
590 ci_t *ci;
591 int ret;
592
593 if (copy_from_user(&mp, data, sizeof(struct c4_musycc_param)))
594 return -EFAULT;
595 ci = get_ci_by_dev(ndev);
596 if (!ci)
597 return -EINVAL;
598 ret = c4_musycc_rw(ci, &mp);
599 if (ret < 0)
600 return ret;
601 if (copy_to_user(data, &mp, sizeof(struct c4_musycc_param)))
602 return -EFAULT;
603 return 0;
604}
605
606static status_t
607do_get_chan(struct net_device *ndev, void *data)
608{
609 struct sbecom_chan_param cp;
610 int ret;
611
612 if (copy_from_user(&cp, data,
613 sizeof(struct sbecom_chan_param)))
614 return -EFAULT;
615
616 ret = c4_get_chan(cp.channum, &cp);
617 if (ret < 0)
618 return ret;
619
620 if (copy_to_user(data, &cp, sizeof(struct sbecom_chan_param)))
621 return -EFAULT;
622 return 0;
623}
624
625static status_t
626do_set_chan(struct net_device *ndev, void *data)
627{
628 struct sbecom_chan_param cp;
629 ci_t *ci;
630
631 if (copy_from_user(&cp, data, sizeof(struct sbecom_chan_param)))
632 return -EFAULT;
633 ci = get_ci_by_dev(ndev);
634 if (!ci)
635 return -EINVAL;
636 return c4_set_chan(cp.channum, &cp);
637}
638
639static status_t
640do_create_chan(struct net_device *ndev, void *data)
641{
642 ci_t *ci;
643 struct net_device *dev;
644 struct sbecom_chan_param cp;
645 int ret;
646
647 if (copy_from_user(&cp, data, sizeof(struct sbecom_chan_param)))
648 return -EFAULT;
649 ci = get_ci_by_dev(ndev);
650 if (!ci)
651 return -EINVAL;
652 dev = create_chan(ndev, ci, &cp);
653 if (!dev)
654 return -EBUSY;
655 ret = c4_new_chan(ci, cp.port, cp.channum, dev);
656 if (ret < 0) {
657 /* needed due to Ioctl calling sequence */
658 rtnl_unlock();
659 unregister_hdlc_device(dev);
660 /* needed due to Ioctl calling sequence */
661 rtnl_lock();
662 free_netdev(dev);
663 }
664 return ret;
665}
666
667static status_t
668do_get_chan_stats(struct net_device *ndev, void *data)
669{
670 struct c4_chan_stats_wrap ccs;
671 int ret;
672
673 if (copy_from_user(&ccs, data,
674 sizeof(struct c4_chan_stats_wrap)))
675 return -EFAULT;
676
677 ret = c4_get_chan_stats(ccs.channum, &ccs.stats);
678 if (ret < 0)
679 return ret;
680
681 if (copy_to_user(data, &ccs,
682 sizeof(struct c4_chan_stats_wrap)))
683 return -EFAULT;
684 return 0;
685}
686static status_t
687do_set_loglevel(struct net_device *ndev, void *data)
688{
689 unsigned int cxt1e1_log_level;
690
691 if (copy_from_user(&cxt1e1_log_level, data, sizeof(int)))
692 return -EFAULT;
693 sbecom_set_loglevel(cxt1e1_log_level);
694 return 0;
695}
696
697static status_t
698do_deluser(struct net_device *ndev, int lockit)
699{
700 if (ndev->flags & IFF_UP)
701 return -EBUSY;
702
703 {
704 ci_t *ci;
705 mch_t *ch;
706 const struct c4_priv *priv;
707 int channum;
708
709 priv = (struct c4_priv *)dev_to_hdlc(ndev)->priv;
710 ci = priv->ci;
711 channum = priv->channum;
712
713 ch = c4_find_chan(channum);
714 if (ch == NULL)
715 return -ENOENT;
716 ch->user = NULL; /* will be freed, below */
717 }
718
719 /* needed if Ioctl calling sequence */
720 if (lockit)
721 rtnl_unlock();
722 unregister_hdlc_device(ndev);
723 /* needed if Ioctl calling sequence */
724 if (lockit)
725 rtnl_lock();
726 free_netdev(ndev);
727 return 0;
728}
729
730int
731do_del_chan(struct net_device *musycc_dev, void *data)
732{
733 struct sbecom_chan_param cp;
734 char buf[sizeof(CHANNAME) + 3];
735 struct net_device *dev;
736 int ret;
737
738 if (copy_from_user(&cp, data,
739 sizeof(struct sbecom_chan_param)))
740 return -EFAULT;
741 if (cp.channum > 999)
742 return -EINVAL;
743 snprintf(buf, sizeof(buf), CHANNAME "%d", cp.channum);
744 dev = __dev_get_by_name(&init_net, buf);
745 if (!dev)
746 return -ENODEV;
747 ret = do_deluser(dev, 1);
748 if (ret)
749 return ret;
750 return c4_del_chan(cp.channum);
751}
752int c4_reset_board(void *);
753
754int
755do_reset(struct net_device *musycc_dev, void *data)
756{
757 const struct c4_priv *priv;
758 int i;
759
760 for (i = 0; i < 128; i++) {
761 struct net_device *ndev;
762 char buf[sizeof(CHANNAME) + 3];
763
764 sprintf(buf, CHANNAME "%d", i);
765 ndev = __dev_get_by_name(&init_net, buf);
766 if (!ndev)
767 continue;
768 priv = dev_to_hdlc(ndev)->priv;
769
770 if ((unsigned long) (priv->ci) ==
771 (unsigned long) (netdev_priv(musycc_dev))) {
772 ndev->flags &= ~IFF_UP;
773 netif_stop_queue(ndev);
774 do_deluser(ndev, 1);
775 }
776 }
777 return 0;
778}
779
780int
781do_reset_chan_stats(struct net_device *musycc_dev, void *data)
782{
783 struct sbecom_chan_param cp;
784
785 if (copy_from_user(&cp, data,
786 sizeof(struct sbecom_chan_param)))
787 return -EFAULT;
788 return c4_del_chan_stats(cp.channum);
789}
790
791static status_t
792c4_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
793{
794 ci_t *ci;
795 void *data;
796 int iocmd, iolen;
797 status_t ret;
798 static struct data {
799 union {
800 u_int8_t c;
801 u_int32_t i;
802 struct sbe_brd_info bip;
803 struct sbe_drv_info dip;
804 struct sbe_iid_info iip;
805 struct sbe_brd_addr bap;
806 struct sbecom_chan_stats stats;
807 struct sbecom_chan_param param;
808 struct temux_card_stats cards;
809 struct sbecom_card_param cardp;
810 struct sbecom_framer_param frp;
811 } u;
812 } arg;
813
814
815 if (!capable(CAP_SYS_ADMIN))
816 return -EPERM;
817 if (cmd != SIOCDEVPRIVATE + 15)
818 return -EINVAL;
819 ci = get_ci_by_dev(ndev);
820 if (!ci)
821 return -EINVAL;
822 if (ci->state != C_RUNNING)
823 return -ENODEV;
824 if (copy_from_user(&iocmd, ifr->ifr_data, sizeof(iocmd)))
825 return -EFAULT;
826#if 0
827 if (copy_from_user(&len, ifr->ifr_data + sizeof(iocmd), sizeof(len)))
828 return -EFAULT;
829#endif
830
831#if 0
832 pr_info("c4_ioctl: iocmd %x, dir %x type %x nr %x iolen %d.\n", iocmd,
833 _IOC_DIR(iocmd), _IOC_TYPE(iocmd), _IOC_NR(iocmd),
834 _IOC_SIZE(iocmd));
835#endif
836 iolen = _IOC_SIZE(iocmd);
837 if (iolen > sizeof(arg))
838 return -EFAULT;
839 data = ifr->ifr_data + sizeof(iocmd);
840 if (copy_from_user(&arg, data, iolen))
841 return -EFAULT;
842
843 ret = 0;
844 switch (iocmd) {
845 case SBE_IOC_PORT_GET:
846 ret = do_get_port(ndev, data);
847 break;
848 case SBE_IOC_PORT_SET:
849 ret = do_set_port(ndev, data);
850 break;
851 case SBE_IOC_CHAN_GET:
852 ret = do_get_chan(ndev, data);
853 break;
854 case SBE_IOC_CHAN_SET:
855 ret = do_set_chan(ndev, data);
856 break;
857 case C4_DEL_CHAN:
858 ret = do_del_chan(ndev, data);
859 break;
860 case SBE_IOC_CHAN_NEW:
861 ret = do_create_chan(ndev, data);
862 break;
863 case SBE_IOC_CHAN_GET_STAT:
864 ret = do_get_chan_stats(ndev, data);
865 break;
866 case SBE_IOC_LOGLEVEL:
867 ret = do_set_loglevel(ndev, data);
868 break;
869 case SBE_IOC_RESET_DEV:
870 ret = do_reset(ndev, data);
871 break;
872 case SBE_IOC_CHAN_DEL_STAT:
873 ret = do_reset_chan_stats(ndev, data);
874 break;
875 case C4_LOOP_PORT:
876 ret = do_port_loop(ndev, data);
877 break;
878 case C4_RW_FRMR:
879 ret = do_framer_rw(ndev, data);
880 break;
881 case C4_RW_MSYC:
882 ret = do_musycc_rw(ndev, data);
883 break;
884 case C4_RW_PLD:
885 ret = do_pld_rw(ndev, data);
886 break;
887 case SBE_IOC_IID_GET:
888 ret = (iolen == sizeof(struct sbe_iid_info)) ?
889 c4_get_iidinfo(ci, &arg.u.iip) : -EFAULT;
890 if (ret == 0) /* no error, copy data */
891 if (copy_to_user(data, &arg, iolen))
892 return -EFAULT;
893 break;
894 default:
895 ret = -EINVAL;
896 break;
897 }
898 return ret;
899}
900
901static const struct net_device_ops c4_ops = {
902 .ndo_open = void_open,
903 .ndo_start_xmit = c4_linux_xmit,
904 .ndo_do_ioctl = c4_ioctl,
905};
906
907static void c4_setup(struct net_device *dev)
908{
909 dev->type = ARPHRD_VOID;
910 dev->netdev_ops = &c4_ops;
911}
912
913struct net_device *__init
914c4_add_dev(hdw_info_t *hi, int brdno, unsigned long f0, unsigned long f1,
915 int irq0, int irq1)
916{
917 struct net_device *ndev;
918 ci_t *ci;
919
920 ndev = alloc_netdev(sizeof(ci_t), SBE_IFACETMPL, c4_setup);
921 if (!ndev) {
922 pr_warning("%s: no memory for struct net_device !\n",
923 hi->devname);
924 error_flag = -ENOMEM;
925 return NULL;
926 }
927 ci = (ci_t *)(netdev_priv(ndev));
928 ndev->irq = irq0;
929
930 ci->hdw_info = hi;
931 ci->state = C_INIT; /* mark as hardware not available */
932 ci->next = c4_list;
933 c4_list = ci;
934 ci->brdno = ci->next ? ci->next->brdno + 1 : 0;
935
936 if (!CI)
937 CI = ci; /* DEBUG, only board 0 usage */
938
939 strcpy(ci->devname, hi->devname);
940
941 /* tasklet */
942#if defined(SBE_ISR_TASKLET)
943 tasklet_init(&ci->ci_musycc_isr_tasklet,
944 (void (*) (unsigned long)) musycc_intr_bh_tasklet,
945 (unsigned long) ci);
946
947 if (atomic_read(&ci->ci_musycc_isr_tasklet.count) == 0)
948 tasklet_disable_nosync(&ci->ci_musycc_isr_tasklet);
949#elif defined(SBE_ISR_IMMEDIATE)
950 ci->ci_musycc_isr_tq.routine = (void *)(unsigned long)musycc_intr_bh_tasklet;
951 ci->ci_musycc_isr_tq.data = ci;
952#endif
953
954
955 if (register_netdev(ndev) ||
956 (c4_init(ci, (u_char *) f0, (u_char *) f1) != SBE_DRVR_SUCCESS)) {
957 kfree(netdev_priv(ndev));
958 kfree(ndev);
959 error_flag = -ENODEV;
960 return NULL;
961 }
962 /*************************************************************
963 * int request_irq(unsigned int irq,
964 * void (*handler)(int, void *, struct pt_regs *),
965 * unsigned long flags, const char *dev_name, void *dev_id);
966 * wherein:
967 * irq -> The interrupt number that is being requested.
968 * handler -> Pointer to handling function being installed.
969 * flags -> A bit mask of options related to interrupt management.
970 * dev_name -> String used in /proc/interrupts to show owner of interrupt.
971 * dev_id -> Pointer (for shared interrupt lines) to point to its own
972 * private data area (to identify which device is interrupting).
973 *
974 * extern void free_irq(unsigned int irq, void *dev_id);
975 **************************************************************/
976
977 if (request_irq(irq0, &c4_linux_interrupt,
978 IRQF_SHARED,
979 ndev->name, ndev)) {
980 pr_warning("%s: MUSYCC could not get irq: %d\n",
981 ndev->name, irq0);
982 unregister_netdev(ndev);
983 kfree(netdev_priv(ndev));
984 kfree(ndev);
985 error_flag = -EIO;
986 return NULL;
987 }
988#ifdef CONFIG_SBE_PMCC4_NCOMM
989 if (request_irq(irq1, &c4_ebus_interrupt, IRQF_SHARED, ndev->name, ndev)) {
990 pr_warning("%s: EBUS could not get irq: %d\n", hi->devname, irq1);
991 unregister_netdev(ndev);
992 free_irq(irq0, ndev);
993 kfree(netdev_priv(ndev));
994 kfree(ndev);
995 error_flag = -EIO;
996 return NULL;
997 }
998#endif
999
1000 /* setup board identification information */
1001
1002 {
1003 u_int32_t tmp;
1004
1005 /* also sets PROM format type (promfmt) for later usage */
1006 hdw_sn_get(hi, brdno);
1007
1008 switch (hi->promfmt) {
1009 case PROM_FORMAT_TYPE1:
1010 memcpy(ndev->dev_addr,
1011 (FLD_TYPE1 *) (hi->mfg_info.pft1.Serial), 6);
1012 /* unaligned data acquisition */
1013 memcpy(&tmp, (FLD_TYPE1 *) (hi->mfg_info.pft1.Id), 4);
1014 ci->brd_id = cpu_to_be32(tmp);
1015 break;
1016 case PROM_FORMAT_TYPE2:
1017 memcpy(ndev->dev_addr,
1018 (FLD_TYPE2 *) (hi->mfg_info.pft2.Serial), 6);
1019 /* unaligned data acquisition */
1020 memcpy(&tmp, (FLD_TYPE2 *) (hi->mfg_info.pft2.Id), 4);
1021 ci->brd_id = cpu_to_be32(tmp);
1022 break;
1023 default:
1024 ci->brd_id = 0;
1025 memset(ndev->dev_addr, 0, 6);
1026 break;
1027 }
1028
1029#if 1
1030 /* requires bid to be preset */
1031 sbeid_set_hdwbid(ci);
1032#else
1033 /* requires hdw_bid to be preset */
1034 sbeid_set_bdtype(ci);
1035#endif
1036 }
1037
1038#ifdef CONFIG_PROC_FS
1039 sbecom_proc_brd_init(ci);
1040#endif
1041#if defined(SBE_ISR_TASKLET)
1042 tasklet_enable(&ci->ci_musycc_isr_tasklet);
1043#endif
1044
1045 error_flag = c4_init2(ci);
1046 if (error_flag != SBE_DRVR_SUCCESS) {
1047#ifdef CONFIG_PROC_FS
1048 sbecom_proc_brd_cleanup(ci);
1049#endif
1050 unregister_netdev(ndev);
1051 free_irq(irq1, ndev);
1052 free_irq(irq0, ndev);
1053 kfree(netdev_priv(ndev));
1054 kfree(ndev);
1055 /* failure, error_flag is set */
1056 return NULL;
1057 }
1058 return ndev;
1059}
1060
1061static int __init
1062c4_mod_init(void)
1063{
1064 int rtn;
1065
1066 rtn = c4hw_attach_all();
1067 if (rtn)
1068 return -rtn; /* installation failure - see system log */
1069
1070 /* housekeeping notifications */
1071 if (cxt1e1_log_level != log_level_default)
1072 pr_info("NOTE: driver parameter <cxt1e1_log_level> changed from default %d to %d.\n",
1073 log_level_default, cxt1e1_log_level);
1074 if (cxt1e1_max_mru != max_mru_default)
1075 pr_info("NOTE: driver parameter <cxt1e1_max_mru> changed from default %d to %d.\n",
1076 max_mru_default, cxt1e1_max_mru);
1077 if (cxt1e1_max_mtu != max_mtu_default)
1078 pr_info("NOTE: driver parameter <cxt1e1_max_mtu> changed from default %d to %d.\n",
1079 max_mtu_default, cxt1e1_max_mtu);
1080 if (max_rxdesc_used != max_rxdesc_default) {
1081 if (max_rxdesc_used > 2000)
1082 max_rxdesc_used = 2000; /* out-of-bounds reset */
1083 pr_info("NOTE: driver parameter <max_rxdesc_used> changed from default %d to %d.\n",
1084 max_rxdesc_default, max_rxdesc_used);
1085 }
1086 if (max_txdesc_used != max_txdesc_default) {
1087 if (max_txdesc_used > 1000)
1088 max_txdesc_used = 1000; /* out-of-bounds reset */
1089 pr_info("NOTE: driver parameter <max_txdesc_used> changed from default %d to %d.\n",
1090 max_txdesc_default, max_txdesc_used);
1091 }
1092 return 0; /* installation success */
1093}
1094
1095
1096 /*
1097 * find any still allocated hdlc registrations and unregister via call to
1098 * do_deluser()
1099 */
1100
1101static void __exit
1102cleanup_hdlc(void)
1103{
1104 hdw_info_t *hi;
1105 ci_t *ci;
1106 struct net_device *ndev;
1107 int i, j, k;
1108
1109 for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
1110 if (hi->ndev) { /* a board has been attached */
1111 ci = (ci_t *)(netdev_priv(hi->ndev));
1112 for (j = 0; j < ci->max_port; j++)
1113 for (k = 0; k < MUSYCC_NCHANS; k++) {
1114 ndev = ci->port[j].chan[k]->user;
1115 if (ndev)
1116 do_deluser(ndev, 0);
1117 }
1118 }
1119 }
1120}
1121
1122
1123static void __exit
1124c4_mod_remove(void)
1125{
1126 cleanup_hdlc(); /* delete any missed channels */
1127 cleanup_devs();
1128 c4_cleanup();
1129 cleanup_ioremap();
1130 pr_info("SBE - driver removed.\n");
1131}
1132
1133module_init(c4_mod_init);
1134module_exit(c4_mod_remove);
1135
1136MODULE_AUTHOR("SBE Technical Services <support@sbei.com>");
1137MODULE_DESCRIPTION("wanPCI-CxT1E1 Generic HDLC WAN Driver module");
1138#ifdef MODULE_LICENSE
1139MODULE_LICENSE("GPL");
1140#endif
1141
1142/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/musycc.c b/drivers/staging/cxt1e1/musycc.c
deleted file mode 100644
index 9495c0b91966..000000000000
--- a/drivers/staging/cxt1e1/musycc.c
+++ /dev/null
@@ -1,1736 +0,0 @@
1static unsigned int max_intcnt;
2static unsigned int max_bh;
3
4/*-----------------------------------------------------------------------------
5 * musycc.c -
6 *
7 * Copyright (C) 2007 One Stop Systems, Inc.
8 * Copyright (C) 2003-2006 SBE, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * For further information, contact via email: support@onestopsystems.com
21 * One Stop Systems, Inc. Escondido, California U.S.A.
22 *-----------------------------------------------------------------------------
23 */
24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/types.h>
28#include "pmcc4_sysdep.h"
29#include <linux/kernel.h>
30#include <linux/errno.h>
31#include <linux/init.h>
32#include "sbecom_inline_linux.h"
33#include "libsbew.h"
34#include "pmcc4_private.h"
35#include "pmcc4.h"
36#include "musycc.h"
37
38#define sd_find_chan(ci,ch) c4_find_chan(ch)
39
40
41/*******************************************************************/
42/* global driver variables */
43extern ci_t *c4_list;
44extern int drvr_state;
45
46extern int cxt1e1_max_mru;
47extern int cxt1e1_max_mtu;
48extern int max_rxdesc_used;
49extern int max_txdesc_used;
50extern ci_t *CI; /* dummy pointr to board ZEROE's data - DEBUG
51 * USAGE */
52
53
54/*******************************************************************/
55/* forward references */
56void c4_fifo_free(mpi_t *, int);
57void c4_wk_chan_restart(mch_t *);
58void musycc_bh_tx_eom(mpi_t *, int);
59int musycc_chan_up(ci_t *, int);
60status_t __init musycc_init(ci_t *);
61void musycc_intr_bh_tasklet(ci_t *);
62void musycc_serv_req(mpi_t *, u_int32_t);
63void musycc_update_timeslots(mpi_t *);
64
65/*******************************************************************/
66
67static int
68musycc_dump_rxbuffer_ring_locked(mch_t *ch)
69{
70 struct mdesc *m;
71
72 u_int32_t status;
73 int n;
74
75#ifdef RLD_DUMP_BUFDATA
76 u_int32_t *dp;
77 int len = 0;
78#endif
79 if (ch->rxd_num == 0)
80 pr_info(" ZERO receive buffers allocated for this channel.");
81 else {
82 FLUSH_MEM_READ();
83 m = &ch->mdr[ch->rxix_irq_srv];
84 for (n = ch->rxd_num; n; n--) {
85 status = le32_to_cpu(m->status);
86 pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
87 (m == &ch->mdr[ch->rxix_irq_srv]) ? 'F' : ' ',
88 (unsigned long) m, n,
89 status,
90 m->data ? (status & HOST_RX_OWNED ? 'H' : 'M') : '-',
91 status & POLL_DISABLED ? 'P' : '-',
92 status & EOBIRQ_ENABLE ? 'b' : '-',
93 status & EOMIRQ_ENABLE ? 'm' : '-',
94 status & LENGTH_MASK,
95 le32_to_cpu(m->data), le32_to_cpu(m->next));
96#ifdef RLD_DUMP_BUFDATA
97 len = status & LENGTH_MASK;
98
99#if 1
100 if (m->data && (status & HOST_RX_OWNED))
101#else
102 /* always dump regardless of valid RX data */
103 if (m->data)
104#endif
105 {
106 dp = (u_int32_t *)OS_phystov((void *)(le32_to_cpu(m->data)));
107 if (len >= 0x10)
108 pr_info(" %x[%x]: %08X %08X %08X %08x\n",
109 (u_int32_t)dp, len,
110 *dp, *(dp + 1),
111 *(dp + 2), *(dp + 3));
112 else if (len >= 0x08)
113 pr_info(" %x[%x]: %08X %08X\n",
114 (u_int32_t)dp, len,
115 *dp, *(dp + 1));
116 else
117 pr_info(" %x[%x]: %08X\n",
118 (u_int32_t)dp,
119 len, *dp);
120 }
121#endif
122 m = m->snext;
123 }
124 }
125 pr_info("\n");
126
127 return 0;
128}
129
130static int
131musycc_dump_rxbuffer_ring(mch_t *ch)
132{
133 unsigned long flags = 0;
134 int ret;
135
136 spin_lock_irqsave(&ch->ch_rxlock, flags);
137 ret = musycc_dump_rxbuffer_ring_locked(ch);
138 spin_unlock_irqrestore(&ch->ch_rxlock, flags);
139
140 return ret;
141}
142
143static int
144musycc_dump_txbuffer_ring_locked(mch_t *ch)
145{
146 struct mdesc *m;
147 u_int32_t status;
148 int n;
149#ifdef RLD_DUMP_BUFDATA
150 u_int32_t *dp;
151 int len = 0;
152#endif
153
154 if (ch->txd_num == 0)
155 pr_info(" ZERO transmit buffers allocated for this channel.");
156 else {
157 FLUSH_MEM_READ();
158 m = ch->txd_irq_srv;
159 for (n = ch->txd_num; n; n--) {
160 status = le32_to_cpu(m->status);
161 pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
162 (m == ch->txd_usr_add) ? 'F' : ' ',
163 (m == ch->txd_irq_srv) ? 'L' : ' ',
164 (unsigned long) m, n,
165 status,
166 m->data ? (status & MUSYCC_TX_OWNED ? 'M' : 'H') : '-',
167 status & POLL_DISABLED ? 'P' : '-',
168 status & EOBIRQ_ENABLE ? 'b' : '-',
169 status & EOMIRQ_ENABLE ? 'm' : '-',
170 status & LENGTH_MASK,
171 le32_to_cpu(m->data), le32_to_cpu(m->next));
172#ifdef RLD_DUMP_BUFDATA
173 len = status & LENGTH_MASK;
174
175 if (m->data) {
176 dp = (u_int32_t *)OS_phystov((void *)(le32_to_cpu(m->data)));
177 if (len >= 0x10)
178 pr_info(" %x[%x]: %08X %08X %08X %08x\n",
179 (u_int32_t) dp, len,
180 *dp, *(dp + 1),
181 *(dp + 2), *(dp + 3));
182 else if (len >= 0x08)
183 pr_info(" %x[%x]: %08X %08X\n",
184 (u_int32_t)dp, len,
185 *dp, *(dp + 1));
186 else
187 pr_info(" %x[%x]: %08X\n",
188 (u_int32_t)dp, len, *dp);
189 }
190#endif
191 m = m->snext;
192 }
193 } /* -for- */
194 pr_info("\n");
195
196 return 0;
197}
198
199static int
200musycc_dump_txbuffer_ring(mch_t *ch)
201{
202 unsigned long flags = 0;
203 int ret;
204
205 spin_lock_irqsave(&ch->ch_txlock, flags);
206 ret = musycc_dump_txbuffer_ring_locked(ch);
207 spin_unlock_irqrestore(&ch->ch_txlock, flags);
208
209 return ret;
210}
211
212/*
213 * The following supports a backdoor debug facility which can be used to
214 * display the state of a board's channel.
215 */
216
217status_t
218musycc_dump_ring(ci_t *ci, unsigned int chan)
219{
220 mch_t *ch;
221 int bh;
222
223 if (chan >= MAX_CHANS_USED)
224 return SBE_DRVR_FAIL; /* E2BIG */
225
226 bh = atomic_read(&ci->bh_pending);
227 pr_info(">> bh_pend %d [%d] ihead %d itail %d [%d] th_cnt %d bh_cnt %d wdcnt %d note %d\n",
228 bh, max_bh, ci->iqp_headx, ci->iqp_tailx, max_intcnt,
229 ci->intlog.drvr_intr_thcount,
230 ci->intlog.drvr_intr_bhcount,
231 ci->wdcount, ci->wd_notify);
232 max_bh = 0; /* reset counter */
233 max_intcnt = 0; /* reset counter */
234
235 ch = sd_find_chan(dummy, chan);
236 if (!ch) {
237 pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
238 return ENOENT;
239 }
240 pr_info(">> CI %p CHANNEL %3d @ %p: state %x status/p %x/%x\n",
241 ci, chan, ch, ch->state,
242 ch->status, ch->p.status);
243 pr_info("--------------------------------\n");
244 pr_info("TX Buffer Ring - Channel %d, txd_num %d. (bd/ch pend %d %d), TXD required %d, txpkt %lu\n",
245 chan, ch->txd_num,
246 (u_int32_t)atomic_read(&ci->tx_pending),
247 (u_int32_t)atomic_read(&ch->tx_pending),
248 ch->txd_required, ch->s.tx_packets);
249 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
250 ch->user, ch->txd_irq_srv, ch->txd_usr_add,
251 sd_queue_stopped(ch->user),
252 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
253 musycc_dump_txbuffer_ring(ch);
254 pr_info("RX Buffer Ring - Channel %d, rxd_num %d. IRQ_SRV[%d] 0x%p, start_rx %x rxpkt %lu\n",
255 chan, ch->rxd_num, ch->rxix_irq_srv,
256 &ch->mdr[ch->rxix_irq_srv], ch->ch_start_rx, ch->s.rx_packets);
257 musycc_dump_rxbuffer_ring(ch);
258
259 return SBE_DRVR_SUCCESS;
260}
261
262
263status_t
264musycc_dump_rings(ci_t *ci, unsigned int start_chan)
265{
266 unsigned int chan;
267
268 for (chan = start_chan; chan < (start_chan + 5); chan++)
269 musycc_dump_ring(ci, chan);
270 return SBE_DRVR_SUCCESS;
271}
272
273
274/*
275 * NOTE on musycc_init_mdt(): These MUSYCC writes are only operational after
276 * a MUSYCC GROUP_INIT command has been issued.
277 */
278
279void
280musycc_init_mdt(mpi_t *pi)
281{
282 u_int32_t *addr, cfg;
283 int i;
284
285 /*
286 * This Idle Code insertion takes effect prior to channel's first
287 * transmitted message. After that, each message contains its own Idle
288 * Code information which is to be issued after the message is
289 * transmitted (Ref.MUSYCC 5.2.2.3: MCENBL bit in Group Configuration
290 * Descriptor).
291 */
292
293 addr = (u_int32_t *) ((u_long) pi->reg + MUSYCC_MDT_BASE03_ADDR);
294 cfg = CFG_CH_FLAG_7E << IDLE_CODE;
295
296 for (i = 0; i < 32; addr++, i++)
297 pci_write_32(addr, cfg);
298}
299
300
301/* Set TX thp to the next unprocessed md */
302
303void
304musycc_update_tx_thp(mch_t *ch)
305{
306 struct mdesc *md;
307 unsigned long flags;
308
309 spin_lock_irqsave(&ch->ch_txlock, flags);
310 while (1) {
311 md = ch->txd_irq_srv;
312 FLUSH_MEM_READ();
313 if (!md->data) {
314 /* No MDs with buffers to process */
315 spin_unlock_irqrestore(&ch->ch_txlock, flags);
316 return;
317 }
318 if ((le32_to_cpu(md->status)) & MUSYCC_TX_OWNED) {
319 /* this is the MD to restart TX with */
320 break;
321 }
322 /*
323 * Otherwise, we have a valid, host-owned message descriptor which
324 * has been successfully transmitted and whose buffer can be freed,
325 * so... process this MD, it's owned by the host. (This might give
326 * as a new, updated txd_irq_srv.)
327 */
328 musycc_bh_tx_eom(ch->up, ch->gchan);
329 }
330 md = ch->txd_irq_srv;
331 ch->up->regram->thp[ch->gchan] = cpu_to_le32(OS_vtophys(md));
332 FLUSH_MEM_WRITE();
333
334 if (ch->tx_full) {
335 ch->tx_full = 0;
336 ch->txd_required = 0;
337 sd_enable_xmit(ch->user); /* re-enable to catch flow controlled
338 * channel */
339 }
340 spin_unlock_irqrestore(&ch->ch_txlock, flags);
341
342#ifdef RLD_TRANS_DEBUG
343 pr_info("++ musycc_update_tx_thp[%d]: setting thp = %p, sts %x\n",
344 ch->channum, md, md->status);
345#endif
346}
347
348
349/*
350 * This is the workq task executed by the OS when our queue_work() is
351 * scheduled and run. It can fire off either RX or TX ACTIVATION depending
352 * upon the channel's ch_start_tx and ch_start_rx variables. This routine
353 * is implemented as a work queue so that the call to the service request is
354 * able to sleep, awaiting an interrupt acknowledgment response (SACK) from
355 * the hardware.
356 */
357
358void
359musycc_wq_chan_restart(void *arg) /* channel private structure */
360{
361 mch_t *ch;
362 mpi_t *pi;
363 struct mdesc *md;
364
365#if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
366 static int hereb4 = 7;
367#endif
368
369 ch = container_of(arg, struct c4_chan_info, ch_work);
370 pi = ch->up;
371
372#ifdef RLD_TRANS_DEBUG
373 pr_info("wq_chan_restart[%d]: start_RT[%d/%d] status %x\n",
374 ch->channum, ch->ch_start_rx, ch->ch_start_tx, ch->status);
375
376#endif
377
378 /**********************************/
379 /** check for RX restart request **/
380 /**********************************/
381
382 if ((ch->ch_start_rx) && (ch->status & RX_ENABLED)) {
383
384 ch->ch_start_rx = 0;
385#if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
386 if (hereb4) { /* RLD DEBUG */
387 hereb4--;
388#ifdef RLD_TRANS_DEBUG
389 md = &ch->mdr[ch->rxix_irq_srv];
390 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
391 ch->channum, ch->rxix_irq_srv, md,
392 le32_to_cpu(md->status), ch->s.rx_packets);
393#elif defined(RLD_RXACT_DEBUG)
394 md = &ch->mdr[ch->rxix_irq_srv];
395 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
396 ch->channum, ch->rxix_irq_srv,
397 md, le32_to_cpu(md->status),
398 ch->s.rx_packets);
399 musycc_dump_rxbuffer_ring(ch); /* RLD DEBUG */
400#endif
401 }
402#endif
403 musycc_serv_req(pi, SR_CHANNEL_ACTIVATE |
404 SR_RX_DIRECTION | ch->gchan);
405 }
406 /**********************************/
407 /** check for TX restart request **/
408 /**********************************/
409
410 if ((ch->ch_start_tx) && (ch->status & TX_ENABLED)) {
411 /* find next unprocessed message, then set TX thp to it */
412 musycc_update_tx_thp(ch);
413
414 md = ch->txd_irq_srv;
415 if (!md) {
416#ifdef RLD_TRANS_DEBUG
417 pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n",
418 ch->channum);
419#endif
420 } else if (md->data && ((le32_to_cpu(md->status)) &
421 MUSYCC_TX_OWNED)) {
422 ch->ch_start_tx = 0;
423
424#ifdef RLD_TRANS_DEBUG
425 pr_info("++ musycc_wq_chan_restart() CHAN TX ACTIVATE: chan %d txd_irq_srv %p = sts %x, txpkt %lu\n",
426 ch->channum, ch->txd_irq_srv,
427 ch->txd_irq_srv->status, ch->s.tx_packets);
428#endif
429 musycc_serv_req(pi, SR_CHANNEL_ACTIVATE |
430 SR_TX_DIRECTION | ch->gchan);
431 }
432#ifdef RLD_RESTART_DEBUG
433 else {
434 /* retain request to start until retried and we have data to xmit */
435 pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
436 ch->channum, md,
437 le32_to_cpu(md->status),
438 le32_to_cpu(md->data), ch->ch_start_tx);
439 musycc_dump_txbuffer_ring_locked(ch);
440 }
441#endif
442 }
443}
444
445
446 /*
447 * Channel restart either fires of a workqueue request (2.6) or lodges a
448 * watchdog activation sequence (2.4).
449 */
450
451void
452musycc_chan_restart(mch_t *ch)
453{
454#ifdef RLD_RESTART_DEBUG
455 pr_info("++ musycc_chan_restart[%d]: txd_irq_srv @ %p = sts %x\n",
456 ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status);
457#endif
458
459 /* 2.6 - find next unprocessed message, then set TX thp to it */
460#ifdef RLD_RESTART_DEBUG
461 pr_info(">> musycc_chan_restart: scheduling Chan %x workQ @ %p\n",
462 ch->channum, &ch->ch_work);
463#endif
464 c4_wk_chan_restart(ch); /* work queue mechanism fires off: Ref:
465 * musycc_wq_chan_restart () */
466}
467
468
469void
470rld_put_led(mpi_t *pi, u_int32_t ledval)
471{
472 static u_int32_t led;
473
474 if (ledval == 0)
475 led = 0;
476 else
477 led |= ledval;
478
479 /* RLD DEBUG TRANHANG */
480 pci_write_32((u_int32_t *) &pi->up->cpldbase->leds, led);
481}
482
483
484#define MUSYCC_SR_RETRY_CNT 9
485
486void
487musycc_serv_req(mpi_t *pi, u_int32_t req)
488{
489 volatile u_int32_t r;
490 int rcnt;
491
492 /*
493 * PORT NOTE: Semaphore protect service loop guarantees only a single
494 * operation at a time. Per MUSYCC Manual - "Issuing service requests to
495 * the same channel group without first receiving ACK from each request
496 * may cause the host to lose track of which service request has been
497 * acknowledged."
498 */
499
500 SD_SEM_TAKE(&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
501 * group */
502
503 if (pi->sr_last == req) {
504#ifdef RLD_TRANS_DEBUG
505 pr_info(">> same SR, Port %d Req %x\n", pi->portnum, req);
506#endif
507
508 /*
509 * The most likely repeated request is the channel activation command
510 * which follows the occurrence of a Transparent mode TX ONR or a
511 * BUFF error. If the previous command was a CHANNEL ACTIVATE,
512 * precede it with a NOOP command in order maintain coherent control
513 * of this current (re)ACTIVATE.
514 */
515
516 r = (pi->sr_last & ~SR_GCHANNEL_MASK);
517 if ((r == (SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION)) ||
518 (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION))) {
519#ifdef RLD_TRANS_DEBUG
520 pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
521#endif
522 /* allow this next request */
523 SD_SEM_GIVE(&pi->sr_sem_busy);
524 musycc_serv_req(pi, SR_NOOP);
525 /* relock & continue w/ original req */
526 SD_SEM_TAKE(&pi->sr_sem_busy, "serv");
527 } else if (req == SR_NOOP) {
528 /* no need to issue back-to-back
529 * SR_NOOP commands at this time
530 */
531#ifdef RLD_TRANS_DEBUG
532 pr_info(">> same Port SR_NOOP skipped, Port %d\n",
533 pi->portnum);
534#endif
535 /* allow this next request */
536 SD_SEM_GIVE(&pi->sr_sem_busy);
537 return;
538 }
539 }
540 rcnt = 0;
541 pi->sr_last = req;
542rewrite:
543 pci_write_32((u_int32_t *) &pi->reg->srd, req);
544 FLUSH_MEM_WRITE();
545
546 /*
547 * Per MUSYCC Manual, Section 6.1,2 - "When writing an SCR service
548 * request, the host must ensure at least one PCI bus clock cycle has
549 * elapsed before writing another service request. To meet this minimum
550 * elapsed service request write timing interval, it is recommended that
551 * the host follow any SCR write with another operation which reads from
552 * the same address."
553 */
554
555 /* adhere to write timing imposition */
556 r = pci_read_32((u_int32_t *) &pi->reg->srd);
557
558
559 if ((r != req) && (req != SR_CHIP_RESET) &&
560 (++rcnt <= MUSYCC_SR_RETRY_CNT)) {
561 if (cxt1e1_log_level >= LOG_MONITOR)
562 pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
563 pi->up->devname, rcnt, req, pi->sr_last, r,
564 (pi->portnum * MUSYCC_NCHANS) + (req & 0x1f));
565 /* this delay helps reduce reissue counts
566 * (reason not yet researched)
567 */
568 OS_uwait_dummy();
569 goto rewrite;
570 }
571 if (rcnt > MUSYCC_SR_RETRY_CNT) {
572 pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
573 pi->up->devname, MUSYCC_SR_RETRY_CNT,
574 req, pi->portnum);
575 SD_SEM_GIVE(&pi->sr_sem_busy); /* allow any next request */
576 return;
577 }
578 if (req == SR_CHIP_RESET) {
579 /*
580 * PORT NOTE: the CHIP_RESET command is NOT ack'd by the MUSYCC, thus
581 * the upcoming delay is used. Though the MUSYCC documentation
582 * suggests a read-after-write would supply the required delay, it's
583 * unclear what CPU/BUS clock speeds might have been assumed when
584 * suggesting this 'lack of ACK' workaround. Thus the use of uwait.
585 */
586 OS_uwait(100000, "icard"); /* 100ms */
587 } else {
588 FLUSH_MEM_READ();
589 /* sleep until SACK interrupt occurs */
590 SD_SEM_TAKE(&pi->sr_sem_wait, "sakack");
591 }
592 SD_SEM_GIVE(&pi->sr_sem_busy); /* allow any next request */
593}
594
595
596#ifdef SBE_PMCC4_ENABLE
597void
598musycc_update_timeslots(mpi_t *pi)
599{
600 int i, ch;
601 char e1mode = IS_FRAME_ANY_E1(pi->p.port_mode);
602
603 for (i = 0; i < 32; i++) {
604 int usedby = 0, last = 0, ts, j, bits[8];
605
606 u_int8_t lastval = 0;
607
608 if (((i == 0) && e1mode) || /* disable if E1 mode */
609 ((i == 16) && ((pi->p.port_mode == CFG_FRAME_E1CRC_CAS) ||
610 (pi->p.port_mode == CFG_FRAME_E1CRC_CAS_AMI))) ||
611 ((i > 23) && (!e1mode))) /* disable if T1 mode */
612 /* make tslot unavailable for this mode */
613 pi->tsm[i] = 0xff;
614 else
615 /* make tslot available for assignment */
616 pi->tsm[i] = 0x00;
617 for (j = 0; j < 8; j++)
618 bits[j] = -1;
619 for (ch = 0; ch < MUSYCC_NCHANS; ch++) {
620 if ((pi->chan[ch]->state == UP) &&
621 (pi->chan[ch]->p.bitmask[i])) {
622 usedby++;
623 last = ch;
624 lastval = pi->chan[ch]->p.bitmask[i];
625 for (j = 0; j < 8; j++)
626 if (lastval & (1 << j))
627 bits[j] = ch;
628 pi->tsm[i] |= lastval;
629 }
630 }
631 if (!usedby)
632 ts = 0;
633 else if ((usedby == 1) && (lastval == 0xff))
634 ts = (4 << 5) | last;
635 else if ((usedby == 1) && (lastval == 0x7f))
636 ts = (5 << 5) | last;
637 else {
638 int idx;
639
640 if (bits[0] < 0)
641 ts = (6 << 5) | (idx = last);
642 else
643 ts = (7 << 5) | (idx = bits[0]);
644 for (j = 1; j < 8; j++) {
645 pi->regram->rscm[idx * 8 + j] =
646 (bits[j] < 0) ? 0 : (0x80 | bits[j]);
647 pi->regram->tscm[idx * 8 + j] =
648 (bits[j] < 0) ? 0 : (0x80 | bits[j]);
649 }
650 }
651 pi->regram->rtsm[i] = ts;
652 pi->regram->ttsm[i] = ts;
653 }
654 FLUSH_MEM_WRITE();
655
656 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
657 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
658 musycc_serv_req(pi, SR_SUBCHANNEL_MAP | SR_RX_DIRECTION);
659 musycc_serv_req(pi, SR_SUBCHANNEL_MAP | SR_TX_DIRECTION);
660}
661#endif
662
663
664#ifdef SBE_WAN256T3_ENABLE
665 void
666musycc_update_timeslots(mpi_t *pi)
667{
668 mch_t *ch;
669
670 u_int8_t ts, hmask, tsen;
671 int gchan;
672 int i;
673
674#ifdef SBE_PMCC4_ENABLE
675 hmask = (0x1f << pi->up->p.hypersize) & 0x1f;
676#endif
677#ifdef SBE_WAN256T3_ENABLE
678 hmask = (0x1f << hyperdummy) & 0x1f;
679#endif
680 for (i = 0; i < 128; i++) {
681 gchan = ((pi->portnum * MUSYCC_NCHANS) +
682 (i & hmask)) % MUSYCC_NCHANS;
683 ch = pi->chan[gchan];
684 if (ch->p.mode_56k)
685 tsen = MODE_56KBPS;
686 else
687 tsen = MODE_64KBPS; /* also the default */
688 ts = ((pi->portnum % 4) == (i / 32)) ? (tsen << 5) | (i & hmask) : 0;
689 pi->regram->rtsm[i] = ts;
690 pi->regram->ttsm[i] = ts;
691 }
692 FLUSH_MEM_WRITE();
693 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
694 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
695}
696#endif
697
698
699 /*
700 * This routine converts a generic library channel configuration parameter
701 * into a hardware specific register value (IE. MUSYCC CCD Register).
702 */
703u_int32_t
704musycc_chan_proto(int proto)
705{
706 int reg;
707
708 switch (proto) {
709 case CFG_CH_PROTO_TRANS: /* 0 */
710 reg = MUSYCC_CCD_TRANS;
711 break;
712 case CFG_CH_PROTO_SS7: /* 1 */
713 reg = MUSYCC_CCD_SS7;
714 break;
715 default:
716 case CFG_CH_PROTO_ISLP_MODE: /* 4 */
717 case CFG_CH_PROTO_HDLC_FCS16: /* 2 */
718 reg = MUSYCC_CCD_HDLC_FCS16;
719 break;
720 case CFG_CH_PROTO_HDLC_FCS32: /* 3 */
721 reg = MUSYCC_CCD_HDLC_FCS32;
722 break;
723 }
724
725 return reg;
726}
727
728#ifdef SBE_WAN256T3_ENABLE
729static void __init
730musycc_init_port(mpi_t *pi)
731{
732 pci_write_32((u_int32_t *) &pi->reg->gbp, OS_vtophys(pi->regram));
733
734 pi->regram->grcd =
735 __constant_cpu_to_le32(MUSYCC_GRCD_RX_ENABLE |
736 MUSYCC_GRCD_TX_ENABLE |
737 MUSYCC_GRCD_SF_ALIGN |
738 MUSYCC_GRCD_SUBCHAN_DISABLE |
739 MUSYCC_GRCD_OOFMP_DISABLE |
740 MUSYCC_GRCD_COFAIRQ_DISABLE |
741 MUSYCC_GRCD_MC_ENABLE |
742 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
743
744 pi->regram->pcd =
745 __constant_cpu_to_le32(MUSYCC_PCD_E1X4_MODE |
746 MUSYCC_PCD_TXDATA_RISING |
747 MUSYCC_PCD_TX_DRIVEN);
748
749 /* Message length descriptor */
750 pi->regram->mld = __constant_cpu_to_le32(cxt1e1_max_mru | (cxt1e1_max_mru << 16));
751 FLUSH_MEM_WRITE();
752
753 musycc_serv_req(pi, SR_GROUP_INIT | SR_RX_DIRECTION);
754 musycc_serv_req(pi, SR_GROUP_INIT | SR_TX_DIRECTION);
755
756 musycc_init_mdt(pi);
757
758 musycc_update_timeslots(pi);
759}
760#endif
761
762
763status_t __init
764musycc_init(ci_t *ci)
765{
766 char *regaddr; /* temp for address boundary calculations */
767 int i, gchan;
768
769 OS_sem_init(&ci->sem_wdbusy, SEM_AVAILABLE); /* watchdog exclusion */
770
771 /*
772 * Per MUSYCC manual, Section 6.3.4 - "The host must allocate a dword
773 * aligned memory segment for interrupt queue pointers."
774 */
775
776#define INT_QUEUE_BOUNDARY 4
777
778 regaddr = kzalloc((INT_QUEUE_SIZE + 1) * sizeof(u_int32_t),
779 GFP_KERNEL | GFP_DMA);
780 if (!regaddr)
781 return -ENOMEM;
782 ci->iqd_p_saved = regaddr; /* save orig value for free's usage */
783 /* this calculates closest boundary */
784 ci->iqd_p = (u_int32_t *) ((unsigned long)(regaddr + INT_QUEUE_BOUNDARY - 1) &
785 (~(INT_QUEUE_BOUNDARY - 1)));
786
787 for (i = 0; i < INT_QUEUE_SIZE; i++)
788 ci->iqd_p[i] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
789
790 for (i = 0; i < ci->max_port; i++) {
791 mpi_t *pi = &ci->port[i];
792
793 /*
794 * Per MUSYCC manual, Section 6.3.2 - "The host must allocate a 2KB
795 * bound memory segment for Channel Group 0."
796 */
797
798#define GROUP_BOUNDARY 0x800
799
800 regaddr = kzalloc(sizeof(struct musycc_groupr) + GROUP_BOUNDARY,
801 GFP_KERNEL | GFP_DMA);
802 if (!regaddr) {
803 for (gchan = 0; gchan < i; gchan++) {
804 pi = &ci->port[gchan];
805 kfree(pi->reg);
806 pi->reg = NULL;
807 }
808 return -ENOMEM;
809 }
810 pi->regram_saved = regaddr; /* save orig value for free's usage */
811 /* this calculates closest boundary */
812 pi->regram = (struct musycc_groupr *) ((unsigned long)(regaddr + GROUP_BOUNDARY - 1) &
813 (~(GROUP_BOUNDARY - 1)));
814 }
815
816 /* any board centric MUSYCC commands will use group ZERO as its "home" */
817 ci->regram = ci->port[0].regram;
818 musycc_serv_req(&ci->port[0], SR_CHIP_RESET);
819
820 pci_write_32((u_int32_t *) &ci->reg->gbp, OS_vtophys(ci->regram));
821 pci_flush_write(ci);
822#ifdef CONFIG_SBE_PMCC4_NCOMM
823 ci->regram->__glcd = __constant_cpu_to_le32(GCD_MAGIC);
824#else
825 /* standard driver POLLS for INTB via CPLD register */
826 ci->regram->__glcd = __constant_cpu_to_le32(GCD_MAGIC |
827 MUSYCC_GCD_INTB_DISABLE);
828#endif
829
830 ci->regram->__iqp = cpu_to_le32(OS_vtophys(&ci->iqd_p[0]));
831 ci->regram->__iql = __constant_cpu_to_le32(INT_QUEUE_SIZE - 1);
832 pci_write_32((u_int32_t *) &ci->reg->dacbp, 0);
833 FLUSH_MEM_WRITE();
834
835 ci->state = C_RUNNING; /* mark as full interrupt processing
836 * available */
837
838 musycc_serv_req(&ci->port[0], SR_GLOBAL_INIT); /* FIRST INTERRUPT ! */
839
840 /* sanity check settable parameters */
841
842 if (cxt1e1_max_mru > 0xffe) {
843 pr_warning("Maximum allowed MRU exceeded, resetting %d to %d.\n",
844 cxt1e1_max_mru, 0xffe);
845 cxt1e1_max_mru = 0xffe;
846 }
847 if (cxt1e1_max_mtu > 0xffe) {
848 pr_warning("Maximum allowed MTU exceeded, resetting %d to %d.\n",
849 cxt1e1_max_mtu, 0xffe);
850 cxt1e1_max_mtu = 0xffe;
851 }
852#ifdef SBE_WAN256T3_ENABLE
853 for (i = 0; i < MUSYCC_NPORTS; i++)
854 musycc_init_port(&ci->port[i]);
855#endif
856
857 return SBE_DRVR_SUCCESS; /* no error */
858}
859
860
861void
862musycc_bh_tx_eom(mpi_t *pi, int gchan)
863{
864 mch_t *ch;
865 struct mdesc *md;
866
867 volatile u_int32_t status;
868
869 ch = pi->chan[gchan];
870 if (!ch || ch->state != UP) {
871 if (cxt1e1_log_level >= LOG_ERROR)
872 pr_info("%s: intr: xmit EOM on uninitialized channel %d\n",
873 pi->up->devname, gchan);
874 }
875 if (!ch || !ch->mdt)
876 return; /* note: mdt==0 implies a malloc()
877 * failure w/in chan_up() routine */
878
879 do {
880 FLUSH_MEM_READ();
881 md = ch->txd_irq_srv;
882 status = le32_to_cpu(md->status);
883
884 /*
885 * Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
886 * Transmit Buffer Descriptor during Transparent Mode.
887 */
888 if (status & MUSYCC_TX_OWNED) {
889 int readCount, loopCount;
890
891 /***********************************************************/
892 /* HW Bug Fix */
893 /* ---------- */
894 /* Under certain PCI Bus loading conditions, the data */
895 /* associated with an update of Shared Memory is delayed */
896 /* relative to its PCI Interrupt. This is caught when */
897 /* the host determines it does not yet OWN the descriptor. */
898 /***********************************************************/
899
900 readCount = 0;
901 while (status & MUSYCC_TX_OWNED) {
902 for (loopCount = 0; loopCount < 0x30; loopCount++)
903 /* use call to avoid optimization
904 * removal of dummy delay */
905 OS_uwait_dummy();
906 FLUSH_MEM_READ();
907 status = le32_to_cpu(md->status);
908 if (readCount++ > 40)
909 break; /* don't wait any longer */
910 }
911 if (status & MUSYCC_TX_OWNED) {
912 if (cxt1e1_log_level >= LOG_MONITOR) {
913 pr_info("%s: Port %d Chan %2d - unexpected TX msg ownership intr (md %p sts %x)\n",
914 pi->up->devname, pi->portnum,
915 ch->channum, md, status);
916 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
917 ch->user, ch->txd_irq_srv,
918 ch->txd_usr_add,
919 sd_queue_stopped(ch->user),
920 ch->ch_start_tx, ch->tx_full,
921 ch->txd_free, ch->p.chan_mode);
922 musycc_dump_txbuffer_ring_locked(ch);
923 }
924 break; /* Not our mdesc, done */
925 } else {
926 if (cxt1e1_log_level >= LOG_MONITOR)
927 pr_info("%s: Port %d Chan %2d - recovered TX msg ownership [%d] (md %p sts %x)\n",
928 pi->up->devname, pi->portnum,
929 ch->channum, readCount,
930 md, status);
931 }
932 }
933 ch->txd_irq_srv = md->snext;
934
935 md->data = 0;
936 if (md->mem_token) {
937 /* upcount channel */
938 atomic_sub(OS_mem_token_tlen(md->mem_token),
939 &ch->tx_pending);
940 /* upcount card */
941 atomic_sub(OS_mem_token_tlen(md->mem_token),
942 &pi->up->tx_pending);
943#ifdef SBE_WAN256T3_ENABLE
944 if (!atomic_read(&pi->up->tx_pending))
945 wan256t3_led(pi->up, LED_TX, 0);
946#endif
947 OS_mem_token_free_irq(md->mem_token);
948 md->mem_token = NULL;
949 }
950 md->status = 0;
951#ifdef RLD_TXFULL_DEBUG
952 if (cxt1e1_log_level >= LOG_MONITOR2)
953 pr_info("~~ tx_eom: tx_full %x txd_free %d -> %d\n",
954 ch->tx_full, ch->txd_free, ch->txd_free + 1);
955#endif
956 ++ch->txd_free;
957 FLUSH_MEM_WRITE();
958
959 if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) &&
960 (status & EOBIRQ_ENABLE)) {
961 if (cxt1e1_log_level >= LOG_MONITOR)
962 pr_info("%s: Mode (%x) incorrect EOB status (%x)\n",
963 pi->up->devname, ch->p.chan_mode,
964 status);
965 if ((status & EOMIRQ_ENABLE) == 0)
966 break;
967 }
968 } while ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) &&
969 ((status & EOMIRQ_ENABLE) == 0));
970 /*
971 * NOTE: (The above 'while' is coupled w/ previous 'do', way above.) Each
972 * Transparent data buffer has the EOB bit, and NOT the EOM bit, set and
973 * will furthermore have a separate IQD associated with each messages
974 * buffer.
975 */
976
977 FLUSH_MEM_READ();
978 /*
979 * Smooth flow control hysterisis by maintaining task stoppage until half
980 * the available write buffers are available.
981 */
982 if (ch->tx_full && (ch->txd_free >= (ch->txd_num / 2))) {
983 /*
984 * Then, only releave task stoppage if we actually have enough
985 * buffers to service the last requested packet. It may require MORE
986 * than half the available!
987 */
988 if (ch->txd_free >= ch->txd_required) {
989
990#ifdef RLD_TXFULL_DEBUG
991 if (cxt1e1_log_level >= LOG_MONITOR2)
992 pr_info("tx_eom[%d]: enable xmit tx_full no more, txd_free %d txd_num/2 %d\n",
993 ch->channum,
994 ch->txd_free, ch->txd_num / 2);
995#endif
996 ch->tx_full = 0;
997 ch->txd_required = 0;
998 /* re-enable to catch flow controlled channel */
999 sd_enable_xmit(ch->user);
1000 }
1001 }
1002#ifdef RLD_TXFULL_DEBUG
1003 else if (ch->tx_full) {
1004 if (cxt1e1_log_level >= LOG_MONITOR2)
1005 pr_info("tx_eom[%d]: bypass TX enable though room available? (txd_free %d txd_num/2 %d)\n",
1006 ch->channum,
1007 ch->txd_free, ch->txd_num / 2);
1008 }
1009#endif
1010
1011 FLUSH_MEM_WRITE();
1012}
1013
1014
1015static void
1016musycc_bh_rx_eom(mpi_t *pi, int gchan)
1017{
1018 mch_t *ch;
1019 void *m, *m2;
1020 struct mdesc *md;
1021 volatile u_int32_t status;
1022 u_int32_t error;
1023
1024 ch = pi->chan[gchan];
1025 if (!ch || ch->state != UP) {
1026 if (cxt1e1_log_level > LOG_ERROR)
1027 pr_info("%s: intr: receive EOM on uninitialized channel %d\n",
1028 pi->up->devname, gchan);
1029 return;
1030 }
1031 if (!ch->mdr)
1032 return; /* can this happen ? */
1033
1034 for (;;) {
1035 FLUSH_MEM_READ();
1036 md = &ch->mdr[ch->rxix_irq_srv];
1037 status = le32_to_cpu(md->status);
1038 if (!(status & HOST_RX_OWNED))
1039 break; /* Not our mdesc, done */
1040 m = md->mem_token;
1041 error = (status >> 16) & 0xf;
1042 if (error == 0) {
1043 {
1044 m2 = OS_mem_token_alloc(cxt1e1_max_mru);
1045 if (m2) {
1046 /* substitute the mbuf+cluster */
1047 md->mem_token = m2;
1048 md->data = cpu_to_le32(OS_vtophys(
1049 OS_mem_token_data(m2)));
1050
1051 /* pass the received mbuf upward */
1052 sd_recv_consume(m, status & LENGTH_MASK,
1053 ch->user);
1054 ch->s.rx_packets++;
1055 ch->s.rx_bytes += status & LENGTH_MASK;
1056 } else
1057 ch->s.rx_dropped++;
1058 }
1059 } else if (error == ERR_FCS)
1060 ch->s.rx_crc_errors++;
1061 else if (error == ERR_ALIGN)
1062 ch->s.rx_missed_errors++;
1063 else if (error == ERR_ABT)
1064 ch->s.rx_missed_errors++;
1065 else if (error == ERR_LNG)
1066 ch->s.rx_length_errors++;
1067 else if (error == ERR_SHT)
1068 ch->s.rx_length_errors++;
1069 FLUSH_MEM_WRITE();
1070 status = cxt1e1_max_mru;
1071 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1072 status |= EOBIRQ_ENABLE;
1073 md->status = cpu_to_le32(status);
1074
1075 /* Check next mdesc in the ring */
1076 if (++ch->rxix_irq_srv >= ch->rxd_num)
1077 ch->rxix_irq_srv = 0;
1078 FLUSH_MEM_WRITE();
1079 }
1080}
1081
1082
1083irqreturn_t
1084musycc_intr_th_handler(void *devp)
1085{
1086 ci_t *ci = (ci_t *) devp;
1087 volatile u_int32_t status, currInt = 0;
1088 u_int32_t nextInt, intCnt;
1089
1090 /*
1091 * Hardware not available, potential interrupt hang. But since interrupt
1092 * might be shared, just return.
1093 */
1094 if (ci->state == C_INIT)
1095 return IRQ_NONE;
1096 /*
1097 * Marked as hardware available. Don't service interrupts, just clear the
1098 * event.
1099 */
1100
1101 if (ci->state == C_IDLE) {
1102 status = pci_read_32((u_int32_t *) &ci->reg->isd);
1103
1104 /* clear the interrupt but process nothing else */
1105 pci_write_32((u_int32_t *) &ci->reg->isd, status);
1106 return IRQ_HANDLED;
1107 }
1108 FLUSH_PCI_READ();
1109 FLUSH_MEM_READ();
1110
1111 status = pci_read_32((u_int32_t *) &ci->reg->isd);
1112 nextInt = INTRPTS_NEXTINT(status);
1113 intCnt = INTRPTS_INTCNT(status);
1114 ci->intlog.drvr_intr_thcount++;
1115
1116 /*********************************************************/
1117 /* HW Bug Fix */
1118 /* ---------- */
1119 /* Under certain PCI Bus loading conditions, the */
1120 /* MUSYCC looses the data associated with an update */
1121 /* of its ISD and erroneously returns the immediately */
1122 /* preceding 'nextInt' value. However, the 'intCnt' */
1123 /* value appears to be correct. By not starting service */
1124 /* where the 'missing' 'nextInt' SHOULD point causes */
1125 /* the IQD not to be serviced - the 'not serviced' */
1126 /* entries then remain and continue to increase as more */
1127 /* incorrect ISD's are encountered. */
1128 /*********************************************************/
1129
1130 if (nextInt != INTRPTS_NEXTINT(ci->intlog.this_status_new)) {
1131 if (cxt1e1_log_level >= LOG_MONITOR) {
1132 pr_info("%s: note - updated ISD from %08x to %08x\n",
1133 ci->devname, status,
1134 (status & (~INTRPTS_NEXTINT_M)) |
1135 ci->intlog.this_status_new);
1136 }
1137 /*
1138 * Replace bogus status with software corrected value.
1139 *
1140 * It's not known whether, during this problem occurrence, if the
1141 * INTFULL bit is correctly reported or not.
1142 */
1143 status = (status & (~INTRPTS_NEXTINT_M)) |
1144 (ci->intlog.this_status_new);
1145 nextInt = INTRPTS_NEXTINT(status);
1146 }
1147 /**********************************************/
1148 /* Cn847x Bug Fix */
1149 /* -------------- */
1150 /* Fix for inability to write back same index */
1151 /* as read for a full interrupt queue. */
1152 /**********************************************/
1153
1154 if (intCnt == INT_QUEUE_SIZE)
1155 currInt = ((intCnt - 1) + nextInt) & (INT_QUEUE_SIZE - 1);
1156 else
1157 /************************************************/
1158 /* Interrupt Write Location Issues */
1159 /* ------------------------------- */
1160 /* When the interrupt status descriptor is */
1161 /* written, the interrupt line is de-asserted */
1162 /* by the Cn847x. In the case of MIPS */
1163 /* microprocessors, this must occur at the */
1164 /* beginning of the interrupt handler so that */
1165 /* the interrupt handle is not re-entered due */
1166 /* to interrupt dis-assertion latency. */
1167 /* In the case of all other processors, this */
1168 /* action should occur at the end of the */
1169 /* interrupt handler to avoid overwriting the */
1170 /* interrupt queue. */
1171 /************************************************/
1172
1173 if (intCnt)
1174 currInt = (intCnt + nextInt) & (INT_QUEUE_SIZE - 1);
1175 else {
1176 /*
1177 * NOTE: Servicing an interrupt whose ISD contains a count of ZERO
1178 * can be indicative of a Shared Interrupt chain. Our driver can be
1179 * called from the system's interrupt handler as a matter of the OS
1180 * walking the chain. As the chain is walked, the interrupt will
1181 * eventually be serviced by the correct driver/handler.
1182 */
1183 return IRQ_NONE;
1184 }
1185
1186 ci->iqp_tailx = currInt;
1187
1188 currInt <<= INTRPTS_NEXTINT_S;
1189 ci->intlog.last_status_new = ci->intlog.this_status_new;
1190 ci->intlog.this_status_new = currInt;
1191
1192 if ((cxt1e1_log_level >= LOG_WARN) && (status & INTRPTS_INTFULL_M))
1193 pr_info("%s: Interrupt queue full condition occurred\n",
1194 ci->devname);
1195 if (cxt1e1_log_level >= LOG_DEBUG)
1196 pr_info("%s: interrupts pending, isd @ 0x%p: %x curr %d cnt %d NEXT %d\n",
1197 ci->devname, &ci->reg->isd,
1198 status, nextInt, intCnt,
1199 (intCnt + nextInt) & (INT_QUEUE_SIZE - 1));
1200
1201 FLUSH_MEM_WRITE();
1202#if defined(SBE_ISR_TASKLET)
1203 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1204 atomic_inc(&ci->bh_pending);
1205 tasklet_schedule(&ci->ci_musycc_isr_tasklet);
1206#elif defined(SBE_ISR_IMMEDIATE)
1207 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1208 atomic_inc(&ci->bh_pending);
1209 queue_task(&ci->ci_musycc_isr_tq, &tq_immediate);
1210 mark_bh(IMMEDIATE_BH);
1211#elif defined(SBE_ISR_INLINE)
1212 (void) musycc_intr_bh_tasklet(ci);
1213 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1214#endif
1215 return IRQ_HANDLED;
1216}
1217
1218
1219#if defined(SBE_ISR_IMMEDIATE)
1220unsigned long
1221#else
1222void
1223#endif
1224musycc_intr_bh_tasklet(ci_t *ci)
1225{
1226 mpi_t *pi;
1227 mch_t *ch;
1228 unsigned int intCnt;
1229 volatile u_int32_t currInt = 0;
1230 volatile unsigned int headx, tailx;
1231 int readCount, loopCount;
1232 int group, gchan, event, err, tx;
1233 u_int32_t badInt = INT_EMPTY_ENTRY;
1234 u_int32_t badInt2 = INT_EMPTY_ENTRY2;
1235
1236 /*
1237 * Hardware not available, potential interrupt hang. But since interrupt
1238 * might be shared, just return.
1239 */
1240 if ((drvr_state != SBE_DRVR_AVAILABLE) || (ci->state == C_INIT)) {
1241#if defined(SBE_ISR_IMMEDIATE)
1242 return 0L;
1243#else
1244 return;
1245#endif
1246 }
1247#if defined(SBE_ISR_TASKLET) || defined(SBE_ISR_IMMEDIATE)
1248 if (drvr_state != SBE_DRVR_AVAILABLE) {
1249#if defined(SBE_ISR_TASKLET)
1250 return;
1251#elif defined(SBE_ISR_IMMEDIATE)
1252 return 0L;
1253#endif
1254 }
1255#elif defined(SBE_ISR_INLINE)
1256 /* no semaphore taken, no double checks */
1257#endif
1258
1259 ci->intlog.drvr_intr_bhcount++;
1260 FLUSH_MEM_READ();
1261 {
1262 unsigned int bh = atomic_read(&ci->bh_pending);
1263
1264 max_bh = max(bh, max_bh);
1265 }
1266 atomic_set(&ci->bh_pending, 0);/* if here, no longer pending */
1267 while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx)) {
1268 intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
1269 currInt = le32_to_cpu(ci->iqd_p[headx]);
1270
1271 max_intcnt = max(intCnt, max_intcnt); /* RLD DEBUG */
1272
1273 /**************************************************/
1274 /* HW Bug Fix */
1275 /* ---------- */
1276 /* The following code checks for the condition */
1277 /* of interrupt assertion before interrupt */
1278 /* queue update. This is a problem on several */
1279 /* PCI-Local bridge chips found on some products. */
1280 /**************************************************/
1281
1282 readCount = 0;
1283 if ((currInt == badInt) || (currInt == badInt2))
1284 ci->intlog.drvr_int_failure++;
1285
1286 while ((currInt == badInt) || (currInt == badInt2)) {
1287 for (loopCount = 0; loopCount < 0x30; loopCount++)
1288 /* use call to avoid optimization
1289 * removal of dummy delay
1290 */
1291 OS_uwait_dummy();
1292 FLUSH_MEM_READ();
1293 currInt = le32_to_cpu(ci->iqd_p[headx]);
1294 if (readCount++ > 20)
1295 break;
1296 }
1297
1298 /* catch failure of Bug Fix checking */
1299 if ((currInt == badInt) || (currInt == badInt2)) {
1300 if (cxt1e1_log_level >= LOG_WARN)
1301 pr_info("%s: Illegal Interrupt Detected @ 0x%p, mod %d.)\n",
1302 ci->devname, &ci->iqd_p[headx], headx);
1303
1304 /*
1305 * If the descriptor has not recovered, then leaving the EMPTY
1306 * entry set will not signal to the MUSYCC that this descriptor
1307 * has been serviced. The Interrupt Queue can then start losing
1308 * available descriptors and MUSYCC eventually encounters and
1309 * reports the INTFULL condition. Per manual, changing any bit
1310 * marks descriptor as available, thus the use of different
1311 * EMPTY_ENTRY values.
1312 */
1313
1314 if (currInt == badInt)
1315 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY2);
1316 else
1317 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
1318 /* insure wrapness */
1319 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1);
1320 FLUSH_MEM_WRITE();
1321 FLUSH_MEM_READ();
1322 continue;
1323 }
1324 group = INTRPT_GRP(currInt);
1325 gchan = INTRPT_CH(currInt);
1326 event = INTRPT_EVENT(currInt);
1327 err = INTRPT_ERROR(currInt);
1328 tx = currInt & INTRPT_DIR_M;
1329
1330 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
1331 FLUSH_MEM_WRITE();
1332
1333 if (cxt1e1_log_level >= LOG_DEBUG) {
1334 if (err != 0)
1335 pr_info(" %08x -> err: %2d,", currInt, err);
1336
1337 pr_info("+ interrupt event: %d, grp: %d, chan: %2d, side: %cX\n",
1338 event, group, gchan, tx ? 'T' : 'R');
1339 }
1340 /* notice that here we assume 1-1 group - port mapping */
1341 pi = &ci->port[group];
1342 ch = pi->chan[gchan];
1343 switch (event) {
1344 case EVE_SACK: /* Service Request Acknowledge */
1345 if (cxt1e1_log_level >= LOG_DEBUG) {
1346 volatile u_int32_t r;
1347
1348 r = pci_read_32((u_int32_t *) &pi->reg->srd);
1349 pr_info("- SACK cmd: %08x (hdw= %08x)\n",
1350 pi->sr_last, r);
1351 }
1352 /* wake up waiting process */
1353 SD_SEM_GIVE(&pi->sr_sem_wait);
1354 break;
1355 case EVE_CHABT: /* Change To Abort Code (0x7e -> 0xff) */
1356 case EVE_CHIC: /* Change To Idle Code (0xff -> 0x7e) */
1357 break;
1358 case EVE_EOM: /* End Of Message */
1359 case EVE_EOB: /* End Of Buffer (Transparent mode) */
1360 if (tx)
1361 musycc_bh_tx_eom(pi, gchan);
1362 else
1363 musycc_bh_rx_eom(pi, gchan);
1364 /*
1365 * MUSYCC Interrupt Descriptor section states that EOB and EOM
1366 * can be combined with the NONE error (as well as others). So
1367 * drop thru to catch this...
1368 */
1369 case EVE_NONE:
1370 if (err == ERR_SHT)
1371 ch->s.rx_length_errors++;
1372 break;
1373 default:
1374 if (cxt1e1_log_level >= LOG_WARN)
1375 pr_info("%s: unexpected interrupt event: %d, iqd[%d]: %08x, port: %d\n", ci->devname,
1376 event, headx, currInt, group);
1377 break;
1378 } /* switch on event */
1379
1380
1381 /*
1382 * Per MUSYCC Manual, Section 6.4.8.3 [Transmit Errors], TX errors
1383 * are service-affecting and require action to resume normal
1384 * bit-level processing.
1385 */
1386
1387 switch (err) {
1388 case ERR_ONR:
1389 /*
1390 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors], this
1391 * error requires Transmit channel reactivation.
1392 *
1393 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], this error
1394 * requires Receive channel reactivation.
1395 */
1396 if (tx) {
1397
1398 /*
1399 * TX ONR Error only occurs when channel is configured for
1400 * Transparent Mode. However, this code will catch and
1401 * re-activate on ANY TX ONR error.
1402 */
1403
1404 /*
1405 * Set flag to re-enable on any next transmit attempt.
1406 */
1407 ch->ch_start_tx = CH_START_TX_ONR;
1408
1409#ifdef RLD_TRANS_DEBUG
1410 if (1 || cxt1e1_log_level >= LOG_MONITOR)
1411#else
1412 if (cxt1e1_log_level >= LOG_MONITOR)
1413#endif
1414 {
1415 pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
1416 ci->devname, ch->channum,
1417 ch->p.chan_mode,
1418 sd_queue_stopped(ch->user),
1419 ch->txd_free);
1420#ifdef RLD_DEBUG
1421 /* problem = ONR on HDLC mode */
1422 if (ch->p.chan_mode == 2) {
1423 pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
1424 (u_int32_t)ch->txd_irq_srv,
1425 (u_int32_t)ch->txd_usr_add,
1426 sd_queue_stopped(ch->user),
1427 ch->ch_start_tx,
1428 ch->tx_full,
1429 ch->txd_free,
1430 ch->p.chan_mode);
1431 musycc_dump_txbuffer_ring_locked(ch);
1432 }
1433#endif
1434 }
1435 } else { /* RX buffer overrun */
1436 /*
1437 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors],
1438 * channel recovery for this RX ONR error IS required. It is
1439 * also suggested to increase the number of receive buffers
1440 * for this channel. Receive channel reactivation IS
1441 * required, and data has been lost.
1442 */
1443 ch->s.rx_over_errors++;
1444 ch->ch_start_rx = CH_START_RX_ONR;
1445
1446 if (cxt1e1_log_level >= LOG_WARN) {
1447 pr_info("%s: RX buffer overflow [ONR] on channel %d, mode %x\n",
1448 ci->devname, ch->channum,
1449 ch->p.chan_mode);
1450#ifdef RLD_DEBUG
1451 musycc_dump_rxbuffer_ring_locked(ch);
1452#endif
1453 }
1454 }
1455 musycc_chan_restart(ch);
1456 break;
1457 case ERR_BUF:
1458 if (tx) {
1459 ch->s.tx_fifo_errors++;
1460 ch->ch_start_tx = CH_START_TX_BUF;
1461 /*
1462 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors],
1463 * this BUFF error requires Transmit channel reactivation.
1464 */
1465 if (cxt1e1_log_level >= LOG_MONITOR)
1466 pr_info("%s: TX buffer underrun [BUFF] on channel %d, mode %x\n",
1467 ci->devname, ch->channum,
1468 ch->p.chan_mode);
1469 } else { /* RX buffer overrun */
1470 ch->s.rx_over_errors++;
1471 /*
1472 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], HDLC
1473 * mode requires NO recovery for this RX BUFF error is
1474 * required. It is suggested to increase the FIFO buffer
1475 * space for this channel. Receive channel reactivation is
1476 * not required, but data has been lost.
1477 */
1478 if (cxt1e1_log_level >= LOG_WARN)
1479 pr_info("%s: RX buffer overrun [BUFF] on channel %d, mode %x\n",
1480 ci->devname, ch->channum,
1481 ch->p.chan_mode);
1482 /*
1483 * Per MUSYCC manual, Section 6.4.9.4 [Receive Errors],
1484 * Transparent mode DOES require recovery for the RX BUFF
1485 * error. It is suggested to increase the FIFO buffer space
1486 * for this channel. Receive channel reactivation IS
1487 * required and data has been lost.
1488 */
1489 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1490 ch->ch_start_rx = CH_START_RX_BUF;
1491 }
1492
1493 if (tx || (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1494 musycc_chan_restart(ch);
1495 break;
1496 default:
1497 break;
1498 } /* switch on err */
1499
1500 /* Check for interrupt lost condition */
1501 if ((currInt & INTRPT_ILOST_M) &&
1502 (cxt1e1_log_level >= LOG_ERROR))
1503 pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
1504 ci->devname);
1505 /* insure wrapness */
1506 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1);
1507 FLUSH_MEM_WRITE();
1508 FLUSH_MEM_READ();
1509 } /* while */
1510 if ((cxt1e1_log_level >= LOG_MONITOR2) &&
1511 (ci->iqp_headx != ci->iqp_tailx)) {
1512 int bh;
1513
1514 bh = atomic_read(&CI->bh_pending);
1515 pr_info("_bh_: late arrivals, head %d != tail %d, pending %d\n",
1516 ci->iqp_headx, ci->iqp_tailx, bh);
1517 }
1518#if defined(SBE_ISR_IMMEDIATE)
1519 return 0L;
1520#endif
1521 /* else, nothing returned */
1522}
1523
1524#ifdef SBE_PMCC4_ENABLE
1525 status_t
1526musycc_chan_down(ci_t *dummy, int channum)
1527{
1528 mpi_t *pi;
1529 mch_t *ch;
1530 int i, gchan;
1531
1532 ch = sd_find_chan(dummy, channum);
1533 if (!ch)
1534 return -EINVAL;
1535 pi = ch->up;
1536 gchan = ch->gchan;
1537
1538 /* Deactivate the channel */
1539 musycc_serv_req(pi, SR_CHANNEL_DEACTIVATE | SR_RX_DIRECTION | gchan);
1540 ch->ch_start_rx = 0;
1541 musycc_serv_req(pi, SR_CHANNEL_DEACTIVATE | SR_TX_DIRECTION | gchan);
1542 ch->ch_start_tx = 0;
1543
1544 if (ch->state == DOWN)
1545 return 0;
1546 ch->state = DOWN;
1547
1548 pi->regram->thp[gchan] = 0;
1549 pi->regram->tmp[gchan] = 0;
1550 pi->regram->rhp[gchan] = 0;
1551 pi->regram->rmp[gchan] = 0;
1552 FLUSH_MEM_WRITE();
1553 for (i = 0; i < ch->txd_num; i++)
1554 if (ch->mdt[i].mem_token)
1555 OS_mem_token_free(ch->mdt[i].mem_token);
1556
1557 for (i = 0; i < ch->rxd_num; i++)
1558 if (ch->mdr[i].mem_token)
1559 OS_mem_token_free(ch->mdr[i].mem_token);
1560
1561 kfree(ch->mdr);
1562 ch->mdr = NULL;
1563 ch->rxd_num = 0;
1564 kfree(ch->mdt);
1565 ch->mdt = NULL;
1566 ch->txd_num = 0;
1567
1568 musycc_update_timeslots(pi);
1569 c4_fifo_free(pi, ch->gchan);
1570
1571 pi->openchans--;
1572 return 0;
1573}
1574#endif
1575
1576int
1577musycc_start_xmit(ci_t *ci, int channum, void *mem_token)
1578{
1579 mch_t *ch;
1580 struct mdesc *md;
1581 void *m2;
1582 int txd_need_cnt;
1583 u_int32_t len;
1584
1585 ch = sd_find_chan(ci, channum);
1586 if (!ch)
1587 return -ENOENT;
1588
1589 /* full interrupt processing available */
1590 if (ci->state != C_RUNNING)
1591 return -EINVAL;
1592 if (ch->state != UP)
1593 return -EINVAL;
1594
1595 /* how else to flag unwritable state ? */
1596 if (!(ch->status & TX_ENABLED))
1597 return -EROFS;
1598
1599#ifdef RLD_TRANS_DEBUG
1600 if (1 || cxt1e1_log_level >= LOG_MONITOR2)
1601#else
1602 if (cxt1e1_log_level >= LOG_MONITOR2)
1603#endif
1604 {
1605 pr_info("++ start_xmt[%d]: state %x start %x full %d free %d required %d stopped %x\n",
1606 channum, ch->state, ch->ch_start_tx, ch->tx_full,
1607 ch->txd_free, ch->txd_required,
1608 sd_queue_stopped(ch->user));
1609 }
1610 /***********************************************/
1611 /** Determine total amount of data to be sent **/
1612 /***********************************************/
1613 m2 = mem_token;
1614 txd_need_cnt = 0;
1615 for (len = OS_mem_token_tlen(m2); len > 0;
1616 m2 = (void *) OS_mem_token_next(m2)) {
1617 if (!OS_mem_token_len(m2))
1618 continue;
1619 txd_need_cnt++;
1620 len -= OS_mem_token_len(m2);
1621 }
1622
1623 if (txd_need_cnt == 0) {
1624 if (cxt1e1_log_level >= LOG_MONITOR2)
1625 pr_info("%s channel %d: no TX data in User buffer\n",
1626 ci->devname, channum);
1627 OS_mem_token_free(mem_token);
1628 return 0; /* no data to send */
1629 }
1630 /*************************************************/
1631 /** Are there sufficient descriptors available? **/
1632 /*************************************************/
1633 if (txd_need_cnt > ch->txd_num) { /* never enough descriptors for this
1634 * large a buffer */
1635 if (cxt1e1_log_level >= LOG_DEBUG)
1636 pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
1637 ch->txd_num, txd_need_cnt + 1);
1638 ch->s.tx_dropped++;
1639 OS_mem_token_free(mem_token);
1640 return 0;
1641 }
1642
1643 /************************************************************/
1644 /** flow control the line if not enough descriptors remain **/
1645 /************************************************************/
1646 if (txd_need_cnt > ch->txd_free) {
1647 if (cxt1e1_log_level >= LOG_MONITOR2)
1648 pr_info("start_xmit[%d]: EBUSY - need more descriptors, have %d of %d need %d\n",
1649 channum, ch->txd_free,
1650 ch->txd_num, txd_need_cnt);
1651 ch->tx_full = 1;
1652 ch->txd_required = txd_need_cnt;
1653 sd_disable_xmit(ch->user);
1654 return -EBUSY; /* tell user to try again later */
1655 }
1656 /**************************************************/
1657 /** Put the user data into MUSYCC data buffer(s) **/
1658 /**************************************************/
1659 m2 = mem_token;
1660 md = ch->txd_usr_add; /* get current available descriptor */
1661
1662 for (len = OS_mem_token_tlen(m2); len > 0; m2 = OS_mem_token_next(m2)) {
1663 int u = OS_mem_token_len(m2);
1664
1665 if (!u)
1666 continue;
1667 len -= u;
1668
1669 /*
1670 * Enable following chunks, yet wait to enable the FIRST chunk until
1671 * after ALL subsequent chunks are setup.
1672 */
1673 if (md != ch->txd_usr_add) /* not first chunk */
1674 /* transfer ownership from HOST to MUSYCC */
1675 u |= MUSYCC_TX_OWNED;
1676
1677 if (len) /* not last chunk */
1678 u |= EOBIRQ_ENABLE;
1679 else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS) {
1680 /*
1681 * Per MUSYCC Ref 6.4.9 for Transparent Mode, the host must
1682 * always clear EOMIRQ_ENABLE in every Transmit Buffer Descriptor
1683 * (IE. don't set herein).
1684 */
1685 u |= EOBIRQ_ENABLE;
1686 } else
1687 u |= EOMIRQ_ENABLE; /* EOM, last HDLC chunk */
1688
1689
1690 /* last chunk in hdlc mode */
1691 u |= (ch->p.idlecode << IDLE_CODE);
1692 if (ch->p.pad_fill_count) {
1693 u |= (PADFILL_ENABLE | (ch->p.pad_fill_count << EXTRA_FLAGS));
1694 }
1695 /* Fill in mds on last segment, others set ZERO
1696 * so that entire token is removed ONLY when ALL
1697 * segments have been transmitted.
1698 */
1699 md->mem_token = len ? NULL : mem_token;
1700
1701 md->data = cpu_to_le32(OS_vtophys(OS_mem_token_data(m2)));
1702 FLUSH_MEM_WRITE();
1703 md->status = cpu_to_le32(u);
1704 --ch->txd_free;
1705 md = md->snext;
1706 }
1707 FLUSH_MEM_WRITE();
1708
1709
1710 /*
1711 * Now transfer ownership of first chunk from HOST to MUSYCC in order to
1712 * fire-off this XMIT.
1713 */
1714 ch->txd_usr_add->status |= __constant_cpu_to_le32(MUSYCC_TX_OWNED);
1715 FLUSH_MEM_WRITE();
1716 ch->txd_usr_add = md;
1717
1718 len = OS_mem_token_tlen(mem_token);
1719 atomic_add(len, &ch->tx_pending);
1720 atomic_add(len, &ci->tx_pending);
1721 ch->s.tx_packets++;
1722 ch->s.tx_bytes += len;
1723 /*
1724 * If an ONR was seen, then channel requires poking to restart
1725 * transmission.
1726 */
1727 if (ch->ch_start_tx)
1728 musycc_chan_restart(ch);
1729#ifdef SBE_WAN256T3_ENABLE
1730 wan256t3_led(ci, LED_TX, LEDV_G);
1731#endif
1732 return 0;
1733}
1734
1735
1736/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/musycc.h b/drivers/staging/cxt1e1/musycc.h
deleted file mode 100644
index 56fb42f0f64e..000000000000
--- a/drivers/staging/cxt1e1/musycc.h
+++ /dev/null
@@ -1,427 +0,0 @@
1#ifndef _INC_MUSYCC_H_
2#define _INC_MUSYCC_H_
3
4/*-----------------------------------------------------------------------------
5 * musycc.h - Multichannel Synchronous Communications Controller
6 * CN8778/8474A/8472A/8471A
7 *
8 * Copyright (C) 2002-2005 SBE, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * For further information, contact via email: support@sbei.com
21 * SBE, Inc. San Ramon, California U.S.A.
22 *-----------------------------------------------------------------------------
23 */
24
25#include <linux/types.h>
26
27#define VINT8 volatile u_int8_t
28#define VINT32 volatile u_int32_t
29
30#include "pmcc4_defs.h"
31
32
33/*------------------------------------------------------------------------
34// Vendor, Board Identification definitions
35//------------------------------------------------------------------------
36*/
37
38#define PCI_VENDOR_ID_CONEXANT 0x14f1
39#define PCI_DEVICE_ID_CN8471 0x8471
40#define PCI_DEVICE_ID_CN8472 0x8472
41#define PCI_DEVICE_ID_CN8474 0x8474
42#define PCI_DEVICE_ID_CN8478 0x8478
43#define PCI_DEVICE_ID_CN8500 0x8500
44#define PCI_DEVICE_ID_CN8501 0x8501
45#define PCI_DEVICE_ID_CN8502 0x8502
46#define PCI_DEVICE_ID_CN8503 0x8503
47
48#define INT_QUEUE_SIZE MUSYCC_NIQD
49
50/* RAM image of MUSYCC registers laid out as a C structure */
51struct musycc_groupr {
52 VINT32 thp[32]; /* Transmit Head Pointer [5-29] */
53 VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */
54 VINT32 rhp[32]; /* Receive Head Pointer [5-29] */
55 VINT32 rmp[32]; /* Receive Message Pointer [5-30] */
56 VINT8 ttsm[128]; /* Time Slot Map [5-22] */
57 VINT8 tscm[256]; /* Subchannel Map [5-24] */
58 VINT32 tcct[32]; /* Channel Configuration [5-26] */
59 VINT8 rtsm[128]; /* Time Slot Map [5-22] */
60 VINT8 rscm[256]; /* Subchannel Map [5-24] */
61 VINT32 rcct[32]; /* Channel Configuration [5-26] */
62 VINT32 __glcd; /* Global Configuration Descriptor [5-10] */
63 VINT32 __iqp; /* Interrupt Queue Pointer [5-36] */
64 VINT32 __iql; /* Interrupt Queue Length [5-36] */
65 VINT32 grcd; /* Group Configuration Descriptor [5-16] */
66 VINT32 mpd; /* Memory Protection Descriptor [5-18] */
67 VINT32 mld; /* Message Length Descriptor [5-20] */
68 VINT32 pcd; /* Port Configuration Descriptor [5-19] */
69};
70
71/* hardware MUSYCC registers laid out as a C structure */
72struct musycc_globalr {
73 VINT32 gbp; /* Group Base Pointer */
74 VINT32 dacbp; /* Dual Address Cycle Base Pointer */
75 VINT32 srd; /* Service Request Descriptor */
76 VINT32 isd; /* Interrupt Service Descriptor */
77 /*
78 * adjust __thp due to above 4 registers, which are not contained
79 * within musycc_groupr[]. All __XXX[] are just place holders,
80 * anyhow.
81 */
82 VINT32 __thp[32 - 4]; /* Transmit Head Pointer [5-29] */
83 VINT32 __tmp[32]; /* Transmit Message Pointer [5-30] */
84 VINT32 __rhp[32]; /* Receive Head Pointer [5-29] */
85 VINT32 __rmp[32]; /* Receive Message Pointer [5-30] */
86 VINT8 ttsm[128]; /* Time Slot Map [5-22] */
87 VINT8 tscm[256]; /* Subchannel Map [5-24] */
88 VINT32 tcct[32]; /* Channel Configuration [5-26] */
89 VINT8 rtsm[128]; /* Time Slot Map [5-22] */
90 VINT8 rscm[256]; /* Subchannel Map [5-24] */
91 VINT32 rcct[32]; /* Channel Configuration [5-26] */
92 VINT32 glcd; /* Global Configuration Descriptor [5-10] */
93 VINT32 iqp; /* Interrupt Queue Pointer [5-36] */
94 VINT32 iql; /* Interrupt Queue Length [5-36] */
95 VINT32 grcd; /* Group Configuration Descriptor [5-16] */
96 VINT32 mpd; /* Memory Protection Descriptor [5-18] */
97 VINT32 mld; /* Message Length Descriptor [5-20] */
98 VINT32 pcd; /* Port Configuration Descriptor [5-19] */
99 VINT32 rbist; /* Receive BIST status [5-4] */
100 VINT32 tbist; /* Receive BIST status [5-4] */
101};
102
103/* Global Config Descriptor bit macros */
104#define MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */
105#define MUSYCC_GCD_INTEL_SELECT 0x00000400 /* MPU type select */
106#define MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */
107#define MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */
108#define MUSYCC_GCD_BLAPSE 12 /* Position index for BLAPSE bit
109 * field */
110#define MUSYCC_GCD_ALAPSE 8 /* Position index for ALAPSE bit
111 * field */
112#define MUSYCC_GCD_ELAPSE 4 /* Position index for ELAPSE bit
113 * field */
114#define MUSYCC_GCD_PORTMAP_3 3 /* Reserved */
115#define MUSYCC_GCD_PORTMAP_2 2 /* Port 0=>Grp 0,1,2,3; Port 1=>Grp
116 * 4,5,6,7 */
117#define MUSYCC_GCD_PORTMAP_1 1 /* Port 0=>Grp 0,1; Port 1=>Grp 2,3,
118 * etc... */
119#define MUSYCC_GCD_PORTMAP_0 0 /* Port 0=>Grp 0; Port 1=>Grp 2,
120 * etc... */
121
122/* and board specific assignments... */
123#ifdef SBE_WAN256T3_ENABLE
124#define BLAPSE_VAL 0
125#define ALAPSE_VAL 0
126#define ELAPSE_VAL 7
127#define PORTMAP_VAL MUSYCC_GCD_PORTMAP_2
128#endif
129
130#ifdef SBE_PMCC4_ENABLE
131#define BLAPSE_VAL 7
132#define ALAPSE_VAL 3
133#define ELAPSE_VAL 7
134#define PORTMAP_VAL MUSYCC_GCD_PORTMAP_0
135#endif
136
137#define GCD_MAGIC (((BLAPSE_VAL)<<(MUSYCC_GCD_BLAPSE)) | \
138 ((ALAPSE_VAL)<<(MUSYCC_GCD_ALAPSE)) | \
139 ((ELAPSE_VAL)<<(MUSYCC_GCD_ELAPSE)) | \
140 (MUSYCC_GCD_ECLK_ENABLE) | PORTMAP_VAL)
141
142/* Group Config Descriptor bit macros */
143#define MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */
144#define MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */
145#define MUSYCC_GRCD_SUBCHAN_DISABLE 0x00000004 /* Master disable for
146 * subchanneling */
147#define MUSYCC_GRCD_OOFMP_DISABLE 0x00000008 /* Out of Frame message
148 * processing disabled all
149 * channels */
150#define MUSYCC_GRCD_OOFIRQ_DISABLE 0x00000010 /* Out of Frame/In Frame irqs
151 * disabled */
152#define MUSYCC_GRCD_COFAIRQ_DISABLE 0x00000020 /* Change of Frame Alignment
153 * irq disabled */
154#define MUSYCC_GRCD_INHRBSD 0x00000100 /* Receive Buffer Status
155 * overwrite disabled */
156#define MUSYCC_GRCD_INHTBSD 0x00000200 /* Transmit Buffer Status
157 * overwrite disabled */
158#define MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */
159#define MUSYCC_GRCD_MC_ENABLE 0x00000040 /* Message configuration bits
160 * copy enable. Conexant sez
161 * turn this on */
162#define MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */
163#define MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */
164#define MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */
165#define MUSYCC_GRCD_POLLTH_SHIFT 10 /* Position index for poll throttle
166 * bit field */
167#define MUSYCC_GRCD_SUERM_THRESH_SHIFT 16 /* Position index for SUERM
168 * count threshold */
169
170/* Port Config Descriptor bit macros */
171#define MUSYCC_PCD_E1X2_MODE 2 /* Port mode in bits 0-2. T1 and E1 */
172#define MUSYCC_PCD_E1X4_MODE 3 /* are defined in cn847x.h */
173#define MUSYCC_PCD_NX64_MODE 4
174#define MUSYCC_PCD_TXDATA_RISING 0x00000010 /* Sample Tx data on TCLK
175 * rising edge */
176#define MUSYCC_PCD_TXSYNC_RISING 0x00000020 /* Sample Tx frame sync on
177 * TCLK rising edge */
178#define MUSYCC_PCD_RXDATA_RISING 0x00000040 /* Sample Rx data on RCLK
179 * rising edge */
180#define MUSYCC_PCD_RXSYNC_RISING 0x00000080 /* Sample Rx frame sync on
181 * RCLK rising edge */
182#define MUSYCC_PCD_ROOF_RISING 0x00000100 /* Sample Rx Out Of Frame
183 * signal on RCLK rising edge */
184#define MUSYCC_PCD_TX_DRIVEN 0x00000200 /* No mapped timeslots causes
185 * logic 1 on output, else
186 * tristate */
187#define MUSYCC_PCD_PORTMODE_MASK 0xfffffff8 /* For changing the port mode
188 * between E1 and T1 */
189
190/* Time Slot Descriptor bit macros */
191#define MUSYCC_TSD_MODE_64KBPS 4
192#define MUSYCC_TSD_MODE_56KBPS 5
193#define MUSYCC_TSD_SUBCHANNEL_WO_FIRST 6
194#define MUSYCC_TSD_SUBCHANNEL_WITH_FIRST 7
195
196/* Message Descriptor bit macros */
197#define MUSYCC_MDT_BASE03_ADDR 0x00006000
198
199/* Channel Config Descriptor bit macros */
200#define MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */
201#define MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */
202#define MUSYCC_CCD_MSGIRQ_DISABLE 0x00000008 /* LNG, FCS, ALIGN, and ABT
203 * irqs disabled */
204#define MUSYCC_CCD_IDLEIRQ_DISABLE 0x00000010 /* CHABT, CHIC, and SHT irqs
205 * disabled */
206#define MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */
207#define MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */
208#define MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */
209#define MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */
210#define MUSYCC_CCD_FCS_XFER 0x00000200 /* Propagate FCS along with
211 * received data */
212#define MUSYCC_CCD_PROTO_SHIFT 12 /* Position index for protocol bit
213 * field */
214#define MUSYCC_CCD_TRANS 0 /* Protocol mode in bits 12-14 */
215#define MUSYCC_CCD_SS7 1
216#define MUSYCC_CCD_HDLC_FCS16 2
217#define MUSYCC_CCD_HDLC_FCS32 3
218#define MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */
219#define MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */
220#define MUSYCC_CCD_MAX_LENGTH 10 /* Position index for max length bit
221 * field */
222#define MUSYCC_CCD_BUFFER_LENGTH 16 /* Position index for internal data
223 * buffer length */
224#define MUSYCC_CCD_BUFFER_LOC 24 /* Position index for internal data
225 * buffer starting location */
226
227/****************************************************************************
228 * Interrupt Descriptor Information */
229
230#define INT_EMPTY_ENTRY 0xfeedface
231#define INT_EMPTY_ENTRY2 0xdeadface
232
233/****************************************************************************
234 * Interrupt Status Descriptor
235 *
236 * NOTE: One must first fetch the value of the interrupt status descriptor
237 * into a local variable, then pass that value into the read macros. This
238 * is required to avoid race conditions.
239 ***/
240
241#define INTRPTS_NEXTINT_M 0x7FFF0000
242#define INTRPTS_NEXTINT_S 16
243#define INTRPTS_NEXTINT(x) ((x & INTRPTS_NEXTINT_M) >> INTRPTS_NEXTINT_S)
244
245#define INTRPTS_INTFULL_M 0x00008000
246#define INTRPTS_INTFULL_S 15
247#define INTRPTS_INTFULL(x) ((x & INTRPTS_INTFULL_M) >> INTRPTS_INTFULL_S)
248
249#define INTRPTS_INTCNT_M 0x00007FFF
250#define INTRPTS_INTCNT_S 0
251#define INTRPTS_INTCNT(x) ((x & INTRPTS_INTCNT_M) >> INTRPTS_INTCNT_S)
252
253
254/****************************************************************************
255 * Interrupt Descriptor
256 ***/
257
258#define INTRPT_DIR_M 0x80000000
259#define INTRPT_DIR_S 31
260#define INTRPT_DIR(x) ((x & INTRPT_DIR_M) >> INTRPT_DIR_S)
261
262#define INTRPT_GRP_M 0x60000000
263#define INTRPT_GRP_MSB_M 0x00004000
264#define INTRPT_GRP_S 29
265#define INTRPT_GRP_MSB_S 12
266#define INTRPT_GRP(x) (((x & INTRPT_GRP_M) >> INTRPT_GRP_S) | \
267 ((x & INTRPT_GRP_MSB_M) >> INTRPT_GRP_MSB_S))
268
269#define INTRPT_CH_M 0x1F000000
270#define INTRPT_CH_S 24
271#define INTRPT_CH(x) ((x & INTRPT_CH_M) >> INTRPT_CH_S)
272
273#define INTRPT_EVENT_M 0x00F00000
274#define INTRPT_EVENT_S 20
275#define INTRPT_EVENT(x) ((x & INTRPT_EVENT_M) >> INTRPT_EVENT_S)
276
277#define INTRPT_ERROR_M 0x000F0000
278#define INTRPT_ERROR_S 16
279#define INTRPT_ERROR(x) ((x & INTRPT_ERROR_M) >> INTRPT_ERROR_S)
280
281#define INTRPT_ILOST_M 0x00008000
282#define INTRPT_ILOST_S 15
283#define INTRPT_ILOST(x) ((x & INTRPT_ILOST_M) >> INTRPT_ILOST_S)
284
285#define INTRPT_PERR_M 0x00004000
286#define INTRPT_PERR_S 14
287#define INTRPT_PERR(x) ((x & INTRPT_PERR_M) >> INTRPT_PERR_S)
288
289#define INTRPT_BLEN_M 0x00003FFF
290#define INTRPT_BLEN_S 0
291#define INTRPT_BLEN(x) ((x & INTRPT_BLEN_M) >> INTRPT_BLEN_S)
292
293
294/* Buffer Descriptor bit macros */
295#define OWNER_BIT 0x80000000 /* Set for MUSYCC owner on xmit, host
296 * owner on receive */
297#define HOST_TX_OWNED 0x00000000 /* Host owns descriptor */
298#define MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */
299#define HOST_RX_OWNED 0x80000000 /* Host owns descriptor */
300#define MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */
301
302#define POLL_DISABLED 0x40000000 /* MUSYCC not allowed to poll buffer
303 * for ownership */
304#define EOMIRQ_ENABLE 0x20000000 /* This buffer contains the end of
305 * the message */
306#define EOBIRQ_ENABLE 0x10000000 /* EOB irq enabled */
307#define PADFILL_ENABLE 0x01000000 /* Enable padfill */
308#define REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */
309#define LENGTH_MASK 0X3fff /* This part of status descriptor is
310 * length */
311#define IDLE_CODE 25 /* Position index for idle code (2
312 * bits) */
313#define EXTRA_FLAGS 16 /* Position index for minimum flags
314 * between messages (8 bits) */
315#define IDLE_CODE_MASK 0x03 /* Gets rid of garbage before the
316 * pattern is OR'd in */
317#define EXTRA_FLAGS_MASK 0xff /* Gets rid of garbage before the
318 * pattern is OR'd in */
319#define PCI_PERMUTED_OWNER_BIT 0x00000080 /* For flipping the bit on
320 * the polled mode descriptor */
321
322/* Service Request Descriptor bit macros */
323#define SREQ 8 /* Position index for service request bit
324 * field */
325#define SR_NOOP (0<<(SREQ)) /* No Operation. Generates SACK */
326#define SR_CHIP_RESET (1<<(SREQ)) /* Soft chip reset */
327#define SR_GROUP_RESET (2<<(SREQ)) /* Group reset */
328#define SR_GLOBAL_INIT (4<<(SREQ)) /* Global init: read global
329 * config deswc and interrupt
330 * queue desc */
331#define SR_GROUP_INIT (5<<(SREQ)) /* Group init: read Timeslot
332 * and Subchannel maps,
333 * Channel Config, */
334 /*
335 * Group Config, Memory Protect, Message Length, and Port Config
336 * Descriptors
337 */
338#define SR_CHANNEL_ACTIVATE (8<<(SREQ)) /* Init channel, read Head
339 * Pointer, process first
340 * Message Descriptor */
341#define SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */
342#define SR_CHANNEL_DEACTIVATE (9<<(SREQ)) /* Stop channel processing */
343#define SR_JUMP (10<<(SREQ)) /* a: Process new Message
344 * List */
345#define SR_CHANNEL_CONFIG (11<<(SREQ)) /* b: Read channel
346 * Configuration Descriptor */
347#define SR_GLOBAL_CONFIG (16<<(SREQ)) /* 10: Read Global
348 * Configuration Descriptor */
349#define SR_INTERRUPT_Q (17<<(SREQ)) /* 11: Read Interrupt Queue
350 * Descriptor */
351#define SR_GROUP_CONFIG (18<<(SREQ)) /* 12: Read Group
352 * Configuration Descriptor */
353#define SR_MEMORY_PROTECT (19<<(SREQ)) /* 13: Read Memory Protection
354 * Descriptor */
355#define SR_MESSAGE_LENGTH (20<<(SREQ)) /* 14: Read Message Length
356 * Descriptor */
357#define SR_PORT_CONFIG (21<<(SREQ)) /* 15: Read Port
358 * Configuration Descriptor */
359#define SR_TIMESLOT_MAP (24<<(SREQ)) /* 18: Read Timeslot Map */
360#define SR_SUBCHANNEL_MAP (25<<(SREQ)) /* 19: Read Subchannel Map */
361#define SR_CHAN_CONFIG_TABLE (26<<(SREQ)) /* 20: Read Channel
362 * Configuration Table for
363 * the group */
364#define SR_TX_DIRECTION 0x00000020 /* Transmit direction bit.
365 * Bit off indicates receive
366 * direction */
367#define SR_RX_DIRECTION 0x00000000
368
369/* Interrupt Descriptor bit macros */
370#define GROUP10 29 /* Position index for the 2 LS group
371 * bits */
372#define CHANNEL 24 /* Position index for channel bits */
373#define INT_IQD_TX 0x80000000
374#define INT_IQD_GRP 0x60000000
375#define INT_IQD_CHAN 0x1f000000
376#define INT_IQD_EVENT 0x00f00000
377#define INT_IQD_ERROR 0x000f0000
378#define INT_IQD_ILOST 0x00008000
379#define INT_IQD_PERR 0x00004000
380#define INT_IQD_BLEN 0x00003fff
381
382/* Interrupt Descriptor Events */
383#define EVE_EVENT 20 /* Position index for event bits */
384#define EVE_NONE 0 /* No event to report in this
385 * interrupt */
386#define EVE_SACK 1 /* Service Request acknowledge */
387#define EVE_EOB 2 /* End of Buffer */
388#define EVE_EOM 3 /* End of Message */
389#define EVE_EOP 4 /* End of Padfill */
390#define EVE_CHABT 5 /* Change to Abort Code */
391#define EVE_CHIC 6 /* Change to Idle Code */
392#define EVE_FREC 7 /* Frame Recovery */
393#define EVE_SINC 8 /* MTP2 SUERM Increment */
394#define EVE_SDEC 9 /* MTP2 SUERM Decrement */
395#define EVE_SFILT 10 /* MTP2 SUERM Filtered Message */
396/* Interrupt Descriptor Errors */
397#define ERR_ERRORS 16 /* Position index for error bits */
398#define ERR_BUF 1 /* Buffer Error */
399#define ERR_COFA 2 /* Change of Frame Alignment Error */
400#define ERR_ONR 3 /* Owner Bit Error */
401#define ERR_PROT 4 /* Memory Protection Error */
402#define ERR_OOF 8 /* Out of Frame Error */
403#define ERR_FCS 9 /* FCS Error */
404#define ERR_ALIGN 10 /* Octet Alignment Error */
405#define ERR_ABT 11 /* Abort Termination */
406#define ERR_LNG 12 /* Long Message Error */
407#define ERR_SHT 13 /* Short Message Error */
408#define ERR_SUERR 14 /* SUERM threshold exceeded */
409#define ERR_PERR 15 /* PCI Parity Error */
410/* Other Stuff */
411#define TRANSMIT_DIRECTION 0x80000000 /* Transmit direction bit. Bit off
412 * indicates receive direction */
413#define ILOST 0x00008000 /* Interrupt Lost */
414#define GROUPMSB 0x00004000 /* Group number MSB */
415#define SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */
416#define INITIAL_STATUS 0x10000 /* IRQ status should be this after
417 * reset */
418
419/* This must be defined on an entire channel group (Port) basis */
420#define SUERM_THRESHOLD 0x1f
421
422#undef VINT32
423#undef VINT8
424
425#endif /*** _INC_MUSYCC_H_ ***/
426
427/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/pmc93x6_eeprom.c b/drivers/staging/cxt1e1/pmc93x6_eeprom.c
deleted file mode 100644
index ba588f1b2110..000000000000
--- a/drivers/staging/cxt1e1/pmc93x6_eeprom.c
+++ /dev/null
@@ -1,532 +0,0 @@
1/* pmc93x6_eeprom.c - PMC's 93LC46 EEPROM Device
2 *
3 * The 93LC46 is a low-power, serial Electrically Erasable and
4 * Programmable Read Only Memory organized as 128 8-bit bytes.
5 *
6 * Accesses to the 93LC46 are done in a bit serial stream, organized
7 * in a 3 wire format. Writes are internally timed by the device
8 * (the In data bit is pulled low until the write is complete and
9 * then is pulled high) and take about 6 milliseconds.
10 *
11 * Copyright (C) 2003-2005 SBE, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/types.h>
27#include "pmcc4_sysdep.h"
28#include "sbecom_inline_linux.h"
29#include "pmcc4.h"
30#include "sbe_promformat.h"
31#include "pmc93x6_eeprom.h"
32
33#ifndef TRUE
34#define TRUE 1
35#define FALSE 0
36#endif
37
38/*------------------------------------------------------------------------
39 * EEPROM address definitions
40 *------------------------------------------------------------------------
41 *
42 * The offset in the definitions below allows the test to skip over
43 * areas of the EEPROM that other programs (such a VxWorks) are
44 * using.
45 */
46
47#define EE_MFG (long)0 /* Index to manufacturing record */
48#define EE_FIRST 0x28 /* Index to start testing at */
49#define EE_LIMIT 128 /* Index to end testing at */
50
51/* Bit Ordering for Instructions
52 *
53 * A0, A1, A2, A3, A4, A5, A6, OP0, OP1, SB (lsb, or 1st bit out)
54 *
55 */
56
57#define EPROM_EWEN 0x0019 /* Erase/Write enable (reversed) */
58#define EPROM_EWDS 0x0001 /* Erase/Write disable (reversed) */
59#define EPROM_READ 0x0003 /* Read (reversed) */
60#define EPROM_WRITE 0x0005 /* Write (reversed) */
61#define EPROM_ERASE 0x0007 /* Erase (reversed) */
62#define EPROM_ERAL 0x0009 /* Erase All (reversed) */
63#define EPROM_WRAL 0x0011 /* Write All (reversed) */
64
65#define EPROM_ADR_SZ 7 /* Number of bits in offset address */
66#define EPROM_OP_SZ 3 /* Number of bits in command */
67#define SIZE_ADDR_OP (EPROM_ADR_SZ + EPROM_OP_SZ)
68#define LC46A_MAX_OPS 10 /* Number of bits in Instruction */
69#define NUM_OF_BITS 8 /* Number of bits in data */
70
71/* EEPROM signal bits */
72#define EPROM_ACTIVE_OUT_BIT 0x0001 /* Out data bit */
73#define EPROM_ACTIVE_IN_BIT 0x0002 /* In data bit */
74#define ACTIVE_IN_BIT_SHIFT 0x0001 /* Shift In data bit to LSB */
75#define EPROM_ENCS 0x0004 /* Set EEPROM CS during operation */
76
77/*------------------------------------------------------------------------
78 * The ByteReverse table is used to reverses the 8 bits within a byte
79 *------------------------------------------------------------------------
80 */
81
82static unsigned char ByteReverse[256];
83static int ByteReverseBuilt = FALSE;
84
85/*------------------------------------------------------------------------
86 * mfg_template - initial serial EEPROM data structure
87 *------------------------------------------------------------------------
88 */
89
90static u8 mfg_template[sizeof(FLD_TYPE2)] = {
91 PROM_FORMAT_TYPE2, /* type; */
92 0x00, 0x1A, /* length[2]; */
93 0x00, 0x00, 0x00, 0x00, /* Crc32[4]; */
94 0x11, 0x76, /* Id[2]; */
95 0x07, 0x05, /* SubId[2] E1; */
96 0x00, 0xA0, 0xD6, 0x00, 0x00, 0x00, /* Serial[6]; */
97 0x00, 0x00, 0x00, 0x00, /* CreateTime[4]; */
98 0x00, 0x00, 0x00, 0x00, /* HeatRunTime[4]; */
99 0x00, 0x00, 0x00, 0x00, /* HeatRunIterations[4]; */
100 0x00, 0x00, 0x00, 0x00, /* HeatRunErrors[4]; */
101};
102
103/*------------------------------------------------------------------------
104 * BuildByteReverse - build the 8-bit reverse table
105 *------------------------------------------------------------------------
106 *
107 * The 'ByteReverse' table reverses the 8 bits within a byte
108 * (the MSB becomes the LSB etc.).
109 */
110
111static void BuildByteReverse(void)
112{
113 /* Used to build by powers to 2 */
114 long half;
115 int i;
116
117 ByteReverse[0] = 0;
118
119 for (half = 1; half < sizeof(ByteReverse); half <<= 1)
120 for (i = 0; i < half; i++)
121 ByteReverse[half + i] =
122 (char)(ByteReverse[i] | (0x80 / half));
123
124 ByteReverseBuilt = TRUE;
125}
126
127/*------------------------------------------------------------------------
128 * eeprom_delay - small delay for EEPROM timing
129 *------------------------------------------------------------------------
130 */
131
132static void eeprom_delay(void)
133{
134 int timeout;
135
136 for (timeout = 20; timeout; --timeout)
137 OS_uwait_dummy();
138}
139
140/*------------------------------------------------------------------------
141 * eeprom_put_byte - Send a byte to the EEPROM serially
142 *------------------------------------------------------------------------
143 *
144 * Given the PCI address and the data, this routine serially sends
145 * the data to the EEPROM.
146 */
147
148static void eeprom_put_byte(long addr, long data, int count)
149{
150 u_int32_t output;
151
152 while (--count >= 0) {
153 /* Get next data bit */
154 output = (data & EPROM_ACTIVE_OUT_BIT) ? 1 : 0;
155 /* Add Chip Select */
156 output |= EPROM_ENCS;
157 data >>= 1;
158
159 eeprom_delay();
160 /* Output it */
161 pci_write_32((u_int32_t *) addr, output);
162 }
163}
164
165/*------------------------------------------------------------------------
166 * eeprom_get_byte - Receive a byte from the EEPROM serially
167 *------------------------------------------------------------------------
168 *
169 * Given the PCI address, this routine serially fetches the data
170 * from the EEPROM.
171 */
172
173static u_int32_t eeprom_get_byte(long addr)
174{
175 u_int32_t input;
176 u_int32_t data;
177 int count;
178
179/* Start the Reading of DATA
180 *
181 * The first read is a dummy as the data is latched in the
182 * EPLD and read on the next read access to the EEPROM.
183 */
184
185 input = pci_read_32((u_int32_t *) addr);
186
187 data = 0;
188 count = NUM_OF_BITS;
189 while (--count >= 0) {
190 eeprom_delay();
191 input = pci_read_32((u_int32_t *) addr);
192
193 /* Shift data over */
194 data <<= 1;
195 data |= (input & EPROM_ACTIVE_IN_BIT) ? 1 : 0;
196
197 }
198
199 return data;
200}
201
202/*------------------------------------------------------------------------
203 * disable_pmc_eeprom - Disable writes to the EEPROM
204 *------------------------------------------------------------------------
205 *
206 * Issue the EEPROM command to disable writes.
207 */
208
209static void disable_pmc_eeprom(long addr)
210{
211 eeprom_put_byte(addr, EPROM_EWDS, SIZE_ADDR_OP);
212
213 /* this removes Chip Select from EEPROM */
214 pci_write_32((u_int32_t *) addr, 0);
215}
216
217/*------------------------------------------------------------------------
218 * enable_pmc_eeprom - Enable writes to the EEPROM
219 *------------------------------------------------------------------------
220 *
221 * Issue the EEPROM command to enable writes.
222 */
223
224static void enable_pmc_eeprom(long addr)
225{
226 eeprom_put_byte(addr, EPROM_EWEN, SIZE_ADDR_OP);
227
228 /* this removes Chip Select from EEPROM */
229 pci_write_32((u_int32_t *) addr, 0);
230}
231
232/*------------------------------------------------------------------------
233 * pmc_eeprom_read - EEPROM location read
234 *------------------------------------------------------------------------
235 *
236 * Given a EEPROM PCI address and location offset, this routine returns
237 * the contents of the specified location to the calling routine.
238 */
239
240static u_int32_t pmc_eeprom_read(long addr, long mem_offset)
241{
242 /* Data from chip */
243 u_int32_t data;
244
245 if (!ByteReverseBuilt)
246 BuildByteReverse();
247
248 /* Reverse address */
249 mem_offset = ByteReverse[0x7F & mem_offset];
250
251 /*
252 * NOTE: The max offset address is 128 or half the reversal table. So
253 * the LSB is always zero and counts as a built in shift of one bit.
254 * So even though we need to shift 3 bits to make room for the command,
255 * we only need to shift twice more because of the built in shift.
256 */
257
258 /* Shift for command */
259 mem_offset <<= 2;
260 /* Add command */
261 mem_offset |= EPROM_READ;
262
263 /* Output chip address */
264 eeprom_put_byte(addr, mem_offset, SIZE_ADDR_OP);
265
266 /* Read chip data */
267 data = eeprom_get_byte(addr);
268
269 /* Remove Chip Select from EEPROM */
270 pci_write_32((u_int32_t *) addr, 0);
271
272 return (data & 0x000000FF);
273}
274
275/*------------------------------------------------------------------------
276 * pmc_eeprom_write - EEPROM location write
277 *------------------------------------------------------------------------
278 *
279 * Given a EEPROM PCI address, location offset and value, this
280 * routine writes the value to the specified location.
281 *
282 * Note: it is up to the caller to determine if the write
283 * operation succeeded.
284 */
285
286static int pmc_eeprom_write(long addr, long mem_offset, u_int32_t data)
287{
288 u_int32_t temp;
289 int count;
290
291 if (!ByteReverseBuilt)
292 BuildByteReverse();
293
294 /* Reverse address */
295 mem_offset = ByteReverse[0x7F & mem_offset];
296
297 /*
298 * NOTE: The max offset address is 128 or half the reversal table. So
299 * the LSB is always zero and counts as a built in shift of one bit.
300 * So even though we need to shift 3 bits to make room for the command,
301 * we only need to shift twice more because of the built in shift.
302 */
303
304 /* Shift for command */
305 mem_offset <<= 2;
306 /* Add command */
307 mem_offset |= EPROM_WRITE;
308
309 /* Output chip address */
310 eeprom_put_byte(addr, mem_offset, SIZE_ADDR_OP);
311
312 /* Reverse data */
313 data = ByteReverse[0xFF & data];
314 /* Output chip data */
315 eeprom_put_byte(addr, data, NUM_OF_BITS);
316
317 /* Remove Chip Select from EEPROM */
318 pci_write_32((u_int32_t *) addr, 0);
319
320/*
321 * Must see Data In at a low state before completing this transaction.
322 *
323 * Afterwards, the data bit will return to a high state, ~6 ms, terminating
324 * the operation.
325 */
326 /* Re-enable Chip Select */
327 pci_write_32((u_int32_t *) addr, EPROM_ENCS);
328 /* discard first read */
329 temp = pci_read_32((u_int32_t *) addr);
330 temp = pci_read_32((u_int32_t *) addr);
331 if (temp & EPROM_ACTIVE_IN_BIT) {
332 temp = pci_read_32((u_int32_t *) addr);
333 if (temp & EPROM_ACTIVE_IN_BIT) {
334 /* Remove Chip Select from EEPROM */
335 pci_write_32((u_int32_t *) addr, 0);
336 return 1;
337 }
338 }
339 count = 1000;
340 while (count--) {
341 for (temp = 0; temp < 0x10; temp++)
342 OS_uwait_dummy();
343
344 if (pci_read_32((u_int32_t *) addr) & EPROM_ACTIVE_IN_BIT)
345 break;
346 }
347
348 if (count == -1)
349 return 2;
350
351 return 0;
352}
353
354/*------------------------------------------------------------------------
355 * pmcGetBuffValue - read the specified value from buffer
356 *------------------------------------------------------------------------
357 */
358
359static long pmcGetBuffValue(char *ptr, int size)
360{
361 long value = 0;
362 int index;
363
364 for (index = 0; index < size; ++index) {
365 value <<= 8;
366 value |= ptr[index] & 0xFF;
367 }
368
369 return value;
370}
371
372/*------------------------------------------------------------------------
373 * pmcSetBuffValue - save the specified value to buffer
374 *------------------------------------------------------------------------
375 */
376
377static void pmcSetBuffValue(char *ptr, long value, int size)
378{
379 int index = size;
380
381 while (--index >= 0) {
382 ptr[index] = (char)(value & 0xFF);
383 value >>= 8;
384 }
385}
386
387/*------------------------------------------------------------------------
388 * pmc_eeprom_read_buffer - read EEPROM data into specified buffer
389 *------------------------------------------------------------------------
390 */
391
392void
393pmc_eeprom_read_buffer(long addr, long mem_offset, char *dest_ptr, int size)
394{
395 while (--size >= 0)
396 *dest_ptr++ = (char)pmc_eeprom_read(addr, mem_offset++);
397}
398
399/*------------------------------------------------------------------------
400 * pmc_eeprom_write_buffer - write EEPROM data from specified buffer
401 *------------------------------------------------------------------------
402 */
403
404void
405pmc_eeprom_write_buffer(long addr, long mem_offset, char *dest_ptr, int size)
406{
407 enable_pmc_eeprom(addr);
408
409 while (--size >= 0)
410 pmc_eeprom_write(addr, mem_offset++, *dest_ptr++);
411
412 disable_pmc_eeprom(addr);
413}
414
415/*------------------------------------------------------------------------
416 * pmcCalcCrc - calculate the CRC for the serial EEPROM structure
417 *------------------------------------------------------------------------
418 */
419
420static u_int32_t pmcCalcCrc_T01(void *bufp)
421{
422 FLD_TYPE2 *buf = bufp;
423 /* CRC of the structure */
424 u_int32_t crc;
425
426 /* Calc CRC for type and length fields */
427 sbeCrc((u_int8_t *) &buf->type,
428 (u_int32_t) STRUCT_OFFSET(FLD_TYPE1, Crc32),
429 (u_int32_t) 0, (u_int32_t *) &crc);
430
431#ifdef EEPROM_TYPE_DEBUG
432 /* RLD DEBUG */
433 pr_info("sbeCrc: crc 1 calculated as %08x\n", crc);
434#endif
435 return ~crc;
436}
437
438static u_int32_t pmcCalcCrc_T02(void *bufp)
439{
440 FLD_TYPE2 *buf = bufp;
441 /* CRC of the structure */
442 u_int32_t crc;
443
444 /* Calc CRC for type and length fields */
445 sbeCrc((u_int8_t *) &buf->type,
446 (u_int32_t) STRUCT_OFFSET(FLD_TYPE2, Crc32),
447 (u_int32_t) 0, (u_int32_t *) &crc);
448
449 /* Calc CRC for remaining fields */
450 sbeCrc((u_int8_t *) &buf->Id[0],
451 (u_int32_t) (sizeof(FLD_TYPE2) - STRUCT_OFFSET(FLD_TYPE2, Id)),
452 (u_int32_t) crc, (u_int32_t *) &crc);
453
454#ifdef EEPROM_TYPE_DEBUG
455 /* RLD DEBUG */
456 pr_info("sbeCrc: crc 2 calculated as %08x\n", crc);
457#endif
458 return crc;
459}
460
461/*------------------------------------------------------------------------
462 * pmc_init_seeprom - initialize the serial EEPROM structure
463 *------------------------------------------------------------------------
464 *
465 * At the front of the serial EEPROM there is a record that contains
466 * manufacturing information. If the info does not already exist, it
467 * is created. The only field modifiable by the operator is the
468 * serial number field.
469 */
470
471void pmc_init_seeprom(u_int32_t addr, u_int32_t serialNum)
472{
473 /* Memory image of structure */
474 PROMFORMAT buffer;
475 /* CRC of structure */
476 u_int32_t crc;
477 time_t createTime;
478
479 createTime = get_seconds();
480
481 /* use template data */
482 memcpy(&buffer.fldType2, mfg_template, sizeof(buffer.fldType2));
483
484 /* Update serial number field in buffer */
485 pmcSetBuffValue(&buffer.fldType2.Serial[3], serialNum, 3);
486
487 /* Update create time field in buffer */
488 pmcSetBuffValue(&buffer.fldType2.CreateTime[0], createTime, 4);
489
490 /* Update CRC field in buffer */
491 crc = pmcCalcCrc_T02(&buffer);
492 pmcSetBuffValue(&buffer.fldType2.Crc32[0], crc, 4);
493
494#ifdef DEBUG
495 for (i = 0; i < sizeof(FLD_TYPE2); ++i)
496 pr_info("[%02X] = %02X\n", i, buffer.bytes[i] & 0xFF);
497#endif
498
499 /* Write structure to serial EEPROM */
500 pmc_eeprom_write_buffer(addr, EE_MFG, (char *)&buffer,
501 sizeof(FLD_TYPE2));
502}
503
504char pmc_verify_cksum(void *bufp)
505{
506 FLD_TYPE1 *buf1 = bufp;
507 FLD_TYPE2 *buf2 = bufp;
508 /* CRC read from EEPROM */
509 u_int32_t crc1, crc2;
510
511 /* Retrieve contents of CRC field */
512 crc1 = pmcGetBuffValue(&buf1->Crc32[0], sizeof(buf1->Crc32));
513#ifdef EEPROM_TYPE_DEBUG
514 /* RLD DEBUG */
515 pr_info("EEPROM: chksum 1 reads as %08x\n", crc1);
516#endif
517 if ((buf1->type == PROM_FORMAT_TYPE1) &&
518 (pmcCalcCrc_T01((void *)buf1) == crc1))
519 return PROM_FORMAT_TYPE1; /* checksum type 1 verified */
520
521 crc2 = pmcGetBuffValue(&buf2->Crc32[0], sizeof(buf2->Crc32));
522#ifdef EEPROM_TYPE_DEBUG
523 /* RLD DEBUG */
524 pr_info("EEPROM: chksum 2 reads as %08x\n", crc2);
525#endif
526 if ((buf2->type == PROM_FORMAT_TYPE2) &&
527 (pmcCalcCrc_T02((void *)buf2) == crc2))
528 return PROM_FORMAT_TYPE2; /* checksum type 2 verified */
529
530 /* failed to validate */
531 return PROM_FORMAT_Unk;
532}
diff --git a/drivers/staging/cxt1e1/pmc93x6_eeprom.h b/drivers/staging/cxt1e1/pmc93x6_eeprom.h
deleted file mode 100644
index 96c48cb83260..000000000000
--- a/drivers/staging/cxt1e1/pmc93x6_eeprom.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef _INC_PMC93X6_EEPROM_H_
2#define _INC_PMC93X6_EEPROM_H_
3
4/*-----------------------------------------------------------------------------
5 * pmc93x6_eeprom.h -
6 *
7 * Copyright (C) 2002-2004 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *-----------------------------------------------------------------------------
22 */
23
24#include <linux/types.h>
25
26#ifdef __KERNEL__
27
28#include "pmcc4_private.h"
29
30void pmc_eeprom_read_buffer (long, long, char *, int);
31void pmc_eeprom_write_buffer (long, long, char *, int);
32void pmc_init_seeprom (u_int32_t, u_int32_t);
33char pmc_verify_cksum (void *);
34
35#endif /*** __KERNEL__ ***/
36
37#endif
38
39/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/pmcc4.h b/drivers/staging/cxt1e1/pmcc4.h
deleted file mode 100644
index 0220bbf3445a..000000000000
--- a/drivers/staging/cxt1e1/pmcc4.h
+++ /dev/null
@@ -1,108 +0,0 @@
1#ifndef _INC_PMCC4_H_
2#define _INC_PMCC4_H_
3
4/*-----------------------------------------------------------------------------
5 * pmcc4.h -
6 *
7 * Copyright (C) 2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *-----------------------------------------------------------------------------
22 */
23
24#include <linux/types.h>
25
26typedef int status_t;
27
28#define SBE_DRVR_FAIL 0
29#define SBE_DRVR_SUCCESS 1
30
31/********************/
32/* PMCC4 memory Map */
33/********************/
34
35#define COMET_OFFSET(x) (0x80000+(x)*0x10000)
36#define EEPROM_OFFSET 0xC0000
37#define CPLD_OFFSET 0xD0000
38
39 struct pmcc4_timeslot_param
40 {
41 u_int8_t card; /* the card number */
42 u_int8_t port; /* the port number */
43 u_int8_t _reserved1;
44 u_int8_t _reserved2;
45
46 /*
47 * each byte in bitmask below represents one timeslot (bitmask[0] is
48 * for timeslot 0 and so on), each bit in the byte selects timeslot
49 * bits for this channel (0xff - whole timeslot, 0x7f - 56kbps mode)
50 */
51 u_int8_t bitmask[32];
52 };
53
54 struct c4_musycc_param
55 {
56 u_int8_t RWportnum;
57 u_int16_t offset;
58 u_int32_t value;
59 };
60
61/*Alarm values */
62#define sbeE1RMAI 0x100
63#define sbeYelAlm 0x04
64#define sbeRedAlm 0x02
65#define sbeAISAlm 0x01
66
67#define sbeE1errSMF 0x02
68#define sbeE1CRC 0x01
69
70#ifdef __KERNEL__
71
72/*
73 * Device Driver interface, routines are for internal use only.
74 */
75
76#include "pmcc4_private.h"
77
78char *get_hdlc_name (hdlc_device *);
79
80/*
81 * external interface
82 */
83
84void c4_cleanup (void);
85status_t c4_chan_up (ci_t *, int channum);
86status_t c4_del_chan_stats (int channum);
87status_t c4_del_chan (int channum);
88status_t c4_get_iidinfo (ci_t *ci, struct sbe_iid_info *iip);
89int c4_is_chan_up (int channum);
90
91void *getuserbychan (int channum);
92void pci_flush_write (ci_t *ci);
93void sbecom_set_loglevel (int debuglevel);
94char *sbeid_get_bdname (ci_t *ci);
95void sbeid_set_bdtype (ci_t *ci);
96void sbeid_set_hdwbid (ci_t *ci);
97void sbeCrc(u_int8_t *, u_int32_t, u_int32_t, u_int32_t *);
98
99void VMETRO_TRIGGER (ci_t *, int); /* Note: int = 0(default)
100 * thru 15 */
101
102#if defined (SBE_ISR_TASKLET)
103void musycc_intr_bh_tasklet (ci_t *);
104
105#endif
106
107#endif /*** __KERNEL __ ***/
108#endif /* _INC_PMCC4_H_ */
diff --git a/drivers/staging/cxt1e1/pmcc4_cpld.h b/drivers/staging/cxt1e1/pmcc4_cpld.h
deleted file mode 100644
index a51209bc5274..000000000000
--- a/drivers/staging/cxt1e1/pmcc4_cpld.h
+++ /dev/null
@@ -1,91 +0,0 @@
1#ifndef _INC_PMCC4_CPLD_H_
2#define _INC_PMCC4_CPLD_H_
3
4/*-----------------------------------------------------------------------------
5 * pmcc4_cpld.h -
6 *
7 * Copyright (C) 2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *-----------------------------------------------------------------------------
22 */
23
24#include <linux/types.h>
25
26/********************************/
27/* iSPLD control chip registers */
28/********************************/
29
30#if 0
31#define CPLD_MCSR 0x0
32#define CPLD_MCLK 0x1
33#define CPLD_LEDS 0x2
34#define CPLD_INTR 0x3
35#endif
36
37 struct c4_cpld
38 {
39 volatile u_int32_t mcsr;/* r/w: Master Clock Source Register */
40 volatile u_int32_t mclk;/* r/w: Master Clock Register */
41 volatile u_int32_t leds;/* r/w: LED Register */
42 volatile u_int32_t intr;/* r: Interrupt Register */
43 };
44
45 typedef struct c4_cpld c4cpld_t;
46
47/* mcsr note: sourcing COMET must be initialized to Master Mode */
48#define PMCC4_CPLD_MCSR_IND 0 /* ports used individual BP Clk as
49 * source, no slaves */
50#define PMCC4_CPLD_MCSR_CMT_1 1 /* COMET 1 BP Clk is source, 2,3,4
51 * are Clk slaves */
52#define PMCC4_CPLD_MCSR_CMT_2 2 /* COMET 2 BP Clk is source, 1,3,4
53 * are Clk slaves */
54#define PMCC4_CPLD_MCSR_CMT_3 3 /* COMET 3 BP Clk is source, 1,2,4
55 * are Clk slaves */
56#define PMCC4_CPLD_MCSR_CMT_4 4 /* COMET 4 BP Clk is source, 1,2,3
57 * are Clk slaves */
58
59#define PMCC4_CPLD_MCLK_MASK 0x0f
60#define PMCC4_CPLD_MCLK_P1 0x1
61#define PMCC4_CPLD_MCLK_P2 0x2
62#define PMCC4_CPLD_MCLK_P3 0x4
63#define PMCC4_CPLD_MCLK_P4 0x8
64#define PMCC4_CPLD_MCLK_T1 0x00
65#define PMCC4_CPLD_MCLK_P1_E1 0x01
66#define PMCC4_CPLD_MCLK_P2_E1 0x02
67#define PMCC4_CPLD_MCLK_P3_E1 0x04
68#define PMCC4_CPLD_MCLK_P4_E1 0x08
69
70#define PMCC4_CPLD_LED_OFF 0
71#define PMCC4_CPLD_LED_ON 1
72#define PMCC4_CPLD_LED_GP0 0x01 /* port 0, green */
73#define PMCC4_CPLD_LED_YP0 0x02 /* port 0, yellow */
74#define PMCC4_CPLD_LED_GP1 0x04 /* port 1, green */
75#define PMCC4_CPLD_LED_YP1 0x08 /* port 1, yellow */
76#define PMCC4_CPLD_LED_GP2 0x10 /* port 2, green */
77#define PMCC4_CPLD_LED_YP2 0x20 /* port 2, yellow */
78#define PMCC4_CPLD_LED_GP3 0x40 /* port 3, green */
79#define PMCC4_CPLD_LED_YP3 0x80 /* port 3, yellow */
80#define PMCC4_CPLD_LED_GREEN (PMCC4_CPLD_LED_GP0 | PMCC4_CPLD_LED_GP1 | \
81 PMCC4_CPLD_LED_GP2 | PMCC4_CPLD_LED_GP3 )
82#define PMCC4_CPLD_LED_YELLOW (PMCC4_CPLD_LED_YP0 | PMCC4_CPLD_LED_YP1 | \
83 PMCC4_CPLD_LED_YP2 | PMCC4_CPLD_LED_YP3)
84
85#define PMCC4_CPLD_INTR_MASK 0x0f
86#define PMCC4_CPLD_INTR_CMT_1 0x01
87#define PMCC4_CPLD_INTR_CMT_2 0x02
88#define PMCC4_CPLD_INTR_CMT_3 0x04
89#define PMCC4_CPLD_INTR_CMT_4 0x08
90
91#endif /* _INC_PMCC4_CPLD_H_ */
diff --git a/drivers/staging/cxt1e1/pmcc4_defs.h b/drivers/staging/cxt1e1/pmcc4_defs.h
deleted file mode 100644
index 83ceae4324b2..000000000000
--- a/drivers/staging/cxt1e1/pmcc4_defs.h
+++ /dev/null
@@ -1,68 +0,0 @@
1#ifndef _INC_PMCC4_DEFS_H_
2#define _INC_PMCC4_DEFS_H_
3
4/*-----------------------------------------------------------------------------
5 * c4_defs.h -
6 *
7 * Implementation elements of the wanPMC-C4T1E1 device driver
8 *
9 * Copyright (C) 2005 SBE, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * For further information, contact via email: support@sbei.com
22 * SBE, Inc. San Ramon, California U.S.A.
23 *-----------------------------------------------------------------------------
24 */
25
26
27#define MAX_BOARDS 8
28#define MAX_CHANS_USED 128
29
30#ifdef SBE_PMCC4_ENABLE
31#define MUSYCC_NPORTS 4 /* CN8474 */
32#endif
33#ifdef SBE_WAN256T3_ENABLE
34#define MUSYCC_NPORTS 8 /* CN8478 */
35#endif
36#define MUSYCC_NCHANS 32 /* actually, chans per port */
37
38#define MUSYCC_NIQD 0x1000 /* power of 2 */
39#define MUSYCC_MRU 2048 /* default */
40#define MUSYCC_MTU 2048 /* default */
41#define MUSYCC_TXDESC_MIN 10 /* HDLC mode default */
42#define MUSYCC_RXDESC_MIN 18 /* HDLC mode default */
43#define MUSYCC_TXDESC_TRANS 4 /* Transparent mode minimum # of TX descriptors */
44#define MUSYCC_RXDESC_TRANS 12 /* Transparent mode minimum # of RX descriptors */
45
46#define MAX_DEFAULT_IFQLEN 32 /* network qlen */
47
48
49#define SBE_IFACETMPL "pmcc4-%d"
50#ifdef IFNAMSIZ
51#define SBE_IFACETMPL_SIZE IFNAMSIZ
52#else
53#define SBE_IFACETMPL_SIZE 16
54#endif
55
56/* we want the PMCC4 watchdog to fire off every 250ms */
57#define WATCHDOG_TIMEOUT 250000
58
59/* if we restart the watchdog every 250ms, then we'll time out
60 * an additional 300ms later */
61#define WATCHDOG_UTIMEOUT (WATCHDOG_TIMEOUT+300000)
62
63#if !defined(SBE_ISR_TASKLET) && !defined(SBE_ISR_IMMEDIATE) && !defined(SBE_ISR_INLINE)
64#define SBE_ISR_TASKLET
65#endif
66
67#endif /*** _INC_PMCC4_DEFS_H_ ***/
68
diff --git a/drivers/staging/cxt1e1/pmcc4_drv.c b/drivers/staging/cxt1e1/pmcc4_drv.c
deleted file mode 100644
index 76bebdd18b3a..000000000000
--- a/drivers/staging/cxt1e1/pmcc4_drv.c
+++ /dev/null
@@ -1,1613 +0,0 @@
1/*-----------------------------------------------------------------------------
2 * pmcc4_drv.c -
3 *
4 * Copyright (C) 2007 One Stop Systems, Inc.
5 * Copyright (C) 2002-2006 SBE, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * For further information, contact via email: support@onestopsystems.com
18 * One Stop Systems, Inc. Escondido, California U.S.A.
19 *-----------------------------------------------------------------------------
20 */
21
22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24#include <linux/types.h>
25#include "pmcc4_sysdep.h"
26#include <linux/errno.h>
27#include <linux/kernel.h>
28#include <linux/sched.h> /* include for timer */
29#include <linux/timer.h> /* include for timer */
30#include <linux/hdlc.h>
31#include <linux/io.h>
32
33#include "sbecom_inline_linux.h"
34#include "libsbew.h"
35#include "pmcc4_private.h"
36#include "pmcc4.h"
37#include "pmcc4_ioctls.h"
38#include "musycc.h"
39#include "comet.h"
40#include "sbe_bid.h"
41
42#define KERN_WARN KERN_WARNING
43
44/* forward references */
45status_t c4_wk_chan_init (mpi_t *, mch_t *);
46void c4_wq_port_cleanup (mpi_t *);
47status_t c4_wq_port_init (mpi_t *);
48
49int c4_loop_port (ci_t *, int, u_int8_t);
50status_t c4_set_port (ci_t *, int);
51status_t musycc_chan_down (ci_t *, int);
52
53u_int32_t musycc_chan_proto (int);
54status_t musycc_dump_ring (ci_t *, unsigned int);
55status_t __init musycc_init (ci_t *);
56void musycc_init_mdt (mpi_t *);
57void musycc_serv_req (mpi_t *, u_int32_t);
58void musycc_update_timeslots (mpi_t *);
59
60extern void musycc_update_tx_thp (mch_t *);
61extern int cxt1e1_log_level;
62extern int cxt1e1_max_mru;
63extern int cxt1e1_max_mtu;
64extern int max_rxdesc_used, max_rxdesc_default;
65extern int max_txdesc_used, max_txdesc_default;
66
67#if defined (__powerpc__)
68extern void *memset (void *s, int c, size_t n);
69
70#endif
71
72int drvr_state = SBE_DRVR_INIT;
73ci_t *c4_list = NULL;
74ci_t *CI; /* dummy pointer to board ZEROE's data -
75 * DEBUG USAGE */
76
77
78void
79sbecom_set_loglevel (int d)
80{
81 /*
82 * The code within the following -if- clause is a backdoor debug facility
83 * which can be used to display the state of a board's channel.
84 */
85 if (d > LOG_DEBUG)
86 {
87 unsigned int channum = d - (LOG_DEBUG + 1); /* convert to ZERO
88 * relativity */
89
90 (void) musycc_dump_ring ((ci_t *) CI, channum); /* CI implies support
91 * for card 0 only */
92 } else
93 {
94 if (cxt1e1_log_level != d)
95 {
96 pr_info("log level changed from %d to %d\n", cxt1e1_log_level, d);
97 cxt1e1_log_level = d; /* set new */
98 } else
99 pr_info("log level is %d\n", cxt1e1_log_level);
100 }
101}
102
103
104mch_t *
105c4_find_chan (int channum)
106{
107 ci_t *ci;
108 mch_t *ch;
109 int portnum, gchan;
110
111 for (ci = c4_list; ci; ci = ci->next)
112 for (portnum = 0; portnum < ci->max_port; portnum++)
113 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
114 {
115 ch = ci->port[portnum].chan[gchan];
116 if (ch) {
117 if ((ch->state != UNASSIGNED) &&
118 (ch->channum == channum))
119 return ch;
120 }
121 }
122 return NULL;
123}
124
125/***
126 * Check port state and set LED states using watchdog or ioctl...
127 * also check for in-band SF loopback commands (& cause results if they are there)
128 *
129 * Alarm function depends on comet bits indicating change in
130 * link status (linkMask) to keep the link status indication straight.
131 *
132 * Indications are only LED and system log -- except when ioctl is invoked.
133 *
134 * "alarmed" record (a.k.a. copyVal, in some cases below) decodes as:
135 *
136 * RMAI (E1 only) 0x100
137 * alarm LED on 0x80
138 * link LED on 0x40
139 * link returned 0x20 (link was down, now it's back and 'port get' hasn't run)
140 * change in LED 0x10 (update LED register because value has changed)
141 * link is down 0x08
142 * YelAlm(RAI) 0x04
143 * RedAlm 0x02
144 * AIS(blue)Alm 0x01
145 *
146 * note "link has returned" indication is reset on read
147 * (e.g. by use of the c4_control port get command)
148 */
149
150#define sbeLinkMask 0x41 /* change in signal status (lost/recovered) +
151 * state */
152#define sbeLinkChange 0x40
153#define sbeLinkDown 0x01
154#define sbeAlarmsMask 0x07 /* red / yellow / blue alarm conditions */
155#define sbeE1AlarmsMask 0x107 /* alarm conditions */
156
157#define COMET_LBCMD_READ 0x80 /* read only (do not set, return read value) */
158
159void
160checkPorts (ci_t *ci)
161{
162#ifndef CONFIG_SBE_PMCC4_NCOMM
163 /*
164 * PORT POINT - NCOMM needs to avoid this code since the polling of
165 * alarms conflicts with NCOMM's interrupt servicing implementation.
166 */
167
168 struct s_comet_reg *comet;
169 volatile u_int32_t value;
170 u_int32_t copyVal, LEDval;
171
172 u_int8_t portnum;
173
174 LEDval = 0;
175 for (portnum = 0; portnum < ci->max_port; portnum++)
176 {
177 copyVal = 0x12f & (ci->alarmed[portnum]); /* port's alarm record */
178 comet = ci->port[portnum].cometbase;
179 value = pci_read_32 ((u_int32_t *) &comet->cdrc_ists) & sbeLinkMask; /* link loss reg */
180
181 if (value & sbeLinkChange) /* is there a change in the link stuff */
182 {
183 /* if there's been a change (above) and yet it's the same (below) */
184 if (!(((copyVal >> 3) & sbeLinkDown) ^ (value & sbeLinkDown)))
185 {
186 if (value & sbeLinkDown)
187 pr_warning("%s: Port %d momentarily recovered.\n",
188 ci->devname, portnum);
189 else
190 pr_warning("%s: Warning: Port %d link was briefly down.\n",
191 ci->devname, portnum);
192 } else if (value & sbeLinkDown)
193 pr_warning("%s: Warning: Port %d link is down.\n",
194 ci->devname, portnum);
195 else
196 {
197 pr_warning("%s: Port %d link has recovered.\n",
198 ci->devname, portnum);
199 copyVal |= 0x20; /* record link transition to up */
200 }
201 copyVal |= 0x10; /* change (link) --> update LEDs */
202 }
203 copyVal &= 0x137; /* clear LED & link old history bits &
204 * save others */
205 if (value & sbeLinkDown)
206 copyVal |= 0x08; /* record link status (now) */
207 else
208 { /* if link is up, do this */
209 copyVal |= 0x40; /* LED indicate link is up */
210 /* Alarm things & the like ... first if E1, then if T1 */
211 if (IS_FRAME_ANY_E1 (ci->port[portnum].p.port_mode))
212 {
213 /*
214 * first check Codeword (SaX) changes & CRC and
215 * sub-multi-frame errors
216 */
217 /*
218 * note these errors are printed every time they are detected
219 * vs. alarms
220 */
221 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_nat_ists); /* codeword */
222 if (value & 0x1f)
223 { /* if errors (crc or smf only) */
224 if (value & 0x10)
225 pr_warning("%s: E1 Port %d Codeword Sa4 change detected.\n",
226 ci->devname, portnum);
227 if (value & 0x08)
228 pr_warning("%s: E1 Port %d Codeword Sa5 change detected.\n",
229 ci->devname, portnum);
230 if (value & 0x04)
231 pr_warning("%s: E1 Port %d Codeword Sa6 change detected.\n",
232 ci->devname, portnum);
233 if (value & 0x02)
234 pr_warning("%s: E1 Port %d Codeword Sa7 change detected.\n",
235 ci->devname, portnum);
236 if (value & 0x01)
237 pr_warning("%s: E1 Port %d Codeword Sa8 change detected.\n",
238 ci->devname, portnum);
239 }
240 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_mists); /* crc & smf */
241 if (value & 0x3)
242 { /* if errors (crc or smf only) */
243 if (value & sbeE1CRC)
244 pr_warning("%s: E1 Port %d CRC-4 error(s) detected.\n",
245 ci->devname, portnum);
246 if (value & sbeE1errSMF) /* error in sub-multiframe */
247 pr_warning("%s: E1 Port %d received errored SMF.\n",
248 ci->devname, portnum);
249 }
250 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_masts) & 0xcc; /* alarms */
251 /*
252 * pack alarms together (bitmiser), and construct similar to
253 * T1
254 */
255 /* RAI,RMAI,.,.,LOF,AIS,.,. ==> RMAI,.,.,.,.,.,RAI,LOF,AIS */
256 /* see 0x97 */
257 value = (value >> 2);
258 if (value & 0x30)
259 {
260 if (value & 0x20)
261 value |= 0x40; /* RAI */
262 if (value & 0x10)
263 value |= 0x100; /* RMAI */
264 value &= ~0x30;
265 } /* finished packing alarm in handy order */
266 if (value != (copyVal & sbeE1AlarmsMask))
267 { /* if alarms changed */
268 copyVal |= 0x10;/* change LED status */
269 if ((copyVal & sbeRedAlm) && !(value & sbeRedAlm))
270 {
271 copyVal &= ~sbeRedAlm;
272 pr_warning("%s: E1 Port %d LOF alarm ended.\n",
273 ci->devname, portnum);
274 } else if (!(copyVal & sbeRedAlm) && (value & sbeRedAlm))
275 {
276 copyVal |= sbeRedAlm;
277 pr_warning("%s: E1 Warning: Port %d LOF alarm.\n",
278 ci->devname, portnum);
279 } else if ((copyVal & sbeYelAlm) && !(value & sbeYelAlm))
280 {
281 copyVal &= ~sbeYelAlm;
282 pr_warning("%s: E1 Port %d RAI alarm ended.\n",
283 ci->devname, portnum);
284 } else if (!(copyVal & sbeYelAlm) && (value & sbeYelAlm))
285 {
286 copyVal |= sbeYelAlm;
287 pr_warning("%s: E1 Warning: Port %d RAI alarm.\n",
288 ci->devname, portnum);
289 } else if ((copyVal & sbeE1RMAI) && !(value & sbeE1RMAI))
290 {
291 copyVal &= ~sbeE1RMAI;
292 pr_warning("%s: E1 Port %d RMAI alarm ended.\n",
293 ci->devname, portnum);
294 } else if (!(copyVal & sbeE1RMAI) && (value & sbeE1RMAI))
295 {
296 copyVal |= sbeE1RMAI;
297 pr_warning("%s: E1 Warning: Port %d RMAI alarm.\n",
298 ci->devname, portnum);
299 } else if ((copyVal & sbeAISAlm) && !(value & sbeAISAlm))
300 {
301 copyVal &= ~sbeAISAlm;
302 pr_warning("%s: E1 Port %d AIS alarm ended.\n",
303 ci->devname, portnum);
304 } else if (!(copyVal & sbeAISAlm) && (value & sbeAISAlm))
305 {
306 copyVal |= sbeAISAlm;
307 pr_warning("%s: E1 Warning: Port %d AIS alarm.\n",
308 ci->devname, portnum);
309 }
310 }
311 /* end of E1 alarm code */
312 } else
313 { /* if a T1 mode */
314 value = pci_read_32 ((u_int32_t *) &comet->t1_almi_ists); /* alarms */
315 value &= sbeAlarmsMask;
316 if (value != (copyVal & sbeAlarmsMask))
317 { /* if alarms changed */
318 copyVal |= 0x10;/* change LED status */
319 if ((copyVal & sbeRedAlm) && !(value & sbeRedAlm))
320 {
321 copyVal &= ~sbeRedAlm;
322 pr_warning("%s: Port %d red alarm ended.\n",
323 ci->devname, portnum);
324 } else if (!(copyVal & sbeRedAlm) && (value & sbeRedAlm))
325 {
326 copyVal |= sbeRedAlm;
327 pr_warning("%s: Warning: Port %d red alarm.\n",
328 ci->devname, portnum);
329 } else if ((copyVal & sbeYelAlm) && !(value & sbeYelAlm))
330 {
331 copyVal &= ~sbeYelAlm;
332 pr_warning("%s: Port %d yellow (RAI) alarm ended.\n",
333 ci->devname, portnum);
334 } else if (!(copyVal & sbeYelAlm) && (value & sbeYelAlm))
335 {
336 copyVal |= sbeYelAlm;
337 pr_warning("%s: Warning: Port %d yellow (RAI) alarm.\n",
338 ci->devname, portnum);
339 } else if ((copyVal & sbeAISAlm) && !(value & sbeAISAlm))
340 {
341 copyVal &= ~sbeAISAlm;
342 pr_warning("%s: Port %d blue (AIS) alarm ended.\n",
343 ci->devname, portnum);
344 } else if (!(copyVal & sbeAISAlm) && (value & sbeAISAlm))
345 {
346 copyVal |= sbeAISAlm;
347 pr_warning("%s: Warning: Port %d blue (AIS) alarm.\n",
348 ci->devname, portnum);
349 }
350 }
351 } /* end T1 mode alarm checks */
352 }
353 if (copyVal & sbeAlarmsMask)
354 copyVal |= 0x80; /* if alarm turn yel LED on */
355 if (copyVal & 0x10)
356 LEDval |= 0x100; /* tag if LED values have changed */
357 LEDval |= ((copyVal & 0xc0) >> (6 - (portnum * 2)));
358
359 ci->alarmed[portnum] &= 0xfffff000; /* out with the old (it's fff
360 * ... foo) */
361 ci->alarmed[portnum] |= (copyVal); /* in with the new */
362
363 /*
364 * enough with the alarms and LED's, now let's check for loopback
365 * requests
366 */
367
368 if (IS_FRAME_ANY_T1 (ci->port[portnum].p.port_mode))
369 { /* if a T1 mode */
370 /*
371 * begin in-band (SF) loopback code detection -- start by reading
372 * command
373 */
374 value = pci_read_32 ((u_int32_t *) &comet->ibcd_ies); /* detect reg. */
375 value &= 0x3; /* trim to handy bits */
376 if (value & 0x2)
377 { /* activate loopback (sets for deactivate
378 * code length) */
379 copyVal = c4_loop_port (ci, portnum, COMET_LBCMD_READ); /* read line loopback
380 * mode */
381 if (copyVal != COMET_MDIAG_LINELB) /* don't do it again if
382 * already in that mode */
383 c4_loop_port (ci, portnum, COMET_MDIAG_LINELB); /* put port in line
384 * loopback mode */
385 }
386 if (value & 0x1)
387 { /* deactivate loopback (sets for activate
388 * code length) */
389 copyVal = c4_loop_port (ci, portnum, COMET_LBCMD_READ); /* read line loopback
390 * mode */
391 if (copyVal != COMET_MDIAG_LBOFF) /* don't do it again if
392 * already in that mode */
393 c4_loop_port (ci, portnum, COMET_MDIAG_LBOFF); /* take port out of any
394 * loopback mode */
395 }
396 }
397 if (IS_FRAME_ANY_T1ESF (ci->port[portnum].p.port_mode))
398 { /* if a T1 ESF mode */
399 /* begin ESF loopback code */
400 value = pci_read_32 ((u_int32_t *) &comet->t1_rboc_sts) & 0x3f; /* read command */
401 if (value == 0x07)
402 c4_loop_port (ci, portnum, COMET_MDIAG_LINELB); /* put port in line
403 * loopback mode */
404 if (value == 0x0a)
405 c4_loop_port (ci, portnum, COMET_MDIAG_PAYLB); /* put port in payload
406 * loopbk mode */
407 if ((value == 0x1c) || (value == 0x19) || (value == 0x12))
408 c4_loop_port (ci, portnum, COMET_MDIAG_LBOFF); /* take port out of any
409 * loopbk mode */
410 if (cxt1e1_log_level >= LOG_DEBUG)
411 if (value != 0x3f)
412 pr_warning("%s: BOC value = %x on Port %d\n",
413 ci->devname, value, portnum);
414 /* end ESF loopback code */
415 }
416 }
417
418 /* if something is new, update LED's */
419 if (LEDval & 0x100)
420 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, LEDval & 0xff);
421#endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
422}
423
424
425static void
426c4_watchdog (ci_t *ci)
427{
428 if (drvr_state != SBE_DRVR_AVAILABLE)
429 {
430 if (cxt1e1_log_level >= LOG_MONITOR)
431 pr_info("drvr not available (%x)\n", drvr_state);
432 return;
433 }
434 ci->wdcount++;
435 checkPorts (ci);
436 ci->wd_notify = 0;
437}
438
439
440void
441c4_cleanup (void)
442{
443 ci_t *ci, *next;
444 mpi_t *pi;
445 int portnum, j;
446
447 ci = c4_list;
448 while (ci)
449 {
450 next = ci->next; /* protect <next> from upcoming <free> */
451 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, PMCC4_CPLD_LED_OFF);
452 for (portnum = 0; portnum < ci->max_port; portnum++)
453 {
454 pi = &ci->port[portnum];
455 c4_wq_port_cleanup (pi);
456 for (j = 0; j < MUSYCC_NCHANS; j++)
457 {
458 if (pi->chan[j])
459 kfree(pi->chan[j]); /* free mch_t struct */
460 }
461 kfree(pi->regram_saved);
462 }
463 kfree(ci->iqd_p_saved);
464 kfree(ci);
465 ci = next; /* cleanup next board, if any */
466 }
467}
468
469
470/*
471 * This function issues a write to all comet chips and expects the same data
472 * to be returned from the subsequent read. This determines the board build
473 * to be a 1-port, 2-port, or 4-port build. The value returned represents a
474 * bit-mask of the found ports. Only certain configurations are considered
475 * VALID or LEGAL builds.
476 */
477
478int
479c4_get_portcfg (ci_t *ci)
480{
481 struct s_comet_reg *comet;
482 int portnum, mask;
483 u_int32_t wdata, rdata;
484
485 wdata = COMET_MDIAG_LBOFF; /* take port out of any loopback mode */
486
487 mask = 0;
488 for (portnum = 0; portnum < MUSYCC_NPORTS; portnum++)
489 {
490 comet = ci->port[portnum].cometbase;
491 pci_write_32 ((u_int32_t *) &comet->mdiag, wdata);
492 rdata = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
493 if (wdata == rdata)
494 mask |= 1 << portnum;
495 }
496 return mask;
497}
498
499
500/* nothing herein should generate interrupts */
501
502status_t __init
503c4_init (ci_t *ci, u_char *func0, u_char *func1)
504{
505 mpi_t *pi;
506 mch_t *ch;
507 static u_int32_t count = 0;
508 int portnum, j;
509
510 ci->state = C_INIT;
511 ci->brdno = count++;
512 ci->intlog.this_status_new = 0;
513 atomic_set (&ci->bh_pending, 0);
514
515 ci->reg = (struct musycc_globalr *) func0;
516 ci->eeprombase = (u_int32_t *) (func1 + EEPROM_OFFSET);
517 ci->cpldbase = (c4cpld_t *) ((u_int32_t *) (func1 + ISPLD_OFFSET));
518
519 /*** PORT POINT - the following is the first access of any type to the hardware ***/
520#ifdef CONFIG_SBE_PMCC4_NCOMM
521 /* NCOMM driver uses INTB interrupt to monitor CPLD register */
522 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC);
523#else
524 /* standard driver POLLS for INTB via CPLD register */
525 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
526#endif
527
528 {
529 int pmsk;
530
531 /* need comet addresses available for determination of hardware build */
532 for (portnum = 0; portnum < MUSYCC_NPORTS; portnum++)
533 {
534 pi = &ci->port[portnum];
535 pi->cometbase = (struct s_comet_reg *) ((u_int32_t *) (func1 + COMET_OFFSET (portnum)));
536 pi->reg = (struct musycc_globalr *) ((u_char *) ci->reg + (portnum * 0x800));
537 pi->portnum = portnum;
538 pi->p.portnum = portnum;
539 pi->openchans = 0;
540#ifdef SBE_MAP_DEBUG
541 pr_info("Comet-%d: addr = %p\n", portnum, pi->cometbase);
542#endif
543 }
544 pmsk = c4_get_portcfg (ci);
545 switch (pmsk)
546 {
547 case 0x1:
548 ci->max_port = 1;
549 break;
550 case 0x3:
551 ci->max_port = 2;
552 break;
553#if 0
554 case 0x7: /* not built, but could be... */
555 ci->max_port = 3;
556 break;
557#endif
558 case 0xf:
559 ci->max_port = 4;
560 break;
561 default:
562 ci->max_port = 0;
563 pr_warning("%s: illegal port configuration (%x)\n",
564 ci->devname, pmsk);
565 return SBE_DRVR_FAIL;
566 }
567#ifdef SBE_MAP_DEBUG
568 pr_info(">> %s: c4_get_build - pmsk %x max_port %x\n",
569 ci->devname, pmsk, ci->max_port);
570#endif
571 }
572
573 for (portnum = 0; portnum < ci->max_port; portnum++)
574 {
575 pi = &ci->port[portnum];
576 pi->up = ci;
577 pi->sr_last = 0xffffffff;
578 pi->p.port_mode = CFG_FRAME_SF; /* T1 B8ZS, the default */
579 pi->p.portP = (CFG_CLK_PORT_EXTERNAL | CFG_LBO_LH0); /* T1 defaults */
580
581 OS_sem_init (&pi->sr_sem_busy, SEM_AVAILABLE);
582 OS_sem_init (&pi->sr_sem_wait, SEM_TAKEN);
583
584 for (j = 0; j < 32; j++)
585 {
586 pi->fifomap[j] = -1;
587 pi->tsm[j] = 0; /* no assignments, all available */
588 }
589
590 /* allocate channel structures for this port */
591 for (j = 0; j < MUSYCC_NCHANS; j++)
592 {
593 ch = kzalloc(sizeof(mch_t), GFP_KERNEL | GFP_DMA);
594 if (ch)
595 {
596 pi->chan[j] = ch;
597 ch->state = UNASSIGNED;
598 ch->up = pi;
599 ch->gchan = (-1); /* channel assignment not yet known */
600 ch->channum = (-1); /* channel assignment not yet known */
601 ch->p.card = ci->brdno;
602 ch->p.port = portnum;
603 ch->p.channum = (-1); /* channel assignment not yet known */
604 ch->p.mode_56k = 0; /* default is 64kbps mode */
605 } else
606 {
607 pr_warning("failed mch_t malloc, port %d channel %d size %u.\n",
608 portnum, j, (unsigned int) sizeof (mch_t));
609 break;
610 }
611 }
612 }
613
614
615 {
616 /*
617 * Set LEDs through their paces to supply visual proof that LEDs are
618 * functional and not burnt out nor broken.
619 *
620 * YELLOW + GREEN -> OFF.
621 */
622
623 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds,
624 PMCC4_CPLD_LED_GREEN | PMCC4_CPLD_LED_YELLOW);
625 OS_uwait (750000, "leds");
626 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, PMCC4_CPLD_LED_OFF);
627 }
628
629 OS_init_watchdog (&ci->wd, (void (*) (void *)) c4_watchdog, ci, WATCHDOG_TIMEOUT);
630 return SBE_DRVR_SUCCESS;
631}
632
633
634/* better be fully setup to handle interrupts when you call this */
635
636status_t __init
637c4_init2 (ci_t *ci)
638{
639 status_t ret;
640
641 /* PORT POINT: this routine generates first interrupt */
642 ret = musycc_init(ci);
643 if (ret != SBE_DRVR_SUCCESS)
644 return ret;
645
646#if 0
647 ci->p.framing_type = FRAMING_CBP;
648 ci->p.h110enable = 1;
649#if 0
650 ci->p.hypersize = 0;
651#else
652 hyperdummy = 0;
653#endif
654 ci->p.clock = 0; /* Use internal clocking until set to
655 * external */
656 c4_card_set_params (ci, &ci->p);
657#endif
658 OS_start_watchdog (&ci->wd);
659 return SBE_DRVR_SUCCESS;
660}
661
662
663/* This function sets the loopback mode (or clears it, as the case may be). */
664
665int
666c4_loop_port (ci_t *ci, int portnum, u_int8_t cmd)
667{
668 struct s_comet_reg *comet;
669 volatile u_int32_t loopValue;
670
671 comet = ci->port[portnum].cometbase;
672 loopValue = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
673
674 if (cmd & COMET_LBCMD_READ)
675 return loopValue; /* return the read value */
676
677 if (loopValue != cmd)
678 {
679 switch (cmd)
680 {
681 case COMET_MDIAG_LINELB:
682 /* set(SF)loopback down (turn off) code length to 6 bits */
683 pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x05);
684 break;
685 case COMET_MDIAG_LBOFF:
686 /* set (SF) loopback up (turn on) code length to 5 bits */
687 pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x00);
688 break;
689 }
690
691 pci_write_32 ((u_int32_t *) &comet->mdiag, cmd);
692 if (cxt1e1_log_level >= LOG_WARN)
693 pr_info("%s: loopback mode changed to %2x from %2x on Port %d\n",
694 ci->devname, cmd, loopValue, portnum);
695 loopValue = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
696 if (loopValue != cmd)
697 {
698 if (cxt1e1_log_level >= LOG_ERROR)
699 pr_info("%s: write to loop register failed, unknown state for Port %d\n",
700 ci->devname, portnum);
701 }
702 } else
703 {
704 if (cxt1e1_log_level >= LOG_WARN)
705 pr_info("%s: loopback already in that mode (%2x)\n",
706 ci->devname, loopValue);
707 }
708 return 0;
709}
710
711
712/* c4_frame_rw: read or write the comet register specified
713 * (modifies use of port_param to non-standard use of struct)
714 * Specifically:
715 * pp.portnum (one guess)
716 * pp.port_mode offset of register
717 * pp.portP write (or not, i.e. read)
718 * pp.portStatus write value
719 * BTW:
720 * pp.portStatus also used to return read value
721 * pp.portP also used during write, to return old reg value
722 */
723
724status_t
725c4_frame_rw (ci_t *ci, struct sbecom_port_param *pp)
726{
727 struct s_comet_reg *comet;
728 volatile u_int32_t data;
729
730 if (pp->portnum >= ci->max_port)/* sanity check */
731 return -ENXIO;
732
733 comet = ci->port[pp->portnum].cometbase;
734 data = pci_read_32 ((u_int32_t *) comet + pp->port_mode) & 0xff;
735
736 if (pp->portP)
737 { /* control says this is a register
738 * _write_ */
739 if (pp->portStatus == data)
740 pr_info("%s: Port %d already that value! Writing again anyhow.\n",
741 ci->devname, pp->portnum);
742 pp->portP = (u_int8_t) data;
743 pci_write_32 ((u_int32_t *) comet + pp->port_mode,
744 pp->portStatus);
745 data = pci_read_32 ((u_int32_t *) comet + pp->port_mode) & 0xff;
746 }
747 pp->portStatus = (u_int8_t) data;
748 return 0;
749}
750
751
752/* c4_pld_rw: read or write the pld register specified
753 * (modifies use of port_param to non-standard use of struct)
754 * Specifically:
755 * pp.port_mode offset of register
756 * pp.portP write (or not, i.e. read)
757 * pp.portStatus write value
758 * BTW:
759 * pp.portStatus also used to return read value
760 * pp.portP also used during write, to return old reg value
761 */
762
763status_t
764c4_pld_rw (ci_t *ci, struct sbecom_port_param *pp)
765{
766 volatile u_int32_t *regaddr;
767 volatile u_int32_t data;
768 int regnum = pp->port_mode;
769
770 regaddr = (u_int32_t *) ci->cpldbase + regnum;
771 data = pci_read_32 ((u_int32_t *) regaddr) & 0xff;
772
773 if (pp->portP)
774 { /* control says this is a register
775 * _write_ */
776 pp->portP = (u_int8_t) data;
777 pci_write_32 ((u_int32_t *) regaddr, pp->portStatus);
778 data = pci_read_32 ((u_int32_t *) regaddr) & 0xff;
779 }
780 pp->portStatus = (u_int8_t) data;
781 return 0;
782}
783
784/* c4_musycc_rw: read or write the musycc register specified
785 * (modifies use of port_param to non-standard use of struct)
786 * Specifically:
787 * mcp.RWportnum port number and write indication bit (0x80)
788 * mcp.offset offset of register
789 * mcp.value write value going in and read value returning
790 */
791
792/* PORT POINT: TX Subchannel Map registers are write-only
793 * areas within the MUSYCC and always return FF */
794/* PORT POINT: regram and reg structures are minorly different and <offset> ioctl
795 * settings are aligned with the <reg> struct musycc_globalr{} usage.
796 * Also, regram is separately allocated shared memory, allocated for each port.
797 * PORT POINT: access offsets of 0x6000 for Msg Cfg Desc Tbl are for 4-port MUSYCC
798 * only. (An 8-port MUSYCC has 0x16000 offsets for accessing its upper 4 tables.)
799 */
800
801status_t
802c4_musycc_rw (ci_t *ci, struct c4_musycc_param *mcp)
803{
804 mpi_t *pi;
805 volatile u_int32_t *dph; /* hardware implemented register */
806 u_int32_t *dpr = NULL; /* RAM image of registers for group command
807 * usage */
808 int offset = mcp->offset % 0x800; /* group relative address
809 * offset, mcp->portnum is
810 * not used */
811 int portnum, ramread = 0;
812 volatile u_int32_t data;
813
814 /*
815 * Sanity check hardware accessibility. The 0x6000 portion handles port
816 * numbers associated with Msg Descr Tbl decoding.
817 */
818 portnum = (mcp->offset % 0x6000) / 0x800;
819 if (portnum >= ci->max_port)
820 return -ENXIO;
821 pi = &ci->port[portnum];
822 if (mcp->offset >= 0x6000)
823 offset += 0x6000; /* put back in MsgCfgDesc address offset */
824 dph = (u_int32_t *) ((u_long) pi->reg + offset);
825
826 /* read of TX are from RAM image, since hardware returns FF */
827 dpr = (u_int32_t *) ((u_long) pi->regram + offset);
828 if (mcp->offset < 0x6000) /* non MsgDesc Tbl accesses might require
829 * RAM access */
830 {
831 if (offset >= 0x200 && offset < 0x380)
832 ramread = 1;
833 if (offset >= 0x10 && offset < 0x200)
834 ramread = 1;
835 }
836 /* read register from RAM or hardware, depending... */
837 if (ramread)
838 {
839 data = *dpr;
840 //pr_info("c4_musycc_rw: RAM addr %p read data %x (portno %x offset %x RAM ramread %x)\n", dpr, data, portnum, offset, ramread); /* RLD DEBUG */
841 } else
842 {
843 data = pci_read_32 ((u_int32_t *) dph);
844 //pr_info("c4_musycc_rw: REG addr %p read data %x (portno %x offset %x RAM ramread %x)\n", dph, data, portnum, offset, ramread); /* RLD DEBUG */
845 }
846
847
848 if (mcp->RWportnum & 0x80)
849 { /* control says this is a register
850 * _write_ */
851 if (mcp->value == data)
852 pr_info("%s: musycc grp%d already that value! writing again anyhow.\n",
853 ci->devname, (mcp->RWportnum & 0x7));
854 /* write register RAM */
855 if (ramread)
856 *dpr = mcp->value;
857 /* write hardware register */
858 pci_write_32 ((u_int32_t *) dph, mcp->value);
859 }
860 mcp->value = data; /* return the read value (or the 'old
861 * value', if is write) */
862 return 0;
863}
864
865status_t
866c4_get_port (ci_t *ci, int portnum)
867{
868 if (portnum >= ci->max_port) /* sanity check */
869 return -ENXIO;
870
871 SD_SEM_TAKE (&ci->sem_wdbusy, "_wd_"); /* only 1 thru here, per
872 * board */
873 checkPorts (ci);
874 ci->port[portnum].p.portStatus = (u_int8_t) ci->alarmed[portnum];
875 ci->alarmed[portnum] &= 0xdf;
876 SD_SEM_GIVE (&ci->sem_wdbusy); /* release per-board hold */
877 return 0;
878}
879
880status_t
881c4_set_port (ci_t *ci, int portnum)
882{
883 mpi_t *pi;
884 struct sbecom_port_param *pp;
885 int e1mode;
886 u_int8_t clck;
887 int i;
888
889 if (portnum >= ci->max_port) /* sanity check */
890 return -ENXIO;
891
892 pi = &ci->port[portnum];
893 pp = &ci->port[portnum].p;
894 e1mode = IS_FRAME_ANY_E1 (pp->port_mode);
895 if (cxt1e1_log_level >= LOG_MONITOR2)
896 {
897 pr_info("%s: c4_set_port[%d]: entered, e1mode = %x, openchans %d.\n",
898 ci->devname,
899 portnum, e1mode, pi->openchans);
900 }
901 if (pi->openchans)
902 return -EBUSY; /* group needs initialization only for
903 * first channel of a group */
904
905 {
906 status_t ret;
907
908 ret = c4_wq_port_init(pi);
909 if (ret) /* create/init workqueue_struct */
910 return ret;
911 }
912
913 init_comet (ci, pi->cometbase, pp->port_mode, 1 /* clockmaster == true */ , pp->portP);
914 clck = pci_read_32 ((u_int32_t *) &ci->cpldbase->mclk) & PMCC4_CPLD_MCLK_MASK;
915 if (e1mode)
916 clck |= 1 << portnum;
917 else
918 clck &= 0xf ^ (1 << portnum);
919
920 pci_write_32 ((u_int32_t *) &ci->cpldbase->mclk, clck);
921 pci_write_32 ((u_int32_t *) &ci->cpldbase->mcsr, PMCC4_CPLD_MCSR_IND);
922 pci_write_32 ((u_int32_t *) &pi->reg->gbp, OS_vtophys (pi->regram));
923
924 /*********************************************************************/
925 /* ERRATA: If transparent mode is used, do not set OOFMP_DISABLE bit */
926 /*********************************************************************/
927
928 pi->regram->grcd =
929 __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
930 MUSYCC_GRCD_TX_ENABLE |
931 MUSYCC_GRCD_OOFMP_DISABLE |
932 MUSYCC_GRCD_SF_ALIGN | /* per MUSYCC ERRATA,
933 * for T1 * fix */
934 MUSYCC_GRCD_COFAIRQ_DISABLE |
935 MUSYCC_GRCD_MC_ENABLE |
936 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
937
938 pi->regram->pcd =
939 __constant_cpu_to_le32 ((e1mode ? 1 : 0) |
940 MUSYCC_PCD_TXSYNC_RISING |
941 MUSYCC_PCD_RXSYNC_RISING |
942 MUSYCC_PCD_RXDATA_RISING);
943
944 /* Message length descriptor */
945 pi->regram->mld = __constant_cpu_to_le32 (cxt1e1_max_mru | (cxt1e1_max_mru << 16));
946
947 /* tsm algorithm */
948 for (i = 0; i < 32; i++)
949 {
950
951 /*** ASSIGNMENT NOTES: ***/
952 /*** Group's channel ZERO unavailable if E1. ***/
953 /*** Group's channel 16 unavailable if E1 CAS. ***/
954 /*** Group's channels 24-31 unavailable if T1. ***/
955
956 if (((i == 0) && e1mode) ||
957 ((i == 16) && ((pp->port_mode == CFG_FRAME_E1CRC_CAS) || (pp->port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
958 || ((i > 23) && (!e1mode)))
959 {
960 pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
961 } else
962 {
963 pi->tsm[i] = 0x00; /* make tslot available for assignment */
964 }
965 }
966 for (i = 0; i < MUSYCC_NCHANS; i++)
967 {
968 pi->regram->ttsm[i] = 0;
969 pi->regram->rtsm[i] = 0;
970 }
971 FLUSH_MEM_WRITE ();
972 musycc_serv_req (pi, SR_GROUP_INIT | SR_RX_DIRECTION);
973 musycc_serv_req (pi, SR_GROUP_INIT | SR_TX_DIRECTION);
974
975 musycc_init_mdt (pi);
976
977 pi->group_is_set = 1;
978 pi->p = *pp;
979 return 0;
980}
981
982
983unsigned int max_int = 0;
984
985status_t
986c4_new_chan (ci_t *ci, int portnum, int channum, void *user)
987{
988 mpi_t *pi;
989 mch_t *ch;
990 int gchan;
991
992 if (c4_find_chan (channum)) /* a new channel shouldn't already exist */
993 return -EEXIST;
994
995 if (portnum >= ci->max_port) /* sanity check */
996 return -ENXIO;
997
998 pi = &(ci->port[portnum]);
999 /* find any available channel within this port */
1000 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
1001 {
1002 ch = pi->chan[gchan];
1003 if (ch && ch->state == UNASSIGNED) /* no assignment is good! */
1004 break;
1005 }
1006 if (gchan == MUSYCC_NCHANS) /* exhausted table, all were assigned */
1007 return -ENFILE;
1008
1009 ch->up = pi;
1010
1011 /* NOTE: mch_t already cleared during OS_kmalloc() */
1012 ch->state = DOWN;
1013 ch->user = user;
1014 ch->gchan = gchan;
1015 ch->channum = channum; /* mark our channel assignment */
1016 ch->p.channum = channum;
1017#if 1
1018 ch->p.card = ci->brdno;
1019 ch->p.port = portnum;
1020#endif
1021 ch->p.chan_mode = CFG_CH_PROTO_HDLC_FCS16;
1022 ch->p.idlecode = CFG_CH_FLAG_7E;
1023 ch->p.pad_fill_count = 2;
1024 spin_lock_init (&ch->ch_rxlock);
1025 spin_lock_init (&ch->ch_txlock);
1026
1027 {
1028 status_t ret;
1029
1030 ret = c4_wk_chan_init(pi, ch);
1031 if (ret)
1032 return ret;
1033 }
1034
1035 /* save off interface assignments which bound a board */
1036 if (!ci->first_if) /* first channel registered is assumed to
1037 * be the lowest channel */
1038 {
1039 ci->first_if = ci->last_if = user;
1040 ci->first_channum = ci->last_channum = channum;
1041 } else
1042 {
1043 ci->last_if = user;
1044 if (ci->last_channum < channum) /* higher number channel found */
1045 ci->last_channum = channum;
1046 }
1047 return 0;
1048}
1049
1050status_t
1051c4_del_chan (int channum)
1052{
1053 mch_t *ch;
1054
1055 ch = c4_find_chan(channum);
1056 if (!ch)
1057 return -ENOENT;
1058
1059 if (ch->state == UP)
1060 musycc_chan_down ((ci_t *) 0, channum);
1061 ch->state = UNASSIGNED;
1062 ch->gchan = (-1);
1063 ch->channum = (-1);
1064 ch->p.channum = (-1);
1065 return 0;
1066}
1067
1068status_t
1069c4_del_chan_stats (int channum)
1070{
1071 mch_t *ch;
1072
1073 ch = c4_find_chan(channum);
1074 if (!ch)
1075 return -ENOENT;
1076
1077 memset (&ch->s, 0, sizeof (struct sbecom_chan_stats));
1078 return 0;
1079}
1080
1081
1082status_t
1083c4_set_chan (int channum, struct sbecom_chan_param *p)
1084{
1085 mch_t *ch;
1086 int i, x = 0;
1087
1088 ch = c4_find_chan(channum);
1089 if (!ch)
1090 return -ENOENT;
1091
1092#if 1
1093 if (ch->p.card != p->card ||
1094 ch->p.port != p->port ||
1095 ch->p.channum != p->channum)
1096 return -EINVAL;
1097#endif
1098
1099 if (!(ch->up->group_is_set))
1100 {
1101 return -EIO; /* out of order, SET_PORT command
1102 * required prior to first group's
1103 * SET_CHAN command */
1104 }
1105 /*
1106 * Check for change of parameter settings in order to invoke closing of
1107 * channel prior to hardware poking.
1108 */
1109
1110 if (ch->p.status != p->status || ch->p.chan_mode != p->chan_mode ||
1111 ch->p.data_inv != p->data_inv || ch->p.intr_mask != p->intr_mask ||
1112 ch->txd_free < ch->txd_num) /* to clear out queued messages */
1113 x = 1; /* we have a change requested */
1114 for (i = 0; i < 32; i++) /* check for timeslot mapping changes */
1115 if (ch->p.bitmask[i] != p->bitmask[i])
1116 x = 1; /* we have a change requested */
1117 ch->p = *p;
1118 if (x && (ch->state == UP)) /* if change request and channel is
1119 * open... */
1120 {
1121 status_t ret;
1122
1123 ret = musycc_chan_down((ci_t *)0, channum);
1124 if (ret)
1125 return ret;
1126 ret = c4_chan_up(ch->up->up, channum);
1127 if (ret)
1128 return ret;
1129 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
1130 * channel */
1131 }
1132 return 0;
1133}
1134
1135
1136status_t
1137c4_get_chan (int channum, struct sbecom_chan_param *p)
1138{
1139 mch_t *ch;
1140
1141 ch = c4_find_chan(channum);
1142 if (!ch)
1143 return -ENOENT;
1144
1145 *p = ch->p;
1146 return 0;
1147}
1148
1149status_t
1150c4_get_chan_stats (int channum, struct sbecom_chan_stats *p)
1151{
1152 mch_t *ch;
1153
1154 ch = c4_find_chan(channum);
1155 if (!ch)
1156 return -ENOENT;
1157
1158 *p = ch->s;
1159 p->tx_pending = atomic_read (&ch->tx_pending);
1160 return 0;
1161}
1162
1163static int
1164c4_fifo_alloc (mpi_t *pi, int chan, int *len)
1165{
1166 int i, l = 0, start = 0, max = 0, maxstart = 0;
1167
1168 for (i = 0; i < 32; i++)
1169 {
1170 if (pi->fifomap[i] != -1)
1171 {
1172 l = 0;
1173 start = i + 1;
1174 continue;
1175 }
1176 ++l;
1177 if (l > max)
1178 {
1179 max = l;
1180 maxstart = start;
1181 }
1182 if (max == *len)
1183 break;
1184 }
1185 if (max != *len)
1186 {
1187 if (cxt1e1_log_level >= LOG_WARN)
1188 pr_info("%s: wanted to allocate %d fifo space, but got only %d\n",
1189 pi->up->devname, *len, max);
1190 *len = max;
1191 }
1192 if (cxt1e1_log_level >= LOG_DEBUG)
1193 pr_info("%s: allocated %d fifo at %d for channel %d/%d\n",
1194 pi->up->devname, max, start, chan, pi->p.portnum);
1195 for (i = maxstart; i < (maxstart + max); i++)
1196 pi->fifomap[i] = chan;
1197 return start;
1198}
1199
1200void
1201c4_fifo_free (mpi_t *pi, int chan)
1202{
1203 int i;
1204
1205 if (cxt1e1_log_level >= LOG_DEBUG)
1206 pr_info("%s: deallocated fifo for channel %d/%d\n",
1207 pi->up->devname, chan, pi->p.portnum);
1208 for (i = 0; i < 32; i++)
1209 if (pi->fifomap[i] == chan)
1210 pi->fifomap[i] = -1;
1211}
1212
1213
1214status_t
1215c4_chan_up (ci_t *ci, int channum)
1216{
1217 mpi_t *pi;
1218 mch_t *ch;
1219 struct mbuf *m;
1220 struct mdesc *md;
1221 int nts, nbuf, txnum, rxnum;
1222 int addr, i, j, gchan;
1223 u_int32_t tmp; /* for optimizing conversion across BE
1224 * platform */
1225
1226 ch = c4_find_chan(channum);
1227 if (!ch)
1228 return -ENOENT;
1229
1230 if (ch->state == UP)
1231 {
1232 if (cxt1e1_log_level >= LOG_MONITOR)
1233 pr_info("%s: channel already UP, graceful early exit\n",
1234 ci->devname);
1235 return 0;
1236 }
1237 pi = ch->up;
1238 gchan = ch->gchan;
1239 /* find nts ('number of timeslots') */
1240 nts = 0;
1241 for (i = 0; i < 32; i++)
1242 {
1243 if (ch->p.bitmask[i] & pi->tsm[i])
1244 {
1245 if (1 || cxt1e1_log_level >= LOG_WARN)
1246 {
1247 pr_info("%s: c4_chan_up[%d] EINVAL (attempt to cfg in-use or unavailable TimeSlot[%d])\n",
1248 ci->devname, channum, i);
1249 pr_info("+ ask4 %x, currently %x\n",
1250 ch->p.bitmask[i], pi->tsm[i]);
1251 }
1252 return -EINVAL;
1253 }
1254 for (j = 0; j < 8; j++)
1255 if (ch->p.bitmask[i] & (1 << j))
1256 nts++;
1257 }
1258
1259 nbuf = nts / 8 ? nts / 8 : 1;
1260 if (!nbuf)
1261 {
1262 /* if( cxt1e1_log_level >= LOG_WARN) */
1263 pr_info("%s: c4_chan_up[%d] ENOBUFS (no TimeSlots assigned)\n",
1264 ci->devname, channum);
1265 return -ENOBUFS; /* this should not happen */
1266 }
1267 addr = c4_fifo_alloc (pi, gchan, &nbuf);
1268 ch->state = UP;
1269
1270 /* Setup the Time Slot Map */
1271 musycc_update_timeslots (pi);
1272
1273 /* ch->tx_limit = nts; */
1274 ch->s.tx_pending = 0;
1275
1276 /* Set Channel Configuration Descriptors */
1277 {
1278 u_int32_t ccd;
1279
1280 ccd = musycc_chan_proto (ch->p.chan_mode) << MUSYCC_CCD_PROTO_SHIFT;
1281 if ((ch->p.chan_mode == CFG_CH_PROTO_ISLP_MODE) ||
1282 (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1283 {
1284 ccd |= MUSYCC_CCD_FCS_XFER; /* Non FSC Mode */
1285 }
1286 ccd |= 2 << MUSYCC_CCD_MAX_LENGTH; /* Select second MTU */
1287 ccd |= ch->p.intr_mask;
1288 ccd |= addr << MUSYCC_CCD_BUFFER_LOC;
1289 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1290 ccd |= (nbuf) << MUSYCC_CCD_BUFFER_LENGTH;
1291 else
1292 ccd |= (nbuf - 1) << MUSYCC_CCD_BUFFER_LENGTH;
1293
1294 if (ch->p.data_inv & CFG_CH_DINV_TX)
1295 ccd |= MUSYCC_CCD_INVERT_DATA; /* Invert data */
1296 pi->regram->tcct[gchan] = cpu_to_le32 (ccd);
1297
1298 if (ch->p.data_inv & CFG_CH_DINV_RX)
1299 ccd |= MUSYCC_CCD_INVERT_DATA; /* Invert data */
1300 else
1301 ccd &= ~MUSYCC_CCD_INVERT_DATA; /* take away data inversion */
1302 pi->regram->rcct[gchan] = cpu_to_le32 (ccd);
1303 FLUSH_MEM_WRITE ();
1304 }
1305
1306 /* Reread the Channel Configuration Descriptor for this channel */
1307 musycc_serv_req (pi, SR_CHANNEL_CONFIG | SR_RX_DIRECTION | gchan);
1308 musycc_serv_req (pi, SR_CHANNEL_CONFIG | SR_TX_DIRECTION | gchan);
1309
1310 /*
1311 * Figure out how many buffers we want. If the customer has changed from
1312 * the defaults, then use the changed values. Otherwise, use Transparent
1313 * mode's specific minimum default settings.
1314 */
1315 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1316 {
1317 if (max_rxdesc_used == max_rxdesc_default) /* use default setting */
1318 max_rxdesc_used = MUSYCC_RXDESC_TRANS;
1319 if (max_txdesc_used == max_txdesc_default) /* use default setting */
1320 max_txdesc_used = MUSYCC_TXDESC_TRANS;
1321 }
1322 /*
1323 * Increase counts when hyperchanneling, since this implies an increase
1324 * in throughput per channel
1325 */
1326 rxnum = max_rxdesc_used + (nts / 4);
1327 txnum = max_txdesc_used + (nts / 4);
1328
1329#if 0
1330 /* DEBUG INFO */
1331 if (cxt1e1_log_level >= LOG_MONITOR)
1332 pr_info("%s: mode %x rxnum %d (rxused %d def %d) txnum %d (txused %d def %d)\n",
1333 ci->devname, ch->p.chan_mode,
1334 rxnum, max_rxdesc_used, max_rxdesc_default,
1335 txnum, max_txdesc_used, max_txdesc_default);
1336#endif
1337
1338 ch->rxd_num = rxnum;
1339 ch->txd_num = txnum;
1340 ch->rxix_irq_srv = 0;
1341
1342 ch->mdr = kzalloc(sizeof(struct mdesc) * rxnum, GFP_KERNEL | GFP_DMA);
1343 ch->mdt = kzalloc(sizeof(struct mdesc) * txnum, GFP_KERNEL | GFP_DMA);
1344 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1345 tmp = __constant_cpu_to_le32 (cxt1e1_max_mru | EOBIRQ_ENABLE);
1346 else
1347 tmp = __constant_cpu_to_le32 (cxt1e1_max_mru);
1348
1349 for (i = 0, md = ch->mdr; i < rxnum; i++, md++)
1350 {
1351 if (i == (rxnum - 1))
1352 {
1353 md->snext = &ch->mdr[0];/* wrapness */
1354 } else
1355 {
1356 md->snext = &ch->mdr[i + 1];
1357 }
1358 md->next = cpu_to_le32 (OS_vtophys (md->snext));
1359
1360 m = OS_mem_token_alloc(cxt1e1_max_mru);
1361 if (!m) {
1362 if (cxt1e1_log_level >= LOG_MONITOR)
1363 pr_info(
1364 "%s: c4_chan_up[%d] - token alloc failure, size = %d.\n",
1365 ci->devname, channum, cxt1e1_max_mru);
1366 goto errfree;
1367 }
1368 md->mem_token = m;
1369 md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m)));
1370 md->status = tmp | MUSYCC_RX_OWNED; /* MUSYCC owns RX descriptor **
1371 * CODING NOTE:
1372 * MUSYCC_RX_OWNED = 0 so no
1373 * need to byteSwap */
1374 }
1375
1376 for (i = 0, md = ch->mdt; i < txnum; i++, md++)
1377 {
1378 md->status = HOST_TX_OWNED; /* Host owns TX descriptor ** CODING
1379 * NOTE: HOST_TX_OWNED = 0 so no need to
1380 * byteSwap */
1381 md->mem_token = NULL;
1382 md->data = 0;
1383 if (i == (txnum - 1))
1384 {
1385 md->snext = &ch->mdt[0];/* wrapness */
1386 } else
1387 {
1388 md->snext = &ch->mdt[i + 1];
1389 }
1390 md->next = cpu_to_le32 (OS_vtophys (md->snext));
1391 }
1392 ch->txd_irq_srv = ch->txd_usr_add = &ch->mdt[0];
1393 ch->txd_free = txnum;
1394 ch->tx_full = 0;
1395 ch->txd_required = 0;
1396
1397 /* Configure it into the chip */
1398 tmp = cpu_to_le32 (OS_vtophys (&ch->mdt[0]));
1399 pi->regram->thp[gchan] = tmp;
1400 pi->regram->tmp[gchan] = tmp;
1401
1402 tmp = cpu_to_le32 (OS_vtophys (&ch->mdr[0]));
1403 pi->regram->rhp[gchan] = tmp;
1404 pi->regram->rmp[gchan] = tmp;
1405
1406 /* Activate the Channel */
1407 FLUSH_MEM_WRITE ();
1408 if (ch->p.status & RX_ENABLED)
1409 {
1410#ifdef RLD_TRANS_DEBUG
1411 pr_info("++ c4_chan_up() CHAN RX ACTIVATE: chan %d\n", ch->channum);
1412#endif
1413 ch->ch_start_rx = 0; /* we are restarting RX... */
1414 musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | gchan);
1415 }
1416 if (ch->p.status & TX_ENABLED)
1417 {
1418#ifdef RLD_TRANS_DEBUG
1419 pr_info("++ c4_chan_up() CHAN TX ACTIVATE: chan %d <delayed>\n", ch->channum);
1420#endif
1421 ch->ch_start_tx = CH_START_TX_1ST; /* we are delaying start
1422 * until receipt from user of
1423 * first packet to transmit. */
1424 }
1425 ch->status = ch->p.status;
1426 pi->openchans++;
1427 return 0;
1428
1429errfree:
1430 while (i > 0)
1431 {
1432 /* Don't leak all the previously allocated mbufs in this loop */
1433 i--;
1434 OS_mem_token_free (ch->mdr[i].mem_token);
1435 }
1436 kfree(ch->mdt);
1437 ch->mdt = NULL;
1438 ch->txd_num = 0;
1439 kfree(ch->mdr);
1440 ch->mdr = NULL;
1441 ch->rxd_num = 0;
1442 ch->state = DOWN;
1443 return -ENOBUFS;
1444}
1445
1446/* stop the hardware from servicing & interrupting */
1447
1448void
1449c4_stopwd (ci_t *ci)
1450{
1451 OS_stop_watchdog (&ci->wd);
1452 SD_SEM_TAKE (&ci->sem_wdbusy, "_stop_"); /* ensure WD not running */
1453 SD_SEM_GIVE (&ci->sem_wdbusy);
1454}
1455
1456
1457void
1458sbecom_get_brdinfo (ci_t *ci, struct sbe_brd_info *bip, u_int8_t *bsn)
1459{
1460 char *np;
1461 u_int32_t sn = 0;
1462 int i;
1463
1464 bip->brdno = ci->brdno; /* our board number */
1465 bip->brd_id = ci->brd_id;
1466 bip->brd_hdw_id = ci->hdw_bid;
1467 bip->brd_chan_cnt = MUSYCC_NCHANS *ci->max_port; /* number of channels
1468 * being used */
1469 bip->brd_port_cnt = ci->max_port; /* number of ports being used */
1470 bip->brd_pci_speed = BINFO_PCI_SPEED_unk; /* PCI speed not yet
1471 * determinable */
1472
1473 if (ci->first_if)
1474 {
1475 {
1476 struct net_device *dev;
1477
1478 dev = (struct net_device *) ci->first_if;
1479 np = (char *) dev->name;
1480 }
1481 strncpy (bip->first_iname, np, CHNM_STRLEN - 1);
1482 } else
1483 strcpy (bip->first_iname, "<NULL>");
1484 if (ci->last_if)
1485 {
1486 {
1487 struct net_device *dev;
1488
1489 dev = (struct net_device *) ci->last_if;
1490 np = (char *) dev->name;
1491 }
1492 strncpy (bip->last_iname, np, CHNM_STRLEN - 1);
1493 } else
1494 strcpy (bip->last_iname, "<NULL>");
1495
1496 if (bsn)
1497 {
1498 for (i = 0; i < 3; i++)
1499 {
1500 bip->brd_mac_addr[i] = *bsn++;
1501 }
1502 for (; i < 6; i++)
1503 {
1504 bip->brd_mac_addr[i] = *bsn;
1505 sn = (sn << 8) | *bsn++;
1506 }
1507 } else
1508 {
1509 for (i = 0; i < 6; i++)
1510 bip->brd_mac_addr[i] = 0;
1511 }
1512 bip->brd_sn = sn;
1513}
1514
1515
1516status_t
1517c4_get_iidinfo (ci_t *ci, struct sbe_iid_info *iip)
1518{
1519 struct net_device *dev;
1520 char *np;
1521
1522 dev = getuserbychan(iip->channum);
1523 if (!dev)
1524 return -ENOENT;
1525
1526 np = dev->name;
1527 strncpy (iip->iname, np, CHNM_STRLEN - 1);
1528 iip->iname[CHNM_STRLEN - 1] = '\0';
1529 return 0;
1530}
1531
1532
1533#ifdef CONFIG_SBE_PMCC4_NCOMM
1534void (*nciInterrupt[MAX_BOARDS][4]) (void);
1535extern void wanpmcC4T1E1_hookInterrupt (int cardID, int deviceID, void *handler);
1536
1537void
1538wanpmcC4T1E1_hookInterrupt (int cardID, int deviceID, void *handler)
1539{
1540 if (cardID < MAX_BOARDS) /* sanity check */
1541 nciInterrupt[cardID][deviceID] = handler;
1542}
1543
1544irqreturn_t
1545c4_ebus_intr_th_handler (void *devp)
1546{
1547 ci_t *ci = (ci_t *) devp;
1548 volatile u_int32_t ists;
1549 int handled = 0;
1550 int brdno;
1551
1552 /* which COMET caused the interrupt */
1553 brdno = ci->brdno;
1554 ists = pci_read_32 ((u_int32_t *) &ci->cpldbase->intr);
1555 if (ists & PMCC4_CPLD_INTR_CMT_1)
1556 {
1557 handled = 0x1;
1558 if (nciInterrupt[brdno][0] != NULL)
1559 (*nciInterrupt[brdno][0]) ();
1560 }
1561 if (ists & PMCC4_CPLD_INTR_CMT_2)
1562 {
1563 handled |= 0x2;
1564 if (nciInterrupt[brdno][1] != NULL)
1565 (*nciInterrupt[brdno][1]) ();
1566 }
1567 if (ists & PMCC4_CPLD_INTR_CMT_3)
1568 {
1569 handled |= 0x4;
1570 if (nciInterrupt[brdno][2] != NULL)
1571 (*nciInterrupt[brdno][2]) ();
1572 }
1573 if (ists & PMCC4_CPLD_INTR_CMT_4)
1574 {
1575 handled |= 0x8;
1576 if (nciInterrupt[brdno][3] != NULL)
1577 (*nciInterrupt[brdno][3]) ();
1578 }
1579#if 0
1580 /*** Test code just de-implements the asserted interrupt. Alternate
1581 vendor will supply COMET interrupt handling code herein or such.
1582 ***/
1583 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
1584#endif
1585
1586 return IRQ_RETVAL (handled);
1587}
1588
1589
1590unsigned long
1591wanpmcC4T1E1_getBaseAddress (int cardID, int deviceID)
1592{
1593 ci_t *ci;
1594 unsigned long base = 0;
1595
1596 ci = c4_list;
1597 while (ci)
1598 {
1599 if (ci->brdno == cardID) /* found valid device */
1600 {
1601 if (deviceID < ci->max_port) /* comet is supported */
1602 base = ((unsigned long) ci->port[deviceID].cometbase);
1603 break;
1604 }
1605 ci = ci->next; /* next board, if any */
1606 }
1607 return base;
1608}
1609
1610#endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
1611
1612
1613/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/pmcc4_ioctls.h b/drivers/staging/cxt1e1/pmcc4_ioctls.h
deleted file mode 100644
index 56a1ee39be18..000000000000
--- a/drivers/staging/cxt1e1/pmcc4_ioctls.h
+++ /dev/null
@@ -1,65 +0,0 @@
1#ifndef _INC_PMCC4_IOCTLS_H_
2#define _INC_PMCC4_IOCTLS_H_
3
4/*-----------------------------------------------------------------------------
5 * pmcc4_ioctls.h -
6 *
7 * Copyright (C) 2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *-----------------------------------------------------------------------------
22 */
23
24#include "sbew_ioc.h"
25
26enum
27{
28 // C4_GET_PORT = 0,
29 // C4_SET_PORT,
30 // C4_GET_CHAN,
31 // C4_SET_CHAN,
32 C4_DEL_CHAN = 0,
33 // C4_CREATE_CHAN,
34 // C4_GET_CHAN_STATS,
35 // C4_RESET,
36 // C4_DEBUG,
37 C4_RESET_STATS,
38 C4_LOOP_PORT,
39 C4_RW_FRMR,
40 C4_RW_MSYC,
41 C4_RW_PLD
42};
43
44#define C4_GET_PORT SBE_IOC_PORT_GET
45#define C4_SET_PORT SBE_IOC_PORT_SET
46#define C4_GET_CHAN SBE_IOC_CHAN_GET
47#define C4_SET_CHAN SBE_IOC_CHAN_SET
48// #define C4_DEL_CHAN XXX
49#define C4_CREATE_CHAN SBE_IOC_CHAN_NEW
50#define C4_GET_CHAN_STATS SBE_IOC_CHAN_GET_STAT
51#define C4_RESET SBE_IOC_RESET_DEV
52#define C4_DEBUG SBE_IOC_LOGLEVEL
53// #define C4_RESET_STATS XXX
54// #define C4_LOOP_PORT XXX
55// #define C4_RW_FRMR XXX
56// #define C4_RW_MSYC XXX
57// #define C4_RW_PLD XXX
58
59struct c4_chan_stats_wrap
60{
61 int channum;
62 struct sbecom_chan_stats stats;
63};
64
65#endif /* _INC_PMCC4_IOCTLS_H_ */
diff --git a/drivers/staging/cxt1e1/pmcc4_private.h b/drivers/staging/cxt1e1/pmcc4_private.h
deleted file mode 100644
index 134ddd6562e9..000000000000
--- a/drivers/staging/cxt1e1/pmcc4_private.h
+++ /dev/null
@@ -1,296 +0,0 @@
1#ifndef _INC_PMCC4_PRIVATE_H_
2#define _INC_PMCC4_PRIVATE_H_
3
4/*-----------------------------------------------------------------------------
5 * pmcc4_private.h -
6 *
7 * Copyright (C) 2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20
21#include <linux/kernel.h>
22#include <linux/sched.h>
23#include <linux/semaphore.h>
24#include <linux/spinlock.h>
25#include <linux/interrupt.h> /* support for tasklets */
26#include <linux/timer.h> /* support for timer */
27#include <linux/workqueue.h>
28#include <linux/hdlc.h>
29
30#include "libsbew.h"
31#include "pmcc4_defs.h"
32#include "pmcc4_cpld.h"
33#include "musycc.h"
34#include "sbe_promformat.h"
35#include "comet.h"
36#include "sbecom_inline_linux.h"
37
38
39/* driver state */
40#define SBE_DRVR_INIT 0x0
41#define SBE_DRVR_AVAILABLE 0x69734F4E
42#define SBE_DRVR_DOWN 0x1
43
44/******************************************************************************
45 * MUSYCC Message Descriptor - coupled to hardware implementation, the first
46 * three u_int32 must not be reordered.
47 */
48
49struct mdesc
50{
51 volatile u_int32_t status; /* Buffer Descriptor */
52 u_int32_t data; /* Data Pointer */
53 u_int32_t next; /* MUSYCC view of Next Pointer */
54 void *mem_token; /* Data */
55 struct mdesc *snext;
56};
57
58
59/*************************************************************************
60 * Private driver data structures, internal use only.
61 */
62
63struct c4_chan_info
64{
65 int gchan; /* channel number within group/port 0-31 */
66 int channum; /* absolute channel number 0-128 */
67 u_int8_t status;
68#define TX_RECOVERY_MASK 0x0f
69#define TX_ONR_RECOVERY 0x01
70#define TX_BUFF_RECOVERY 0x02
71#define RX_RECOVERY_MASK 0xf0
72#define RX_ONR_RECOVERY 0x10
73
74 unsigned char ch_start_rx;
75#define CH_START_RX_NOW 1
76#define CH_START_RX_ONR 2
77#define CH_START_RX_BUF 3
78
79 unsigned char ch_start_tx;
80#define CH_START_TX_1ST 1
81#define CH_START_TX_ONR 2
82#define CH_START_TX_BUF 3
83
84 char tx_full; /* boolean */
85 short txd_free; /* count of TX Desc available */
86 short txd_required; /* count of TX Desc needed by mesg */
87 unsigned short rxd_num; /* must support range up to 2000 */
88 unsigned short txd_num; /* must support range up to 1000 */
89 int rxix_irq_srv;
90
91 enum
92 {
93 UNASSIGNED, /* AVAILABLE, NOTINUSE */
94 DOWN, /* ASSIGNED, NOTINUSE */
95 UP /* ASSIGNED and INUSE */
96 } state;
97
98 struct c4_port_info *up;
99 void *user;
100
101 struct work_struct ch_work;
102 struct mdesc *mdt;
103 struct mdesc *mdr;
104 struct mdesc *txd_irq_srv;
105 struct mdesc *txd_usr_add;
106
107#if 0
108 /*
109 * FUTURE CODE MIGHT SEPARATE TIMESLOT MAP SETUPS INTO SINGLE IOCTL and
110 * REMOVE MAPS FROM CHANNEL PARAMETER STRUCTURE
111 */
112 /*
113 * each byte in bitmask below represents one timeslot (bitmask[0] is for
114 * timeslot 0 and so on), each bit in the byte selects timeslot bits for
115 * this channel (0xff - whole timeslot, 0x7f - 56kbps mode)
116 */
117
118 u_int8_t ts_bitmask[32];
119#endif
120 spinlock_t ch_rxlock;
121 spinlock_t ch_txlock;
122 atomic_t tx_pending;
123
124 struct sbecom_chan_stats s;
125 struct sbecom_chan_param p;
126};
127typedef struct c4_chan_info mch_t;
128
129struct c4_port_info
130{
131
132 struct musycc_globalr *reg;
133 struct musycc_groupr *regram;
134 void *regram_saved; /* Original malloc value may have non-2KB
135 * boundary. Need to save for use when
136 * freeing. */
137 struct s_comet_reg *cometbase;
138 struct sbe_card_info *up;
139
140 /*
141 * The workqueue is used for TX restart of ONR'd channels when in
142 * Transparent mode.
143 */
144
145 struct workqueue_struct *wq_port; /* chan restart work queue */
146 struct semaphore sr_sem_busy; /* service request exclusion
147 * semaphore */
148 struct semaphore sr_sem_wait; /* service request handshake
149 * semaphore */
150 u_int32_t sr_last;
151 short openchans;
152 char portnum;
153 char group_is_set; /* GROUP_INIT command issued to MUSYCC,
154 * otherwise SET_CHAN Ioctl fails */
155
156 mch_t *chan[MUSYCC_NCHANS];
157 struct sbecom_port_param p;
158
159 /*
160 * The MUSYCC timeslot mappings are maintained within the driver and are
161 * modified and reloaded as each of a group's channels are configured.
162 */
163 u_int8_t tsm[32]; /* tsm (time slot map) */
164 int fifomap[32];
165};
166typedef struct c4_port_info mpi_t;
167
168
169#define COMET_OFFSET(x) (0x80000+(x)*0x10000)
170#define EEPROM_OFFSET 0xC0000
171#define ISPLD_OFFSET 0xD0000
172
173/* iSPLD control chip registers */
174#define ISPLD_MCSR 0x0
175#define ISPLD_MCLK 0x1
176#define ISPLD_LEDS 0x2
177#define ISPLD_INTR 0x3
178#define ISPLD_MAX 0x3
179
180struct sbe_card_info
181{
182 struct musycc_globalr *reg;
183 struct musycc_groupr *regram;
184 u_int32_t *iqd_p; /* pointer to dword aligned interrupt queue
185 * descriptors */
186 void *iqd_p_saved; /* Original malloc value may have non-dword
187 * aligned boundary. Need to save for use
188 * when freeing. */
189 unsigned int iqp_headx, iqp_tailx;
190
191 struct semaphore sem_wdbusy;/* watchdog exclusion semaphore */
192 struct watchdog wd; /* statically allocated watchdog structure */
193 atomic_t bh_pending; /* bh queued, but not yet running */
194 u_int32_t brd_id; /* unique PCI ID */
195 u_int16_t hdw_bid; /* on/board hardware ID */
196 unsigned short wdcount;
197 unsigned char max_port;
198 unsigned char brdno; /* our board number */
199 unsigned char wd_notify;
200#define WD_NOTIFY_1TX 1
201#define WD_NOTIFY_BUF 2
202#define WD_NOTIFY_ONR 4
203 enum /* state as regards interrupt processing */
204 {
205 C_INIT, /* of-board-address not configured or are in
206 * process of being removed, don't access
207 * hardware */
208 C_IDLE, /* off-board-addresses are configured, but
209 * don't service interrupts, just clear them
210 * from hardware */
211 C_RUNNING /* life is good, service away */
212 } state;
213
214 struct sbe_card_info *next;
215 u_int32_t *eeprombase; /* mapped address of board's EEPROM */
216 c4cpld_t *cpldbase; /* mapped address of board's CPLD hardware */
217 void *hdw_info;
218#ifdef CONFIG_PROC_FS
219 struct proc_dir_entry *dir_dev;
220#endif
221
222 /* saved off interface assignments which bound a board */
223 hdlc_device *first_if;
224 hdlc_device *last_if;
225 short first_channum, last_channum;
226
227 struct intlog
228 {
229 u_int32_t this_status_new;
230 u_int32_t last_status_new;
231 u_int32_t drvr_intr_thcount;
232 u_int32_t drvr_intr_bhcount;
233 u_int32_t drvr_int_failure;
234 } intlog;
235
236 mpi_t port[MUSYCC_NPORTS];
237 char devname[SBE_IFACETMPL_SIZE + 1];
238 atomic_t tx_pending;
239 u_int32_t alarmed[4]; /* dpm211 */
240
241#if defined(SBE_ISR_TASKLET)
242 struct tasklet_struct ci_musycc_isr_tasklet;
243#elif defined(SBE_ISR_IMMEDIATE)
244 struct tq_struct ci_musycc_isr_tq;
245#endif
246};
247typedef struct sbe_card_info ci_t;
248
249struct s_hdw_info
250{
251 u_int8_t pci_busno;
252 u_int8_t pci_slot;
253 u_int8_t pci_pin[2];
254 u_int8_t revid[2];
255 u_int8_t mfg_info_sts;
256#define EEPROM_OK 0x00
257#define EEPROM_CRCERR 0x01
258 char promfmt; /* prom type, from sbe_promformat.h */
259
260 char devname[SBE_IFACETMPL_SIZE];
261 struct pci_bus *bus;
262 struct net_device *ndev;
263 struct pci_dev *pdev[2];
264
265 unsigned long addr[2];
266 void __iomem *addr_mapped[2];
267 unsigned long len[2];
268
269 union
270 {
271 char data[128];
272 FLD_TYPE1 pft1; /* prom field, type #1 */
273 FLD_TYPE2 pft2; /* prom field, type #2 */
274 } mfg_info;
275};
276typedef struct s_hdw_info hdw_info_t;
277
278/*****************************************************************/
279
280struct c4_priv
281{
282 int channum;
283 struct sbe_card_info *ci;
284};
285
286
287/*****************************************************************/
288
289extern ci_t *c4_list;
290
291mch_t *c4_find_chan (int);
292int c4_set_chan (int channum, struct sbecom_chan_param *);
293int c4_get_chan (int channum, struct sbecom_chan_param *);
294int c4_get_chan_stats (int channum, struct sbecom_chan_stats *);
295
296#endif /* _INC_PMCC4_PRIVATE_H_ */
diff --git a/drivers/staging/cxt1e1/pmcc4_sysdep.h b/drivers/staging/cxt1e1/pmcc4_sysdep.h
deleted file mode 100644
index 2916c2cb13f9..000000000000
--- a/drivers/staging/cxt1e1/pmcc4_sysdep.h
+++ /dev/null
@@ -1,63 +0,0 @@
1#ifndef _INC_PMCC4_SYSDEP_H_
2#define _INC_PMCC4_SYSDEP_H_
3
4/*-----------------------------------------------------------------------------
5 * pmcc4_sysdep.h -
6 *
7 * Copyright (C) 2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20/* reduce multiple autoconf entries to a single definition */
21
22#ifdef CONFIG_SBE_PMCC4_HDLC_V7_MODULE
23#undef CONFIG_SBE_PMCC4_HDLC_V7
24#define CONFIG_SBE_PMCC4_HDLC_V7 1
25#endif
26
27#ifdef CONFIG_SBE_PMCC4_NCOMM_MODULE
28#undef CONFIG_SBE_PMCC4_NCOMM
29#define CONFIG_SBE_PMCC4_NCOMM 1
30#endif
31
32
33/* FLUSH MACROS - if using ioremap_nocache(), then these can be NOOPS,
34 * otherwise a memory barrier needs to be inserted.
35 */
36
37#define FLUSH_PCI_READ() rmb()
38#define FLUSH_PCI_WRITE() wmb()
39#define FLUSH_MEM_READ() rmb()
40#define FLUSH_MEM_WRITE() wmb()
41
42
43/*
44 * System dependent callbacks routines, not inlined...
45 * For inlined system dependent routines, see include/sbecom_inlinux_linux.h
46 */
47
48/*
49 * passes received memory token back to the system, <user> is parameter from
50 * sd_new_chan() used to create the channel which the data arrived on
51 */
52
53void sd_recv_consume(void *token, size_t len, void *user);
54
55void sd_disable_xmit (void *user);
56void sd_enable_xmit (void *user);
57int sd_line_is_ok (void *user);
58void sd_line_is_up (void *user);
59void sd_line_is_down (void *user);
60int sd_queue_stopped (void *user);
61
62#endif /*** _INC_PMCC4_SYSDEP_H_ ***/
63extern int cxt1e1_log_level;
diff --git a/drivers/staging/cxt1e1/sbe_bid.h b/drivers/staging/cxt1e1/sbe_bid.h
deleted file mode 100644
index abc2e55f62fc..000000000000
--- a/drivers/staging/cxt1e1/sbe_bid.h
+++ /dev/null
@@ -1,47 +0,0 @@
1#ifndef _INC_SBEBID_H_
2#define _INC_SBEBID_H_
3
4/*-----------------------------------------------------------------------------
5 * sbe_bid.h -
6 *
7 * Copyright (C) 2004-2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *
22 *-----------------------------------------------------------------------------
23 */
24
25#define SBE_BID_REG 0x00000000 /* Board ID Register */
26
27#define SBE_BID_256T3_E1 0x46 /* SBE wanPTMC-256T3 (E1 Version) */
28#define SBE_BID_256T3_T1 0x42 /* SBE wanPTMC-256T3 (T1 Version) */
29#define SBE_BID_2T3E3 0x43 /* SBE wanPMC-2T3E3 */
30#define SBE_BID_C1T3 0x45 /* SBE wanPMC-C1T3 */
31#define SBE_BID_C24TE1 0x47 /* SBE wanPTMC-C24TE1 */
32#define SBE_BID_C24TE1_RTM_24 0x48 /* C24TE1 RTM (24 Port) */
33#define SBE_BID_C24TE1_RTM_12 0x49 /* C24TE1 RTM (12 Port) */
34#define SBE_BID_C24TE1_RTM_12DSU 0x4A /* C24TE1 RTM (12 Port/DSU) */
35#define SBE_BID_C24TE1_RTM_T3 0x4B /* C24TE1 RTM (T3) */
36#define SBE_BID_C4T1E1 0x41 /* SBE wanPTMC-C4T1E1 */
37#define SBE_BID_HC4T1E1 0x44 /* SBE wanADAPT-HC4T1E1 */
38
39/* bogus temporary usage values */
40#define SBE_BID_PMC_C4T1E1 0xC4 /* SBE wanPMC-C4T1E1 (4 Port) */
41#define SBE_BID_PMC_C2T1E1 0xC2 /* SBE wanPMC-C2T1E1 (2 Port) */
42#define SBE_BID_PMC_C1T1E1 0xC1 /* SBE wanPMC-C1T1E1 (1 Port) */
43#define SBE_BID_PCI_C4T1E1 0x04 /* SBE wanPCI-C4T1E1 (4 Port) */
44#define SBE_BID_PCI_C2T1E1 0x02 /* SBE wanPCI-C2T1E1 (2 Port) */
45#define SBE_BID_PCI_C1T1E1 0x01 /* SBE wanPCI-C1T1E1 (1 Port) */
46
47#endif /*** _INC_SBEBID_H_ ***/
diff --git a/drivers/staging/cxt1e1/sbe_promformat.h b/drivers/staging/cxt1e1/sbe_promformat.h
deleted file mode 100644
index aad411d185f5..000000000000
--- a/drivers/staging/cxt1e1/sbe_promformat.h
+++ /dev/null
@@ -1,130 +0,0 @@
1#ifndef _INC_SBE_PROMFORMAT_H_
2#define _INC_SBE_PROMFORMAT_H_
3
4/*-----------------------------------------------------------------------------
5 * sbe_promformat.h - Contents of seeprom used by dvt and manufacturing tests
6 *
7 * Copyright (C) 2002-2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *
22 *-----------------------------------------------------------------------------
23 */
24
25
26/***
27 * PMCC4 SAMPLE EEPROM IMAGE
28 *
29 * eeprom[00]: 01 11 76 07 01 00 a0 d6
30 * eeprom[08]: 22 34 56 3e 5b c1 1c 3e
31 * eeprom[16]: 5b e1 b6 00 00 00 01 00
32 * eeprom[24]: 00 08 46 d3 7b 5e a8 fb
33 * eeprom[32]: f7 ef df bf 7f 55 00 01
34 * eeprom[40]: 02 04 08 10 20 40 80 ff
35 * eeprom[48]: fe fd fb f7 ef df bf 7f
36 *
37 ***/
38
39
40/*------------------------------------------------------------------------
41 * Type 1 Format
42 * byte:
43 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
44 * -------------------------------------------------------------------------
45 * 01 11 76 SS SS 00 0A D6 <SERIAL NUM> <Create TIME> <Heatrun TIME>
46 * SBE SUB SERIAL # (BCD) (time_t) (time_t)
47 * ID VENDOR (format) (format)
48 *
49 * 19 20 21 22 23 24 25 26
50 * Heat Run Heat Run
51 * Iterations Errors
52 *------------------------------------------------------------------------
53 *
54 *
55 *
56 * Type 2 Format - Added length, CRC in fixed position
57 * byte:
58 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
59 * -------------------------------------------------------------------------
60 * 02 00 1A CC CC CC CC 11 76 07 03 00 0A D6 <SERIAL NUM>
61 * Payload SBE Crc32 SUB System System SERIAL/MAC
62 * Length VENDOR ID ID
63 *
64 * 17 18 19 20 21 22 23 24 25 26 27 28 29 39 31 32
65 * --------------------------------------------------------------------------
66 * <Create TIME> <Heatrun TIME> Heat Run Heat Run
67 * (time_t) (time_t) Iterations Errors
68 *
69 */
70
71#define STRUCT_OFFSET(type, symbol) ((long)&(((type *)0)->symbol))
72
73/*------------------------------------------------------------------------
74 * Historically different Prom format types.
75 *
76 * For diagnostic and failure purposes, do not create a type 0x00 or a
77 * type 0xff
78 *------------------------------------------------------------------------
79 */
80#define PROM_FORMAT_Unk (-1)
81#define PROM_FORMAT_TYPE1 1
82#define PROM_FORMAT_TYPE2 2
83
84
85/****** bit fields for a type 1 formatted seeprom **************************/
86 typedef struct
87 {
88 char type; /* 0x00 */
89 char Id[2]; /* 0x01-0x02 */
90 char SubId[2]; /* 0x03-0x04 */
91 char Serial[6]; /* 0x05-0x0a */
92 char CreateTime[4]; /* 0x0b-0x0e */
93 char HeatRunTime[4]; /* 0x0f-0x12 */
94 char HeatRunIterations[4]; /* 0x13-0x16 */
95 char HeatRunErrors[4]; /* 0x17-0x1a */
96 char Crc32[4]; /* 0x1b-0x1e */
97 } FLD_TYPE1;
98
99
100/****** bit fields for a type 2 formatted seeprom **************************/
101 typedef struct
102 {
103 char type; /* 0x00 */
104 char length[2]; /* 0x01-0x02 */
105 char Crc32[4]; /* 0x03-0x06 */
106 char Id[2]; /* 0x07-0x08 */
107 char SubId[2]; /* 0x09-0x0a */
108 char Serial[6]; /* 0x0b-0x10 */
109 char CreateTime[4]; /* 0x11-0x14 */
110 char HeatRunTime[4]; /* 0x15-0x18 */
111 char HeatRunIterations[4]; /* 0x19-0x1c */
112 char HeatRunErrors[4]; /* 0x1d-0x20 */
113 } FLD_TYPE2;
114
115
116
117/***** this union allows us to access the seeprom as an array of bytes ***/
118/***** or as individual fields ***/
119
120#define SBE_EEPROM_SIZE 128
121#define SBE_MFG_INFO_SIZE sizeof(FLD_TYPE2)
122
123 typedef union
124 {
125 char bytes[128];
126 FLD_TYPE1 fldType1;
127 FLD_TYPE2 fldType2;
128 } PROMFORMAT;
129
130#endif /*** _INC_SBE_PROMFORMAT_H_ ***/
diff --git a/drivers/staging/cxt1e1/sbecom_inline_linux.h b/drivers/staging/cxt1e1/sbecom_inline_linux.h
deleted file mode 100644
index f5835c29ef32..000000000000
--- a/drivers/staging/cxt1e1/sbecom_inline_linux.h
+++ /dev/null
@@ -1,193 +0,0 @@
1#ifndef _INC_SBECOM_INLNX_H_
2#define _INC_SBECOM_INLNX_H_
3
4/*-----------------------------------------------------------------------------
5 * sbecom_inline_linux.h - SBE common Linux inlined routines
6 *
7 * Copyright (C) 2007 One Stop Systems, Inc.
8 * Copyright (C) 2005 SBE, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * For further information, contact via email: support@onestopsystems.com
21 * One Stop Systems, Inc. Escondido, California U.S.A.
22 *-----------------------------------------------------------------------------
23 */
24
25
26#include <linux/types.h>
27#include <linux/module.h>
28#include <linux/kernel.h> /* resolves kmalloc references */
29#include <linux/skbuff.h> /* resolves skb references */
30#include <linux/netdevice.h> /* resolves dev_kree_skb_any */
31#include <asm/byteorder.h> /* resolves cpu_to_le32 */
32
33/* forward reference */
34u_int32_t pci_read_32 (u_int32_t *p);
35void pci_write_32 (u_int32_t *p, u_int32_t v);
36
37
38/*
39 * system dependent callbacks
40 */
41
42/****************/
43/* memory token */
44/****************/
45
46static inline void *
47OS_mem_token_alloc (size_t size)
48{
49 struct sk_buff *skb;
50
51 skb = dev_alloc_skb (size);
52 if (!skb)
53 {
54 //pr_warning("no mem in OS_mem_token_alloc !\n");
55 return NULL;
56 }
57 return skb;
58}
59
60
61static inline void
62OS_mem_token_free (void *token)
63{
64 dev_kfree_skb_any (token);
65}
66
67
68static inline void
69OS_mem_token_free_irq (void *token)
70{
71 dev_kfree_skb_irq (token);
72}
73
74
75static inline void *
76OS_mem_token_data (void *token)
77{
78 return ((struct sk_buff *) token)->data;
79}
80
81
82static inline void *
83OS_mem_token_next (void *token)
84{
85 return NULL;
86}
87
88
89static inline int
90OS_mem_token_len (void *token)
91{
92 return ((struct sk_buff *) token)->len;
93}
94
95
96static inline int
97OS_mem_token_tlen (void *token)
98{
99 return ((struct sk_buff *) token)->len;
100}
101
102
103/***************************************/
104/* virtual to physical addr conversion */
105/***************************************/
106
107static inline u_long
108OS_phystov (void *addr)
109{
110 return (u_long) __va (addr);
111}
112
113
114static inline u_long
115OS_vtophys (void *addr)
116{
117 return __pa (addr);
118}
119
120
121/**********/
122/* semops */
123/**********/
124
125void OS_sem_init (void *, int);
126
127
128static inline void
129OS_sem_free (void *sem)
130{
131 /*
132 * NOOP - since semaphores structures predeclared w/in structures, no
133 * longer malloc'd
134 */
135}
136
137#define SD_SEM_TAKE(sem,desc) down(sem)
138#define SD_SEM_GIVE(sem) up(sem)
139#define SEM_AVAILABLE 1
140#define SEM_TAKEN 0
141
142
143/**********************/
144/* watchdog functions */
145/**********************/
146
147struct watchdog
148{
149 struct timer_list h;
150 struct work_struct work;
151 void *softc;
152 void (*func) (void *softc);
153 int ticks;
154 int init_tq;
155};
156
157
158static inline int
159OS_start_watchdog (struct watchdog *wd)
160{
161 wd->h.expires = jiffies + wd->ticks;
162 add_timer (&wd->h);
163 return 0;
164}
165
166
167static inline int
168OS_stop_watchdog (struct watchdog *wd)
169{
170 del_timer_sync (&wd->h);
171 return 0;
172}
173
174
175static inline int
176OS_free_watchdog (struct watchdog *wd)
177{
178 OS_stop_watchdog (wd);
179 kfree(wd);
180 return 0;
181}
182
183
184/* sleep in microseconds */
185void OS_uwait (int usec, char *description);
186void OS_uwait_dummy (void);
187
188
189/* watchdog functions */
190int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *), void *ci, int usec);
191
192
193#endif /*** _INC_SBECOM_INLNX_H_ ***/
diff --git a/drivers/staging/cxt1e1/sbecrc.c b/drivers/staging/cxt1e1/sbecrc.c
deleted file mode 100644
index 52d3f71e5470..000000000000
--- a/drivers/staging/cxt1e1/sbecrc.c
+++ /dev/null
@@ -1,134 +0,0 @@
1/* Based on "File Verification Using CRC" by Mark R. Nelson in Dr. Dobbs'
2 * Journal, May 1992, pp. 64-67. This algorithm generates the same CRC
3 * values as ZMODEM and PKZIP
4 *
5 * Copyright (C) 2002-2005 SBE, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/types.h>
19#include "pmcc4.h"
20#include "pmcc4_sysdep.h"
21#include "sbecom_inline_linux.h"
22#include "sbe_promformat.h"
23
24/* defines */
25#define CRC32_POLYNOMIAL 0xEDB88320L
26#define CRC_TABLE_ENTRIES 256
27
28
29
30static u_int32_t crcTableInit;
31
32#ifdef STATIC_CRC_TABLE
33static u_int32_t CRCTable[CRC_TABLE_ENTRIES];
34
35#endif
36
37
38/***************************************************************************
39*
40* genCrcTable - fills in CRCTable, as used by sbeCrc()
41*
42* RETURNS: N/A
43*
44* ERRNO: N/A
45***************************************************************************/
46
47static void
48genCrcTable(u_int32_t *CRCTable)
49{
50 int ii, jj;
51 u_int32_t crc;
52
53 for (ii = 0; ii < CRC_TABLE_ENTRIES; ii++) {
54 crc = ii;
55 for (jj = 8; jj > 0; jj--) {
56 if (crc & 1)
57 crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
58 else
59 crc >>= 1;
60 }
61 CRCTable[ii] = crc;
62 }
63
64 crcTableInit++;
65}
66
67
68/***************************************************************************
69*
70* sbeCrc - generates a CRC on a given buffer, and initial CRC
71*
72* This routine calculates the CRC for a buffer of data using the
73* table lookup method. It accepts an original value for the crc,
74* and returns the updated value. This permits "catenation" of
75* discontiguous buffers. An original value of 0 for the "first"
76* buffer is the norm.
77*
78* Based on "File Verification Using CRC" by Mark R. Nelson in Dr. Dobb's
79* Journal, May 1992, pp. 64-67. This algorithm generates the same CRC
80* values as ZMODEM and PKZIP.
81*
82* RETURNS: calculated crc of block
83*
84*/
85
86void
87sbeCrc(u_int8_t *buffer, /* data buffer to crc */
88 u_int32_t count, /* length of block in bytes */
89 u_int32_t initialCrc, /* starting CRC */
90 u_int32_t *result)
91{
92 u_int32_t *tbl = NULL;
93 u_int32_t temp1, temp2, crc;
94
95 /*
96 * if table not yet created, do so. Don't care about "extra" time
97 * checking this every time sbeCrc() is called, since CRC calculations
98 * are already time consuming
99 */
100 if (!crcTableInit) {
101#ifdef STATIC_CRC_TABLE
102 tbl = &CRCTable;
103 genCrcTable(tbl);
104#else
105 tbl = kzalloc(CRC_TABLE_ENTRIES * sizeof(u_int32_t),
106 GFP_KERNEL);
107 if (!tbl) {
108 *result = 0; /* dummy up return value due to malloc
109 * failure */
110 return;
111 }
112 genCrcTable(tbl);
113#endif
114 }
115 /* inverting bits makes ZMODEM & PKZIP compatible */
116 crc = initialCrc ^ 0xFFFFFFFFL;
117
118 while (count-- != 0) {
119 temp1 = (crc >> 8) & 0x00FFFFFFL;
120 temp2 = tbl[((int) crc ^ *buffer++) & 0xff];
121 crc = temp1 ^ temp2;
122 }
123
124 crc ^= 0xFFFFFFFFL;
125
126 *result = crc;
127
128#ifndef STATIC_CRC_TABLE
129 crcTableInit = 0;
130 kfree(tbl);
131#endif
132}
133
134/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/sbeid.c b/drivers/staging/cxt1e1/sbeid.c
deleted file mode 100644
index 97c5c6e7e299..000000000000
--- a/drivers/staging/cxt1e1/sbeid.c
+++ /dev/null
@@ -1,205 +0,0 @@
1/* Copyright (C) 2005 SBE, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/types.h>
15#include "pmcc4_sysdep.h"
16#include "sbecom_inline_linux.h"
17#include "libsbew.h"
18#include "pmcc4_private.h"
19#include "pmcc4.h"
20#include "sbe_bid.h"
21
22char *
23sbeid_get_bdname(ci_t *ci)
24{
25 char *np = NULL;
26
27 switch (ci->brd_id) {
28 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_256T3_E1):
29 np = "wanPTMC-256T3 <E1>";
30 break;
31 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_256T3_T1):
32 np = "wanPTMC-256T3 <T1>";
33 break;
34 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C4T1E1):
35 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C4T1E1_L):
36 np = "wanPMC-C4T1E1";
37 break;
38 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C2T1E1):
39 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C2T1E1_L):
40 np = "wanPMC-C2T1E1";
41 break;
42 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T1E1):
43 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T1E1_L):
44 np = "wanPMC-C1T1E1";
45 break;
46 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C4T1E1):
47 np = "wanPCI-C4T1E1";
48 break;
49 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C2T1E1):
50 np = "wanPCI-C2T1E1";
51 break;
52 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C1T1E1):
53 np = "wanPCI-C1T1E1";
54 break;
55 default:
56 /*** np = "<unknown>"; ***/
57 np = "wanPCI-CxT1E1";
58 break;
59 }
60
61 return np;
62}
63
64
65/* given the presetting of brd_id, set the corresponding hdw_id */
66
67void
68sbeid_set_hdwbid(ci_t *ci)
69{
70 /*
71 * set SBE's unique hardware identification (for legacy boards might not
72 * have this register implemented)
73 */
74
75 switch (ci->brd_id) {
76 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_256T3_E1):
77 ci->hdw_bid = SBE_BID_256T3_E1; /* 0x46 - SBE wanPTMC-256T3 (E1
78 * Version) */
79 break;
80 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_256T3_T1):
81 ci->hdw_bid = SBE_BID_256T3_T1; /* 0x42 - SBE wanPTMC-256T3 (T1
82 * Version) */
83 break;
84 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C4T1E1):
85 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C4T1E1_L):
86 /*
87 * This Board ID is a generic identification. Use the found number
88 * of ports to further define this hardware.
89 */
90 switch (ci->max_port) {
91 default: /* shouldn't need a default, but have one
92 * anyway */
93 case 4:
94 ci->hdw_bid = SBE_BID_PMC_C4T1E1; /* 0xC4 - SBE wanPMC-C4T1E1 */
95 break;
96 case 2:
97 ci->hdw_bid = SBE_BID_PMC_C2T1E1; /* 0xC2 - SBE wanPMC-C2T1E1 */
98 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C2T1E1);
99 break;
100 case 1:
101 ci->hdw_bid = SBE_BID_PMC_C1T1E1; /* 0xC1 - SBE wanPMC-C1T1E1 */
102 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T1E1);
103 break;
104 }
105 break;
106 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C2T1E1):
107 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C2T1E1_L):
108 ci->hdw_bid = SBE_BID_PMC_C2T1E1; /* 0xC2 - SBE wanPMC-C2T1E1 */
109 break;
110 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T1E1):
111 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T1E1_L):
112 ci->hdw_bid = SBE_BID_PMC_C1T1E1; /* 0xC1 - SBE wanPMC-C1T1E1 */
113 break;
114#ifdef SBE_PMCC4_ENABLE
115 /*
116 * This case is entered as a result of the inability to obtain the
117 * <bid> from the board's EEPROM. Assume a PCI board and set
118 * <hdsbid> according to the number ofr found ports.
119 */
120 case 0:
121 /* start by assuming 4-port for ZERO casing */
122 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C4T1E1);
123 /* drop thru to set hdw_bid and alternate PCI CxT1E1 settings */
124#endif
125 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C4T1E1):
126 /*
127 * This Board ID is a generic identification. Use the number of
128 * found ports to further define this hardware.
129 */
130 switch (ci->max_port) {
131 default: /* shouldn't need a default, but have one
132 * anyway */
133 case 4:
134 ci->hdw_bid = SBE_BID_PCI_C4T1E1; /* 0x04 - SBE wanPCI-C4T1E1 */
135 break;
136 case 2:
137 ci->hdw_bid = SBE_BID_PCI_C2T1E1; /* 0x02 - SBE wanPCI-C2T1E1 */
138 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C2T1E1);
139 break;
140 case 1:
141 ci->hdw_bid = SBE_BID_PCI_C1T1E1; /* 0x01 - SBE wanPCI-C1T1E1 */
142 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C1T1E1);
143 break;
144 }
145 break;
146 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C2T1E1):
147 ci->hdw_bid = SBE_BID_PCI_C2T1E1; /* 0x02 - SBE wanPCI-C2T1E1 */
148 break;
149 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C1T1E1):
150 ci->hdw_bid = SBE_BID_PCI_C1T1E1; /* 0x01 - SBE wanPCI-C1T1E1 */
151 break;
152 default:
153 /*** bid = "<unknown>"; ***/
154 ci->hdw_bid = SBE_BID_PMC_C4T1E1; /* 0x41 - SBE wanPTMC-C4T1E1 */
155 break;
156 }
157}
158
159/* given the presetting of hdw_bid, set the corresponding brd_id */
160
161void
162sbeid_set_bdtype(ci_t *ci)
163{
164 /* set SBE's unique PCI VENDOR/DEVID */
165 switch (ci->hdw_bid) {
166 case SBE_BID_C1T3: /* SBE wanPMC-C1T3 */
167 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T3);
168 break;
169 case SBE_BID_C24TE1: /* SBE wanPTMC-C24TE1 */
170 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_C24TE1);
171 break;
172 case SBE_BID_256T3_E1: /* SBE wanPTMC-256T3 E1 Version */
173 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_256T3_E1);
174 break;
175 case SBE_BID_256T3_T1: /* SBE wanPTMC-256T3 T1 Version */
176 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_256T3_T1);
177 break;
178 case SBE_BID_PMC_C4T1E1: /* 0xC4 - SBE wanPMC-C4T1E1 */
179 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C4T1E1);
180 break;
181 case SBE_BID_PMC_C2T1E1: /* 0xC2 - SBE wanPMC-C2T1E1 */
182 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C2T1E1);
183 break;
184 case SBE_BID_PMC_C1T1E1: /* 0xC1 - SBE wanPMC-C1T1E1 */
185 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T1E1);
186 break;
187 case SBE_BID_PCI_C4T1E1: /* 0x04 - SBE wanPCI-C4T1E1 */
188 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C4T1E1);
189 break;
190 case SBE_BID_PCI_C2T1E1: /* 0x02 - SBE wanPCI-C2T1E1 */
191 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C2T1E1);
192 break;
193 case SBE_BID_PCI_C1T1E1: /* 0x01 - SBE wanPCI-C1T1E1 */
194 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C1T1E1);
195 break;
196
197 default:
198 /*** hdw_bid = "<unknown>"; ***/
199 ci->brd_id = SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C4T1E1);
200 break;
201 }
202}
203
204
205/*** End-of-File ***/
diff --git a/drivers/staging/cxt1e1/sbeproc.c b/drivers/staging/cxt1e1/sbeproc.c
deleted file mode 100644
index 1c2e52e8b5fe..000000000000
--- a/drivers/staging/cxt1e1/sbeproc.c
+++ /dev/null
@@ -1,219 +0,0 @@
1/* Copyright (C) 2004-2005 SBE, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/types.h>
17#include <linux/module.h>
18#include <linux/errno.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/proc_fs.h>
22#include <linux/seq_file.h>
23#include <linux/sched.h>
24#include <asm/uaccess.h>
25#include "pmcc4_sysdep.h"
26#include "sbecom_inline_linux.h"
27#include "pmcc4_private.h"
28#include "sbeproc.h"
29
30extern void sbecom_get_brdinfo(ci_t *, struct sbe_brd_info *, u_int8_t *);
31extern struct s_hdw_info hdw_info[MAX_BOARDS];
32
33void sbecom_proc_brd_cleanup(ci_t *ci)
34{
35 if (ci->dir_dev) {
36 char dir[7 + SBE_IFACETMPL_SIZE + 1];
37 snprintf(dir, sizeof(dir), "driver/%s", ci->devname);
38 remove_proc_entry("info", ci->dir_dev);
39 remove_proc_entry(dir, NULL);
40 ci->dir_dev = NULL;
41 }
42}
43
44static void sbecom_proc_get_brdinfo(ci_t *ci, struct sbe_brd_info *bip)
45{
46 hdw_info_t *hi = &hdw_info[ci->brdno];
47 u_int8_t *bsn = NULL;
48
49 switch (hi->promfmt)
50 {
51 case PROM_FORMAT_TYPE1:
52 bsn = (u_int8_t *) hi->mfg_info.pft1.Serial;
53 break;
54 case PROM_FORMAT_TYPE2:
55 bsn = (u_int8_t *) hi->mfg_info.pft2.Serial;
56 break;
57 }
58
59 sbecom_get_brdinfo (ci, bip, bsn);
60
61 pr_devel(">> sbecom_get_brdinfo: returned, first_if %p <%s> last_if %p <%s>\n",
62 bip->first_iname, bip->first_iname,
63 bip->last_iname, bip->last_iname);
64}
65
66/*
67 * Describe the driver state through /proc
68 */
69static int sbecom_proc_get_sbe_info(struct seq_file *m, void *v)
70{
71 ci_t *ci = m->private;
72 char *spd;
73 struct sbe_brd_info *bip;
74
75 bip = kzalloc(sizeof(struct sbe_brd_info), GFP_KERNEL | GFP_DMA);
76 if (!bip)
77 return -ENOMEM;
78
79 pr_devel(">> sbecom_proc_get_sbe_info: entered\n");
80
81 sbecom_proc_get_brdinfo(ci, bip);
82
83 seq_puts(m, "Board Type: ");
84 switch (bip->brd_id) {
85 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T3):
86 seq_puts(m, "wanPMC-C1T3");
87 break;
88 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_256T3_E1):
89 seq_puts(m, "wanPTMC-256T3 <E1>");
90 break;
91 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_256T3_T1):
92 seq_puts(m, "wanPTMC-256T3 <T1>");
93 break;
94 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPTMC_C24TE1):
95 seq_puts(m, "wanPTMC-C24TE1");
96 break;
97
98 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C4T1E1):
99 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C4T1E1_L):
100 seq_puts(m, "wanPMC-C4T1E1");
101 break;
102 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C2T1E1):
103 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C2T1E1_L):
104 seq_puts(m, "wanPMC-C2T1E1");
105 break;
106 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T1E1):
107 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPMC_C1T1E1_L):
108 seq_puts(m, "wanPMC-C1T1E1");
109 break;
110
111 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C4T1E1):
112 seq_puts(m, "wanPCI-C4T1E1");
113 break;
114 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C2T1E1):
115 seq_puts(m, "wanPCI-C2T1E1");
116 break;
117 case SBE_BOARD_ID(PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_WANPCI_C1T1E1):
118 seq_puts(m, "wanPCI-C1T1E1");
119 break;
120
121 default:
122 seq_puts(m, "unknown");
123 break;
124 }
125
126 seq_printf(m, " [%08X]\n", bip->brd_id);
127
128 seq_printf(m, "Board Number: %d\n", bip->brdno);
129 seq_printf(m, "Hardware ID: 0x%02X\n", ci->hdw_bid);
130 seq_printf(m, "Board SN: %06X\n", bip->brd_sn);
131 seq_printf(m, "Board MAC: %pMF\n", bip->brd_mac_addr);
132 seq_printf(m, "Ports: %d\n", ci->max_port);
133 seq_printf(m, "Channels: %d\n", bip->brd_chan_cnt);
134#if 1
135 seq_printf(m, "Interface: %s -> %s\n",
136 bip->first_iname, bip->last_iname);
137#else
138 seq_printf(m, "Interface: <not available> 1st %p lst %p\n",
139 bip->first_iname, bip->last_iname);
140#endif
141
142 switch (bip->brd_pci_speed) {
143 case BINFO_PCI_SPEED_33:
144 spd = "33Mhz";
145 break;
146 case BINFO_PCI_SPEED_66:
147 spd = "66Mhz";
148 break;
149 default:
150 spd = "<not available>";
151 break;
152 }
153 seq_printf(m, "PCI Bus Speed: %s\n", spd);
154
155#ifdef SBE_PMCC4_ENABLE
156 {
157 extern int cxt1e1_max_mru;
158#if 0
159 extern int max_chans_used;
160 extern int cxt1e1_max_mtu;
161#endif
162 extern int max_rxdesc_used, max_txdesc_used;
163
164 seq_printf(m, "\ncxt1e1_max_mru: %d\n", cxt1e1_max_mru);
165#if 0
166 seq_printf(m, "\nmax_chans_used: %d\n", max_chans_used);
167 seq_printf(m, "cxt1e1_max_mtu: %d\n", cxt1e1_max_mtu);
168#endif
169 seq_printf(m, "max_rxdesc_used: %d\n", max_rxdesc_used);
170 seq_printf(m, "max_txdesc_used: %d\n", max_txdesc_used);
171 }
172#endif
173
174 kfree(bip);
175
176 pr_devel(">> proc_fs: finished\n");
177 return 0;
178}
179
180/*
181 * seq_file wrappers for procfile show routines.
182 */
183static int sbecom_proc_open(struct inode *inode, struct file *file)
184{
185 return single_open(file, sbecom_proc_get_sbe_info, PDE_DATA(inode));
186}
187
188static const struct file_operations sbecom_proc_fops = {
189 .open = sbecom_proc_open,
190 .read = seq_read,
191 .llseek = seq_lseek,
192 .release = single_release,
193};
194
195/*
196 * Initialize the /proc subsystem for the specific SBE driver
197 */
198int __init sbecom_proc_brd_init(ci_t *ci)
199{
200 char dir[7 + SBE_IFACETMPL_SIZE + 1];
201
202 snprintf(dir, sizeof(dir), "driver/%s", ci->devname);
203 ci->dir_dev = proc_mkdir(dir, NULL);
204 if (!ci->dir_dev) {
205 pr_err("Unable to create directory /proc/driver/%s\n", ci->devname);
206 goto fail;
207 }
208
209 if (!proc_create_data("info", S_IFREG | S_IRUGO, ci->dir_dev,
210 &sbecom_proc_fops, ci)) {
211 pr_err("Unable to create entry /proc/driver/%s/info\n", ci->devname);
212 goto fail;
213 }
214 return 0;
215
216fail:
217 sbecom_proc_brd_cleanup(ci);
218 return 1;
219}
diff --git a/drivers/staging/cxt1e1/sbeproc.h b/drivers/staging/cxt1e1/sbeproc.h
deleted file mode 100644
index 37285df359c1..000000000000
--- a/drivers/staging/cxt1e1/sbeproc.h
+++ /dev/null
@@ -1,42 +0,0 @@
1#ifndef _INC_SBEPROC_H_
2#define _INC_SBEPROC_H_
3
4/*-----------------------------------------------------------------------------
5 * sbeproc.h -
6 *
7 * Copyright (C) 2004-2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *-----------------------------------------------------------------------------
22 */
23
24
25#ifdef CONFIG_PROC_FS
26void sbecom_proc_brd_cleanup (ci_t *);
27int __init sbecom_proc_brd_init (ci_t *);
28
29#else
30
31static inline void sbecom_proc_brd_cleanup(ci_t *ci)
32{
33}
34
35static inline int __init sbecom_proc_brd_init(ci_t *ci)
36{
37 return 0;
38}
39
40#endif /*** CONFIG_PROC_FS ***/
41
42#endif /*** _INC_SBEPROC_H_ ***/
diff --git a/drivers/staging/cxt1e1/sbew_ioc.h b/drivers/staging/cxt1e1/sbew_ioc.h
deleted file mode 100644
index e1e5bfc9ad37..000000000000
--- a/drivers/staging/cxt1e1/sbew_ioc.h
+++ /dev/null
@@ -1,81 +0,0 @@
1#ifndef _INC_SBEWIOC_H_
2#define _INC_SBEWIOC_H_
3
4/*-----------------------------------------------------------------------------
5 * sbew_ioc.h -
6 *
7 * Copyright (C) 2002-2005 SBE, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *
22 *-----------------------------------------------------------------------------
23 */
24
25#include <linux/ioctl.h>
26
27#define SBE_LOCKFILE "/tmp/.sbewan.LCK"
28
29#define SBE_IOC_COOKIE 0x19780926
30#define SBE_IOC_MAGIC ('s')
31
32/* IOW write - data has to go into driver from application */
33/* IOR read - data has to be returned to application from driver */
34
35/*
36 * Note: for an IOWR Ioctl, the read and write data do not have to
37 * be the same size, but the entity declared within the IOC must be
38 * the larger of the two.
39 */
40
41#define SBE_IOC_LOGLEVEL _IOW(SBE_IOC_MAGIC, 0x00, int)
42#define SBE_IOC_CHAN_NEW _IOW(SBE_IOC_MAGIC, 0x01, int) /* unused */
43#define SBE_IOC_CHAN_UP _IOW(SBE_IOC_MAGIC, 0x02, int) /* unused */
44#define SBE_IOC_CHAN_DOWN _IOW(SBE_IOC_MAGIC, 0x03, int) /* unused */
45#define SBE_IOC_CHAN_GET _IOWR(SBE_IOC_MAGIC, 0x04, struct sbecom_chan_param)
46#define SBE_IOC_CHAN_SET _IOW(SBE_IOC_MAGIC, 0x05, struct sbecom_chan_param)
47#define SBE_IOC_CHAN_GET_STAT _IOWR(SBE_IOC_MAGIC, 0x06, struct sbecom_chan_stats)
48#define SBE_IOC_CHAN_DEL_STAT _IOW(SBE_IOC_MAGIC, 0x07, int)
49#define SBE_IOC_PORTS_ENABLE _IOW(SBE_IOC_MAGIC, 0x0A, int)
50#define SBE_IOC_PORT_GET _IOWR(SBE_IOC_MAGIC, 0x0C, struct sbecom_port_param)
51#define SBE_IOC_PORT_SET _IOW(SBE_IOC_MAGIC, 0x0D, struct sbecom_port_param)
52#define SBE_IOC_READ_VEC _IOWR(SBE_IOC_MAGIC, 0x10, struct sbecom_wrt_vec)
53#define SBE_IOC_WRITE_VEC _IOWR(SBE_IOC_MAGIC, 0x11, struct sbecom_wrt_vec)
54#define SBE_IOC_GET_SN _IOR(SBE_IOC_MAGIC, 0x12, u_int32_t)
55#define SBE_IOC_RESET_DEV _IOW(SBE_IOC_MAGIC, 0x13, int)
56#define SBE_IOC_FRAMER_GET _IOWR(SBE_IOC_MAGIC, 0x14, struct sbecom_framer_param)
57#define SBE_IOC_FRAMER_SET _IOW(SBE_IOC_MAGIC, 0x15, struct sbecom_framer_param)
58#define SBE_IOC_CARD_GET _IOR(SBE_IOC_MAGIC, 0x20, struct sbecom_card_param)
59#define SBE_IOC_CARD_SET _IOW(SBE_IOC_MAGIC, 0x21, struct sbecom_card_param)
60#define SBE_IOC_CARD_GET_STAT _IOR(SBE_IOC_MAGIC, 0x22, struct temux_card_stats)
61#define SBE_IOC_CARD_DEL_STAT _IO(SBE_IOC_MAGIC, 0x23)
62#define SBE_IOC_CARD_CHAN_STAT _IOR(SBE_IOC_MAGIC, 0x24, struct sbecom_chan_stats)
63#define SBE_IOC_CARD_BLINK _IOW(SBE_IOC_MAGIC, 0x30, int)
64#define SBE_IOC_DRVINFO_GET _IOWR(SBE_IOC_MAGIC, 0x31, struct sbe_drv_info)
65#define SBE_IOC_BRDINFO_GET _IOR(SBE_IOC_MAGIC, 0x32, struct sbe_brd_info)
66#define SBE_IOC_IID_GET _IOWR(SBE_IOC_MAGIC, 0x33, struct sbe_iid_info)
67#define SBE_IOC_BRDADDR_GET _IOWR(SBE_IOC_MAGIC, 0x34, struct sbe_brd_addr)
68
69#ifdef NOT_YET_COMMON
70#define SBE_IOC_TSIOC_GET _IOWR(SBE_IOC_MAGIC, 0x16, struct wanc1t3_ts_param)
71#define SBE_IOC_TSIOC_SET _IOW(SBE_IOC_MAGIC, 0x17, struct wanc1t3_ts_param)
72#endif
73
74/*
75 * Restrict SBE_IOC_WRITE_VEC & READ_VEC to a single parameter pair, application
76 * then must issue multiple Ioctls for large blocks of contiguous data.
77 */
78
79#define SBE_IOC_MAXVEC 1
80
81#endif /*** _INC_SBEWIOC_H_ ***/
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 00:22:18 -0500