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authorLinus Torvalds <torvalds@linux-foundation.org>2013-11-18 18:50:07 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-11-18 18:50:07 -0500
commit13509c3a9d20a9df93dc9b944e8bd20fe1b454a7 (patch)
treed7a97d1d10e88bcb93852cb0143a000710e9e246 /drivers
parent1ea406c0e08c717241275064046d29b5bac1b1db (diff)
parentcfff1f4a9367bfe0d88413e8807f8369e9564729 (diff)
Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c changes from Wolfram Sang: - new drivers for exynos5, bcm kona, and st micro - bigger overhauls for drivers mxs and rcar - typical driver bugfixes, cleanups, improvements - got rid of the superfluous 'driver' member in i2c_client struct This touches a few drivers in other subsystems. All acked. * 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (38 commits) i2c: bcm-kona: fix error return code in bcm_kona_i2c_probe() i2c: i2c-eg20t: do not print error message in syslog if no ACK received i2c: bcm-kona: Introduce Broadcom I2C Driver i2c: cbus-gpio: Fix device tree binding i2c: wmt: add missing clk_disable_unprepare() on error i2c: designware: add new ACPI IDs i2c: i801: Add Device IDs for Intel Wildcat Point-LP PCH i2c: exynos5: Remove incorrect clk_disable_unprepare i2c: i2c-st: Add ST I2C controller i2c: exynos5: add High Speed I2C controller driver i2c: rcar: fixup rcar type naming i2c: scmi: remove some bogus NULL checks i2c: sh_mobile & rcar: Enable the driver on all ARM platforms i2c: sh_mobile: Convert to clk_prepare/unprepare i2c: mux: gpio: use reg value for i2c_add_mux_adapter i2c: mux: gpio: use gpio_set_value_cansleep() i2c: Include linux/of.h header i2c: mxs: Fix PIO mode on i.MX23 i2c: mxs: Rework the PIO mode operation i2c: mxs: distinguish i.MX23 and i.MX28 based I2C controller ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/drm_encoder_slave.c8
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/therm/ic.c3
-rw-r--r--drivers/i2c/busses/Kconfig32
-rw-r--r--drivers/i2c/busses/Makefile3
-rw-r--r--drivers/i2c/busses/i2c-bcm-kona.c909
-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c6
-rw-r--r--drivers/i2c/busses/i2c-cbus-gpio.c2
-rw-r--r--drivers/i2c/busses/i2c-davinci.c2
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c2
-rw-r--r--drivers/i2c/busses/i2c-eg20t.c26
-rw-r--r--drivers/i2c/busses/i2c-exynos5.c769
-rw-r--r--drivers/i2c/busses/i2c-gpio.c1
-rw-r--r--drivers/i2c/busses/i2c-i801.c3
-rw-r--r--drivers/i2c/busses/i2c-mv64xxx.c2
-rw-r--r--drivers/i2c/busses/i2c-mxs.c340
-rw-r--r--drivers/i2c/busses/i2c-pnx.c1
-rw-r--r--drivers/i2c/busses/i2c-rcar.c65
-rw-r--r--drivers/i2c/busses/i2c-s3c2410.c1
-rw-r--r--drivers/i2c/busses/i2c-scmi.c6
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c8
-rw-r--r--drivers/i2c/busses/i2c-st.c872
-rw-r--r--drivers/i2c/busses/i2c-wmt.c1
-rw-r--r--drivers/i2c/busses/i2c-xiic.c3
-rw-r--r--drivers/i2c/i2c-core.c16
-rw-r--r--drivers/i2c/i2c-dev.c19
-rw-r--r--drivers/i2c/i2c-smbus.c10
-rw-r--r--drivers/i2c/muxes/i2c-arb-gpio-challenge.c2
-rw-r--r--drivers/i2c/muxes/i2c-mux-gpio.c10
-rw-r--r--drivers/i2c/muxes/i2c-mux-pinctrl.c1
-rw-r--r--drivers/media/i2c/s5c73m3/s5c73m3-core.c2
-rw-r--r--drivers/media/platform/exynos4-is/media-dev.c6
-rw-r--r--drivers/media/v4l2-core/tuner-core.c6
-rw-r--r--drivers/media/v4l2-core/v4l2-common.c10
-rw-r--r--drivers/misc/eeprom/at24.c2
34 files changed, 2937 insertions, 212 deletions
diff --git a/drivers/gpu/drm/drm_encoder_slave.c b/drivers/gpu/drm/drm_encoder_slave.c
index 0cfb60f54766..d18b88b755c3 100644
--- a/drivers/gpu/drm/drm_encoder_slave.c
+++ b/drivers/gpu/drm/drm_encoder_slave.c
@@ -67,12 +67,12 @@ int drm_i2c_encoder_init(struct drm_device *dev,
67 goto fail; 67 goto fail;
68 } 68 }
69 69
70 if (!client->driver) { 70 if (!client->dev.driver) {
71 err = -ENODEV; 71 err = -ENODEV;
72 goto fail_unregister; 72 goto fail_unregister;
73 } 73 }
74 74
75 module = client->driver->driver.owner; 75 module = client->dev.driver->owner;
76 if (!try_module_get(module)) { 76 if (!try_module_get(module)) {
77 err = -ENODEV; 77 err = -ENODEV;
78 goto fail_unregister; 78 goto fail_unregister;
@@ -80,7 +80,7 @@ int drm_i2c_encoder_init(struct drm_device *dev,
80 80
81 encoder->bus_priv = client; 81 encoder->bus_priv = client;
82 82
83 encoder_drv = to_drm_i2c_encoder_driver(client->driver); 83 encoder_drv = to_drm_i2c_encoder_driver(to_i2c_driver(client->dev.driver));
84 84
85 err = encoder_drv->encoder_init(client, dev, encoder); 85 err = encoder_drv->encoder_init(client, dev, encoder);
86 if (err) 86 if (err)
@@ -111,7 +111,7 @@ void drm_i2c_encoder_destroy(struct drm_encoder *drm_encoder)
111{ 111{
112 struct drm_encoder_slave *encoder = to_encoder_slave(drm_encoder); 112 struct drm_encoder_slave *encoder = to_encoder_slave(drm_encoder);
113 struct i2c_client *client = drm_i2c_encoder_get_client(drm_encoder); 113 struct i2c_client *client = drm_i2c_encoder_get_client(drm_encoder);
114 struct module *module = client->driver->driver.owner; 114 struct module *module = client->dev.driver->owner;
115 115
116 i2c_unregister_device(client); 116 i2c_unregister_device(client);
117 encoder->bus_priv = NULL; 117 encoder->bus_priv = NULL;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c b/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c
index 13b850076443..e44ed7b93c6d 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c
@@ -41,7 +41,8 @@ probe_monitoring_device(struct nouveau_i2c_port *i2c,
41 if (!client) 41 if (!client)
42 return false; 42 return false;
43 43
44 if (!client->driver || client->driver->detect(client, info)) { 44 if (!client->dev.driver ||
45 to_i2c_driver(client->dev.driver)->detect(client, info)) {
45 i2c_unregister_device(client); 46 i2c_unregister_device(client);
46 return false; 47 return false;
47 } 48 }
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index cdcbd8368ed3..3b26129f6055 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -109,6 +109,7 @@ config I2C_I801
109 Avoton (SOC) 109 Avoton (SOC)
110 Wellsburg (PCH) 110 Wellsburg (PCH)
111 Coleto Creek (PCH) 111 Coleto Creek (PCH)
112 Wildcat Point-LP (PCH)
112 113
113 This driver can also be built as a module. If so, the module 114 This driver can also be built as a module. If so, the module
114 will be called i2c-i801. 115 will be called i2c-i801.
@@ -345,6 +346,16 @@ config I2C_BCM2835
345 This support is also available as a module. If so, the module 346 This support is also available as a module. If so, the module
346 will be called i2c-bcm2835. 347 will be called i2c-bcm2835.
347 348
349config I2C_BCM_KONA
350 tristate "BCM Kona I2C adapter"
351 depends on ARCH_BCM_MOBILE
352 default y
353 help
354 If you say yes to this option, support will be included for the
355 I2C interface on the Broadcom Kona family of processors.
356
357 If you do not need KONA I2C inteface, say N.
358
348config I2C_BLACKFIN_TWI 359config I2C_BLACKFIN_TWI
349 tristate "Blackfin TWI I2C support" 360 tristate "Blackfin TWI I2C support"
350 depends on BLACKFIN 361 depends on BLACKFIN
@@ -436,6 +447,13 @@ config I2C_EG20T
436 ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. 447 ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
437 ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. 448 ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
438 449
450config I2C_EXYNOS5
451 tristate "Exynos5 high-speed I2C driver"
452 depends on ARCH_EXYNOS5 && OF
453 help
454 Say Y here to include support for high-speed I2C controller in the
455 Exynos5 based Samsung SoCs.
456
439config I2C_GPIO 457config I2C_GPIO
440 tristate "GPIO-based bitbanging I2C" 458 tristate "GPIO-based bitbanging I2C"
441 depends on GPIOLIB 459 depends on GPIOLIB
@@ -665,7 +683,7 @@ config I2C_SH7760
665 683
666config I2C_SH_MOBILE 684config I2C_SH_MOBILE
667 tristate "SuperH Mobile I2C Controller" 685 tristate "SuperH Mobile I2C Controller"
668 depends on SUPERH || ARCH_SHMOBILE 686 depends on SUPERH || ARM || COMPILE_TEST
669 help 687 help
670 If you say yes to this option, support will be included for the 688 If you say yes to this option, support will be included for the
671 built-in I2C interface on the Renesas SH-Mobile processor. 689 built-in I2C interface on the Renesas SH-Mobile processor.
@@ -695,6 +713,16 @@ config I2C_SIRF
695 This driver can also be built as a module. If so, the module 713 This driver can also be built as a module. If so, the module
696 will be called i2c-sirf. 714 will be called i2c-sirf.
697 715
716config I2C_ST
717 tristate "STMicroelectronics SSC I2C support"
718 depends on ARCH_STI
719 help
720 Enable this option to add support for STMicroelectronics SoCs
721 hardware SSC (Synchronous Serial Controller) as an I2C controller.
722
723 This driver can also be built as module. If so, the module
724 will be called i2c-st.
725
698config I2C_STU300 726config I2C_STU300
699 tristate "ST Microelectronics DDC I2C interface" 727 tristate "ST Microelectronics DDC I2C interface"
700 depends on MACH_U300 728 depends on MACH_U300
@@ -768,7 +796,7 @@ config I2C_XLR
768 796
769config I2C_RCAR 797config I2C_RCAR
770 tristate "Renesas R-Car I2C Controller" 798 tristate "Renesas R-Car I2C Controller"
771 depends on ARCH_SHMOBILE && I2C 799 depends on ARM || COMPILE_TEST
772 help 800 help
773 If you say yes to this option, support will be included for the 801 If you say yes to this option, support will be included for the
774 R-Car I2C controller. 802 R-Car I2C controller.
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index d00997f3eb3b..c73eb0ea788e 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -42,6 +42,7 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o
42obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o 42obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
43i2c-designware-pci-objs := i2c-designware-pcidrv.o 43i2c-designware-pci-objs := i2c-designware-pcidrv.o
44obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o 44obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
45obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
45obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o 46obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
46obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o 47obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
47obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o 48obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
@@ -68,6 +69,7 @@ obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
68obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o 69obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
69obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o 70obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
70obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o 71obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o
72obj-$(CONFIG_I2C_ST) += i2c-st.o
71obj-$(CONFIG_I2C_STU300) += i2c-stu300.o 73obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
72obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o 74obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
73obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o 75obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
@@ -87,6 +89,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o
87 89
88# Other I2C/SMBus bus drivers 90# Other I2C/SMBus bus drivers
89obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o 91obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o
92obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o
90obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o 93obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
91obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o 94obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
92obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o 95obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
diff --git a/drivers/i2c/busses/i2c-bcm-kona.c b/drivers/i2c/busses/i2c-bcm-kona.c
new file mode 100644
index 000000000000..036cf03aeb61
--- /dev/null
+++ b/drivers/i2c/busses/i2c-bcm-kona.c
@@ -0,0 +1,909 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/device.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/i2c.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/slab.h>
25
26/* Hardware register offsets and field defintions */
27#define CS_OFFSET 0x00000020
28#define CS_ACK_SHIFT 3
29#define CS_ACK_MASK 0x00000008
30#define CS_ACK_CMD_GEN_START 0x00000000
31#define CS_ACK_CMD_GEN_RESTART 0x00000001
32#define CS_CMD_SHIFT 1
33#define CS_CMD_CMD_NO_ACTION 0x00000000
34#define CS_CMD_CMD_START_RESTART 0x00000001
35#define CS_CMD_CMD_STOP 0x00000002
36#define CS_EN_SHIFT 0
37#define CS_EN_CMD_ENABLE_BSC 0x00000001
38
39#define TIM_OFFSET 0x00000024
40#define TIM_PRESCALE_SHIFT 6
41#define TIM_P_SHIFT 3
42#define TIM_NO_DIV_SHIFT 2
43#define TIM_DIV_SHIFT 0
44
45#define DAT_OFFSET 0x00000028
46
47#define TOUT_OFFSET 0x0000002c
48
49#define TXFCR_OFFSET 0x0000003c
50#define TXFCR_FIFO_FLUSH_MASK 0x00000080
51#define TXFCR_FIFO_EN_MASK 0x00000040
52
53#define IER_OFFSET 0x00000044
54#define IER_READ_COMPLETE_INT_MASK 0x00000010
55#define IER_I2C_INT_EN_MASK 0x00000008
56#define IER_FIFO_INT_EN_MASK 0x00000002
57#define IER_NOACK_EN_MASK 0x00000001
58
59#define ISR_OFFSET 0x00000048
60#define ISR_RESERVED_MASK 0xffffff60
61#define ISR_CMDBUSY_MASK 0x00000080
62#define ISR_READ_COMPLETE_MASK 0x00000010
63#define ISR_SES_DONE_MASK 0x00000008
64#define ISR_ERR_MASK 0x00000004
65#define ISR_TXFIFOEMPTY_MASK 0x00000002
66#define ISR_NOACK_MASK 0x00000001
67
68#define CLKEN_OFFSET 0x0000004C
69#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
70#define CLKEN_M_SHIFT 4
71#define CLKEN_N_SHIFT 1
72#define CLKEN_CLKEN_MASK 0x00000001
73
74#define FIFO_STATUS_OFFSET 0x00000054
75#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
76#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
77
78#define HSTIM_OFFSET 0x00000058
79#define HSTIM_HS_MODE_MASK 0x00008000
80#define HSTIM_HS_HOLD_SHIFT 10
81#define HSTIM_HS_HIGH_PHASE_SHIFT 5
82#define HSTIM_HS_SETUP_SHIFT 0
83
84#define PADCTL_OFFSET 0x0000005c
85#define PADCTL_PAD_OUT_EN_MASK 0x00000004
86
87#define RXFCR_OFFSET 0x00000068
88#define RXFCR_NACK_EN_SHIFT 7
89#define RXFCR_READ_COUNT_SHIFT 0
90#define RXFIFORDOUT_OFFSET 0x0000006c
91
92/* Locally used constants */
93#define MAX_RX_FIFO_SIZE 64U /* bytes */
94#define MAX_TX_FIFO_SIZE 64U /* bytes */
95
96#define STD_EXT_CLK_FREQ 13000000UL
97#define HS_EXT_CLK_FREQ 104000000UL
98
99#define MASTERCODE 0x08 /* Mastercodes are 0000_1xxxb */
100
101#define I2C_TIMEOUT 100 /* msecs */
102
103/* Operations that can be commanded to the controller */
104enum bcm_kona_cmd_t {
105 BCM_CMD_NOACTION = 0,
106 BCM_CMD_START,
107 BCM_CMD_RESTART,
108 BCM_CMD_STOP,
109};
110
111enum bus_speed_index {
112 BCM_SPD_100K = 0,
113 BCM_SPD_400K,
114 BCM_SPD_1MHZ,
115};
116
117enum hs_bus_speed_index {
118 BCM_SPD_3P4MHZ = 0,
119};
120
121/* Internal divider settings for standard mode, fast mode and fast mode plus */
122struct bus_speed_cfg {
123 uint8_t time_m; /* Number of cycles for setup time */
124 uint8_t time_n; /* Number of cycles for hold time */
125 uint8_t prescale; /* Prescale divider */
126 uint8_t time_p; /* Timing coefficient */
127 uint8_t no_div; /* Disable clock divider */
128 uint8_t time_div; /* Post-prescale divider */
129};
130
131/* Internal divider settings for high-speed mode */
132struct hs_bus_speed_cfg {
133 uint8_t hs_hold; /* Number of clock cycles SCL stays low until
134 the end of bit period */
135 uint8_t hs_high_phase; /* Number of clock cycles SCL stays high
136 before it falls */
137 uint8_t hs_setup; /* Number of clock cycles SCL stays low
138 before it rises */
139 uint8_t prescale; /* Prescale divider */
140 uint8_t time_p; /* Timing coefficient */
141 uint8_t no_div; /* Disable clock divider */
142 uint8_t time_div; /* Post-prescale divider */
143};
144
145static const struct bus_speed_cfg std_cfg_table[] = {
146 [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
147 [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
148 [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
149};
150
151static const struct hs_bus_speed_cfg hs_cfg_table[] = {
152 [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00},
153};
154
155struct bcm_kona_i2c_dev {
156 struct device *device;
157
158 void __iomem *base;
159 int irq;
160 struct clk *external_clk;
161
162 struct i2c_adapter adapter;
163
164 struct completion done;
165
166 const struct bus_speed_cfg *std_cfg;
167 const struct hs_bus_speed_cfg *hs_cfg;
168};
169
170static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
171 enum bcm_kona_cmd_t cmd)
172{
173 dev_dbg(dev->device, "%s, %d\n", __func__, cmd);
174
175 switch (cmd) {
176 case BCM_CMD_NOACTION:
177 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
178 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
179 dev->base + CS_OFFSET);
180 break;
181
182 case BCM_CMD_START:
183 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
184 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
185 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
186 dev->base + CS_OFFSET);
187 break;
188
189 case BCM_CMD_RESTART:
190 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
191 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
192 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
193 dev->base + CS_OFFSET);
194 break;
195
196 case BCM_CMD_STOP:
197 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
198 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
199 dev->base + CS_OFFSET);
200 break;
201
202 default:
203 dev_err(dev->device, "Unknown command %d\n", cmd);
204 }
205}
206
207static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
208{
209 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
210 dev->base + CLKEN_OFFSET);
211}
212
213static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
214{
215 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
216 dev->base + CLKEN_OFFSET);
217}
218
219static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid)
220{
221 struct bcm_kona_i2c_dev *dev = devid;
222 uint32_t status = readl(dev->base + ISR_OFFSET);
223
224 if ((status & ~ISR_RESERVED_MASK) == 0)
225 return IRQ_NONE;
226
227 /* Must flush the TX FIFO when NAK detected */
228 if (status & ISR_NOACK_MASK)
229 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
230 dev->base + TXFCR_OFFSET);
231
232 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
233 complete_all(&dev->done);
234
235 return IRQ_HANDLED;
236}
237
238/* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */
239static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev)
240{
241 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
242
243 while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK)
244 if (time_after(jiffies, timeout)) {
245 dev_err(dev->device, "CMDBUSY timeout\n");
246 return -ETIMEDOUT;
247 }
248
249 return 0;
250}
251
252/* Send command to I2C bus */
253static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
254 enum bcm_kona_cmd_t cmd)
255{
256 int rc;
257 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
258
259 /* Make sure the hardware is ready */
260 rc = bcm_kona_i2c_wait_if_busy(dev);
261 if (rc < 0)
262 return rc;
263
264 /* Unmask the session done interrupt */
265 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
266
267 /* Mark as incomplete before sending the command */
268 reinit_completion(&dev->done);
269
270 /* Send the command */
271 bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
272
273 /* Wait for transaction to finish or timeout */
274 time_left = wait_for_completion_timeout(&dev->done, time_left);
275
276 /* Mask all interrupts */
277 writel(0, dev->base + IER_OFFSET);
278
279 if (!time_left) {
280 dev_err(dev->device, "controller timed out\n");
281 rc = -ETIMEDOUT;
282 }
283
284 /* Clear command */
285 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
286
287 return rc;
288}
289
290/* Read a single RX FIFO worth of data from the i2c bus */
291static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
292 uint8_t *buf, unsigned int len,
293 unsigned int last_byte_nak)
294{
295 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
296
297 /* Mark as incomplete before starting the RX FIFO */
298 reinit_completion(&dev->done);
299
300 /* Unmask the read complete interrupt */
301 writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET);
302
303 /* Start the RX FIFO */
304 writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
305 (len << RXFCR_READ_COUNT_SHIFT),
306 dev->base + RXFCR_OFFSET);
307
308 /* Wait for FIFO read to complete */
309 time_left = wait_for_completion_timeout(&dev->done, time_left);
310
311 /* Mask all interrupts */
312 writel(0, dev->base + IER_OFFSET);
313
314 if (!time_left) {
315 dev_err(dev->device, "RX FIFO time out\n");
316 return -EREMOTEIO;
317 }
318
319 /* Read data from FIFO */
320 for (; len > 0; len--, buf++)
321 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
322
323 return 0;
324}
325
326/* Read any amount of data using the RX FIFO from the i2c bus */
327static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
328 struct i2c_msg *msg)
329{
330 unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
331 unsigned int last_byte_nak = 0;
332 unsigned int bytes_read = 0;
333 int rc;
334
335 uint8_t *tmp_buf = msg->buf;
336
337 while (bytes_read < msg->len) {
338 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
339 last_byte_nak = 1; /* NAK last byte of transfer */
340 bytes_to_read = msg->len - bytes_read;
341 }
342
343 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
344 last_byte_nak);
345 if (rc < 0)
346 return -EREMOTEIO;
347
348 bytes_read += bytes_to_read;
349 tmp_buf += bytes_to_read;
350 }
351
352 return 0;
353}
354
355/* Write a single byte of data to the i2c bus */
356static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
357 unsigned int nak_expected)
358{
359 int rc;
360 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
361 unsigned int nak_received;
362
363 /* Make sure the hardware is ready */
364 rc = bcm_kona_i2c_wait_if_busy(dev);
365 if (rc < 0)
366 return rc;
367
368 /* Clear pending session done interrupt */
369 writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
370
371 /* Unmask the session done interrupt */
372 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
373
374 /* Mark as incomplete before sending the data */
375 reinit_completion(&dev->done);
376
377 /* Send one byte of data */
378 writel(data, dev->base + DAT_OFFSET);
379
380 /* Wait for byte to be written */
381 time_left = wait_for_completion_timeout(&dev->done, time_left);
382
383 /* Mask all interrupts */
384 writel(0, dev->base + IER_OFFSET);
385
386 if (!time_left) {
387 dev_dbg(dev->device, "controller timed out\n");
388 return -ETIMEDOUT;
389 }
390
391 nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
392
393 if (nak_received ^ nak_expected) {
394 dev_dbg(dev->device, "unexpected NAK/ACK\n");
395 return -EREMOTEIO;
396 }
397
398 return 0;
399}
400
401/* Write a single TX FIFO worth of data to the i2c bus */
402static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
403 uint8_t *buf, unsigned int len)
404{
405 int k;
406 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
407 unsigned int fifo_status;
408
409 /* Mark as incomplete before sending data to the TX FIFO */
410 reinit_completion(&dev->done);
411
412 /* Unmask the fifo empty and nak interrupt */
413 writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK,
414 dev->base + IER_OFFSET);
415
416 /* Disable IRQ to load a FIFO worth of data without interruption */
417 disable_irq(dev->irq);
418
419 /* Write data into FIFO */
420 for (k = 0; k < len; k++)
421 writel(buf[k], (dev->base + DAT_OFFSET));
422
423 /* Enable IRQ now that data has been loaded */
424 enable_irq(dev->irq);
425
426 /* Wait for FIFO to empty */
427 do {
428 time_left = wait_for_completion_timeout(&dev->done, time_left);
429 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
430 } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
431
432 /* Mask all interrupts */
433 writel(0, dev->base + IER_OFFSET);
434
435 /* Check if there was a NAK */
436 if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
437 dev_err(dev->device, "unexpected NAK\n");
438 return -EREMOTEIO;
439 }
440
441 /* Check if a timeout occured */
442 if (!time_left) {
443 dev_err(dev->device, "completion timed out\n");
444 return -EREMOTEIO;
445 }
446
447 return 0;
448}
449
450
451/* Write any amount of data using TX FIFO to the i2c bus */
452static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
453 struct i2c_msg *msg)
454{
455 unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
456 unsigned int bytes_written = 0;
457 int rc;
458
459 uint8_t *tmp_buf = msg->buf;
460
461 while (bytes_written < msg->len) {
462 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
463 bytes_to_write = msg->len - bytes_written;
464
465 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
466 bytes_to_write);
467 if (rc < 0)
468 return -EREMOTEIO;
469
470 bytes_written += bytes_to_write;
471 tmp_buf += bytes_to_write;
472 }
473
474 return 0;
475}
476
477/* Send i2c address */
478static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
479 struct i2c_msg *msg)
480{
481 unsigned char addr;
482
483 if (msg->flags & I2C_M_TEN) {
484 /* First byte is 11110XX0 where XX is upper 2 bits */
485 addr = 0xF0 | ((msg->addr & 0x300) >> 7);
486 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
487 return -EREMOTEIO;
488
489 /* Second byte is the remaining 8 bits */
490 addr = msg->addr & 0xFF;
491 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
492 return -EREMOTEIO;
493
494 if (msg->flags & I2C_M_RD) {
495 /* For read, send restart command */
496 if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
497 return -EREMOTEIO;
498
499 /* Then re-send the first byte with the read bit set */
500 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
501 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
502 return -EREMOTEIO;
503 }
504 } else {
505 addr = msg->addr << 1;
506
507 if (msg->flags & I2C_M_RD)
508 addr |= 1;
509
510 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
511 return -EREMOTEIO;
512 }
513
514 return 0;
515}
516
517static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
518{
519 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
520 dev->base + CLKEN_OFFSET);
521}
522
523static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
524{
525 writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
526 dev->base + HSTIM_OFFSET);
527
528 writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
529 (dev->std_cfg->time_p << TIM_P_SHIFT) |
530 (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
531 (dev->std_cfg->time_div << TIM_DIV_SHIFT),
532 dev->base + TIM_OFFSET);
533
534 writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
535 (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
536 CLKEN_CLKEN_MASK,
537 dev->base + CLKEN_OFFSET);
538}
539
540static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev)
541{
542 writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) |
543 (dev->hs_cfg->time_p << TIM_P_SHIFT) |
544 (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) |
545 (dev->hs_cfg->time_div << TIM_DIV_SHIFT),
546 dev->base + TIM_OFFSET);
547
548 writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) |
549 (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) |
550 (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT),
551 dev->base + HSTIM_OFFSET);
552
553 writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,
554 dev->base + HSTIM_OFFSET);
555}
556
557static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev)
558{
559 int rc;
560
561 /* Send mastercode at standard speed */
562 rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1);
563 if (rc < 0) {
564 pr_err("High speed handshake failed\n");
565 return rc;
566 }
567
568 /* Configure external clock to higher frequency */
569 rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ);
570 if (rc) {
571 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
572 __func__, rc);
573 return rc;
574 }
575
576 /* Reconfigure internal dividers */
577 bcm_kona_i2c_config_timing_hs(dev);
578
579 /* Send a restart command */
580 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
581 if (rc < 0)
582 dev_err(dev->device, "High speed restart command failed\n");
583
584 return rc;
585}
586
587static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev)
588{
589 int rc;
590
591 /* Reconfigure internal dividers */
592 bcm_kona_i2c_config_timing(dev);
593
594 /* Configure external clock to lower frequency */
595 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
596 if (rc) {
597 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
598 __func__, rc);
599 }
600
601 return rc;
602}
603
604/* Master transfer function */
605static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter,
606 struct i2c_msg msgs[], int num)
607{
608 struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter);
609 struct i2c_msg *pmsg;
610 int rc = 0;
611 int i;
612
613 rc = clk_prepare_enable(dev->external_clk);
614 if (rc) {
615 dev_err(dev->device, "%s: peri clock enable failed. err %d\n",
616 __func__, rc);
617 return rc;
618 }
619
620 /* Enable pad output */
621 writel(0, dev->base + PADCTL_OFFSET);
622
623 /* Enable internal clocks */
624 bcm_kona_i2c_enable_clock(dev);
625
626 /* Send start command */
627 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
628 if (rc < 0) {
629 dev_err(dev->device, "Start command failed rc = %d\n", rc);
630 goto xfer_disable_pad;
631 }
632
633 /* Switch to high speed if applicable */
634 if (dev->hs_cfg) {
635 rc = bcm_kona_i2c_switch_to_hs(dev);
636 if (rc < 0)
637 goto xfer_send_stop;
638 }
639
640 /* Loop through all messages */
641 for (i = 0; i < num; i++) {
642 pmsg = &msgs[i];
643
644 /* Send restart for subsequent messages */
645 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
646 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
647 if (rc < 0) {
648 dev_err(dev->device,
649 "restart cmd failed rc = %d\n", rc);
650 goto xfer_send_stop;
651 }
652 }
653
654 /* Send slave address */
655 if (!(pmsg->flags & I2C_M_NOSTART)) {
656 rc = bcm_kona_i2c_do_addr(dev, pmsg);
657 if (rc < 0) {
658 dev_err(dev->device,
659 "NAK from addr %2.2x msg#%d rc = %d\n",
660 pmsg->addr, i, rc);
661 goto xfer_send_stop;
662 }
663 }
664
665 /* Perform data transfer */
666 if (pmsg->flags & I2C_M_RD) {
667 rc = bcm_kona_i2c_read_fifo(dev, pmsg);
668 if (rc < 0) {
669 dev_err(dev->device, "read failure\n");
670 goto xfer_send_stop;
671 }
672 } else {
673 rc = bcm_kona_i2c_write_fifo(dev, pmsg);
674 if (rc < 0) {
675 dev_err(dev->device, "write failure");
676 goto xfer_send_stop;
677 }
678 }
679 }
680
681 rc = num;
682
683xfer_send_stop:
684 /* Send a STOP command */
685 bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
686
687 /* Return from high speed if applicable */
688 if (dev->hs_cfg) {
689 int hs_rc = bcm_kona_i2c_switch_to_std(dev);
690
691 if (hs_rc)
692 rc = hs_rc;
693 }
694
695xfer_disable_pad:
696 /* Disable pad output */
697 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
698
699 /* Stop internal clock */
700 bcm_kona_i2c_disable_clock(dev);
701
702 clk_disable_unprepare(dev->external_clk);
703
704 return rc;
705}
706
707static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap)
708{
709 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
710 I2C_FUNC_NOSTART;
711}
712
713static const struct i2c_algorithm bcm_algo = {
714 .master_xfer = bcm_kona_i2c_xfer,
715 .functionality = bcm_kona_i2c_functionality,
716};
717
718static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev)
719{
720 unsigned int bus_speed;
721 int ret = of_property_read_u32(dev->device->of_node, "clock-frequency",
722 &bus_speed);
723 if (ret < 0) {
724 dev_err(dev->device, "missing clock-frequency property\n");
725 return -ENODEV;
726 }
727
728 switch (bus_speed) {
729 case 100000:
730 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
731 break;
732 case 400000:
733 dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
734 break;
735 case 1000000:
736 dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
737 break;
738 case 3400000:
739 /* Send mastercode at 100k */
740 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
741 dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ];
742 break;
743 default:
744 pr_err("%d hz bus speed not supported\n", bus_speed);
745 pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n");
746 return -EINVAL;
747 }
748
749 return 0;
750}
751
752static int bcm_kona_i2c_probe(struct platform_device *pdev)
753{
754 int rc = 0;
755 struct bcm_kona_i2c_dev *dev;
756 struct i2c_adapter *adap;
757 struct resource *iomem;
758
759 /* Allocate memory for private data structure */
760 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
761 if (!dev)
762 return -ENOMEM;
763
764 platform_set_drvdata(pdev, dev);
765 dev->device = &pdev->dev;
766 init_completion(&dev->done);
767
768 /* Map hardware registers */
769 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
770 dev->base = devm_ioremap_resource(dev->device, iomem);
771 if (IS_ERR(dev->base))
772 return -ENOMEM;
773
774 /* Get and enable external clock */
775 dev->external_clk = devm_clk_get(dev->device, NULL);
776 if (IS_ERR(dev->external_clk)) {
777 dev_err(dev->device, "couldn't get clock\n");
778 return -ENODEV;
779 }
780
781 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
782 if (rc) {
783 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
784 __func__, rc);
785 return rc;
786 }
787
788 rc = clk_prepare_enable(dev->external_clk);
789 if (rc) {
790 dev_err(dev->device, "couldn't enable clock\n");
791 return rc;
792 }
793
794 /* Parse bus speed */
795 rc = bcm_kona_i2c_assign_bus_speed(dev);
796 if (rc)
797 goto probe_disable_clk;
798
799 /* Enable internal clocks */
800 bcm_kona_i2c_enable_clock(dev);
801
802 /* Configure internal dividers */
803 bcm_kona_i2c_config_timing(dev);
804
805 /* Disable timeout */
806 writel(0, dev->base + TOUT_OFFSET);
807
808 /* Enable autosense */
809 bcm_kona_i2c_enable_autosense(dev);
810
811 /* Enable TX FIFO */
812 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
813 dev->base + TXFCR_OFFSET);
814
815 /* Mask all interrupts */
816 writel(0, dev->base + IER_OFFSET);
817
818 /* Clear all pending interrupts */
819 writel(ISR_CMDBUSY_MASK |
820 ISR_READ_COMPLETE_MASK |
821 ISR_SES_DONE_MASK |
822 ISR_ERR_MASK |
823 ISR_TXFIFOEMPTY_MASK |
824 ISR_NOACK_MASK,
825 dev->base + ISR_OFFSET);
826
827 /* Get the interrupt number */
828 dev->irq = platform_get_irq(pdev, 0);
829 if (dev->irq < 0) {
830 dev_err(dev->device, "no irq resource\n");
831 rc = -ENODEV;
832 goto probe_disable_clk;
833 }
834
835 /* register the ISR handler */
836 rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr,
837 IRQF_SHARED, pdev->name, dev);
838 if (rc) {
839 dev_err(dev->device, "failed to request irq %i\n", dev->irq);
840 goto probe_disable_clk;
841 }
842
843 /* Enable the controller but leave it idle */
844 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
845
846 /* Disable pad output */
847 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
848
849 /* Disable internal clock */
850 bcm_kona_i2c_disable_clock(dev);
851
852 /* Disable external clock */
853 clk_disable_unprepare(dev->external_clk);
854
855 /* Add the i2c adapter */
856 adap = &dev->adapter;
857 i2c_set_adapdata(adap, dev);
858 adap->owner = THIS_MODULE;
859 strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
860 adap->algo = &bcm_algo;
861 adap->dev.parent = &pdev->dev;
862 adap->dev.of_node = pdev->dev.of_node;
863
864 rc = i2c_add_adapter(adap);
865 if (rc) {
866 dev_err(dev->device, "failed to add adapter\n");
867 return rc;
868 }
869
870 dev_info(dev->device, "device registered successfully\n");
871
872 return 0;
873
874probe_disable_clk:
875 bcm_kona_i2c_disable_clock(dev);
876 clk_disable_unprepare(dev->external_clk);
877
878 return rc;
879}
880
881static int bcm_kona_i2c_remove(struct platform_device *pdev)
882{
883 struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev);
884
885 i2c_del_adapter(&dev->adapter);
886
887 return 0;
888}
889
890static const struct of_device_id bcm_kona_i2c_of_match[] = {
891 {.compatible = "brcm,kona-i2c",},
892 {},
893};
894MODULE_DEVICE_TABLE(of, kona_i2c_of_match);
895
896static struct platform_driver bcm_kona_i2c_driver = {
897 .driver = {
898 .name = "bcm-kona-i2c",
899 .owner = THIS_MODULE,
900 .of_match_table = bcm_kona_i2c_of_match,
901 },
902 .probe = bcm_kona_i2c_probe,
903 .remove = bcm_kona_i2c_remove,
904};
905module_platform_driver(bcm_kona_i2c_driver);
906
907MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
908MODULE_DESCRIPTION("Broadcom Kona I2C Driver");
909MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 35a473ba3d81..3b9bd9a3f2b0 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -675,7 +675,7 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
675 p_adap->retries = 3; 675 p_adap->retries = 3;
676 676
677 rc = peripheral_request_list( 677 rc = peripheral_request_list(
678 (unsigned short *)dev_get_platdata(&pdev->dev), 678 dev_get_platdata(&pdev->dev),
679 "i2c-bfin-twi"); 679 "i2c-bfin-twi");
680 if (rc) { 680 if (rc) {
681 dev_err(&pdev->dev, "Can't setup pin mux!\n"); 681 dev_err(&pdev->dev, "Can't setup pin mux!\n");
@@ -723,7 +723,7 @@ out_error_add_adapter:
723 free_irq(iface->irq, iface); 723 free_irq(iface->irq, iface);
724out_error_req_irq: 724out_error_req_irq:
725out_error_no_irq: 725out_error_no_irq:
726 peripheral_free_list((unsigned short *)dev_get_platdata(&pdev->dev)); 726 peripheral_free_list(dev_get_platdata(&pdev->dev));
727out_error_pin_mux: 727out_error_pin_mux:
728 iounmap(iface->regs_base); 728 iounmap(iface->regs_base);
729out_error_ioremap: 729out_error_ioremap:
@@ -739,7 +739,7 @@ static int i2c_bfin_twi_remove(struct platform_device *pdev)
739 739
740 i2c_del_adapter(&(iface->adap)); 740 i2c_del_adapter(&(iface->adap));
741 free_irq(iface->irq, iface); 741 free_irq(iface->irq, iface);
742 peripheral_free_list((unsigned short *)dev_get_platdata(&pdev->dev)); 742 peripheral_free_list(dev_get_platdata(&pdev->dev));
743 iounmap(iface->regs_base); 743 iounmap(iface->regs_base);
744 kfree(iface); 744 kfree(iface);
745 745
diff --git a/drivers/i2c/busses/i2c-cbus-gpio.c b/drivers/i2c/busses/i2c-cbus-gpio.c
index 2d46f13adfdf..ce7ffba2b020 100644
--- a/drivers/i2c/busses/i2c-cbus-gpio.c
+++ b/drivers/i2c/busses/i2c-cbus-gpio.c
@@ -246,6 +246,7 @@ static int cbus_i2c_probe(struct platform_device *pdev)
246 adapter->owner = THIS_MODULE; 246 adapter->owner = THIS_MODULE;
247 adapter->class = I2C_CLASS_HWMON; 247 adapter->class = I2C_CLASS_HWMON;
248 adapter->dev.parent = &pdev->dev; 248 adapter->dev.parent = &pdev->dev;
249 adapter->dev.of_node = pdev->dev.of_node;
249 adapter->nr = pdev->id; 250 adapter->nr = pdev->id;
250 adapter->timeout = HZ; 251 adapter->timeout = HZ;
251 adapter->algo = &cbus_i2c_algo; 252 adapter->algo = &cbus_i2c_algo;
@@ -289,6 +290,7 @@ static struct platform_driver cbus_i2c_driver = {
289 .driver = { 290 .driver = {
290 .owner = THIS_MODULE, 291 .owner = THIS_MODULE,
291 .name = "i2c-cbus-gpio", 292 .name = "i2c-cbus-gpio",
293 .of_match_table = of_match_ptr(i2c_cbus_dt_ids),
292 }, 294 },
293}; 295};
294module_platform_driver(cbus_i2c_driver); 296module_platform_driver(cbus_i2c_driver);
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 960dec61c64e..ff05d9fef4a8 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -795,7 +795,7 @@ static struct platform_driver davinci_i2c_driver = {
795 .name = "i2c_davinci", 795 .name = "i2c_davinci",
796 .owner = THIS_MODULE, 796 .owner = THIS_MODULE,
797 .pm = davinci_i2c_pm_ops, 797 .pm = davinci_i2c_pm_ops,
798 .of_match_table = of_match_ptr(davinci_i2c_of_match), 798 .of_match_table = davinci_i2c_of_match,
799 }, 799 },
800}; 800};
801 801
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 0aa01136f8d9..d0bdac0498ce 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -103,6 +103,8 @@ static int dw_i2c_acpi_configure(struct platform_device *pdev)
103static const struct acpi_device_id dw_i2c_acpi_match[] = { 103static const struct acpi_device_id dw_i2c_acpi_match[] = {
104 { "INT33C2", 0 }, 104 { "INT33C2", 0 },
105 { "INT33C3", 0 }, 105 { "INT33C3", 0 },
106 { "INT3432", 0 },
107 { "INT3433", 0 },
106 { "80860F41", 0 }, 108 { "80860F41", 0 },
107 { } 109 { }
108}; 110};
diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index 0f3752967c4b..ff15ae90aaf5 100644
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -312,24 +312,6 @@ static void pch_i2c_start(struct i2c_algo_pch_data *adap)
312} 312}
313 313
314/** 314/**
315 * pch_i2c_getack() - to confirm ACK/NACK
316 * @adap: Pointer to struct i2c_algo_pch_data.
317 */
318static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
319{
320 u32 reg_val;
321 void __iomem *p = adap->pch_base_address;
322 reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
323
324 if (reg_val != 0) {
325 pch_err(adap, "return%d\n", -EPROTO);
326 return -EPROTO;
327 }
328
329 return 0;
330}
331
332/**
333 * pch_i2c_stop() - generate stop condition in normal mode. 315 * pch_i2c_stop() - generate stop condition in normal mode.
334 * @adap: Pointer to struct i2c_algo_pch_data. 316 * @adap: Pointer to struct i2c_algo_pch_data.
335 */ 317 */
@@ -344,6 +326,7 @@ static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
344static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap) 326static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
345{ 327{
346 long ret; 328 long ret;
329 void __iomem *p = adap->pch_base_address;
347 330
348 ret = wait_event_timeout(pch_event, 331 ret = wait_event_timeout(pch_event,
349 (adap->pch_event_flag != 0), msecs_to_jiffies(1000)); 332 (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
@@ -366,10 +349,9 @@ static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
366 349
367 adap->pch_event_flag = 0; 350 adap->pch_event_flag = 0;
368 351
369 if (pch_i2c_getack(adap)) { 352 if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
370 pch_dbg(adap, "Receive NACK for slave address" 353 pch_dbg(adap, "Receive NACK for slave address setting\n");
371 "setting\n"); 354 return -ENXIO;
372 return -EIO;
373 } 355 }
374 356
375 return 0; 357 return 0;
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
new file mode 100644
index 000000000000..c1ef228095b5
--- /dev/null
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -0,0 +1,769 @@
1/**
2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13
14#include <linux/i2c.h>
15#include <linux/init.h>
16#include <linux/time.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23#include <linux/slab.h>
24#include <linux/io.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/spinlock.h>
28
29/*
30 * HSI2C controller from Samsung supports 2 modes of operation
31 * 1. Auto mode: Where in master automatically controls the whole transaction
32 * 2. Manual mode: Software controls the transaction by issuing commands
33 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
34 *
35 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
36 *
37 * Special bits are available for both modes of operation to set commands
38 * and for checking transfer status
39 */
40
41/* Register Map */
42#define HSI2C_CTL 0x00
43#define HSI2C_FIFO_CTL 0x04
44#define HSI2C_TRAILIG_CTL 0x08
45#define HSI2C_CLK_CTL 0x0C
46#define HSI2C_CLK_SLOT 0x10
47#define HSI2C_INT_ENABLE 0x20
48#define HSI2C_INT_STATUS 0x24
49#define HSI2C_ERR_STATUS 0x2C
50#define HSI2C_FIFO_STATUS 0x30
51#define HSI2C_TX_DATA 0x34
52#define HSI2C_RX_DATA 0x38
53#define HSI2C_CONF 0x40
54#define HSI2C_AUTO_CONF 0x44
55#define HSI2C_TIMEOUT 0x48
56#define HSI2C_MANUAL_CMD 0x4C
57#define HSI2C_TRANS_STATUS 0x50
58#define HSI2C_TIMING_HS1 0x54
59#define HSI2C_TIMING_HS2 0x58
60#define HSI2C_TIMING_HS3 0x5C
61#define HSI2C_TIMING_FS1 0x60
62#define HSI2C_TIMING_FS2 0x64
63#define HSI2C_TIMING_FS3 0x68
64#define HSI2C_TIMING_SLA 0x6C
65#define HSI2C_ADDR 0x70
66
67/* I2C_CTL Register bits */
68#define HSI2C_FUNC_MODE_I2C (1u << 0)
69#define HSI2C_MASTER (1u << 3)
70#define HSI2C_RXCHON (1u << 6)
71#define HSI2C_TXCHON (1u << 7)
72#define HSI2C_SW_RST (1u << 31)
73
74/* I2C_FIFO_CTL Register bits */
75#define HSI2C_RXFIFO_EN (1u << 0)
76#define HSI2C_TXFIFO_EN (1u << 1)
77#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
78#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
79
80/* As per user manual FIFO max depth is 64bytes */
81#define HSI2C_FIFO_MAX 0x40
82/* default trigger levels for Tx and Rx FIFOs */
83#define HSI2C_DEF_TXFIFO_LVL (HSI2C_FIFO_MAX - 0x30)
84#define HSI2C_DEF_RXFIFO_LVL (HSI2C_FIFO_MAX - 0x10)
85
86/* I2C_TRAILING_CTL Register bits */
87#define HSI2C_TRAILING_COUNT (0xf)
88
89/* I2C_INT_EN Register bits */
90#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
91#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
92#define HSI2C_INT_TRAILING_EN (1u << 6)
93#define HSI2C_INT_I2C_EN (1u << 9)
94
95/* I2C_INT_STAT Register bits */
96#define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
97#define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
98#define HSI2C_INT_TX_UNDERRUN (1u << 2)
99#define HSI2C_INT_TX_OVERRUN (1u << 3)
100#define HSI2C_INT_RX_UNDERRUN (1u << 4)
101#define HSI2C_INT_RX_OVERRUN (1u << 5)
102#define HSI2C_INT_TRAILING (1u << 6)
103#define HSI2C_INT_I2C (1u << 9)
104
105/* I2C_FIFO_STAT Register bits */
106#define HSI2C_RX_FIFO_EMPTY (1u << 24)
107#define HSI2C_RX_FIFO_FULL (1u << 23)
108#define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
109#define HSI2C_TX_FIFO_EMPTY (1u << 8)
110#define HSI2C_TX_FIFO_FULL (1u << 7)
111#define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
112
113/* I2C_CONF Register bits */
114#define HSI2C_AUTO_MODE (1u << 31)
115#define HSI2C_10BIT_ADDR_MODE (1u << 30)
116#define HSI2C_HS_MODE (1u << 29)
117
118/* I2C_AUTO_CONF Register bits */
119#define HSI2C_READ_WRITE (1u << 16)
120#define HSI2C_STOP_AFTER_TRANS (1u << 17)
121#define HSI2C_MASTER_RUN (1u << 31)
122
123/* I2C_TIMEOUT Register bits */
124#define HSI2C_TIMEOUT_EN (1u << 31)
125#define HSI2C_TIMEOUT_MASK 0xff
126
127/* I2C_TRANS_STATUS register bits */
128#define HSI2C_MASTER_BUSY (1u << 17)
129#define HSI2C_SLAVE_BUSY (1u << 16)
130#define HSI2C_TIMEOUT_AUTO (1u << 4)
131#define HSI2C_NO_DEV (1u << 3)
132#define HSI2C_NO_DEV_ACK (1u << 2)
133#define HSI2C_TRANS_ABORT (1u << 1)
134#define HSI2C_TRANS_DONE (1u << 0)
135
136/* I2C_ADDR register bits */
137#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
138#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
139#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
140#define MASTER_ID(x) ((x & 0x7) + 0x08)
141
142/*
143 * Controller operating frequency, timing values for operation
144 * are calculated against this frequency
145 */
146#define HSI2C_HS_TX_CLOCK 1000000
147#define HSI2C_FS_TX_CLOCK 100000
148#define HSI2C_HIGH_SPD 1
149#define HSI2C_FAST_SPD 0
150
151#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
152
153struct exynos5_i2c {
154 struct i2c_adapter adap;
155 unsigned int suspended:1;
156
157 struct i2c_msg *msg;
158 struct completion msg_complete;
159 unsigned int msg_ptr;
160
161 unsigned int irq;
162
163 void __iomem *regs;
164 struct clk *clk;
165 struct device *dev;
166 int state;
167
168 spinlock_t lock; /* IRQ synchronization */
169
170 /*
171 * Since the TRANS_DONE bit is cleared on read, and we may read it
172 * either during an IRQ or after a transaction, keep track of its
173 * state here.
174 */
175 int trans_done;
176
177 /* Controller operating frequency */
178 unsigned int fs_clock;
179 unsigned int hs_clock;
180
181 /*
182 * HSI2C Controller can operate in
183 * 1. High speed upto 3.4Mbps
184 * 2. Fast speed upto 1Mbps
185 */
186 int speed_mode;
187};
188
189static const struct of_device_id exynos5_i2c_match[] = {
190 { .compatible = "samsung,exynos5-hsi2c" },
191 {},
192};
193MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
194
195static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
196{
197 writel(readl(i2c->regs + HSI2C_INT_STATUS),
198 i2c->regs + HSI2C_INT_STATUS);
199}
200
201/*
202 * exynos5_i2c_set_timing: updates the registers with appropriate
203 * timing values calculated
204 *
205 * Returns 0 on success, -EINVAL if the cycle length cannot
206 * be calculated.
207 */
208static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
209{
210 u32 i2c_timing_s1;
211 u32 i2c_timing_s2;
212 u32 i2c_timing_s3;
213 u32 i2c_timing_sla;
214 unsigned int t_start_su, t_start_hd;
215 unsigned int t_stop_su;
216 unsigned int t_data_su, t_data_hd;
217 unsigned int t_scl_l, t_scl_h;
218 unsigned int t_sr_release;
219 unsigned int t_ftl_cycle;
220 unsigned int clkin = clk_get_rate(i2c->clk);
221 unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle;
222 unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ?
223 i2c->hs_clock : i2c->fs_clock;
224
225 /*
226 * FPCLK / FI2C =
227 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
228 * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
229 * utemp1 = (TSCLK_L + TSCLK_H + 2)
230 */
231 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
232 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
233
234 /* CLK_DIV max is 256 */
235 for (div = 0; div < 256; div++) {
236 utemp1 = utemp0 / (div + 1);
237
238 /*
239 * SCL_L and SCL_H each has max value of 255
240 * Hence, For the clk_cycle to the have right value
241 * utemp1 has to be less then 512 and more than 4.
242 */
243 if ((utemp1 < 512) && (utemp1 > 4)) {
244 clk_cycle = utemp1 - 2;
245 break;
246 } else if (div == 255) {
247 dev_warn(i2c->dev, "Failed to calculate divisor");
248 return -EINVAL;
249 }
250 }
251
252 t_scl_l = clk_cycle / 2;
253 t_scl_h = clk_cycle / 2;
254 t_start_su = t_scl_l;
255 t_start_hd = t_scl_l;
256 t_stop_su = t_scl_l;
257 t_data_su = t_scl_l / 2;
258 t_data_hd = t_scl_l / 2;
259 t_sr_release = clk_cycle;
260
261 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
262 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
263 i2c_timing_s3 = div << 16 | t_sr_release << 0;
264 i2c_timing_sla = t_data_hd << 0;
265
266 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
267 t_start_su, t_start_hd, t_stop_su);
268 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
269 t_data_su, t_scl_l, t_scl_h);
270 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
271 div, t_sr_release);
272 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
273
274 if (mode == HSI2C_HIGH_SPD) {
275 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
276 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
277 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
278 } else {
279 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
280 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
281 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
282 }
283 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
284
285 return 0;
286}
287
288static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
289{
290 /*
291 * Configure the Fast speed timing values
292 * Even the High Speed mode initially starts with Fast mode
293 */
294 if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) {
295 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");
296 return -EINVAL;
297 }
298
299 /* configure the High speed timing values */
300 if (i2c->speed_mode == HSI2C_HIGH_SPD) {
301 if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) {
302 dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");
303 return -EINVAL;
304 }
305 }
306
307 return 0;
308}
309
310/*
311 * exynos5_i2c_init: configures the controller for I2C functionality
312 * Programs I2C controller for Master mode operation
313 */
314static void exynos5_i2c_init(struct exynos5_i2c *i2c)
315{
316 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
317 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
318
319 /* Clear to disable Timeout */
320 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
321 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
322
323 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
324 i2c->regs + HSI2C_CTL);
325 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
326
327 if (i2c->speed_mode == HSI2C_HIGH_SPD) {
328 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
329 i2c->regs + HSI2C_ADDR);
330 i2c_conf |= HSI2C_HS_MODE;
331 }
332
333 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
334}
335
336static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
337{
338 u32 i2c_ctl;
339
340 /* Set and clear the bit for reset */
341 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
342 i2c_ctl |= HSI2C_SW_RST;
343 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
344
345 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
346 i2c_ctl &= ~HSI2C_SW_RST;
347 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
348
349 /* We don't expect calculations to fail during the run */
350 exynos5_hsi2c_clock_setup(i2c);
351 /* Initialize the configure registers */
352 exynos5_i2c_init(i2c);
353}
354
355/*
356 * exynos5_i2c_irq: top level IRQ servicing routine
357 *
358 * INT_STATUS registers gives the interrupt details. Further,
359 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
360 * state of the bus.
361 */
362static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
363{
364 struct exynos5_i2c *i2c = dev_id;
365 u32 fifo_level, int_status, fifo_status, trans_status;
366 unsigned char byte;
367 int len = 0;
368
369 i2c->state = -EINVAL;
370
371 spin_lock(&i2c->lock);
372
373 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
374 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
375 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
376
377 /* handle interrupt related to the transfer status */
378 if (int_status & HSI2C_INT_I2C) {
379 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
380 if (trans_status & HSI2C_NO_DEV_ACK) {
381 dev_dbg(i2c->dev, "No ACK from device\n");
382 i2c->state = -ENXIO;
383 goto stop;
384 } else if (trans_status & HSI2C_NO_DEV) {
385 dev_dbg(i2c->dev, "No device\n");
386 i2c->state = -ENXIO;
387 goto stop;
388 } else if (trans_status & HSI2C_TRANS_ABORT) {
389 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
390 i2c->state = -EAGAIN;
391 goto stop;
392 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
393 dev_dbg(i2c->dev, "Accessing device timed out\n");
394 i2c->state = -EAGAIN;
395 goto stop;
396 } else if (trans_status & HSI2C_TRANS_DONE) {
397 i2c->trans_done = 1;
398 i2c->state = 0;
399 }
400 }
401
402 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
403 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
404 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
405 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
406 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
407
408 while (len > 0) {
409 byte = (unsigned char)
410 readl(i2c->regs + HSI2C_RX_DATA);
411 i2c->msg->buf[i2c->msg_ptr++] = byte;
412 len--;
413 }
414 i2c->state = 0;
415 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
416 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
417 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
418
419 len = HSI2C_FIFO_MAX - fifo_level;
420 if (len > (i2c->msg->len - i2c->msg_ptr))
421 len = i2c->msg->len - i2c->msg_ptr;
422
423 while (len > 0) {
424 byte = i2c->msg->buf[i2c->msg_ptr++];
425 writel(byte, i2c->regs + HSI2C_TX_DATA);
426 len--;
427 }
428 i2c->state = 0;
429 }
430
431 stop:
432 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
433 (i2c->state < 0)) {
434 writel(0, i2c->regs + HSI2C_INT_ENABLE);
435 exynos5_i2c_clr_pend_irq(i2c);
436 complete(&i2c->msg_complete);
437 }
438
439 spin_unlock(&i2c->lock);
440
441 return IRQ_HANDLED;
442}
443
444/*
445 * exynos5_i2c_wait_bus_idle
446 *
447 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
448 * cleared.
449 *
450 * Returns -EBUSY if the bus cannot be bought to idle
451 */
452static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
453{
454 unsigned long stop_time;
455 u32 trans_status;
456
457 /* wait for 100 milli seconds for the bus to be idle */
458 stop_time = jiffies + msecs_to_jiffies(100) + 1;
459 do {
460 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
461 if (!(trans_status & HSI2C_MASTER_BUSY))
462 return 0;
463
464 usleep_range(50, 200);
465 } while (time_before(jiffies, stop_time));
466
467 return -EBUSY;
468}
469
470/*
471 * exynos5_i2c_message_start: Configures the bus and starts the xfer
472 * i2c: struct exynos5_i2c pointer for the current bus
473 * stop: Enables stop after transfer if set. Set for last transfer of
474 * in the list of messages.
475 *
476 * Configures the bus for read/write function
477 * Sets chip address to talk to, message length to be sent.
478 * Enables appropriate interrupts and sends start xfer command.
479 */
480static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
481{
482 u32 i2c_ctl;
483 u32 int_en = HSI2C_INT_I2C_EN;
484 u32 i2c_auto_conf = 0;
485 u32 fifo_ctl;
486 unsigned long flags;
487
488 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
489 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
490 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
491
492 if (i2c->msg->flags & I2C_M_RD) {
493 i2c_ctl |= HSI2C_RXCHON;
494
495 i2c_auto_conf = HSI2C_READ_WRITE;
496
497 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(HSI2C_DEF_TXFIFO_LVL);
498 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
499 HSI2C_INT_TRAILING_EN);
500 } else {
501 i2c_ctl |= HSI2C_TXCHON;
502
503 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(HSI2C_DEF_RXFIFO_LVL);
504 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
505 }
506
507 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
508
509 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
510 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
511
512
513 /*
514 * Enable interrupts before starting the transfer so that we don't
515 * miss any INT_I2C interrupts.
516 */
517 spin_lock_irqsave(&i2c->lock, flags);
518 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
519
520 if (stop == 1)
521 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
522 i2c_auto_conf |= i2c->msg->len;
523 i2c_auto_conf |= HSI2C_MASTER_RUN;
524 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
525 spin_unlock_irqrestore(&i2c->lock, flags);
526}
527
528static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
529 struct i2c_msg *msgs, int stop)
530{
531 unsigned long timeout;
532 int ret;
533
534 i2c->msg = msgs;
535 i2c->msg_ptr = 0;
536 i2c->trans_done = 0;
537
538 reinit_completion(&i2c->msg_complete);
539
540 exynos5_i2c_message_start(i2c, stop);
541
542 timeout = wait_for_completion_timeout(&i2c->msg_complete,
543 EXYNOS5_I2C_TIMEOUT);
544 if (timeout == 0)
545 ret = -ETIMEDOUT;
546 else
547 ret = i2c->state;
548
549 /*
550 * If this is the last message to be transfered (stop == 1)
551 * Then check if the bus can be brought back to idle.
552 */
553 if (ret == 0 && stop)
554 ret = exynos5_i2c_wait_bus_idle(i2c);
555
556 if (ret < 0) {
557 exynos5_i2c_reset(i2c);
558 if (ret == -ETIMEDOUT)
559 dev_warn(i2c->dev, "%s timeout\n",
560 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
561 }
562
563 /* Return the state as in interrupt routine */
564 return ret;
565}
566
567static int exynos5_i2c_xfer(struct i2c_adapter *adap,
568 struct i2c_msg *msgs, int num)
569{
570 struct exynos5_i2c *i2c = (struct exynos5_i2c *)adap->algo_data;
571 int i = 0, ret = 0, stop = 0;
572
573 if (i2c->suspended) {
574 dev_err(i2c->dev, "HS-I2C is not initialzed.\n");
575 return -EIO;
576 }
577
578 clk_prepare_enable(i2c->clk);
579
580 for (i = 0; i < num; i++, msgs++) {
581 stop = (i == num - 1);
582
583 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
584
585 if (ret < 0)
586 goto out;
587 }
588
589 if (i == num) {
590 ret = num;
591 } else {
592 /* Only one message, cannot access the device */
593 if (i == 1)
594 ret = -EREMOTEIO;
595 else
596 ret = i;
597
598 dev_warn(i2c->dev, "xfer message failed\n");
599 }
600
601 out:
602 clk_disable_unprepare(i2c->clk);
603 return ret;
604}
605
606static u32 exynos5_i2c_func(struct i2c_adapter *adap)
607{
608 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
609}
610
611static const struct i2c_algorithm exynos5_i2c_algorithm = {
612 .master_xfer = exynos5_i2c_xfer,
613 .functionality = exynos5_i2c_func,
614};
615
616static int exynos5_i2c_probe(struct platform_device *pdev)
617{
618 struct device_node *np = pdev->dev.of_node;
619 struct exynos5_i2c *i2c;
620 struct resource *mem;
621 unsigned int op_clock;
622 int ret;
623
624 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
625 if (!i2c) {
626 dev_err(&pdev->dev, "no memory for state\n");
627 return -ENOMEM;
628 }
629
630 if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
631 i2c->speed_mode = HSI2C_FAST_SPD;
632 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
633 } else {
634 if (op_clock >= HSI2C_HS_TX_CLOCK) {
635 i2c->speed_mode = HSI2C_HIGH_SPD;
636 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
637 i2c->hs_clock = op_clock;
638 } else {
639 i2c->speed_mode = HSI2C_FAST_SPD;
640 i2c->fs_clock = op_clock;
641 }
642 }
643
644 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
645 i2c->adap.owner = THIS_MODULE;
646 i2c->adap.algo = &exynos5_i2c_algorithm;
647 i2c->adap.retries = 3;
648
649 i2c->dev = &pdev->dev;
650 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
651 if (IS_ERR(i2c->clk)) {
652 dev_err(&pdev->dev, "cannot get clock\n");
653 return -ENOENT;
654 }
655
656 clk_prepare_enable(i2c->clk);
657
658 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
659 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
660 if (IS_ERR(i2c->regs)) {
661 ret = PTR_ERR(i2c->regs);
662 goto err_clk;
663 }
664
665 i2c->adap.dev.of_node = np;
666 i2c->adap.algo_data = i2c;
667 i2c->adap.dev.parent = &pdev->dev;
668
669 /* Clear pending interrupts from u-boot or misc causes */
670 exynos5_i2c_clr_pend_irq(i2c);
671
672 spin_lock_init(&i2c->lock);
673 init_completion(&i2c->msg_complete);
674
675 i2c->irq = ret = platform_get_irq(pdev, 0);
676 if (ret <= 0) {
677 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
678 ret = -EINVAL;
679 goto err_clk;
680 }
681
682 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
683 IRQF_NO_SUSPEND | IRQF_ONESHOT,
684 dev_name(&pdev->dev), i2c);
685
686 if (ret != 0) {
687 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
688 goto err_clk;
689 }
690
691 ret = exynos5_hsi2c_clock_setup(i2c);
692 if (ret)
693 goto err_clk;
694
695 exynos5_i2c_init(i2c);
696
697 ret = i2c_add_adapter(&i2c->adap);
698 if (ret < 0) {
699 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
700 goto err_clk;
701 }
702
703 platform_set_drvdata(pdev, i2c);
704
705 err_clk:
706 clk_disable_unprepare(i2c->clk);
707 return ret;
708}
709
710static int exynos5_i2c_remove(struct platform_device *pdev)
711{
712 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
713
714 i2c_del_adapter(&i2c->adap);
715
716 return 0;
717}
718
719static int exynos5_i2c_suspend_noirq(struct device *dev)
720{
721 struct platform_device *pdev = to_platform_device(dev);
722 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
723
724 i2c->suspended = 1;
725
726 return 0;
727}
728
729static int exynos5_i2c_resume_noirq(struct device *dev)
730{
731 struct platform_device *pdev = to_platform_device(dev);
732 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
733 int ret = 0;
734
735 clk_prepare_enable(i2c->clk);
736
737 ret = exynos5_hsi2c_clock_setup(i2c);
738 if (ret) {
739 clk_disable_unprepare(i2c->clk);
740 return ret;
741 }
742
743 exynos5_i2c_init(i2c);
744 clk_disable_unprepare(i2c->clk);
745 i2c->suspended = 0;
746
747 return 0;
748}
749
750static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, exynos5_i2c_suspend_noirq,
751 exynos5_i2c_resume_noirq);
752
753static struct platform_driver exynos5_i2c_driver = {
754 .probe = exynos5_i2c_probe,
755 .remove = exynos5_i2c_remove,
756 .driver = {
757 .owner = THIS_MODULE,
758 .name = "exynos5-hsi2c",
759 .pm = &exynos5_i2c_dev_pm_ops,
760 .of_match_table = exynos5_i2c_match,
761 },
762};
763
764module_platform_driver(exynos5_i2c_driver);
765
766MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
767MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
768MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
769MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
index bfa02c6c2dda..d9f7e186a4c7 100644
--- a/drivers/i2c/busses/i2c-gpio.c
+++ b/drivers/i2c/busses/i2c-gpio.c
@@ -15,6 +15,7 @@
15#include <linux/slab.h> 15#include <linux/slab.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/of.h>
18#include <linux/of_gpio.h> 19#include <linux/of_gpio.h>
19 20
20struct i2c_gpio_private_data { 21struct i2c_gpio_private_data {
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 4296d1721272..737e29866887 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -59,6 +59,7 @@
59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61 Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 61 Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
62 Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
62 63
63 Features supported by this driver: 64 Features supported by this driver:
64 Software PEC no 65 Software PEC no
@@ -177,6 +178,7 @@
177#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 178#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
178#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 179#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
179#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 180#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
181#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
180 182
181struct i801_mux_config { 183struct i801_mux_config {
182 char *gpio_chip; 184 char *gpio_chip;
@@ -819,6 +821,7 @@ static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
824 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
822 { 0, } 825 { 0, }
823}; 826};
824 827
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index d3e9cc3153a9..8be7e42aa4de 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -911,7 +911,7 @@ static struct platform_driver mv64xxx_i2c_driver = {
911 .driver = { 911 .driver = {
912 .owner = THIS_MODULE, 912 .owner = THIS_MODULE,
913 .name = MV64XXX_I2C_CTLR_NAME, 913 .name = MV64XXX_I2C_CTLR_NAME,
914 .of_match_table = of_match_ptr(mv64xxx_i2c_of_match_table), 914 .of_match_table = mv64xxx_i2c_of_match_table,
915 }, 915 },
916}; 916};
917 917
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 3aedd86a6468..0cde4e6ab2b2 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Freescale MXS I2C bus driver 2 * Freescale MXS I2C bus driver
3 * 3 *
4 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
4 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K. 5 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
5 * 6 *
6 * based on a (non-working) driver which was: 7 * based on a (non-working) driver which was:
@@ -34,10 +35,12 @@
34 35
35#define MXS_I2C_CTRL0 (0x00) 36#define MXS_I2C_CTRL0 (0x00)
36#define MXS_I2C_CTRL0_SET (0x04) 37#define MXS_I2C_CTRL0_SET (0x04)
38#define MXS_I2C_CTRL0_CLR (0x08)
37 39
38#define MXS_I2C_CTRL0_SFTRST 0x80000000 40#define MXS_I2C_CTRL0_SFTRST 0x80000000
39#define MXS_I2C_CTRL0_RUN 0x20000000 41#define MXS_I2C_CTRL0_RUN 0x20000000
40#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 42#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
43#define MXS_I2C_CTRL0_PIO_MODE 0x01000000
41#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000 44#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
42#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000 45#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
43#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000 46#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
@@ -64,13 +67,13 @@
64#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01 67#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
65 68
66#define MXS_I2C_STAT (0x50) 69#define MXS_I2C_STAT (0x50)
70#define MXS_I2C_STAT_GOT_A_NAK 0x10000000
67#define MXS_I2C_STAT_BUS_BUSY 0x00000800 71#define MXS_I2C_STAT_BUS_BUSY 0x00000800
68#define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400 72#define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400
69 73
70#define MXS_I2C_DATA (0xa0) 74#define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
71 75
72#define MXS_I2C_DEBUG0 (0xb0) 76#define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
73#define MXS_I2C_DEBUG0_CLR (0xb8)
74 77
75#define MXS_I2C_DEBUG0_DMAREQ 0x80000000 78#define MXS_I2C_DEBUG0_DMAREQ 0x80000000
76 79
@@ -95,10 +98,17 @@
95#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ 98#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
96 MXS_I2C_CTRL0_MASTER_MODE) 99 MXS_I2C_CTRL0_MASTER_MODE)
97 100
101enum mxs_i2c_devtype {
102 MXS_I2C_UNKNOWN = 0,
103 MXS_I2C_V1,
104 MXS_I2C_V2,
105};
106
98/** 107/**
99 * struct mxs_i2c_dev - per device, private MXS-I2C data 108 * struct mxs_i2c_dev - per device, private MXS-I2C data
100 * 109 *
101 * @dev: driver model device node 110 * @dev: driver model device node
111 * @dev_type: distinguish i.MX23/i.MX28 features
102 * @regs: IO registers pointer 112 * @regs: IO registers pointer
103 * @cmd_complete: completion object for transaction wait 113 * @cmd_complete: completion object for transaction wait
104 * @cmd_err: error code for last transaction 114 * @cmd_err: error code for last transaction
@@ -106,6 +116,7 @@
106 */ 116 */
107struct mxs_i2c_dev { 117struct mxs_i2c_dev {
108 struct device *dev; 118 struct device *dev;
119 enum mxs_i2c_devtype dev_type;
109 void __iomem *regs; 120 void __iomem *regs;
110 struct completion cmd_complete; 121 struct completion cmd_complete;
111 int cmd_err; 122 int cmd_err;
@@ -291,48 +302,11 @@ write_init_pio_fail:
291 return -EINVAL; 302 return -EINVAL;
292} 303}
293 304
294static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c) 305static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
295{ 306{
296 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 307 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
297 308
298 while (!(readl(i2c->regs + MXS_I2C_DEBUG0) & 309 while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
299 MXS_I2C_DEBUG0_DMAREQ)) {
300 if (time_after(jiffies, timeout))
301 return -ETIMEDOUT;
302 cond_resched();
303 }
304
305 return 0;
306}
307
308static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c, int last)
309{
310 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
311
312 /*
313 * We do not use interrupts in the PIO mode. Due to the
314 * maximum transfer length being 8 bytes in PIO mode, the
315 * overhead of interrupt would be too large and this would
316 * neglect the gain from using the PIO mode.
317 */
318
319 while (!(readl(i2c->regs + MXS_I2C_CTRL1) &
320 MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) {
321 if (time_after(jiffies, timeout))
322 return -ETIMEDOUT;
323 cond_resched();
324 }
325
326 writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ,
327 i2c->regs + MXS_I2C_CTRL1_CLR);
328
329 /*
330 * When ending a transfer with a stop, we have to wait for the bus to
331 * go idle before we report the transfer as completed. Otherwise the
332 * start of the next transfer may race with the end of the current one.
333 */
334 while (last && (readl(i2c->regs + MXS_I2C_STAT) &
335 (MXS_I2C_STAT_BUS_BUSY | MXS_I2C_STAT_CLK_GEN_BUSY))) {
336 if (time_after(jiffies, timeout)) 310 if (time_after(jiffies, timeout))
337 return -ETIMEDOUT; 311 return -ETIMEDOUT;
338 cond_resched(); 312 cond_resched();
@@ -370,106 +344,215 @@ static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
370 writel(reg, i2c->regs + MXS_I2C_CTRL0); 344 writel(reg, i2c->regs + MXS_I2C_CTRL0);
371} 345}
372 346
347/*
348 * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,
349 * CTRL0::PIO_MODE bit description clarifies the order in which the registers
350 * must be written during PIO mode operation. First, the CTRL0 register has
351 * to be programmed with all the necessary bits but the RUN bit. Then the
352 * payload has to be written into the DATA register. Finally, the transmission
353 * is executed by setting the RUN bit in CTRL0.
354 */
355static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
356 u32 data)
357{
358 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
359
360 if (i2c->dev_type == MXS_I2C_V1)
361 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
362
363 writel(data, i2c->regs + MXS_I2C_DATA(i2c));
364 writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
365}
366
373static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap, 367static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
374 struct i2c_msg *msg, uint32_t flags) 368 struct i2c_msg *msg, uint32_t flags)
375{ 369{
376 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); 370 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
377 uint32_t addr_data = msg->addr << 1; 371 uint32_t addr_data = msg->addr << 1;
378 uint32_t data = 0; 372 uint32_t data = 0;
379 int i, shifts_left, ret; 373 int i, ret, xlen = 0, xmit = 0;
374 uint32_t start;
380 375
381 /* Mute IRQs coming from this block. */ 376 /* Mute IRQs coming from this block. */
382 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR); 377 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
383 378
379 /*
380 * MX23 idea:
381 * - Enable CTRL0::PIO_MODE (1 << 24)
382 * - Enable CTRL1::ACK_MODE (1 << 27)
383 *
384 * WARNING! The MX23 is broken in some way, even if it claims
385 * to support PIO, when we try to transfer any amount of data
386 * that is not aligned to 4 bytes, the DMA engine will have
387 * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
388 * transfer. This in turn will mess up the next transfer as
389 * the block it emit one byte write onto the bus terminated
390 * with a NAK+STOP. A possible workaround is to reset the IP
391 * block after every PIO transmission, which might just work.
392 *
393 * NOTE: The CTRL0::PIO_MODE description is important, since
394 * it outlines how the PIO mode is really supposed to work.
395 */
384 if (msg->flags & I2C_M_RD) { 396 if (msg->flags & I2C_M_RD) {
397 /*
398 * PIO READ transfer:
399 *
400 * This transfer MUST be limited to 4 bytes maximum. It is not
401 * possible to transfer more than four bytes via PIO, since we
402 * can not in any way make sure we can read the data from the
403 * DATA register fast enough. Besides, the RX FIFO is only four
404 * bytes deep, thus we can only really read up to four bytes at
405 * time. Finally, there is no bit indicating us that new data
406 * arrived at the FIFO and can thus be fetched from the DATA
407 * register.
408 */
409 BUG_ON(msg->len > 4);
410
385 addr_data |= I2C_SMBUS_READ; 411 addr_data |= I2C_SMBUS_READ;
386 412
387 /* SELECT command. */ 413 /* SELECT command. */
388 mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT); 414 mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
389 415 addr_data);
390 ret = mxs_i2c_pio_wait_dmareq(i2c);
391 if (ret)
392 return ret;
393
394 writel(addr_data, i2c->regs + MXS_I2C_DATA);
395 writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR);
396 416
397 ret = mxs_i2c_pio_wait_cplt(i2c, 0); 417 ret = mxs_i2c_pio_wait_xfer_end(i2c);
398 if (ret) 418 if (ret) {
399 return ret; 419 dev_err(i2c->dev,
400 420 "PIO: Failed to send SELECT command!\n");
401 if (mxs_i2c_pio_check_error_state(i2c))
402 goto cleanup; 421 goto cleanup;
422 }
403 423
404 /* READ command. */ 424 /* READ command. */
405 mxs_i2c_pio_trigger_cmd(i2c, 425 mxs_i2c_pio_trigger_cmd(i2c,
406 MXS_CMD_I2C_READ | flags | 426 MXS_CMD_I2C_READ | flags |
407 MXS_I2C_CTRL0_XFER_COUNT(msg->len)); 427 MXS_I2C_CTRL0_XFER_COUNT(msg->len));
408 428
429 ret = mxs_i2c_pio_wait_xfer_end(i2c);
430 if (ret) {
431 dev_err(i2c->dev,
432 "PIO: Failed to send SELECT command!\n");
433 goto cleanup;
434 }
435
436 data = readl(i2c->regs + MXS_I2C_DATA(i2c));
409 for (i = 0; i < msg->len; i++) { 437 for (i = 0; i < msg->len; i++) {
410 if ((i & 3) == 0) {
411 ret = mxs_i2c_pio_wait_dmareq(i2c);
412 if (ret)
413 return ret;
414 data = readl(i2c->regs + MXS_I2C_DATA);
415 writel(MXS_I2C_DEBUG0_DMAREQ,
416 i2c->regs + MXS_I2C_DEBUG0_CLR);
417 }
418 msg->buf[i] = data & 0xff; 438 msg->buf[i] = data & 0xff;
419 data >>= 8; 439 data >>= 8;
420 } 440 }
421 } else { 441 } else {
442 /*
443 * PIO WRITE transfer:
444 *
445 * The code below implements clock stretching to circumvent
446 * the possibility of kernel not being able to supply data
447 * fast enough. It is possible to transfer arbitrary amount
448 * of data using PIO write.
449 */
422 addr_data |= I2C_SMBUS_WRITE; 450 addr_data |= I2C_SMBUS_WRITE;
423 451
424 /* WRITE command. */
425 mxs_i2c_pio_trigger_cmd(i2c,
426 MXS_CMD_I2C_WRITE | flags |
427 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1));
428
429 /* 452 /*
430 * The LSB of data buffer is the first byte blasted across 453 * The LSB of data buffer is the first byte blasted across
431 * the bus. Higher order bytes follow. Thus the following 454 * the bus. Higher order bytes follow. Thus the following
432 * filling schematic. 455 * filling schematic.
433 */ 456 */
457
434 data = addr_data << 24; 458 data = addr_data << 24;
459
460 /* Start the transfer with START condition. */
461 start = MXS_I2C_CTRL0_PRE_SEND_START;
462
463 /* If the transfer is long, use clock stretching. */
464 if (msg->len > 3)
465 start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
466
435 for (i = 0; i < msg->len; i++) { 467 for (i = 0; i < msg->len; i++) {
436 data >>= 8; 468 data >>= 8;
437 data |= (msg->buf[i] << 24); 469 data |= (msg->buf[i] << 24);
438 if ((i & 3) == 2) { 470
439 ret = mxs_i2c_pio_wait_dmareq(i2c); 471 xmit = 0;
440 if (ret) 472
441 return ret; 473 /* This is the last transfer of the message. */
442 writel(data, i2c->regs + MXS_I2C_DATA); 474 if (i + 1 == msg->len) {
443 writel(MXS_I2C_DEBUG0_DMAREQ, 475 /* Add optional STOP flag. */
444 i2c->regs + MXS_I2C_DEBUG0_CLR); 476 start |= flags;
477 /* Remove RETAIN_CLOCK bit. */
478 start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
479 xmit = 1;
445 } 480 }
446 }
447 481
448 shifts_left = 24 - (i & 3) * 8; 482 /* Four bytes are ready in the "data" variable. */
449 if (shifts_left) { 483 if ((i & 3) == 2)
450 data >>= shifts_left; 484 xmit = 1;
451 ret = mxs_i2c_pio_wait_dmareq(i2c); 485
452 if (ret) 486 /* Nothing interesting happened, continue stuffing. */
453 return ret; 487 if (!xmit)
454 writel(data, i2c->regs + MXS_I2C_DATA); 488 continue;
489
490 /*
491 * Compute the size of the transfer and shift the
492 * data accordingly.
493 *
494 * i = (4k + 0) .... xlen = 2
495 * i = (4k + 1) .... xlen = 3
496 * i = (4k + 2) .... xlen = 4
497 * i = (4k + 3) .... xlen = 1
498 */
499
500 if ((i % 4) == 3)
501 xlen = 1;
502 else
503 xlen = (i % 4) + 2;
504
505 data >>= (4 - xlen) * 8;
506
507 dev_dbg(i2c->dev,
508 "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
509 xlen, i, msg->len,
510 start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
511 start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
512 start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
513
455 writel(MXS_I2C_DEBUG0_DMAREQ, 514 writel(MXS_I2C_DEBUG0_DMAREQ,
456 i2c->regs + MXS_I2C_DEBUG0_CLR); 515 i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
516
517 mxs_i2c_pio_trigger_write_cmd(i2c,
518 start | MXS_I2C_CTRL0_MASTER_MODE |
519 MXS_I2C_CTRL0_DIRECTION |
520 MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
521
522 /* The START condition is sent only once. */
523 start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
524
525 /* Wait for the end of the transfer. */
526 ret = mxs_i2c_pio_wait_xfer_end(i2c);
527 if (ret) {
528 dev_err(i2c->dev,
529 "PIO: Failed to finish WRITE cmd!\n");
530 break;
531 }
532
533 /* Check NAK here. */
534 ret = readl(i2c->regs + MXS_I2C_STAT) &
535 MXS_I2C_STAT_GOT_A_NAK;
536 if (ret) {
537 ret = -ENXIO;
538 goto cleanup;
539 }
457 } 540 }
458 } 541 }
459 542
460 ret = mxs_i2c_pio_wait_cplt(i2c, flags & MXS_I2C_CTRL0_POST_SEND_STOP);
461 if (ret)
462 return ret;
463
464 /* make sure we capture any occurred error into cmd_err */ 543 /* make sure we capture any occurred error into cmd_err */
465 mxs_i2c_pio_check_error_state(i2c); 544 ret = mxs_i2c_pio_check_error_state(i2c);
466 545
467cleanup: 546cleanup:
468 /* Clear any dangling IRQs and re-enable interrupts. */ 547 /* Clear any dangling IRQs and re-enable interrupts. */
469 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR); 548 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
470 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); 549 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
471 550
472 return 0; 551 /* Clear the PIO_MODE on i.MX23 */
552 if (i2c->dev_type == MXS_I2C_V1)
553 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
554
555 return ret;
473} 556}
474 557
475/* 558/*
@@ -479,8 +562,9 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
479 int stop) 562 int stop)
480{ 563{
481 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); 564 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
482 int ret, err; 565 int ret;
483 int flags; 566 int flags;
567 int use_pio = 0;
484 568
485 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; 569 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
486 570
@@ -491,19 +575,21 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
491 return -EINVAL; 575 return -EINVAL;
492 576
493 /* 577 /*
494 * The current boundary to select between PIO/DMA transfer method 578 * The MX28 I2C IP block can only do PIO READ for transfer of to up
495 * is set to 8 bytes, transfers shorter than 8 bytes are transfered 579 * 4 bytes of length. The write transfer is not limited as it can use
496 * using PIO mode while longer transfers use DMA. The 8 byte border is 580 * clock stretching to avoid FIFO underruns.
497 * based on this empirical measurement and a lot of previous frobbing.
498 */ 581 */
582 if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
583 use_pio = 1;
584 if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
585 use_pio = 1;
586
499 i2c->cmd_err = 0; 587 i2c->cmd_err = 0;
500 if (0) { /* disable PIO mode until a proper fix is made */ 588 if (use_pio) {
501 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags); 589 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
502 if (ret) { 590 /* No need to reset the block if NAK was received. */
503 err = mxs_i2c_reset(i2c); 591 if (ret && (ret != -ENXIO))
504 if (err) 592 mxs_i2c_reset(i2c);
505 return err;
506 }
507 } else { 593 } else {
508 reinit_completion(&i2c->cmd_complete); 594 reinit_completion(&i2c->cmd_complete);
509 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); 595 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
@@ -514,9 +600,11 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
514 msecs_to_jiffies(1000)); 600 msecs_to_jiffies(1000));
515 if (ret == 0) 601 if (ret == 0)
516 goto timeout; 602 goto timeout;
603
604 ret = i2c->cmd_err;
517 } 605 }
518 606
519 if (i2c->cmd_err == -ENXIO) { 607 if (ret == -ENXIO) {
520 /* 608 /*
521 * If the transfer fails with a NAK from the slave the 609 * If the transfer fails with a NAK from the slave the
522 * controller halts until it gets told to return to idle state. 610 * controller halts until it gets told to return to idle state.
@@ -525,7 +613,19 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
525 i2c->regs + MXS_I2C_CTRL1_SET); 613 i2c->regs + MXS_I2C_CTRL1_SET);
526 } 614 }
527 615
528 ret = i2c->cmd_err; 616 /*
617 * WARNING!
618 * The i.MX23 is strange. After each and every operation, it's I2C IP
619 * block must be reset, otherwise the IP block will misbehave. This can
620 * be observed on the bus by the block sending out one single byte onto
621 * the bus. In case such an error happens, bit 27 will be set in the
622 * DEBUG0 register. This bit is not documented in the i.MX23 datasheet
623 * and is marked as "TBD" instead. To reset this bit to a correct state,
624 * reset the whole block. Since the block reset does not take long, do
625 * reset the block after every transfer to play safe.
626 */
627 if (i2c->dev_type == MXS_I2C_V1)
628 mxs_i2c_reset(i2c);
529 629
530 dev_dbg(i2c->dev, "Done with err=%d\n", ret); 630 dev_dbg(i2c->dev, "Done with err=%d\n", ret);
531 631
@@ -680,8 +780,28 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
680 return 0; 780 return 0;
681} 781}
682 782
783static struct platform_device_id mxs_i2c_devtype[] = {
784 {
785 .name = "imx23-i2c",
786 .driver_data = MXS_I2C_V1,
787 }, {
788 .name = "imx28-i2c",
789 .driver_data = MXS_I2C_V2,
790 }, { /* sentinel */ }
791};
792MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype);
793
794static const struct of_device_id mxs_i2c_dt_ids[] = {
795 { .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], },
796 { .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], },
797 { /* sentinel */ }
798};
799MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
800
683static int mxs_i2c_probe(struct platform_device *pdev) 801static int mxs_i2c_probe(struct platform_device *pdev)
684{ 802{
803 const struct of_device_id *of_id =
804 of_match_device(mxs_i2c_dt_ids, &pdev->dev);
685 struct device *dev = &pdev->dev; 805 struct device *dev = &pdev->dev;
686 struct mxs_i2c_dev *i2c; 806 struct mxs_i2c_dev *i2c;
687 struct i2c_adapter *adap; 807 struct i2c_adapter *adap;
@@ -693,6 +813,11 @@ static int mxs_i2c_probe(struct platform_device *pdev)
693 if (!i2c) 813 if (!i2c)
694 return -ENOMEM; 814 return -ENOMEM;
695 815
816 if (of_id) {
817 const struct platform_device_id *device_id = of_id->data;
818 i2c->dev_type = device_id->driver_data;
819 }
820
696 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 821 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
697 irq = platform_get_irq(pdev, 0); 822 irq = platform_get_irq(pdev, 0);
698 823
@@ -768,12 +893,6 @@ static int mxs_i2c_remove(struct platform_device *pdev)
768 return 0; 893 return 0;
769} 894}
770 895
771static const struct of_device_id mxs_i2c_dt_ids[] = {
772 { .compatible = "fsl,imx28-i2c", },
773 { /* sentinel */ }
774};
775MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
776
777static struct platform_driver mxs_i2c_driver = { 896static struct platform_driver mxs_i2c_driver = {
778 .driver = { 897 .driver = {
779 .name = DRIVER_NAME, 898 .name = DRIVER_NAME,
@@ -796,6 +915,7 @@ static void __exit mxs_i2c_exit(void)
796} 915}
797module_exit(mxs_i2c_exit); 916module_exit(mxs_i2c_exit);
798 917
918MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
799MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 919MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
800MODULE_DESCRIPTION("MXS I2C Bus Driver"); 920MODULE_DESCRIPTION("MXS I2C Bus Driver");
801MODULE_LICENSE("GPL"); 921MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c
index 1a9ea25f2314..c9a352f0a9a5 100644
--- a/drivers/i2c/busses/i2c-pnx.c
+++ b/drivers/i2c/busses/i2c-pnx.c
@@ -23,6 +23,7 @@
23#include <linux/err.h> 23#include <linux/err.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/of.h>
26 27
27#define I2C_PNX_TIMEOUT_DEFAULT 10 /* msec */ 28#define I2C_PNX_TIMEOUT_DEFAULT 10 /* msec */
28#define I2C_PNX_SPEED_KHZ_DEFAULT 100 29#define I2C_PNX_SPEED_KHZ_DEFAULT 100
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index d2fe11da5e82..2c2fd7c2b116 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -33,6 +33,7 @@
33#include <linux/i2c/i2c-rcar.h> 33#include <linux/i2c/i2c-rcar.h>
34#include <linux/kernel.h> 34#include <linux/kernel.h>
35#include <linux/module.h> 35#include <linux/module.h>
36#include <linux/of_device.h>
36#include <linux/platform_device.h> 37#include <linux/platform_device.h>
37#include <linux/pm_runtime.h> 38#include <linux/pm_runtime.h>
38#include <linux/slab.h> 39#include <linux/slab.h>
@@ -102,8 +103,8 @@ enum {
102#define ID_NACK (1 << 4) 103#define ID_NACK (1 << 4)
103 104
104enum rcar_i2c_type { 105enum rcar_i2c_type {
105 I2C_RCAR_H1, 106 I2C_RCAR_GEN1,
106 I2C_RCAR_H2, 107 I2C_RCAR_GEN2,
107}; 108};
108 109
109struct rcar_i2c_priv { 110struct rcar_i2c_priv {
@@ -226,22 +227,23 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
226 u32 bus_speed, 227 u32 bus_speed,
227 struct device *dev) 228 struct device *dev)
228{ 229{
229 struct clk *clkp = clk_get(NULL, "peripheral_clk"); 230 struct clk *clkp = clk_get(dev, NULL);
230 u32 scgd, cdf; 231 u32 scgd, cdf;
231 u32 round, ick; 232 u32 round, ick;
232 u32 scl; 233 u32 scl;
233 u32 cdf_width; 234 u32 cdf_width;
235 unsigned long rate;
234 236
235 if (!clkp) { 237 if (IS_ERR(clkp)) {
236 dev_err(dev, "there is no peripheral_clk\n"); 238 dev_err(dev, "couldn't get clock\n");
237 return -EIO; 239 return PTR_ERR(clkp);
238 } 240 }
239 241
240 switch (priv->devtype) { 242 switch (priv->devtype) {
241 case I2C_RCAR_H1: 243 case I2C_RCAR_GEN1:
242 cdf_width = 2; 244 cdf_width = 2;
243 break; 245 break;
244 case I2C_RCAR_H2: 246 case I2C_RCAR_GEN2:
245 cdf_width = 3; 247 cdf_width = 3;
246 break; 248 break;
247 default: 249 default:
@@ -264,15 +266,14 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
264 * clkp : peripheral_clk 266 * clkp : peripheral_clk
265 * F[] : integer up-valuation 267 * F[] : integer up-valuation
266 */ 268 */
267 for (cdf = 0; cdf < (1 << cdf_width); cdf++) { 269 rate = clk_get_rate(clkp);
268 ick = clk_get_rate(clkp) / (1 + cdf); 270 cdf = rate / 20000000;
269 if (ick < 20000000) 271 if (cdf >= 1 << cdf_width) {
270 goto ick_find; 272 dev_err(dev, "Input clock %lu too high\n", rate);
273 return -EIO;
271 } 274 }
272 dev_err(dev, "there is no best CDF\n"); 275 ick = rate / (cdf + 1);
273 return -EIO;
274 276
275ick_find:
276 /* 277 /*
277 * it is impossible to calculate large scale 278 * it is impossible to calculate large scale
278 * number on u32. separate it 279 * number on u32. separate it
@@ -290,6 +291,12 @@ ick_find:
290 * 291 *
291 * Calculation result (= SCL) should be less than 292 * Calculation result (= SCL) should be less than
292 * bus_speed for hardware safety 293 * bus_speed for hardware safety
294 *
295 * We could use something along the lines of
296 * div = ick / (bus_speed + 1) + 1;
297 * scgd = (div - 20 - round + 7) / 8;
298 * scl = ick / (20 + (scgd * 8) + round);
299 * (not fully verified) but that would get pretty involved
293 */ 300 */
294 for (scgd = 0; scgd < 0x40; scgd++) { 301 for (scgd = 0; scgd < 0x40; scgd++) {
295 scl = ick / (20 + (scgd * 8) + round); 302 scl = ick / (20 + (scgd * 8) + round);
@@ -306,7 +313,7 @@ scgd_find:
306 /* 313 /*
307 * keep icccr value 314 * keep icccr value
308 */ 315 */
309 priv->icccr = (scgd << (cdf_width) | cdf); 316 priv->icccr = scgd << cdf_width | cdf;
310 317
311 return 0; 318 return 0;
312} 319}
@@ -632,6 +639,15 @@ static const struct i2c_algorithm rcar_i2c_algo = {
632 .functionality = rcar_i2c_func, 639 .functionality = rcar_i2c_func,
633}; 640};
634 641
642static const struct of_device_id rcar_i2c_dt_ids[] = {
643 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
644 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
645 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
646 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
647 {},
648};
649MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
650
635static int rcar_i2c_probe(struct platform_device *pdev) 651static int rcar_i2c_probe(struct platform_device *pdev)
636{ 652{
637 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev); 653 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
@@ -649,10 +665,15 @@ static int rcar_i2c_probe(struct platform_device *pdev)
649 } 665 }
650 666
651 bus_speed = 100000; /* default 100 kHz */ 667 bus_speed = 100000; /* default 100 kHz */
652 if (pdata && pdata->bus_speed) 668 ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
669 if (ret < 0 && pdata && pdata->bus_speed)
653 bus_speed = pdata->bus_speed; 670 bus_speed = pdata->bus_speed;
654 671
655 priv->devtype = platform_get_device_id(pdev)->driver_data; 672 if (pdev->dev.of_node)
673 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
674 dev)->data;
675 else
676 priv->devtype = platform_get_device_id(pdev)->driver_data;
656 677
657 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); 678 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
658 if (ret < 0) 679 if (ret < 0)
@@ -673,6 +694,7 @@ static int rcar_i2c_probe(struct platform_device *pdev)
673 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 694 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
674 adap->retries = 3; 695 adap->retries = 3;
675 adap->dev.parent = dev; 696 adap->dev.parent = dev;
697 adap->dev.of_node = dev->of_node;
676 i2c_set_adapdata(adap, priv); 698 i2c_set_adapdata(adap, priv);
677 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 699 strlcpy(adap->name, pdev->name, sizeof(adap->name));
678 700
@@ -709,9 +731,9 @@ static int rcar_i2c_remove(struct platform_device *pdev)
709} 731}
710 732
711static struct platform_device_id rcar_i2c_id_table[] = { 733static struct platform_device_id rcar_i2c_id_table[] = {
712 { "i2c-rcar", I2C_RCAR_H1 }, 734 { "i2c-rcar", I2C_RCAR_GEN1 },
713 { "i2c-rcar_h1", I2C_RCAR_H1 }, 735 { "i2c-rcar_gen1", I2C_RCAR_GEN1 },
714 { "i2c-rcar_h2", I2C_RCAR_H2 }, 736 { "i2c-rcar_gen2", I2C_RCAR_GEN2 },
715 {}, 737 {},
716}; 738};
717MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table); 739MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
@@ -720,6 +742,7 @@ static struct platform_driver rcar_i2c_driver = {
720 .driver = { 742 .driver = {
721 .name = "i2c-rcar", 743 .name = "i2c-rcar",
722 .owner = THIS_MODULE, 744 .owner = THIS_MODULE,
745 .of_match_table = rcar_i2c_dt_ids,
723 }, 746 },
724 .probe = rcar_i2c_probe, 747 .probe = rcar_i2c_probe,
725 .remove = rcar_i2c_remove, 748 .remove = rcar_i2c_remove,
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 3747b9bf67d6..bf8fb94ebc5d 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -36,6 +36,7 @@
36#include <linux/cpufreq.h> 36#include <linux/cpufreq.h>
37#include <linux/slab.h> 37#include <linux/slab.h>
38#include <linux/io.h> 38#include <linux/io.h>
39#include <linux/of.h>
39#include <linux/of_gpio.h> 40#include <linux/of_gpio.h>
40#include <linux/pinctrl/consumer.h> 41#include <linux/pinctrl/consumer.h>
41 42
diff --git a/drivers/i2c/busses/i2c-scmi.c b/drivers/i2c/busses/i2c-scmi.c
index c447e8d40b78..599235514138 100644
--- a/drivers/i2c/busses/i2c-scmi.c
+++ b/drivers/i2c/busses/i2c-scmi.c
@@ -223,7 +223,7 @@ acpi_smbus_cmi_access(struct i2c_adapter *adap, u16 addr, unsigned short flags,
223 goto out; 223 goto out;
224 224
225 obj = pkg->package.elements + 1; 225 obj = pkg->package.elements + 1;
226 if (obj == NULL || obj->type != ACPI_TYPE_INTEGER) { 226 if (obj->type != ACPI_TYPE_INTEGER) {
227 ACPI_ERROR((AE_INFO, "Invalid argument type")); 227 ACPI_ERROR((AE_INFO, "Invalid argument type"));
228 result = -EIO; 228 result = -EIO;
229 goto out; 229 goto out;
@@ -235,7 +235,7 @@ acpi_smbus_cmi_access(struct i2c_adapter *adap, u16 addr, unsigned short flags,
235 case I2C_SMBUS_BYTE: 235 case I2C_SMBUS_BYTE:
236 case I2C_SMBUS_BYTE_DATA: 236 case I2C_SMBUS_BYTE_DATA:
237 case I2C_SMBUS_WORD_DATA: 237 case I2C_SMBUS_WORD_DATA:
238 if (obj == NULL || obj->type != ACPI_TYPE_INTEGER) { 238 if (obj->type != ACPI_TYPE_INTEGER) {
239 ACPI_ERROR((AE_INFO, "Invalid argument type")); 239 ACPI_ERROR((AE_INFO, "Invalid argument type"));
240 result = -EIO; 240 result = -EIO;
241 goto out; 241 goto out;
@@ -246,7 +246,7 @@ acpi_smbus_cmi_access(struct i2c_adapter *adap, u16 addr, unsigned short flags,
246 data->byte = obj->integer.value; 246 data->byte = obj->integer.value;
247 break; 247 break;
248 case I2C_SMBUS_BLOCK_DATA: 248 case I2C_SMBUS_BLOCK_DATA:
249 if (obj == NULL || obj->type != ACPI_TYPE_BUFFER) { 249 if (obj->type != ACPI_TYPE_BUFFER) {
250 ACPI_ERROR((AE_INFO, "Invalid argument type")); 250 ACPI_ERROR((AE_INFO, "Invalid argument type"));
251 result = -EIO; 251 result = -EIO;
252 goto out; 252 goto out;
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 55110ddbed1f..1d79585ba4b3 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -235,7 +235,7 @@ static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
235 int offset; 235 int offset;
236 236
237 /* Get clock rate after clock is enabled */ 237 /* Get clock rate after clock is enabled */
238 clk_enable(pd->clk); 238 clk_prepare_enable(pd->clk);
239 i2c_clk_khz = clk_get_rate(pd->clk) / 1000; 239 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
240 i2c_clk_khz /= pd->clks_per_count; 240 i2c_clk_khz /= pd->clks_per_count;
241 241
@@ -270,14 +270,14 @@ static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
270 pd->icic &= ~ICIC_ICCHB8; 270 pd->icic &= ~ICIC_ICCHB8;
271 271
272out: 272out:
273 clk_disable(pd->clk); 273 clk_disable_unprepare(pd->clk);
274} 274}
275 275
276static void activate_ch(struct sh_mobile_i2c_data *pd) 276static void activate_ch(struct sh_mobile_i2c_data *pd)
277{ 277{
278 /* Wake up device and enable clock */ 278 /* Wake up device and enable clock */
279 pm_runtime_get_sync(pd->dev); 279 pm_runtime_get_sync(pd->dev);
280 clk_enable(pd->clk); 280 clk_prepare_enable(pd->clk);
281 281
282 /* Enable channel and configure rx ack */ 282 /* Enable channel and configure rx ack */
283 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 283 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
@@ -300,7 +300,7 @@ static void deactivate_ch(struct sh_mobile_i2c_data *pd)
300 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 300 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
301 301
302 /* Disable clock and mark device as idle */ 302 /* Disable clock and mark device as idle */
303 clk_disable(pd->clk); 303 clk_disable_unprepare(pd->clk);
304 pm_runtime_put_sync(pd->dev); 304 pm_runtime_put_sync(pd->dev);
305} 305}
306 306
diff --git a/drivers/i2c/busses/i2c-st.c b/drivers/i2c/busses/i2c-st.c
new file mode 100644
index 000000000000..9cf715d69551
--- /dev/null
+++ b/drivers/i2c/busses/i2c-st.c
@@ -0,0 +1,872 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics
3 *
4 * I2C master mode controller driver, used in STMicroelectronics devices.
5 *
6 * Author: Maxime Coquelin <maxime.coquelin@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2, as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/i2c.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/err.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24
25/* SSC registers */
26#define SSC_BRG 0x000
27#define SSC_TBUF 0x004
28#define SSC_RBUF 0x008
29#define SSC_CTL 0x00C
30#define SSC_IEN 0x010
31#define SSC_STA 0x014
32#define SSC_I2C 0x018
33#define SSC_SLAD 0x01C
34#define SSC_REP_START_HOLD 0x020
35#define SSC_START_HOLD 0x024
36#define SSC_REP_START_SETUP 0x028
37#define SSC_DATA_SETUP 0x02C
38#define SSC_STOP_SETUP 0x030
39#define SSC_BUS_FREE 0x034
40#define SSC_TX_FSTAT 0x038
41#define SSC_RX_FSTAT 0x03C
42#define SSC_PRE_SCALER_BRG 0x040
43#define SSC_CLR 0x080
44#define SSC_NOISE_SUPP_WIDTH 0x100
45#define SSC_PRSCALER 0x104
46#define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108
47#define SSC_PRSCALER_DATAOUT 0x10c
48
49/* SSC Control */
50#define SSC_CTL_DATA_WIDTH_9 0x8
51#define SSC_CTL_DATA_WIDTH_MSK 0xf
52#define SSC_CTL_BM 0xf
53#define SSC_CTL_HB BIT(4)
54#define SSC_CTL_PH BIT(5)
55#define SSC_CTL_PO BIT(6)
56#define SSC_CTL_SR BIT(7)
57#define SSC_CTL_MS BIT(8)
58#define SSC_CTL_EN BIT(9)
59#define SSC_CTL_LPB BIT(10)
60#define SSC_CTL_EN_TX_FIFO BIT(11)
61#define SSC_CTL_EN_RX_FIFO BIT(12)
62#define SSC_CTL_EN_CLST_RX BIT(13)
63
64/* SSC Interrupt Enable */
65#define SSC_IEN_RIEN BIT(0)
66#define SSC_IEN_TIEN BIT(1)
67#define SSC_IEN_TEEN BIT(2)
68#define SSC_IEN_REEN BIT(3)
69#define SSC_IEN_PEEN BIT(4)
70#define SSC_IEN_AASEN BIT(6)
71#define SSC_IEN_STOPEN BIT(7)
72#define SSC_IEN_ARBLEN BIT(8)
73#define SSC_IEN_NACKEN BIT(10)
74#define SSC_IEN_REPSTRTEN BIT(11)
75#define SSC_IEN_TX_FIFO_HALF BIT(12)
76#define SSC_IEN_RX_FIFO_HALF_FULL BIT(14)
77
78/* SSC Status */
79#define SSC_STA_RIR BIT(0)
80#define SSC_STA_TIR BIT(1)
81#define SSC_STA_TE BIT(2)
82#define SSC_STA_RE BIT(3)
83#define SSC_STA_PE BIT(4)
84#define SSC_STA_CLST BIT(5)
85#define SSC_STA_AAS BIT(6)
86#define SSC_STA_STOP BIT(7)
87#define SSC_STA_ARBL BIT(8)
88#define SSC_STA_BUSY BIT(9)
89#define SSC_STA_NACK BIT(10)
90#define SSC_STA_REPSTRT BIT(11)
91#define SSC_STA_TX_FIFO_HALF BIT(12)
92#define SSC_STA_TX_FIFO_FULL BIT(13)
93#define SSC_STA_RX_FIFO_HALF BIT(14)
94
95/* SSC I2C Control */
96#define SSC_I2C_I2CM BIT(0)
97#define SSC_I2C_STRTG BIT(1)
98#define SSC_I2C_STOPG BIT(2)
99#define SSC_I2C_ACKG BIT(3)
100#define SSC_I2C_AD10 BIT(4)
101#define SSC_I2C_TXENB BIT(5)
102#define SSC_I2C_REPSTRTG BIT(11)
103#define SSC_I2C_SLAVE_DISABLE BIT(12)
104
105/* SSC Tx FIFO Status */
106#define SSC_TX_FSTAT_STATUS 0x07
107
108/* SSC Rx FIFO Status */
109#define SSC_RX_FSTAT_STATUS 0x07
110
111/* SSC Clear bit operation */
112#define SSC_CLR_SSCAAS BIT(6)
113#define SSC_CLR_SSCSTOP BIT(7)
114#define SSC_CLR_SSCARBL BIT(8)
115#define SSC_CLR_NACK BIT(10)
116#define SSC_CLR_REPSTRT BIT(11)
117
118/* SSC Clock Prescaler */
119#define SSC_PRSC_VALUE 0x0f
120
121
122#define SSC_TXFIFO_SIZE 0x8
123#define SSC_RXFIFO_SIZE 0x8
124
125enum st_i2c_mode {
126 I2C_MODE_STANDARD,
127 I2C_MODE_FAST,
128 I2C_MODE_END,
129};
130
131/**
132 * struct st_i2c_timings - per-Mode tuning parameters
133 * @rate: I2C bus rate
134 * @rep_start_hold: I2C repeated start hold time requirement
135 * @rep_start_setup: I2C repeated start set up time requirement
136 * @start_hold: I2C start hold time requirement
137 * @data_setup_time: I2C data set up time requirement
138 * @stop_setup_time: I2C stop set up time requirement
139 * @bus_free_time: I2C bus free time requirement
140 * @sda_pulse_min_limit: I2C SDA pulse mini width limit
141 */
142struct st_i2c_timings {
143 u32 rate;
144 u32 rep_start_hold;
145 u32 rep_start_setup;
146 u32 start_hold;
147 u32 data_setup_time;
148 u32 stop_setup_time;
149 u32 bus_free_time;
150 u32 sda_pulse_min_limit;
151};
152
153/**
154 * struct st_i2c_client - client specific data
155 * @addr: 8-bit slave addr, including r/w bit
156 * @count: number of bytes to be transfered
157 * @xfered: number of bytes already transferred
158 * @buf: data buffer
159 * @result: result of the transfer
160 * @stop: last I2C msg to be sent, i.e. STOP to be generated
161 */
162struct st_i2c_client {
163 u8 addr;
164 u32 count;
165 u32 xfered;
166 u8 *buf;
167 int result;
168 bool stop;
169};
170
171/**
172 * struct st_i2c_dev - private data of the controller
173 * @adap: I2C adapter for this controller
174 * @dev: device for this controller
175 * @base: virtual memory area
176 * @complete: completion of I2C message
177 * @irq: interrupt line for th controller
178 * @clk: hw ssc block clock
179 * @mode: I2C mode of the controller. Standard or Fast only supported
180 * @scl_min_width_us: SCL line minimum pulse width in us
181 * @sda_min_width_us: SDA line minimum pulse width in us
182 * @client: I2C transfert information
183 * @busy: I2C transfer on-going
184 */
185struct st_i2c_dev {
186 struct i2c_adapter adap;
187 struct device *dev;
188 void __iomem *base;
189 struct completion complete;
190 int irq;
191 struct clk *clk;
192 int mode;
193 u32 scl_min_width_us;
194 u32 sda_min_width_us;
195 struct st_i2c_client client;
196 bool busy;
197};
198
199static inline void st_i2c_set_bits(void __iomem *reg, u32 mask)
200{
201 writel_relaxed(readl_relaxed(reg) | mask, reg);
202}
203
204static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask)
205{
206 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
207}
208
209/* From I2C Specifications v0.5 */
210static struct st_i2c_timings i2c_timings[] = {
211 [I2C_MODE_STANDARD] = {
212 .rate = 100000,
213 .rep_start_hold = 4000,
214 .rep_start_setup = 4700,
215 .start_hold = 4000,
216 .data_setup_time = 250,
217 .stop_setup_time = 4000,
218 .bus_free_time = 4700,
219 },
220 [I2C_MODE_FAST] = {
221 .rate = 400000,
222 .rep_start_hold = 600,
223 .rep_start_setup = 600,
224 .start_hold = 600,
225 .data_setup_time = 100,
226 .stop_setup_time = 600,
227 .bus_free_time = 1300,
228 },
229};
230
231static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev)
232{
233 int count, i;
234
235 /*
236 * Counter only counts up to 7 but fifo size is 8...
237 * When fifo is full, counter is 0 and RIR bit of status register is
238 * set
239 */
240 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
241 count = SSC_RXFIFO_SIZE;
242 else
243 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
244 SSC_RX_FSTAT_STATUS;
245
246 for (i = 0; i < count; i++)
247 readl_relaxed(i2c_dev->base + SSC_RBUF);
248}
249
250static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev)
251{
252 /*
253 * FIFO needs to be emptied before reseting the IP,
254 * else the controller raises a BUSY error.
255 */
256 st_i2c_flush_rx_fifo(i2c_dev);
257
258 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
259 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
260}
261
262/**
263 * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings
264 * @i2c_dev: Controller's private data
265 */
266static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev)
267{
268 unsigned long rate;
269 u32 val, ns_per_clk;
270 struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode];
271
272 st_i2c_soft_reset(i2c_dev);
273
274 val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL |
275 SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP;
276 writel_relaxed(val, i2c_dev->base + SSC_CLR);
277
278 /* SSC Control register setup */
279 val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9;
280 writel_relaxed(val, i2c_dev->base + SSC_CTL);
281
282 rate = clk_get_rate(i2c_dev->clk);
283 ns_per_clk = 1000000000 / rate;
284
285 /* Baudrate */
286 val = rate / (2 * t->rate);
287 writel_relaxed(val, i2c_dev->base + SSC_BRG);
288
289 /* Pre-scaler baudrate */
290 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG);
291
292 /* Enable I2C mode */
293 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C);
294
295 /* Repeated start hold time */
296 val = t->rep_start_hold / ns_per_clk;
297 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD);
298
299 /* Repeated start set up time */
300 val = t->rep_start_setup / ns_per_clk;
301 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP);
302
303 /* Start hold time */
304 val = t->start_hold / ns_per_clk;
305 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD);
306
307 /* Data set up time */
308 val = t->data_setup_time / ns_per_clk;
309 writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP);
310
311 /* Stop set up time */
312 val = t->stop_setup_time / ns_per_clk;
313 writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP);
314
315 /* Bus free time */
316 val = t->bus_free_time / ns_per_clk;
317 writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE);
318
319 /* Prescalers set up */
320 val = rate / 10000000;
321 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER);
322 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT);
323
324 /* Noise suppression witdh */
325 val = i2c_dev->scl_min_width_us * rate / 100000000;
326 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH);
327
328 /* Noise suppression max output data delay width */
329 val = i2c_dev->sda_min_width_us * rate / 100000000;
330 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT);
331}
332
333static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev)
334{
335 u32 sta;
336 int i;
337
338 for (i = 0; i < 10; i++) {
339 sta = readl_relaxed(i2c_dev->base + SSC_STA);
340 if (!(sta & SSC_STA_BUSY))
341 return 0;
342
343 usleep_range(2000, 4000);
344 }
345
346 dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta);
347
348 return -EBUSY;
349}
350
351/**
352 * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO
353 * @i2c_dev: Controller's private data
354 * @byte: Data to write in the Tx FIFO
355 */
356static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte)
357{
358 u16 tbuf = byte << 1;
359
360 writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF);
361}
362
363/**
364 * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode
365 * @i2c_dev: Controller's private data
366 *
367 * This functions fills the Tx FIFO with I2C transfert buffer when
368 * in write mode.
369 */
370static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev)
371{
372 struct st_i2c_client *c = &i2c_dev->client;
373 u32 tx_fstat, sta;
374 int i;
375
376 sta = readl_relaxed(i2c_dev->base + SSC_STA);
377 if (sta & SSC_STA_TX_FIFO_FULL)
378 return;
379
380 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
381 tx_fstat &= SSC_TX_FSTAT_STATUS;
382
383 if (c->count < (SSC_TXFIFO_SIZE - tx_fstat))
384 i = c->count;
385 else
386 i = SSC_TXFIFO_SIZE - tx_fstat;
387
388 for (; i > 0; i--, c->count--, c->buf++)
389 st_i2c_write_tx_fifo(i2c_dev, *c->buf);
390}
391
392/**
393 * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode
394 * @i2c_dev: Controller's private data
395 *
396 * This functions fills the Tx FIFO with fixed pattern when
397 * in read mode to trigger clock.
398 */
399static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max)
400{
401 struct st_i2c_client *c = &i2c_dev->client;
402 u32 tx_fstat, sta;
403 int i;
404
405 sta = readl_relaxed(i2c_dev->base + SSC_STA);
406 if (sta & SSC_STA_TX_FIFO_FULL)
407 return;
408
409 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
410 tx_fstat &= SSC_TX_FSTAT_STATUS;
411
412 if (max < (SSC_TXFIFO_SIZE - tx_fstat))
413 i = max;
414 else
415 i = SSC_TXFIFO_SIZE - tx_fstat;
416
417 for (; i > 0; i--, c->xfered++)
418 st_i2c_write_tx_fifo(i2c_dev, 0xff);
419}
420
421static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev)
422{
423 struct st_i2c_client *c = &i2c_dev->client;
424 u32 i, sta;
425 u16 rbuf;
426
427 sta = readl_relaxed(i2c_dev->base + SSC_STA);
428 if (sta & SSC_STA_RIR) {
429 i = SSC_RXFIFO_SIZE;
430 } else {
431 i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT);
432 i &= SSC_RX_FSTAT_STATUS;
433 }
434
435 for (; (i > 0) && (c->count > 0); i--, c->count--) {
436 rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1;
437 *c->buf++ = (u8)rbuf & 0xff;
438 }
439
440 if (i) {
441 dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i);
442 st_i2c_flush_rx_fifo(i2c_dev);
443 }
444}
445
446/**
447 * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition
448 * @i2c_dev: Controller's private data
449 */
450static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev)
451{
452 struct st_i2c_client *c = &i2c_dev->client;
453
454 st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN);
455 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
456
457 if (c->stop) {
458 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN);
459 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
460 } else {
461 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN);
462 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG);
463 }
464}
465
466/**
467 * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write
468 * @i2c_dev: Controller's private data
469 */
470static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev)
471{
472 struct st_i2c_client *c = &i2c_dev->client;
473
474 st_i2c_flush_rx_fifo(i2c_dev);
475
476 if (!c->count)
477 /* End of xfer, send stop or repstart */
478 st_i2c_terminate_xfer(i2c_dev);
479 else
480 st_i2c_wr_fill_tx_fifo(i2c_dev);
481}
482
483/**
484 * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read
485 * @i2c_dev: Controller's private data
486 */
487static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev)
488{
489 struct st_i2c_client *c = &i2c_dev->client;
490 u32 ien;
491
492 /* Trash the address read back */
493 if (!c->xfered) {
494 readl_relaxed(i2c_dev->base + SSC_RBUF);
495 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB);
496 } else {
497 st_i2c_read_rx_fifo(i2c_dev);
498 }
499
500 if (!c->count) {
501 /* End of xfer, send stop or repstart */
502 st_i2c_terminate_xfer(i2c_dev);
503 } else if (c->count == 1) {
504 /* Penultimate byte to xfer, disable ACK gen. */
505 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG);
506
507 /* Last received byte is to be handled by NACK interrupt */
508 ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN;
509 writel_relaxed(ien, i2c_dev->base + SSC_IEN);
510
511 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count);
512 } else {
513 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1);
514 }
515}
516
517/**
518 * st_i2c_isr() - Interrupt routine
519 * @irq: interrupt number
520 * @data: Controller's private data
521 */
522static irqreturn_t st_i2c_isr_thread(int irq, void *data)
523{
524 struct st_i2c_dev *i2c_dev = data;
525 struct st_i2c_client *c = &i2c_dev->client;
526 u32 sta, ien;
527 int it;
528
529 ien = readl_relaxed(i2c_dev->base + SSC_IEN);
530 sta = readl_relaxed(i2c_dev->base + SSC_STA);
531
532 /* Use __fls() to check error bits first */
533 it = __fls(sta & ien);
534 if (it < 0) {
535 dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n",
536 sta, ien);
537 return IRQ_NONE;
538 }
539
540 switch (1 << it) {
541 case SSC_STA_TE:
542 if (c->addr & I2C_M_RD)
543 st_i2c_handle_read(i2c_dev);
544 else
545 st_i2c_handle_write(i2c_dev);
546 break;
547
548 case SSC_STA_STOP:
549 case SSC_STA_REPSTRT:
550 writel_relaxed(0, i2c_dev->base + SSC_IEN);
551 complete(&i2c_dev->complete);
552 break;
553
554 case SSC_STA_NACK:
555 writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR);
556
557 /* Last received byte handled by NACK interrupt */
558 if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) {
559 st_i2c_handle_read(i2c_dev);
560 break;
561 }
562
563 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
564 writel_relaxed(it, i2c_dev->base + SSC_IEN);
565
566 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
567 c->result = -EIO;
568 break;
569
570 case SSC_STA_ARBL:
571 writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR);
572
573 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
574 writel_relaxed(it, i2c_dev->base + SSC_IEN);
575
576 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
577 c->result = -EIO;
578 break;
579
580 default:
581 dev_err(i2c_dev->dev,
582 "it %d unhandled (sta=0x%04x)\n", it, sta);
583 }
584
585 /*
586 * Read IEN register to ensure interrupt mask write is effective
587 * before re-enabling interrupt at GIC level, and thus avoid spurious
588 * interrupts.
589 */
590 readl(i2c_dev->base + SSC_IEN);
591
592 return IRQ_HANDLED;
593}
594
595/**
596 * st_i2c_xfer_msg() - Transfer a single I2C message
597 * @i2c_dev: Controller's private data
598 * @msg: I2C message to transfer
599 * @is_first: first message of the sequence
600 * @is_last: last message of the sequence
601 */
602static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg,
603 bool is_first, bool is_last)
604{
605 struct st_i2c_client *c = &i2c_dev->client;
606 u32 ctl, i2c, it;
607 unsigned long timeout;
608 int ret;
609
610 c->addr = (u8)(msg->addr << 1);
611 c->addr |= (msg->flags & I2C_M_RD);
612 c->buf = msg->buf;
613 c->count = msg->len;
614 c->xfered = 0;
615 c->result = 0;
616 c->stop = is_last;
617
618 reinit_completion(&i2c_dev->complete);
619
620 ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
621 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
622
623 i2c = SSC_I2C_TXENB;
624 if (c->addr & I2C_M_RD)
625 i2c |= SSC_I2C_ACKG;
626 st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c);
627
628 /* Write slave address */
629 st_i2c_write_tx_fifo(i2c_dev, c->addr);
630
631 /* Pre-fill Tx fifo with data in case of write */
632 if (!(c->addr & I2C_M_RD))
633 st_i2c_wr_fill_tx_fifo(i2c_dev);
634
635 it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN;
636 writel_relaxed(it, i2c_dev->base + SSC_IEN);
637
638 if (is_first) {
639 ret = st_i2c_wait_free_bus(i2c_dev);
640 if (ret)
641 return ret;
642
643 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
644 }
645
646 timeout = wait_for_completion_timeout(&i2c_dev->complete,
647 i2c_dev->adap.timeout);
648 ret = c->result;
649
650 if (!timeout) {
651 dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n",
652 c->addr);
653 ret = -ETIMEDOUT;
654 }
655
656 i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG;
657 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c);
658
659 writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT,
660 i2c_dev->base + SSC_CLR);
661
662 return ret;
663}
664
665/**
666 * st_i2c_xfer() - Transfer a single I2C message
667 * @i2c_adap: Adapter pointer to the controller
668 * @msgs: Pointer to data to be written.
669 * @num: Number of messages to be executed
670 */
671static int st_i2c_xfer(struct i2c_adapter *i2c_adap,
672 struct i2c_msg msgs[], int num)
673{
674 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
675 int ret, i;
676
677 i2c_dev->busy = true;
678
679 ret = clk_prepare_enable(i2c_dev->clk);
680 if (ret) {
681 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
682 return ret;
683 }
684
685 pinctrl_pm_select_default_state(i2c_dev->dev);
686
687 st_i2c_hw_config(i2c_dev);
688
689 for (i = 0; (i < num) && !ret; i++)
690 ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1);
691
692 pinctrl_pm_select_idle_state(i2c_dev->dev);
693
694 clk_disable_unprepare(i2c_dev->clk);
695
696 i2c_dev->busy = false;
697
698 return (ret < 0) ? ret : i;
699}
700
701#ifdef CONFIG_PM_SLEEP
702static int st_i2c_suspend(struct device *dev)
703{
704 struct platform_device *pdev =
705 container_of(dev, struct platform_device, dev);
706 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
707
708 if (i2c_dev->busy)
709 return -EBUSY;
710
711 pinctrl_pm_select_sleep_state(dev);
712
713 return 0;
714}
715
716static int st_i2c_resume(struct device *dev)
717{
718 pinctrl_pm_select_default_state(dev);
719 /* Go in idle state if available */
720 pinctrl_pm_select_idle_state(dev);
721
722 return 0;
723}
724
725static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume);
726#define ST_I2C_PM (&st_i2c_pm)
727#else
728#define ST_I2C_PM NULL
729#endif
730
731static u32 st_i2c_func(struct i2c_adapter *adap)
732{
733 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
734}
735
736static struct i2c_algorithm st_i2c_algo = {
737 .master_xfer = st_i2c_xfer,
738 .functionality = st_i2c_func,
739};
740
741static int st_i2c_of_get_deglitch(struct device_node *np,
742 struct st_i2c_dev *i2c_dev)
743{
744 int ret;
745
746 ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us",
747 &i2c_dev->scl_min_width_us);
748 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
749 dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n");
750 return ret;
751 }
752
753 ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us",
754 &i2c_dev->sda_min_width_us);
755 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
756 dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n");
757 return ret;
758 }
759
760 return 0;
761}
762
763static int st_i2c_probe(struct platform_device *pdev)
764{
765 struct device_node *np = pdev->dev.of_node;
766 struct st_i2c_dev *i2c_dev;
767 struct resource *res;
768 u32 clk_rate;
769 struct i2c_adapter *adap;
770 int ret;
771
772 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
773 if (!i2c_dev)
774 return -ENOMEM;
775
776 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
777 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
778 if (IS_ERR(i2c_dev->base))
779 return PTR_ERR(i2c_dev->base);
780
781 i2c_dev->irq = irq_of_parse_and_map(np, 0);
782 if (!i2c_dev->irq) {
783 dev_err(&pdev->dev, "IRQ missing or invalid\n");
784 return -EINVAL;
785 }
786
787 i2c_dev->clk = of_clk_get_by_name(np, "ssc");
788 if (IS_ERR(i2c_dev->clk)) {
789 dev_err(&pdev->dev, "Unable to request clock\n");
790 return PTR_ERR(i2c_dev->clk);
791 }
792
793 i2c_dev->mode = I2C_MODE_STANDARD;
794 ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
795 if ((!ret) && (clk_rate == 400000))
796 i2c_dev->mode = I2C_MODE_FAST;
797
798 i2c_dev->dev = &pdev->dev;
799
800 ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq,
801 NULL, st_i2c_isr_thread,
802 IRQF_ONESHOT, pdev->name, i2c_dev);
803 if (ret) {
804 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
805 return ret;
806 }
807
808 pinctrl_pm_select_default_state(i2c_dev->dev);
809 /* In case idle state available, select it */
810 pinctrl_pm_select_idle_state(i2c_dev->dev);
811
812 ret = st_i2c_of_get_deglitch(np, i2c_dev);
813 if (ret)
814 return ret;
815
816 adap = &i2c_dev->adap;
817 i2c_set_adapdata(adap, i2c_dev);
818 snprintf(adap->name, sizeof(adap->name), "ST I2C(0x%x)", res->start);
819 adap->owner = THIS_MODULE;
820 adap->timeout = 2 * HZ;
821 adap->retries = 0;
822 adap->algo = &st_i2c_algo;
823 adap->dev.parent = &pdev->dev;
824 adap->dev.of_node = pdev->dev.of_node;
825
826 init_completion(&i2c_dev->complete);
827
828 ret = i2c_add_adapter(adap);
829 if (ret) {
830 dev_err(&pdev->dev, "Failed to add adapter\n");
831 return ret;
832 }
833
834 platform_set_drvdata(pdev, i2c_dev);
835
836 dev_info(i2c_dev->dev, "%s initialized\n", adap->name);
837
838 return 0;
839}
840
841static int st_i2c_remove(struct platform_device *pdev)
842{
843 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
844
845 i2c_del_adapter(&i2c_dev->adap);
846
847 return 0;
848}
849
850static struct of_device_id st_i2c_match[] = {
851 { .compatible = "st,comms-ssc-i2c", },
852 { .compatible = "st,comms-ssc4-i2c", },
853 {},
854};
855MODULE_DEVICE_TABLE(of, st_i2c_match);
856
857static struct platform_driver st_i2c_driver = {
858 .driver = {
859 .name = "st-i2c",
860 .owner = THIS_MODULE,
861 .of_match_table = st_i2c_match,
862 .pm = ST_I2C_PM,
863 },
864 .probe = st_i2c_probe,
865 .remove = st_i2c_remove,
866};
867
868module_platform_driver(st_i2c_driver);
869
870MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>");
871MODULE_DESCRIPTION("STMicroelectronics I2C driver");
872MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
index 31395fa8121d..2c8a3e4f9008 100644
--- a/drivers/i2c/busses/i2c-wmt.c
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -349,6 +349,7 @@ static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
349 err = clk_set_rate(i2c_dev->clk, 20000000); 349 err = clk_set_rate(i2c_dev->clk, 20000000);
350 if (err) { 350 if (err) {
351 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n"); 351 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
352 clk_disable_unprepare(i2c_dev->clk);
352 return err; 353 return err;
353 } 354 }
354 355
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 4c8b368d463b..fc2716afdfd9 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -40,6 +40,7 @@
40#include <linux/i2c-xiic.h> 40#include <linux/i2c-xiic.h>
41#include <linux/io.h> 41#include <linux/io.h>
42#include <linux/slab.h> 42#include <linux/slab.h>
43#include <linux/of.h>
43 44
44#define DRIVER_NAME "xiic-i2c" 45#define DRIVER_NAME "xiic-i2c"
45 46
@@ -702,7 +703,7 @@ static int xiic_i2c_probe(struct platform_device *pdev)
702 if (irq < 0) 703 if (irq < 0)
703 goto resource_missing; 704 goto resource_missing;
704 705
705 pdata = (struct xiic_i2c_platform_data *)dev_get_platdata(&pdev->dev); 706 pdata = dev_get_platdata(&pdev->dev);
706 707
707 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); 708 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
708 if (!i2c) 709 if (!i2c)
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 75ba8608383e..5923cfa390c8 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -248,7 +248,7 @@ static int i2c_device_probe(struct device *dev)
248 driver = to_i2c_driver(dev->driver); 248 driver = to_i2c_driver(dev->driver);
249 if (!driver->probe || !driver->id_table) 249 if (!driver->probe || !driver->id_table)
250 return -ENODEV; 250 return -ENODEV;
251 client->driver = driver; 251
252 if (!device_can_wakeup(&client->dev)) 252 if (!device_can_wakeup(&client->dev))
253 device_init_wakeup(&client->dev, 253 device_init_wakeup(&client->dev,
254 client->flags & I2C_CLIENT_WAKE); 254 client->flags & I2C_CLIENT_WAKE);
@@ -257,7 +257,6 @@ static int i2c_device_probe(struct device *dev)
257 acpi_dev_pm_attach(&client->dev, true); 257 acpi_dev_pm_attach(&client->dev, true);
258 status = driver->probe(client, i2c_match_id(driver->id_table, client)); 258 status = driver->probe(client, i2c_match_id(driver->id_table, client));
259 if (status) { 259 if (status) {
260 client->driver = NULL;
261 i2c_set_clientdata(client, NULL); 260 i2c_set_clientdata(client, NULL);
262 acpi_dev_pm_detach(&client->dev, true); 261 acpi_dev_pm_detach(&client->dev, true);
263 } 262 }
@@ -281,10 +280,8 @@ static int i2c_device_remove(struct device *dev)
281 dev->driver = NULL; 280 dev->driver = NULL;
282 status = 0; 281 status = 0;
283 } 282 }
284 if (status == 0) { 283 if (status == 0)
285 client->driver = NULL;
286 i2c_set_clientdata(client, NULL); 284 i2c_set_clientdata(client, NULL);
287 }
288 acpi_dev_pm_detach(&client->dev, true); 285 acpi_dev_pm_detach(&client->dev, true);
289 return status; 286 return status;
290} 287}
@@ -1614,9 +1611,14 @@ static int i2c_cmd(struct device *dev, void *_arg)
1614{ 1611{
1615 struct i2c_client *client = i2c_verify_client(dev); 1612 struct i2c_client *client = i2c_verify_client(dev);
1616 struct i2c_cmd_arg *arg = _arg; 1613 struct i2c_cmd_arg *arg = _arg;
1614 struct i2c_driver *driver;
1615
1616 if (!client || !client->dev.driver)
1617 return 0;
1617 1618
1618 if (client && client->driver && client->driver->command) 1619 driver = to_i2c_driver(client->dev.driver);
1619 client->driver->command(client, arg->cmd, arg->arg); 1620 if (driver->command)
1621 driver->command(client, arg->cmd, arg->arg);
1620 return 0; 1622 return 0;
1621} 1623}
1622 1624
diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
index c3ccdea3d180..80b47e8ce030 100644
--- a/drivers/i2c/i2c-dev.c
+++ b/drivers/i2c/i2c-dev.c
@@ -102,8 +102,8 @@ static void return_i2c_dev(struct i2c_dev *i2c_dev)
102 kfree(i2c_dev); 102 kfree(i2c_dev);
103} 103}
104 104
105static ssize_t show_adapter_name(struct device *dev, 105static ssize_t name_show(struct device *dev,
106 struct device_attribute *attr, char *buf) 106 struct device_attribute *attr, char *buf)
107{ 107{
108 struct i2c_dev *i2c_dev = i2c_dev_get_by_minor(MINOR(dev->devt)); 108 struct i2c_dev *i2c_dev = i2c_dev_get_by_minor(MINOR(dev->devt));
109 109
@@ -111,7 +111,13 @@ static ssize_t show_adapter_name(struct device *dev,
111 return -ENODEV; 111 return -ENODEV;
112 return sprintf(buf, "%s\n", i2c_dev->adap->name); 112 return sprintf(buf, "%s\n", i2c_dev->adap->name);
113} 113}
114static DEVICE_ATTR(name, S_IRUGO, show_adapter_name, NULL); 114static DEVICE_ATTR_RO(name);
115
116static struct attribute *i2c_attrs[] = {
117 &dev_attr_name.attr,
118 NULL,
119};
120ATTRIBUTE_GROUPS(i2c);
115 121
116/* ------------------------------------------------------------------------- */ 122/* ------------------------------------------------------------------------- */
117 123
@@ -562,15 +568,10 @@ static int i2cdev_attach_adapter(struct device *dev, void *dummy)
562 res = PTR_ERR(i2c_dev->dev); 568 res = PTR_ERR(i2c_dev->dev);
563 goto error; 569 goto error;
564 } 570 }
565 res = device_create_file(i2c_dev->dev, &dev_attr_name);
566 if (res)
567 goto error_destroy;
568 571
569 pr_debug("i2c-dev: adapter [%s] registered as minor %d\n", 572 pr_debug("i2c-dev: adapter [%s] registered as minor %d\n",
570 adap->name, adap->nr); 573 adap->name, adap->nr);
571 return 0; 574 return 0;
572error_destroy:
573 device_destroy(i2c_dev_class, MKDEV(I2C_MAJOR, adap->nr));
574error: 575error:
575 return_i2c_dev(i2c_dev); 576 return_i2c_dev(i2c_dev);
576 return res; 577 return res;
@@ -589,7 +590,6 @@ static int i2cdev_detach_adapter(struct device *dev, void *dummy)
589 if (!i2c_dev) /* attach_adapter must have failed */ 590 if (!i2c_dev) /* attach_adapter must have failed */
590 return 0; 591 return 0;
591 592
592 device_remove_file(i2c_dev->dev, &dev_attr_name);
593 return_i2c_dev(i2c_dev); 593 return_i2c_dev(i2c_dev);
594 device_destroy(i2c_dev_class, MKDEV(I2C_MAJOR, adap->nr)); 594 device_destroy(i2c_dev_class, MKDEV(I2C_MAJOR, adap->nr));
595 595
@@ -637,6 +637,7 @@ static int __init i2c_dev_init(void)
637 res = PTR_ERR(i2c_dev_class); 637 res = PTR_ERR(i2c_dev_class);
638 goto out_unreg_chrdev; 638 goto out_unreg_chrdev;
639 } 639 }
640 i2c_dev_class->dev_groups = i2c_groups;
640 641
641 /* Keep track of adapters which will be added or removed later */ 642 /* Keep track of adapters which will be added or removed later */
642 res = bus_register_notifier(&i2c_bus_type, &i2cdev_notifier); 643 res = bus_register_notifier(&i2c_bus_type, &i2cdev_notifier);
diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c
index 44d4c6071c15..c99b22987366 100644
--- a/drivers/i2c/i2c-smbus.c
+++ b/drivers/i2c/i2c-smbus.c
@@ -46,6 +46,7 @@ static int smbus_do_alert(struct device *dev, void *addrp)
46{ 46{
47 struct i2c_client *client = i2c_verify_client(dev); 47 struct i2c_client *client = i2c_verify_client(dev);
48 struct alert_data *data = addrp; 48 struct alert_data *data = addrp;
49 struct i2c_driver *driver;
49 50
50 if (!client || client->addr != data->addr) 51 if (!client || client->addr != data->addr)
51 return 0; 52 return 0;
@@ -54,12 +55,13 @@ static int smbus_do_alert(struct device *dev, void *addrp)
54 55
55 /* 56 /*
56 * Drivers should either disable alerts, or provide at least 57 * Drivers should either disable alerts, or provide at least
57 * a minimal handler. Lock so client->driver won't change. 58 * a minimal handler. Lock so the driver won't change.
58 */ 59 */
59 device_lock(dev); 60 device_lock(dev);
60 if (client->driver) { 61 if (client->dev.driver) {
61 if (client->driver->alert) 62 driver = to_i2c_driver(client->dev.driver);
62 client->driver->alert(client, data->flag); 63 if (driver->alert)
64 driver->alert(client, data->flag);
63 else 65 else
64 dev_warn(&client->dev, "no driver alert()!\n"); 66 dev_warn(&client->dev, "no driver alert()!\n");
65 } else 67 } else
diff --git a/drivers/i2c/muxes/i2c-arb-gpio-challenge.c b/drivers/i2c/muxes/i2c-arb-gpio-challenge.c
index 928656e241dd..c58e093b6032 100644
--- a/drivers/i2c/muxes/i2c-arb-gpio-challenge.c
+++ b/drivers/i2c/muxes/i2c-arb-gpio-challenge.c
@@ -238,7 +238,7 @@ static struct platform_driver i2c_arbitrator_driver = {
238 .driver = { 238 .driver = {
239 .owner = THIS_MODULE, 239 .owner = THIS_MODULE,
240 .name = "i2c-arb-gpio-challenge", 240 .name = "i2c-arb-gpio-challenge",
241 .of_match_table = of_match_ptr(i2c_arbitrator_of_match), 241 .of_match_table = i2c_arbitrator_of_match,
242 }, 242 },
243}; 243};
244 244
diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c
index a764da777f08..8a8c56f4b026 100644
--- a/drivers/i2c/muxes/i2c-mux-gpio.c
+++ b/drivers/i2c/muxes/i2c-mux-gpio.c
@@ -30,15 +30,15 @@ static void i2c_mux_gpio_set(const struct gpiomux *mux, unsigned val)
30 int i; 30 int i;
31 31
32 for (i = 0; i < mux->data.n_gpios; i++) 32 for (i = 0; i < mux->data.n_gpios; i++)
33 gpio_set_value(mux->gpio_base + mux->data.gpios[i], 33 gpio_set_value_cansleep(mux->gpio_base + mux->data.gpios[i],
34 val & (1 << i)); 34 val & (1 << i));
35} 35}
36 36
37static int i2c_mux_gpio_select(struct i2c_adapter *adap, void *data, u32 chan) 37static int i2c_mux_gpio_select(struct i2c_adapter *adap, void *data, u32 chan)
38{ 38{
39 struct gpiomux *mux = data; 39 struct gpiomux *mux = data;
40 40
41 i2c_mux_gpio_set(mux, mux->data.values[chan]); 41 i2c_mux_gpio_set(mux, chan);
42 42
43 return 0; 43 return 0;
44} 44}
@@ -228,7 +228,7 @@ static int i2c_mux_gpio_probe(struct platform_device *pdev)
228 unsigned int class = mux->data.classes ? mux->data.classes[i] : 0; 228 unsigned int class = mux->data.classes ? mux->data.classes[i] : 0;
229 229
230 mux->adap[i] = i2c_add_mux_adapter(parent, &pdev->dev, mux, nr, 230 mux->adap[i] = i2c_add_mux_adapter(parent, &pdev->dev, mux, nr,
231 i, class, 231 mux->data.values[i], class,
232 i2c_mux_gpio_select, deselect); 232 i2c_mux_gpio_select, deselect);
233 if (!mux->adap[i]) { 233 if (!mux->adap[i]) {
234 ret = -ENODEV; 234 ret = -ENODEV;
@@ -283,7 +283,7 @@ static struct platform_driver i2c_mux_gpio_driver = {
283 .driver = { 283 .driver = {
284 .owner = THIS_MODULE, 284 .owner = THIS_MODULE,
285 .name = "i2c-mux-gpio", 285 .name = "i2c-mux-gpio",
286 .of_match_table = of_match_ptr(i2c_mux_gpio_of_match), 286 .of_match_table = i2c_mux_gpio_of_match,
287 }, 287 },
288}; 288};
289 289
diff --git a/drivers/i2c/muxes/i2c-mux-pinctrl.c b/drivers/i2c/muxes/i2c-mux-pinctrl.c
index 68a37157377d..d7978dc4ad0b 100644
--- a/drivers/i2c/muxes/i2c-mux-pinctrl.c
+++ b/drivers/i2c/muxes/i2c-mux-pinctrl.c
@@ -24,6 +24,7 @@
24#include <linux/i2c-mux-pinctrl.h> 24#include <linux/i2c-mux-pinctrl.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/slab.h> 26#include <linux/slab.h>
27#include <linux/of.h>
27 28
28struct i2c_mux_pinctrl { 29struct i2c_mux_pinctrl {
29 struct device *dev; 30 struct device *dev;
diff --git a/drivers/media/i2c/s5c73m3/s5c73m3-core.c b/drivers/media/i2c/s5c73m3/s5c73m3-core.c
index 31f40b342049..6fec9384d86e 100644
--- a/drivers/media/i2c/s5c73m3/s5c73m3-core.c
+++ b/drivers/media/i2c/s5c73m3/s5c73m3-core.c
@@ -1581,7 +1581,7 @@ static int s5c73m3_probe(struct i2c_client *client,
1581 oif_sd = &state->oif_sd; 1581 oif_sd = &state->oif_sd;
1582 1582
1583 v4l2_subdev_init(sd, &s5c73m3_subdev_ops); 1583 v4l2_subdev_init(sd, &s5c73m3_subdev_ops);
1584 sd->owner = client->driver->driver.owner; 1584 sd->owner = client->dev.driver->owner;
1585 v4l2_set_subdevdata(sd, state); 1585 v4l2_set_subdevdata(sd, state);
1586 strlcpy(sd->name, "S5C73M3", sizeof(sd->name)); 1586 strlcpy(sd->name, "S5C73M3", sizeof(sd->name));
1587 1587
diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c
index a83511278317..7a4ee4c0449d 100644
--- a/drivers/media/platform/exynos4-is/media-dev.c
+++ b/drivers/media/platform/exynos4-is/media-dev.c
@@ -411,8 +411,8 @@ static int fimc_md_of_add_sensor(struct fimc_md *fmd,
411 411
412 device_lock(&client->dev); 412 device_lock(&client->dev);
413 413
414 if (!client->driver || 414 if (!client->dev.driver ||
415 !try_module_get(client->driver->driver.owner)) { 415 !try_module_get(client->dev.driver->owner)) {
416 ret = -EPROBE_DEFER; 416 ret = -EPROBE_DEFER;
417 v4l2_info(&fmd->v4l2_dev, "No driver found for %s\n", 417 v4l2_info(&fmd->v4l2_dev, "No driver found for %s\n",
418 node->full_name); 418 node->full_name);
@@ -442,7 +442,7 @@ static int fimc_md_of_add_sensor(struct fimc_md *fmd,
442 fmd->num_sensors++; 442 fmd->num_sensors++;
443 443
444mod_put: 444mod_put:
445 module_put(client->driver->driver.owner); 445 module_put(client->dev.driver->owner);
446dev_put: 446dev_put:
447 device_unlock(&client->dev); 447 device_unlock(&client->dev);
448 put_device(&client->dev); 448 put_device(&client->dev);
diff --git a/drivers/media/v4l2-core/tuner-core.c b/drivers/media/v4l2-core/tuner-core.c
index 4b8a9a39d7f4..20c09229a08e 100644
--- a/drivers/media/v4l2-core/tuner-core.c
+++ b/drivers/media/v4l2-core/tuner-core.c
@@ -43,7 +43,7 @@
43 43
44#define UNSET (-1U) 44#define UNSET (-1U)
45 45
46#define PREFIX (t->i2c->driver->driver.name) 46#define PREFIX (t->i2c->dev.driver->name)
47 47
48/* 48/*
49 * Driver modprobe parameters 49 * Driver modprobe parameters
@@ -452,7 +452,7 @@ static void set_type(struct i2c_client *c, unsigned int type,
452 } 452 }
453 453
454 tuner_dbg("%s %s I2C addr 0x%02x with type %d used for 0x%02x\n", 454 tuner_dbg("%s %s I2C addr 0x%02x with type %d used for 0x%02x\n",
455 c->adapter->name, c->driver->driver.name, c->addr << 1, type, 455 c->adapter->name, c->dev.driver->name, c->addr << 1, type,
456 t->mode_mask); 456 t->mode_mask);
457 return; 457 return;
458 458
@@ -556,7 +556,7 @@ static void tuner_lookup(struct i2c_adapter *adap,
556 int mode_mask; 556 int mode_mask;
557 557
558 if (pos->i2c->adapter != adap || 558 if (pos->i2c->adapter != adap ||
559 strcmp(pos->i2c->driver->driver.name, "tuner")) 559 strcmp(pos->i2c->dev.driver->name, "tuner"))
560 continue; 560 continue;
561 561
562 mode_mask = pos->mode_mask; 562 mode_mask = pos->mode_mask;
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
index 037d7a55aa8c..433d6d77942e 100644
--- a/drivers/media/v4l2-core/v4l2-common.c
+++ b/drivers/media/v4l2-core/v4l2-common.c
@@ -236,14 +236,14 @@ void v4l2_i2c_subdev_init(struct v4l2_subdev *sd, struct i2c_client *client,
236 v4l2_subdev_init(sd, ops); 236 v4l2_subdev_init(sd, ops);
237 sd->flags |= V4L2_SUBDEV_FL_IS_I2C; 237 sd->flags |= V4L2_SUBDEV_FL_IS_I2C;
238 /* the owner is the same as the i2c_client's driver owner */ 238 /* the owner is the same as the i2c_client's driver owner */
239 sd->owner = client->driver->driver.owner; 239 sd->owner = client->dev.driver->owner;
240 sd->dev = &client->dev; 240 sd->dev = &client->dev;
241 /* i2c_client and v4l2_subdev point to one another */ 241 /* i2c_client and v4l2_subdev point to one another */
242 v4l2_set_subdevdata(sd, client); 242 v4l2_set_subdevdata(sd, client);
243 i2c_set_clientdata(client, sd); 243 i2c_set_clientdata(client, sd);
244 /* initialize name */ 244 /* initialize name */
245 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 245 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
246 client->driver->driver.name, i2c_adapter_id(client->adapter), 246 client->dev.driver->name, i2c_adapter_id(client->adapter),
247 client->addr); 247 client->addr);
248} 248}
249EXPORT_SYMBOL_GPL(v4l2_i2c_subdev_init); 249EXPORT_SYMBOL_GPL(v4l2_i2c_subdev_init);
@@ -274,11 +274,11 @@ struct v4l2_subdev *v4l2_i2c_new_subdev_board(struct v4l2_device *v4l2_dev,
274 loaded. This delay-load mechanism doesn't work if other drivers 274 loaded. This delay-load mechanism doesn't work if other drivers
275 want to use the i2c device, so explicitly loading the module 275 want to use the i2c device, so explicitly loading the module
276 is the best alternative. */ 276 is the best alternative. */
277 if (client == NULL || client->driver == NULL) 277 if (client == NULL || client->dev.driver == NULL)
278 goto error; 278 goto error;
279 279
280 /* Lock the module so we can safely get the v4l2_subdev pointer */ 280 /* Lock the module so we can safely get the v4l2_subdev pointer */
281 if (!try_module_get(client->driver->driver.owner)) 281 if (!try_module_get(client->dev.driver->owner))
282 goto error; 282 goto error;
283 sd = i2c_get_clientdata(client); 283 sd = i2c_get_clientdata(client);
284 284
@@ -287,7 +287,7 @@ struct v4l2_subdev *v4l2_i2c_new_subdev_board(struct v4l2_device *v4l2_dev,
287 if (v4l2_device_register_subdev(v4l2_dev, sd)) 287 if (v4l2_device_register_subdev(v4l2_dev, sd))
288 sd = NULL; 288 sd = NULL;
289 /* Decrease the module use count to match the first try_module_get. */ 289 /* Decrease the module use count to match the first try_module_get. */
290 module_put(client->driver->driver.owner); 290 module_put(client->dev.driver->owner);
291 291
292error: 292error:
293 /* If we have a client but no subdev, then something went wrong and 293 /* If we have a client but no subdev, then something went wrong and
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 94b8a3324319..d87f77f790d6 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -22,7 +22,7 @@
22#include <linux/jiffies.h> 22#include <linux/jiffies.h>
23#include <linux/of.h> 23#include <linux/of.h>
24#include <linux/i2c.h> 24#include <linux/i2c.h>
25#include <linux/i2c/at24.h> 25#include <linux/platform_data/at24.h>
26 26
27/* 27/*
28 * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable. 28 * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 00:41:49 -0500