Merge branch 'tegra/soc' into next/drivers

This is a dependency for the tegra/clk branch.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Conflicts:
	drivers/clocksource/tegra20_timer.c

3 files changed, 23 insertions, 38 deletions

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 1e2de7305362..b92d48be4cc9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -711,8 +711,8 @@ static void tegra20_pll_init(void)
 }
 
 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
-                                      "pll_p_cclk", "pll_p_out4_cclk",
-                                      "pll_p_out3_cclk", "clk_d", "pll_x" };
+                                      "pll_p", "pll_p_out4",
+                                      "pll_p_out3", "clk_d", "pll_x" };
 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
                                       "pll_p_out3", "pll_p_out2", "clk_d",
                                       "clk_32k", "pll_m_out1" };
@@ -721,38 +721,6 @@ static void tegra20_super_clk_init(void)
 {
         struct clk *clk;
 
-        /*
-         * DIV_U71 dividers for CCLK, these dividers are used only
-         * if parent clock is fixed rate.
-         */
-
-        /*
-         * Clock input to cclk divided from pll_p using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_cclk", NULL);
-
-        /*
-         * Clock input to cclk divided from pll_p_out3 using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
-
-        /*
-         * Clock input to cclk divided from pll_p_out4 using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
-
         /* CCLK */
         clk = tegra_clk_register_super_mux("cclk", cclk_parents,
                               ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 2e4d8a666c36..ae877b021b54 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -172,7 +172,7 @@ static void __init tegra20_init_timer(struct device_node *np)
                 BUG();
         }
 
-        clk = clk_get_sys("timer", NULL);
+        clk = of_clk_get(np, 0);
         if (IS_ERR(clk)) {
                 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
                 rate = 12000000;
@@ -235,7 +235,7 @@ static void __init tegra20_init_rtc(struct device_node *np)
          * rtc registers are used by read_persistent_clock, keep the rtc clock
          * enabled
          */
-        clk = clk_get_sys("rtc-tegra", NULL);
+        clk = of_clk_get(np, 0);
         if (IS_ERR(clk))
                 pr_warn("Unable to get rtc-tegra clock\n");
         else
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 414ad912232f..e3956359202c 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -72,6 +72,7 @@ struct tegra_gpio_bank {
         u32 oe[4];
         u32 int_enb[4];
         u32 int_lvl[4];
+        u32 wake_enb[4];
 #endif
 };
 
@@ -333,15 +334,31 @@ static int tegra_gpio_suspend(struct device *dev)
                         bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
                         bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
                         bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
+
+                        /* Enable gpio irq for wake up source */
+                        tegra_gpio_writel(bank->wake_enb[p],
+                                          GPIO_INT_ENB(gpio));
                 }
         }
         local_irq_restore(flags);
         return 0;
 }
 
-static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
+static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 {
         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+        int gpio = d->hwirq;
+        u32 port, bit, mask;
+
+        port = GPIO_PORT(gpio);
+        bit = GPIO_BIT(gpio);
+        mask = BIT(bit);
+
+        if (enable)
+                bank->wake_enb[port] |= mask;
+        else
+                bank->wake_enb[port] &= ~mask;
+
         return irq_set_irq_wake(bank->irq, enable);
 }
 #endif
@@ -353,7 +370,7 @@ static struct irq_chip tegra_gpio_irq_chip = {
         .irq_unmask     = tegra_gpio_irq_unmask,
         .irq_set_type   = tegra_gpio_irq_set_type,
 #ifdef CONFIG_PM_SLEEP
-        .irq_set_wake   = tegra_gpio_wake_enable,
+        .irq_set_wake   = tegra_gpio_irq_set_wake,
 #endif
 };