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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-02-16 20:40:25 -0500
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-02-16 20:40:25 -0500
commit0ecdca26e556eae9668ce6de9554757dddb942ef (patch)
tree21d62c01d0c0d5aeea2524252ed8dec6ca20b6d4 /drivers
parent7569e8dc2213ecc47024ea5edbadc8736487d926 (diff)
ide: use PIO/MMIO operations directly where possible (v2)
This results in smaller/faster/simpler code and allows future optimizations. Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}. v2: * updated for scc_pata Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ide/h8300/ide-h8300.c2
-rw-r--r--drivers/ide/ide-dma.c5
-rw-r--r--drivers/ide/ide-iops.c24
-rw-r--r--drivers/ide/ide.c2
-rw-r--r--drivers/ide/legacy/ht6560b.c14
-rw-r--r--drivers/ide/pci/aec62xx.c6
-rw-r--r--drivers/ide/pci/alim15x3.c4
-rw-r--r--drivers/ide/pci/cmd64x.c18
-rw-r--r--drivers/ide/pci/cs5530.c22
-rw-r--r--drivers/ide/pci/cy82c693.c12
-rw-r--r--drivers/ide/pci/hpt366.c2
-rw-r--r--drivers/ide/pci/ns87415.c10
-rw-r--r--drivers/ide/pci/opti621.c63
-rw-r--r--drivers/ide/pci/pdc202xx_new.c8
-rw-r--r--drivers/ide/pci/pdc202xx_old.c41
-rw-r--r--drivers/ide/pci/serverworks.c4
-rw-r--r--drivers/ide/pci/sgiioc4.c67
-rw-r--r--drivers/ide/pci/siimage.c24
-rw-r--r--drivers/ide/pci/sl82c105.c2
-rw-r--r--drivers/ide/pci/tc86c001.c26
-rw-r--r--drivers/ide/pci/trm290.c38
-rw-r--r--drivers/ide/ppc/scc_pata.c122
22 files changed, 262 insertions, 254 deletions
diff --git a/drivers/ide/h8300/ide-h8300.c b/drivers/ide/h8300/ide-h8300.c
index 608ca871744b..c45bfb825a37 100644
--- a/drivers/ide/h8300/ide-h8300.c
+++ b/drivers/ide/h8300/ide-h8300.c
@@ -81,8 +81,6 @@ static inline void hwif_setup(ide_hwif_t *hwif)
81 hwif->OUTSW = mm_outsw; 81 hwif->OUTSW = mm_outsw;
82 hwif->INW = mm_inw; 82 hwif->INW = mm_inw;
83 hwif->INSW = mm_insw; 83 hwif->INSW = mm_insw;
84 hwif->OUTL = NULL;
85 hwif->INL = NULL;
86 hwif->OUTSL = NULL; 84 hwif->OUTSL = NULL;
87 hwif->INSL = NULL; 85 hwif->INSL = NULL;
88} 86}
diff --git a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c
index 941846c21624..b7b663ee7343 100644
--- a/drivers/ide/ide-dma.c
+++ b/drivers/ide/ide-dma.c
@@ -565,7 +565,10 @@ int ide_dma_setup(ide_drive_t *drive)
565 } 565 }
566 566
567 /* PRD table */ 567 /* PRD table */
568 hwif->OUTL(hwif->dmatable_dma, hwif->dma_prdtable); 568 if (hwif->mmio == 2)
569 writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable);
570 else
571 outl(hwif->dmatable_dma, hwif->dma_prdtable);
569 572
570 /* specify r/w */ 573 /* specify r/w */
571 hwif->OUTB(reading, hwif->dma_command); 574 hwif->OUTB(reading, hwif->dma_command);
diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c
index badde6331775..09c30cbf4bd7 100644
--- a/drivers/ide/ide-iops.c
+++ b/drivers/ide/ide-iops.c
@@ -49,11 +49,6 @@ static void ide_insw (unsigned long port, void *addr, u32 count)
49 insw(port, addr, count); 49 insw(port, addr, count);
50} 50}
51 51
52static u32 ide_inl (unsigned long port)
53{
54 return (u32) inl(port);
55}
56
57static void ide_insl (unsigned long port, void *addr, u32 count) 52static void ide_insl (unsigned long port, void *addr, u32 count)
58{ 53{
59 insl(port, addr, count); 54 insl(port, addr, count);
@@ -79,11 +74,6 @@ static void ide_outsw (unsigned long port, void *addr, u32 count)
79 outsw(port, addr, count); 74 outsw(port, addr, count);
80} 75}
81 76
82static void ide_outl (u32 val, unsigned long port)
83{
84 outl(val, port);
85}
86
87static void ide_outsl (unsigned long port, void *addr, u32 count) 77static void ide_outsl (unsigned long port, void *addr, u32 count)
88{ 78{
89 outsl(port, addr, count); 79 outsl(port, addr, count);
@@ -94,12 +84,10 @@ void default_hwif_iops (ide_hwif_t *hwif)
94 hwif->OUTB = ide_outb; 84 hwif->OUTB = ide_outb;
95 hwif->OUTBSYNC = ide_outbsync; 85 hwif->OUTBSYNC = ide_outbsync;
96 hwif->OUTW = ide_outw; 86 hwif->OUTW = ide_outw;
97 hwif->OUTL = ide_outl;
98 hwif->OUTSW = ide_outsw; 87 hwif->OUTSW = ide_outsw;
99 hwif->OUTSL = ide_outsl; 88 hwif->OUTSL = ide_outsl;
100 hwif->INB = ide_inb; 89 hwif->INB = ide_inb;
101 hwif->INW = ide_inw; 90 hwif->INW = ide_inw;
102 hwif->INL = ide_inl;
103 hwif->INSW = ide_insw; 91 hwif->INSW = ide_insw;
104 hwif->INSL = ide_insl; 92 hwif->INSL = ide_insl;
105} 93}
@@ -123,11 +111,6 @@ static void ide_mm_insw (unsigned long port, void *addr, u32 count)
123 __ide_mm_insw((void __iomem *) port, addr, count); 111 __ide_mm_insw((void __iomem *) port, addr, count);
124} 112}
125 113
126static u32 ide_mm_inl (unsigned long port)
127{
128 return (u32) readl((void __iomem *) port);
129}
130
131static void ide_mm_insl (unsigned long port, void *addr, u32 count) 114static void ide_mm_insl (unsigned long port, void *addr, u32 count)
132{ 115{
133 __ide_mm_insl((void __iomem *) port, addr, count); 116 __ide_mm_insl((void __iomem *) port, addr, count);
@@ -153,11 +136,6 @@ static void ide_mm_outsw (unsigned long port, void *addr, u32 count)
153 __ide_mm_outsw((void __iomem *) port, addr, count); 136 __ide_mm_outsw((void __iomem *) port, addr, count);
154} 137}
155 138
156static void ide_mm_outl (u32 value, unsigned long port)
157{
158 writel(value, (void __iomem *) port);
159}
160
161static void ide_mm_outsl (unsigned long port, void *addr, u32 count) 139static void ide_mm_outsl (unsigned long port, void *addr, u32 count)
162{ 140{
163 __ide_mm_outsl((void __iomem *) port, addr, count); 141 __ide_mm_outsl((void __iomem *) port, addr, count);
@@ -170,12 +148,10 @@ void default_hwif_mmiops (ide_hwif_t *hwif)
170 this one is controller specific! */ 148 this one is controller specific! */
171 hwif->OUTBSYNC = ide_mm_outbsync; 149 hwif->OUTBSYNC = ide_mm_outbsync;
172 hwif->OUTW = ide_mm_outw; 150 hwif->OUTW = ide_mm_outw;
173 hwif->OUTL = ide_mm_outl;
174 hwif->OUTSW = ide_mm_outsw; 151 hwif->OUTSW = ide_mm_outsw;
175 hwif->OUTSL = ide_mm_outsl; 152 hwif->OUTSL = ide_mm_outsl;
176 hwif->INB = ide_mm_inb; 153 hwif->INB = ide_mm_inb;
177 hwif->INW = ide_mm_inw; 154 hwif->INW = ide_mm_inw;
178 hwif->INL = ide_mm_inl;
179 hwif->INSW = ide_mm_insw; 155 hwif->INSW = ide_mm_insw;
180 hwif->INSL = ide_mm_insl; 156 hwif->INSL = ide_mm_insl;
181} 157}
diff --git a/drivers/ide/ide.c b/drivers/ide/ide.c
index 15b13831ee14..92ab39d5bc25 100644
--- a/drivers/ide/ide.c
+++ b/drivers/ide/ide.c
@@ -518,13 +518,11 @@ static void ide_hwif_restore(ide_hwif_t *hwif, ide_hwif_t *tmp_hwif)
518 hwif->OUTB = tmp_hwif->OUTB; 518 hwif->OUTB = tmp_hwif->OUTB;
519 hwif->OUTBSYNC = tmp_hwif->OUTBSYNC; 519 hwif->OUTBSYNC = tmp_hwif->OUTBSYNC;
520 hwif->OUTW = tmp_hwif->OUTW; 520 hwif->OUTW = tmp_hwif->OUTW;
521 hwif->OUTL = tmp_hwif->OUTL;
522 hwif->OUTSW = tmp_hwif->OUTSW; 521 hwif->OUTSW = tmp_hwif->OUTSW;
523 hwif->OUTSL = tmp_hwif->OUTSL; 522 hwif->OUTSL = tmp_hwif->OUTSL;
524 523
525 hwif->INB = tmp_hwif->INB; 524 hwif->INB = tmp_hwif->INB;
526 hwif->INW = tmp_hwif->INW; 525 hwif->INW = tmp_hwif->INW;
527 hwif->INL = tmp_hwif->INL;
528 hwif->INSW = tmp_hwif->INSW; 526 hwif->INSW = tmp_hwif->INSW;
529 hwif->INSL = tmp_hwif->INSL; 527 hwif->INSL = tmp_hwif->INSL;
530 528
diff --git a/drivers/ide/legacy/ht6560b.c b/drivers/ide/legacy/ht6560b.c
index c48e87e512d3..19ccd006f205 100644
--- a/drivers/ide/legacy/ht6560b.c
+++ b/drivers/ide/legacy/ht6560b.c
@@ -143,16 +143,16 @@ static void ht6560b_selectproc (ide_drive_t *drive)
143 current_timing = timing; 143 current_timing = timing;
144 if (drive->media != ide_disk || !drive->present) 144 if (drive->media != ide_disk || !drive->present)
145 select |= HT_PREFETCH_MODE; 145 select |= HT_PREFETCH_MODE;
146 (void) HWIF(drive)->INB(HT_CONFIG_PORT); 146 (void)inb(HT_CONFIG_PORT);
147 (void) HWIF(drive)->INB(HT_CONFIG_PORT); 147 (void)inb(HT_CONFIG_PORT);
148 (void) HWIF(drive)->INB(HT_CONFIG_PORT); 148 (void)inb(HT_CONFIG_PORT);
149 (void) HWIF(drive)->INB(HT_CONFIG_PORT); 149 (void)inb(HT_CONFIG_PORT);
150 HWIF(drive)->OUTB(select, HT_CONFIG_PORT); 150 outb(select, HT_CONFIG_PORT);
151 /* 151 /*
152 * Set timing for this drive: 152 * Set timing for this drive:
153 */ 153 */
154 HWIF(drive)->OUTB(timing, IDE_SELECT_REG); 154 outb(timing, IDE_SELECT_REG);
155 (void) HWIF(drive)->INB(IDE_STATUS_REG); 155 (void)inb(IDE_STATUS_REG);
156#ifdef DEBUG 156#ifdef DEBUG
157 printk("ht6560b: %s: select=%#x timing=%#x\n", 157 printk("ht6560b: %s: select=%#x timing=%#x\n",
158 drive->name, select, timing); 158 drive->name, select, timing);
diff --git a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c
index 199507391ae8..30f8de6176dd 100644
--- a/drivers/ide/pci/aec62xx.c
+++ b/drivers/ide/pci/aec62xx.c
@@ -94,9 +94,9 @@ static u8 aec62xx_ratemask (ide_drive_t *drive)
94 switch(hwif->pci_dev->device) { 94 switch(hwif->pci_dev->device) {
95 case PCI_DEVICE_ID_ARTOP_ATP865: 95 case PCI_DEVICE_ID_ARTOP_ATP865:
96 case PCI_DEVICE_ID_ARTOP_ATP865R: 96 case PCI_DEVICE_ID_ARTOP_ATP865R:
97 mode = (hwif->INB(((hwif->channel) ? 97 mode = (inb(hwif->channel ?
98 hwif->mate->dma_status : 98 hwif->mate->dma_status :
99 hwif->dma_status)) & 0x10) ? 4 : 3; 99 hwif->dma_status) & 0x10) ? 4 : 3;
100 break; 100 break;
101 case PCI_DEVICE_ID_ARTOP_ATP860: 101 case PCI_DEVICE_ID_ARTOP_ATP860:
102 case PCI_DEVICE_ID_ARTOP_ATP860R: 102 case PCI_DEVICE_ID_ARTOP_ATP860R:
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c
index 68df77ec502b..2baed4e04beb 100644
--- a/drivers/ide/pci/alim15x3.c
+++ b/drivers/ide/pci/alim15x3.c
@@ -852,8 +852,8 @@ static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
852{ 852{
853 if (m5229_revision < 0x20) 853 if (m5229_revision < 0x20)
854 return; 854 return;
855 if (!(hwif->channel)) 855 if (!hwif->channel)
856 hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2); 856 outb(inb(dmabase + 2) & 0x60, dmabase + 2);
857 ide_setup_dma(hwif, dmabase, 8); 857 ide_setup_dma(hwif, dmabase, 8);
858} 858}
859 859
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
index b1f9f5f3615e..a76451a074c6 100644
--- a/drivers/ide/pci/cmd64x.c
+++ b/drivers/ide/pci/cmd64x.c
@@ -507,13 +507,13 @@ static int cmd64x_ide_dma_end (ide_drive_t *drive)
507 507
508 drive->waiting_for_dma = 0; 508 drive->waiting_for_dma = 0;
509 /* read DMA command state */ 509 /* read DMA command state */
510 dma_cmd = hwif->INB(hwif->dma_command); 510 dma_cmd = inb(hwif->dma_command);
511 /* stop DMA */ 511 /* stop DMA */
512 hwif->OUTB((dma_cmd & ~1), hwif->dma_command); 512 outb(dma_cmd & ~1, hwif->dma_command);
513 /* get DMA status */ 513 /* get DMA status */
514 dma_stat = hwif->INB(hwif->dma_status); 514 dma_stat = inb(hwif->dma_status);
515 /* clear the INTR & ERROR bits */ 515 /* clear the INTR & ERROR bits */
516 hwif->OUTB(dma_stat|6, hwif->dma_status); 516 outb(dma_stat | 6, hwif->dma_status);
517 if (cmd64x_alt_dma_status(dev)) { 517 if (cmd64x_alt_dma_status(dev)) {
518 u8 dma_intr = 0; 518 u8 dma_intr = 0;
519 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 : 519 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
@@ -535,7 +535,7 @@ static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
535 struct pci_dev *dev = hwif->pci_dev; 535 struct pci_dev *dev = hwif->pci_dev;
536 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 : 536 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
537 MRDMODE_INTR_CH0; 537 MRDMODE_INTR_CH0;
538 u8 dma_stat = hwif->INB(hwif->dma_status); 538 u8 dma_stat = inb(hwif->dma_status);
539 539
540 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat); 540 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
541#ifdef DEBUG 541#ifdef DEBUG
@@ -565,13 +565,13 @@ static int cmd646_1_ide_dma_end (ide_drive_t *drive)
565 565
566 drive->waiting_for_dma = 0; 566 drive->waiting_for_dma = 0;
567 /* get DMA status */ 567 /* get DMA status */
568 dma_stat = hwif->INB(hwif->dma_status); 568 dma_stat = inb(hwif->dma_status);
569 /* read DMA command state */ 569 /* read DMA command state */
570 dma_cmd = hwif->INB(hwif->dma_command); 570 dma_cmd = inb(hwif->dma_command);
571 /* stop DMA */ 571 /* stop DMA */
572 hwif->OUTB((dma_cmd & ~1), hwif->dma_command); 572 outb(dma_cmd & ~1, hwif->dma_command);
573 /* clear the INTR & ERROR bits */ 573 /* clear the INTR & ERROR bits */
574 hwif->OUTB(dma_stat|6, hwif->dma_status); 574 outb(dma_stat | 6, hwif->dma_status);
575 /* and free any DMA resources */ 575 /* and free any DMA resources */
576 ide_destroy_dmatable(drive); 576 ide_destroy_dmatable(drive);
577 /* verify good DMA status */ 577 /* verify good DMA status */
diff --git a/drivers/ide/pci/cs5530.c b/drivers/ide/pci/cs5530.c
index 98f260196c4b..68b5d278ca01 100644
--- a/drivers/ide/pci/cs5530.c
+++ b/drivers/ide/pci/cs5530.c
@@ -81,8 +81,8 @@ static void cs5530_tuneproc (ide_drive_t *drive, u8 pio) /* pio=255 means "autot
81 81
82 pio = ide_get_best_pio_mode(drive, pio, 4, NULL); 82 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
83 if (!cs5530_set_xfer_mode(drive, modes[pio])) { 83 if (!cs5530_set_xfer_mode(drive, modes[pio])) {
84 format = (hwif->INL(basereg+4) >> 31) & 1; 84 format = (inl(basereg + 4) >> 31) & 1;
85 hwif->OUTL(cs5530_pio_timings[format][pio], 85 outl(cs5530_pio_timings[format][pio],
86 basereg+(drive->select.b.unit<<3)); 86 basereg+(drive->select.b.unit<<3));
87 } 87 }
88} 88}
@@ -183,17 +183,17 @@ static int cs5530_config_dma (ide_drive_t *drive)
183 break; 183 break;
184 } 184 }
185 basereg = CS5530_BASEREG(hwif); 185 basereg = CS5530_BASEREG(hwif);
186 reg = hwif->INL(basereg+4); /* get drive0 config register */ 186 reg = inl(basereg + 4); /* get drive0 config register */
187 timings |= reg & 0x80000000; /* preserve PIO format bit */ 187 timings |= reg & 0x80000000; /* preserve PIO format bit */
188 if (unit == 0) { /* are we configuring drive0? */ 188 if (unit == 0) { /* are we configuring drive0? */
189 hwif->OUTL(timings, basereg+4); /* write drive0 config register */ 189 outl(timings, basereg + 4); /* write drive0 config register */
190 } else { 190 } else {
191 if (timings & 0x00100000) 191 if (timings & 0x00100000)
192 reg |= 0x00100000; /* enable UDMA timings for both drives */ 192 reg |= 0x00100000; /* enable UDMA timings for both drives */
193 else 193 else
194 reg &= ~0x00100000; /* disable UDMA timings for both drives */ 194 reg &= ~0x00100000; /* disable UDMA timings for both drives */
195 hwif->OUTL(reg, basereg+4); /* write drive0 config register */ 195 outl(reg, basereg + 4); /* write drive0 config register */
196 hwif->OUTL(timings, basereg+12); /* write drive1 config register */ 196 outl(timings, basereg + 12); /* write drive1 config register */
197 } 197 }
198 198
199 /* 199 /*
@@ -315,17 +315,17 @@ static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
315 315
316 hwif->tuneproc = &cs5530_tuneproc; 316 hwif->tuneproc = &cs5530_tuneproc;
317 basereg = CS5530_BASEREG(hwif); 317 basereg = CS5530_BASEREG(hwif);
318 d0_timings = hwif->INL(basereg+0); 318 d0_timings = inl(basereg + 0);
319 if (CS5530_BAD_PIO(d0_timings)) { 319 if (CS5530_BAD_PIO(d0_timings)) {
320 /* PIO timings not initialized? */ 320 /* PIO timings not initialized? */
321 hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+0); 321 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
322 if (!hwif->drives[0].autotune) 322 if (!hwif->drives[0].autotune)
323 hwif->drives[0].autotune = 1; 323 hwif->drives[0].autotune = 1;
324 /* needs autotuning later */ 324 /* needs autotuning later */
325 } 325 }
326 if (CS5530_BAD_PIO(hwif->INL(basereg+8))) { 326 if (CS5530_BAD_PIO(inl(basereg + 8))) {
327 /* PIO timings not initialized? */ 327 /* PIO timings not initialized? */
328 hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+8); 328 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
329 if (!hwif->drives[1].autotune) 329 if (!hwif->drives[1].autotune)
330 hwif->drives[1].autotune = 1; 330 hwif->drives[1].autotune = 1;
331 /* needs autotuning later */ 331 /* needs autotuning later */
diff --git a/drivers/ide/pci/cy82c693.c b/drivers/ide/pci/cy82c693.c
index 603a7bebf117..103b9db97853 100644
--- a/drivers/ide/pci/cy82c693.c
+++ b/drivers/ide/pci/cy82c693.c
@@ -197,8 +197,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
197#if CY82C693_DEBUG_LOGS 197#if CY82C693_DEBUG_LOGS
198 /* for debug let's show the previous values */ 198 /* for debug let's show the previous values */
199 199
200 HWIF(drive)->OUTB(index, CY82_INDEX_PORT); 200 outb(index, CY82_INDEX_PORT);
201 data = HWIF(drive)->INB(CY82_DATA_PORT); 201 data = inb(CY82_DATA_PORT);
202 202
203 printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n", 203 printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
204 drive->name, HWIF(drive)->channel, drive->select.b.unit, 204 drive->name, HWIF(drive)->channel, drive->select.b.unit,
@@ -207,8 +207,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
207 207
208 data = (u8)mode|(u8)(single<<2); 208 data = (u8)mode|(u8)(single<<2);
209 209
210 HWIF(drive)->OUTB(index, CY82_INDEX_PORT); 210 outb(index, CY82_INDEX_PORT);
211 HWIF(drive)->OUTB(data, CY82_DATA_PORT); 211 outb(data, CY82_DATA_PORT);
212 212
213#if CY82C693_DEBUG_INFO 213#if CY82C693_DEBUG_INFO
214 printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", 214 printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
@@ -227,8 +227,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
227 */ 227 */
228 228
229 data = BUSMASTER_TIMEOUT; 229 data = BUSMASTER_TIMEOUT;
230 HWIF(drive)->OUTB(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); 230 outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
231 HWIF(drive)->OUTB(data, CY82_DATA_PORT); 231 outb(data, CY82_DATA_PORT);
232 232
233#if CY82C693_DEBUG_INFO 233#if CY82C693_DEBUG_INFO
234 printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n", 234 printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index d3f6f9da96b2..eccf29f7f89d 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -836,7 +836,7 @@ static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
836 return 0; 836 return 0;
837 } 837 }
838 838
839 dma_stat = hwif->INB(hwif->dma_status); 839 dma_stat = inb(hwif->dma_status);
840 /* return 1 if INTR asserted */ 840 /* return 1 if INTR asserted */
841 if (dma_stat & 4) 841 if (dma_stat & 4)
842 return 1; 842 return 1;
diff --git a/drivers/ide/pci/ns87415.c b/drivers/ide/pci/ns87415.c
index 8aaea4ea5549..7f2090fac6cb 100644
--- a/drivers/ide/pci/ns87415.c
+++ b/drivers/ide/pci/ns87415.c
@@ -166,10 +166,10 @@ static int ns87415_ide_dma_end (ide_drive_t *drive)
166 /* get dma command mode */ 166 /* get dma command mode */
167 dma_cmd = hwif->INB(hwif->dma_command); 167 dma_cmd = hwif->INB(hwif->dma_command);
168 /* stop DMA */ 168 /* stop DMA */
169 hwif->OUTB(dma_cmd & ~1, hwif->dma_command); 169 outb(dma_cmd & ~1, hwif->dma_command);
170 /* from ERRATA: clear the INTR & ERROR bits */ 170 /* from ERRATA: clear the INTR & ERROR bits */
171 dma_cmd = hwif->INB(hwif->dma_command); 171 dma_cmd = hwif->INB(hwif->dma_command);
172 hwif->OUTB(dma_cmd|6, hwif->dma_command); 172 outb(dma_cmd | 6, hwif->dma_command);
173 /* and free any DMA resources */ 173 /* and free any DMA resources */
174 ide_destroy_dmatable(drive); 174 ide_destroy_dmatable(drive);
175 /* verify good DMA status */ 175 /* verify good DMA status */
@@ -243,9 +243,9 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
243 * to SELECT_DRIVE() properly during first probe_hwif(). 243 * to SELECT_DRIVE() properly during first probe_hwif().
244 */ 244 */
245 timeout = 10000; 245 timeout = 10000;
246 hwif->OUTB(12, hwif->io_ports[IDE_CONTROL_OFFSET]); 246 outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
247 udelay(10); 247 udelay(10);
248 hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]); 248 outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
249 do { 249 do {
250 udelay(50); 250 udelay(50);
251 stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 251 stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
@@ -263,7 +263,7 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
263 if (!hwif->dma_base) 263 if (!hwif->dma_base)
264 return; 264 return;
265 265
266 hwif->OUTB(0x60, hwif->dma_status); 266 outb(0x60, hwif->dma_status);
267 hwif->dma_setup = &ns87415_ide_dma_setup; 267 hwif->dma_setup = &ns87415_ide_dma_setup;
268 hwif->ide_dma_check = &ns87415_ide_dma_check; 268 hwif->ide_dma_check = &ns87415_ide_dma_check;
269 hwif->ide_dma_end = &ns87415_ide_dma_end; 269 hwif->ide_dma_end = &ns87415_ide_dma_end;
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
index 22bbf613f948..9ca60dd2185e 100644
--- a/drivers/ide/pci/opti621.c
+++ b/drivers/ide/pci/opti621.c
@@ -176,34 +176,35 @@ static int cmpt_clk(int time, int bus_speed)
176 return ((time*bus_speed+999)/1000); 176 return ((time*bus_speed+999)/1000);
177} 177}
178 178
179static void write_reg(ide_hwif_t *hwif, u8 value, int reg)
180/* Write value to register reg, base of register 179/* Write value to register reg, base of register
181 * is at reg_base (0x1f0 primary, 0x170 secondary, 180 * is at reg_base (0x1f0 primary, 0x170 secondary,
182 * if not changed by PCI configuration). 181 * if not changed by PCI configuration).
183 * This is from setupvic.exe program. 182 * This is from setupvic.exe program.
184 */ 183 */
184static void write_reg(u8 value, int reg)
185{ 185{
186 hwif->INW(reg_base+1); 186 inw(reg_base + 1);
187 hwif->INW(reg_base+1); 187 inw(reg_base + 1);
188 hwif->OUTB(3, reg_base+2); 188 outb(3, reg_base + 2);
189 hwif->OUTB(value, reg_base+reg); 189 outb(value, reg_base + reg);
190 hwif->OUTB(0x83, reg_base+2); 190 outb(0x83, reg_base + 2);
191} 191}
192 192
193static u8 read_reg(ide_hwif_t *hwif, int reg)
194/* Read value from register reg, base of register 193/* Read value from register reg, base of register
195 * is at reg_base (0x1f0 primary, 0x170 secondary, 194 * is at reg_base (0x1f0 primary, 0x170 secondary,
196 * if not changed by PCI configuration). 195 * if not changed by PCI configuration).
197 * This is from setupvic.exe program. 196 * This is from setupvic.exe program.
198 */ 197 */
198static u8 read_reg(int reg)
199{ 199{
200 u8 ret = 0; 200 u8 ret = 0;
201 201
202 hwif->INW(reg_base+1); 202 inw(reg_base + 1);
203 hwif->INW(reg_base+1); 203 inw(reg_base + 1);
204 hwif->OUTB(3, reg_base+2); 204 outb(3, reg_base + 2);
205 ret = hwif->INB(reg_base+reg); 205 ret = inb(reg_base + reg);
206 hwif->OUTB(0x83, reg_base+2); 206 outb(0x83, reg_base + 2);
207
207 return ret; 208 return ret;
208} 209}
209 210
@@ -286,39 +287,39 @@ static void opti621_tune_drive (ide_drive_t *drive, u8 pio)
286 reg_base = hwif->io_ports[IDE_DATA_OFFSET]; 287 reg_base = hwif->io_ports[IDE_DATA_OFFSET];
287 288
288 /* allow Register-B */ 289 /* allow Register-B */
289 hwif->OUTB(0xc0, reg_base+CNTRL_REG); 290 outb(0xc0, reg_base + CNTRL_REG);
290 /* hmm, setupvic.exe does this ;-) */ 291 /* hmm, setupvic.exe does this ;-) */
291 hwif->OUTB(0xff, reg_base+5); 292 outb(0xff, reg_base + 5);
292 /* if reads 0xff, adapter not exist? */ 293 /* if reads 0xff, adapter not exist? */
293 (void) hwif->INB(reg_base+CNTRL_REG); 294 (void)inb(reg_base + CNTRL_REG);
294 /* if reads 0xc0, no interface exist? */ 295 /* if reads 0xc0, no interface exist? */
295 read_reg(hwif, CNTRL_REG); 296 read_reg(CNTRL_REG);
296 /* read version, probably 0 */ 297 /* read version, probably 0 */
297 read_reg(hwif, STRAP_REG); 298 read_reg(STRAP_REG);
298 299
299 /* program primary drive */ 300 /* program primary drive */
300 /* select Index-0 for Register-A */ 301 /* select Index-0 for Register-A */
301 write_reg(hwif, 0, MISC_REG); 302 write_reg(0, MISC_REG);
302 /* set read cycle timings */ 303 /* set read cycle timings */
303 write_reg(hwif, cycle1, READ_REG); 304 write_reg(cycle1, READ_REG);
304 /* set write cycle timings */ 305 /* set write cycle timings */
305 write_reg(hwif, cycle1, WRITE_REG); 306 write_reg(cycle1, WRITE_REG);
306 307
307 /* program secondary drive */ 308 /* program secondary drive */
308 /* select Index-1 for Register-B */ 309 /* select Index-1 for Register-B */
309 write_reg(hwif, 1, MISC_REG); 310 write_reg(1, MISC_REG);
310 /* set read cycle timings */ 311 /* set read cycle timings */
311 write_reg(hwif, cycle2, READ_REG); 312 write_reg(cycle2, READ_REG);
312 /* set write cycle timings */ 313 /* set write cycle timings */
313 write_reg(hwif, cycle2, WRITE_REG); 314 write_reg(cycle2, WRITE_REG);
314 315
315 /* use Register-A for drive 0 */ 316 /* use Register-A for drive 0 */
316 /* use Register-B for drive 1 */ 317 /* use Register-B for drive 1 */
317 write_reg(hwif, 0x85, CNTRL_REG); 318 write_reg(0x85, CNTRL_REG);
318 319
319 /* set address setup, DRDY timings, */ 320 /* set address setup, DRDY timings, */
320 /* and read prefetch for both drives */ 321 /* and read prefetch for both drives */
321 write_reg(hwif, misc, MISC_REG); 322 write_reg(misc, MISC_REG);
322 323
323 spin_unlock_irqrestore(&ide_lock, flags); 324 spin_unlock_irqrestore(&ide_lock, flags);
324} 325}
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index b13a06c5cb2d..32f37e4c1292 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -101,8 +101,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
101{ 101{
102 u8 value; 102 u8 value;
103 103
104 hwif->OUTB(index, hwif->dma_vendor1); 104 outb(index, hwif->dma_vendor1);
105 value = hwif->INB(hwif->dma_vendor3); 105 value = inb(hwif->dma_vendor3);
106 106
107 DBG("index[%02X] value[%02X]\n", index, value); 107 DBG("index[%02X] value[%02X]\n", index, value);
108 return value; 108 return value;
@@ -115,8 +115,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
115 */ 115 */
116static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value) 116static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
117{ 117{
118 hwif->OUTB(index, hwif->dma_vendor1); 118 outb(index, hwif->dma_vendor1);
119 hwif->OUTB(value, hwif->dma_vendor3); 119 outb(value, hwif->dma_vendor3);
120 DBG("index[%02X] value[%02X]\n", index, value); 120 DBG("index[%02X] value[%02X]\n", index, value);
121} 121}
122 122
diff --git a/drivers/ide/pci/pdc202xx_old.c b/drivers/ide/pci/pdc202xx_old.c
index a2be3d2fd3f6..d3be342e5162 100644
--- a/drivers/ide/pci/pdc202xx_old.c
+++ b/drivers/ide/pci/pdc202xx_old.c
@@ -240,17 +240,17 @@ static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
240static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) 240static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
241{ 241{
242 unsigned long clock_reg = hwif->dma_master + 0x11; 242 unsigned long clock_reg = hwif->dma_master + 0x11;
243 u8 clock = hwif->INB(clock_reg); 243 u8 clock = inb(clock_reg);
244 244
245 hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); 245 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
246} 246}
247 247
248static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) 248static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
249{ 249{
250 unsigned long clock_reg = hwif->dma_master + 0x11; 250 unsigned long clock_reg = hwif->dma_master + 0x11;
251 u8 clock = hwif->INB(clock_reg); 251 u8 clock = inb(clock_reg);
252 252
253 hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); 253 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
254} 254}
255 255
256static int config_chipset_for_dma (ide_drive_t *drive) 256static int config_chipset_for_dma (ide_drive_t *drive)
@@ -357,14 +357,14 @@ static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
357 unsigned long high_16 = hwif->dma_master; 357 unsigned long high_16 = hwif->dma_master;
358 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 358 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
359 u32 word_count = 0; 359 u32 word_count = 0;
360 u8 clock = hwif->INB(high_16 + 0x11); 360 u8 clock = inb(high_16 + 0x11);
361 361
362 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11); 362 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
363 word_count = (rq->nr_sectors << 8); 363 word_count = (rq->nr_sectors << 8);
364 word_count = (rq_data_dir(rq) == READ) ? 364 word_count = (rq_data_dir(rq) == READ) ?
365 word_count | 0x05000000 : 365 word_count | 0x05000000 :
366 word_count | 0x06000000; 366 word_count | 0x06000000;
367 hwif->OUTL(word_count, atapi_reg); 367 outl(word_count, atapi_reg);
368 } 368 }
369 ide_dma_start(drive); 369 ide_dma_start(drive);
370} 370}
@@ -377,9 +377,9 @@ static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
377 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 377 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
378 u8 clock = 0; 378 u8 clock = 0;
379 379
380 hwif->OUTL(0, atapi_reg); /* zero out extra */ 380 outl(0, atapi_reg); /* zero out extra */
381 clock = hwif->INB(high_16 + 0x11); 381 clock = inb(high_16 + 0x11);
382 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11); 382 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
383 } 383 }
384 if (drive->current_speed > XFER_UDMA_2) 384 if (drive->current_speed > XFER_UDMA_2)
385 pdc_old_disable_66MHz_clock(drive->hwif); 385 pdc_old_disable_66MHz_clock(drive->hwif);
@@ -390,8 +390,8 @@ static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
390{ 390{
391 ide_hwif_t *hwif = HWIF(drive); 391 ide_hwif_t *hwif = HWIF(drive);
392 unsigned long high_16 = hwif->dma_master; 392 unsigned long high_16 = hwif->dma_master;
393 u8 dma_stat = hwif->INB(hwif->dma_status); 393 u8 dma_stat = inb(hwif->dma_status);
394 u8 sc1d = hwif->INB((high_16 + 0x001d)); 394 u8 sc1d = inb(high_16 + 0x001d);
395 395
396 if (hwif->channel) { 396 if (hwif->channel) {
397 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */ 397 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
@@ -427,11 +427,11 @@ static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
427static void pdc202xx_reset_host (ide_hwif_t *hwif) 427static void pdc202xx_reset_host (ide_hwif_t *hwif)
428{ 428{
429 unsigned long high_16 = hwif->dma_master; 429 unsigned long high_16 = hwif->dma_master;
430 u8 udma_speed_flag = hwif->INB(high_16|0x001f); 430 u8 udma_speed_flag = inb(high_16 | 0x001f);
431 431
432 hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f)); 432 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
433 mdelay(100); 433 mdelay(100);
434 hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f)); 434 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
435 mdelay(2000); /* 2 seconds ?! */ 435 mdelay(2000); /* 2 seconds ?! */
436 436
437 printk(KERN_WARNING "PDC202XX: %s channel reset.\n", 437 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
@@ -519,9 +519,9 @@ static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
519 return; 519 return;
520 } 520 }
521 521
522 udma_speed_flag = hwif->INB((dmabase|0x1f)); 522 udma_speed_flag = inb(dmabase | 0x1f);
523 primary_mode = hwif->INB((dmabase|0x1a)); 523 primary_mode = inb(dmabase | 0x1a);
524 secondary_mode = hwif->INB((dmabase|0x1b)); 524 secondary_mode = inb(dmabase | 0x1b);
525 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ 525 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
526 "Primary %s Mode " \ 526 "Primary %s Mode " \
527 "Secondary %s Mode.\n", hwif->cds->name, 527 "Secondary %s Mode.\n", hwif->cds->name,
@@ -534,9 +534,8 @@ static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
534 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", 534 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
535 hwif->cds->name, udma_speed_flag, 535 hwif->cds->name, udma_speed_flag,
536 (udma_speed_flag|1)); 536 (udma_speed_flag|1));
537 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f)); 537 outb(udma_speed_flag | 1, dmabase | 0x1f);
538 printk("%sACTIVE\n", 538 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
539 (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
540 } 539 }
541#endif /* CONFIG_PDC202XX_BURST */ 540#endif /* CONFIG_PDC202XX_BURST */
542 541
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c
index 9e92e7ba0227..36decbe3afcb 100644
--- a/drivers/ide/pci/serverworks.c
+++ b/drivers/ide/pci/serverworks.c
@@ -160,7 +160,7 @@ static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
160 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || 160 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
161 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { 161 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
162 if (!drive->init_speed) { 162 if (!drive->init_speed) {
163 u8 dma_stat = hwif->INB(hwif->dma_status); 163 u8 dma_stat = inb(hwif->dma_status);
164 164
165dma_pio: 165dma_pio:
166 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) && 166 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
@@ -529,7 +529,7 @@ static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
529 if (!noautodma) 529 if (!noautodma)
530 hwif->autodma = 1; 530 hwif->autodma = 1;
531 531
532 dma_stat = hwif->INB(hwif->dma_status); 532 dma_stat = inb(hwif->dma_status);
533 hwif->drives[0].autodma = (dma_stat & 0x20); 533 hwif->drives[0].autodma = (dma_stat & 0x20);
534 hwif->drives[1].autodma = (dma_stat & 0x40); 534 hwif->drives[1].autodma = (dma_stat & 0x40);
535 hwif->drives[0].autotune = (!(dma_stat & 0x20)); 535 hwif->drives[0].autotune = (!(dma_stat & 0x20));
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
index 81d44ed37f34..2af8a71e688e 100644
--- a/drivers/ide/pci/sgiioc4.c
+++ b/drivers/ide/pci/sgiioc4.c
@@ -110,24 +110,24 @@ sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
110static void 110static void
111sgiioc4_maskproc(ide_drive_t * drive, int mask) 111sgiioc4_maskproc(ide_drive_t * drive, int mask)
112{ 112{
113 ide_hwif_t *hwif = HWIF(drive); 113 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
114 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 114 (void __iomem *)IDE_CONTROL_REG);
115 IDE_CONTROL_REG);
116} 115}
117 116
118 117
119static int 118static int
120sgiioc4_checkirq(ide_hwif_t * hwif) 119sgiioc4_checkirq(ide_hwif_t * hwif)
121{ 120{
122 u8 intr_reg = 121 unsigned long intr_addr =
123 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4); 122 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
124 123
125 if (intr_reg & 0x03) 124 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
126 return 1; 125 return 1;
127 126
128 return 0; 127 return 0;
129} 128}
130 129
130static u8 sgiioc4_INB(unsigned long);
131 131
132static int 132static int
133sgiioc4_clearirq(ide_drive_t * drive) 133sgiioc4_clearirq(ide_drive_t * drive)
@@ -138,21 +138,21 @@ sgiioc4_clearirq(ide_drive_t * drive)
138 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2); 138 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
139 139
140 /* Code to check for PCI error conditions */ 140 /* Code to check for PCI error conditions */
141 intr_reg = hwif->INL(other_ir); 141 intr_reg = readl((void __iomem *)other_ir);
142 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */ 142 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
143 /* 143 /*
144 * Using hwif->INB to read the IDE_STATUS_REG has a side effect 144 * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
145 * of clearing the interrupt. The first read should clear it 145 * of clearing the interrupt. The first read should clear it
146 * if it is set. The second read should return a "clear" status 146 * if it is set. The second read should return a "clear" status
147 * if it got cleared. If not, then spin for a bit trying to 147 * if it got cleared. If not, then spin for a bit trying to
148 * clear it. 148 * clear it.
149 */ 149 */
150 u8 stat = hwif->INB(IDE_STATUS_REG); 150 u8 stat = sgiioc4_INB(IDE_STATUS_REG);
151 int count = 0; 151 int count = 0;
152 stat = hwif->INB(IDE_STATUS_REG); 152 stat = sgiioc4_INB(IDE_STATUS_REG);
153 while ((stat & 0x80) && (count++ < 100)) { 153 while ((stat & 0x80) && (count++ < 100)) {
154 udelay(1); 154 udelay(1);
155 stat = hwif->INB(IDE_STATUS_REG); 155 stat = sgiioc4_INB(IDE_STATUS_REG);
156 } 156 }
157 157
158 if (intr_reg & 0x02) { 158 if (intr_reg & 0x02) {
@@ -161,9 +161,9 @@ sgiioc4_clearirq(ide_drive_t * drive)
161 pci_stat_cmd_reg; 161 pci_stat_cmd_reg;
162 162
163 pci_err_addr_low = 163 pci_err_addr_low =
164 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET]); 164 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
165 pci_err_addr_high = 165 pci_err_addr_high =
166 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + 4); 166 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
167 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND, 167 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
168 &pci_stat_cmd_reg); 168 &pci_stat_cmd_reg);
169 printk(KERN_ERR 169 printk(KERN_ERR
@@ -180,9 +180,9 @@ sgiioc4_clearirq(ide_drive_t * drive)
180 } 180 }
181 181
182 /* Clear the Interrupt, Error bits on the IOC4 */ 182 /* Clear the Interrupt, Error bits on the IOC4 */
183 hwif->OUTL(0x03, other_ir); 183 writel(0x03, (void __iomem *)other_ir);
184 184
185 intr_reg = hwif->INL(other_ir); 185 intr_reg = readl((void __iomem *)other_ir);
186 } 186 }
187 187
188 return intr_reg & 3; 188 return intr_reg & 3;
@@ -191,23 +191,25 @@ sgiioc4_clearirq(ide_drive_t * drive)
191static void sgiioc4_ide_dma_start(ide_drive_t * drive) 191static void sgiioc4_ide_dma_start(ide_drive_t * drive)
192{ 192{
193 ide_hwif_t *hwif = HWIF(drive); 193 ide_hwif_t *hwif = HWIF(drive);
194 unsigned int reg = hwif->INL(hwif->dma_base + IOC4_DMA_CTRL * 4); 194 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
195 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
195 unsigned int temp_reg = reg | IOC4_S_DMA_START; 196 unsigned int temp_reg = reg | IOC4_S_DMA_START;
196 197
197 hwif->OUTL(temp_reg, hwif->dma_base + IOC4_DMA_CTRL * 4); 198 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
198} 199}
199 200
200static u32 201static u32
201sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base) 202sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
202{ 203{
204 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
203 u32 ioc4_dma; 205 u32 ioc4_dma;
204 int count; 206 int count;
205 207
206 count = 0; 208 count = 0;
207 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4); 209 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
208 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) { 210 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
209 udelay(1); 211 udelay(1);
210 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4); 212 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
211 } 213 }
212 return ioc4_dma; 214 return ioc4_dma;
213} 215}
@@ -218,11 +220,11 @@ sgiioc4_ide_dma_end(ide_drive_t * drive)
218{ 220{
219 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0; 221 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
220 ide_hwif_t *hwif = HWIF(drive); 222 ide_hwif_t *hwif = HWIF(drive);
221 u64 dma_base = hwif->dma_base; 223 unsigned long dma_base = hwif->dma_base;
222 int dma_stat = 0; 224 int dma_stat = 0;
223 unsigned long *ending_dma = ide_get_hwifdata(hwif); 225 unsigned long *ending_dma = ide_get_hwifdata(hwif);
224 226
225 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4); 227 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
226 228
227 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); 229 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
228 230
@@ -254,8 +256,8 @@ sgiioc4_ide_dma_end(ide_drive_t * drive)
254 dma_stat = 1; 256 dma_stat = 1;
255 } 257 }
256 258
257 bc_dev = hwif->INL(dma_base + IOC4_BC_DEV * 4); 259 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
258 bc_mem = hwif->INL(dma_base + IOC4_BC_MEM * 4); 260 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
259 261
260 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) { 262 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
261 if (bc_dev > bc_mem + 8) { 263 if (bc_dev > bc_mem + 8) {
@@ -436,16 +438,17 @@ sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
436{ 438{
437 u32 ioc4_dma; 439 u32 ioc4_dma;
438 ide_hwif_t *hwif = HWIF(drive); 440 ide_hwif_t *hwif = HWIF(drive);
439 u64 dma_base = hwif->dma_base; 441 unsigned long dma_base = hwif->dma_base;
442 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
440 u32 dma_addr, ending_dma_addr; 443 u32 dma_addr, ending_dma_addr;
441 444
442 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4); 445 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
443 446
444 if (ioc4_dma & IOC4_S_DMA_ACTIVE) { 447 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
445 printk(KERN_WARNING 448 printk(KERN_WARNING
446 "%s(%s):Warning!! DMA from previous transfer was still active\n", 449 "%s(%s):Warning!! DMA from previous transfer was still active\n",
447 __FUNCTION__, drive->name); 450 __FUNCTION__, drive->name);
448 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4); 451 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
449 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); 452 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
450 453
451 if (ioc4_dma & IOC4_S_DMA_STOP) 454 if (ioc4_dma & IOC4_S_DMA_STOP)
@@ -454,13 +457,13 @@ sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
454 __FUNCTION__, drive->name); 457 __FUNCTION__, drive->name);
455 } 458 }
456 459
457 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4); 460 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
458 if (ioc4_dma & IOC4_S_DMA_ERROR) { 461 if (ioc4_dma & IOC4_S_DMA_ERROR) {
459 printk(KERN_WARNING 462 printk(KERN_WARNING
460 "%s(%s) : Warning!! - DMA Error during Previous" 463 "%s(%s) : Warning!! - DMA Error during Previous"
461 " transfer | status 0x%x\n", 464 " transfer | status 0x%x\n",
462 __FUNCTION__, drive->name, ioc4_dma); 465 __FUNCTION__, drive->name, ioc4_dma);
463 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4); 466 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
464 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); 467 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
465 468
466 if (ioc4_dma & IOC4_S_DMA_STOP) 469 if (ioc4_dma & IOC4_S_DMA_STOP)
@@ -471,14 +474,14 @@ sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
471 474
472 /* Address of the Scatter Gather List */ 475 /* Address of the Scatter Gather List */
473 dma_addr = cpu_to_le32(hwif->dmatable_dma); 476 dma_addr = cpu_to_le32(hwif->dmatable_dma);
474 hwif->OUTL(dma_addr, dma_base + IOC4_DMA_PTR_L * 4); 477 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
475 478
476 /* Address of the Ending DMA */ 479 /* Address of the Ending DMA */
477 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE); 480 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
478 ending_dma_addr = cpu_to_le32(hwif->dma_status); 481 ending_dma_addr = cpu_to_le32(hwif->dma_status);
479 hwif->OUTL(ending_dma_addr, dma_base + IOC4_DMA_END_ADDR * 4); 482 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
480 483
481 hwif->OUTL(dma_direction, dma_base + IOC4_DMA_CTRL * 4); 484 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
482 drive->waiting_for_dma = 1; 485 drive->waiting_for_dma = 1;
483} 486}
484 487
@@ -688,7 +691,7 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
688 default_hwif_mmiops(hwif); 691 default_hwif_mmiops(hwif);
689 692
690 /* Initializing chipset IRQ Registers */ 693 /* Initializing chipset IRQ Registers */
691 hwif->OUTL(0x03, irqport + IOC4_INTR_SET * 4); 694 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
692 695
693 ide_init_sgiioc4(hwif); 696 ide_init_sgiioc4(hwif);
694 697
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
index 367733c8c1de..505878cc21ea 100644
--- a/drivers/ide/pci/siimage.c
+++ b/drivers/ide/pci/siimage.c
@@ -460,11 +460,11 @@ static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
460 unsigned long addr = siimage_selreg(hwif, 0x1); 460 unsigned long addr = siimage_selreg(hwif, 0x1);
461 461
462 if (SATA_ERROR_REG) { 462 if (SATA_ERROR_REG) {
463 u32 ext_stat = hwif->INL(base + 0x10); 463 u32 ext_stat = readl((void __iomem *)(base + 0x10));
464 u8 watchdog = 0; 464 u8 watchdog = 0;
465 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { 465 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
466 u32 sata_error = hwif->INL(SATA_ERROR_REG); 466 u32 sata_error = readl((void __iomem *)SATA_ERROR_REG);
467 hwif->OUTL(sata_error, SATA_ERROR_REG); 467 writel(sata_error, (void __iomem *)SATA_ERROR_REG);
468 watchdog = (sata_error & 0x00680000) ? 1 : 0; 468 watchdog = (sata_error & 0x00680000) ? 1 : 0;
469 printk(KERN_WARNING "%s: sata_error = 0x%08x, " 469 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
470 "watchdog = %d, %s\n", 470 "watchdog = %d, %s\n",
@@ -481,11 +481,11 @@ static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
481 } 481 }
482 482
483 /* return 1 if INTR asserted */ 483 /* return 1 if INTR asserted */
484 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04) 484 if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
485 return 1; 485 return 1;
486 486
487 /* return 1 if Device INTR asserted */ 487 /* return 1 if Device INTR asserted */
488 if ((hwif->INB(addr) & 8) == 8) 488 if ((readb((void __iomem *)addr) & 8) == 8)
489 return 0; //return 1; 489 return 0; //return 1;
490 490
491 return 0; 491 return 0;
@@ -507,9 +507,9 @@ static int siimage_busproc (ide_drive_t * drive, int state)
507 u32 stat_config = 0; 507 u32 stat_config = 0;
508 unsigned long addr = siimage_selreg(hwif, 0); 508 unsigned long addr = siimage_selreg(hwif, 0);
509 509
510 if (hwif->mmio) { 510 if (hwif->mmio)
511 stat_config = hwif->INL(addr); 511 stat_config = readl((void __iomem *)addr);
512 } else 512 else
513 pci_read_config_dword(hwif->pci_dev, addr, &stat_config); 513 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
514 514
515 switch (state) { 515 switch (state) {
@@ -545,9 +545,10 @@ static int siimage_reset_poll (ide_drive_t *drive)
545 if (SATA_STATUS_REG) { 545 if (SATA_STATUS_REG) {
546 ide_hwif_t *hwif = HWIF(drive); 546 ide_hwif_t *hwif = HWIF(drive);
547 547
548 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) { 548 /* SATA_STATUS_REG is valid only when in MMIO mode */
549 if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) {
549 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", 550 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
550 hwif->name, hwif->INL(SATA_STATUS_REG)); 551 hwif->name, readl((void __iomem *)SATA_STATUS_REG));
551 HWGROUP(drive)->polling = 0; 552 HWGROUP(drive)->polling = 0;
552 return ide_started; 553 return ide_started;
553 } 554 }
@@ -607,7 +608,8 @@ static void siimage_reset (ide_drive_t *drive)
607 } 608 }
608 609
609 if (SATA_STATUS_REG) { 610 if (SATA_STATUS_REG) {
610 u32 sata_stat = hwif->INL(SATA_STATUS_REG); 611 /* SATA_STATUS_REG is valid only when in MMIO mode */
612 u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG);
611 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n", 613 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
612 hwif->name, sata_stat, __FUNCTION__); 614 hwif->name, sata_stat, __FUNCTION__);
613 if (!(sata_stat)) { 615 if (!(sata_stat)) {
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c
index 1cb8afe9cb3c..c7025858f237 100644
--- a/drivers/ide/pci/sl82c105.c
+++ b/drivers/ide/pci/sl82c105.c
@@ -215,7 +215,7 @@ static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
215 * Was DMA enabled? If so, disable it - we're resetting the 215 * Was DMA enabled? If so, disable it - we're resetting the
216 * host. The IDE layer will be handling the drive for us. 216 * host. The IDE layer will be handling the drive for us.
217 */ 217 */
218 val = hwif->INB(dma_base); 218 val = inb(dma_base);
219 if (val & 1) { 219 if (val & 1) {
220 outb(val & ~1, dma_base); 220 outb(val & ~1, dma_base);
221 printk("sl82c105: DMA was enabled\n"); 221 printk("sl82c105: DMA was enabled\n");
diff --git a/drivers/ide/pci/tc86c001.c b/drivers/ide/pci/tc86c001.c
index 4e893808f063..b408508a96ee 100644
--- a/drivers/ide/pci/tc86c001.c
+++ b/drivers/ide/pci/tc86c001.c
@@ -45,7 +45,7 @@ static int tc86c001_tune_chipset(ide_drive_t *drive, u8 speed)
45 45
46 scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f; 46 scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
47 scr |= mode; 47 scr |= mode;
48 hwif->OUTW(scr, scr_port); 48 outw(scr, scr_port);
49 49
50 return ide_config_drive_speed(drive, speed); 50 return ide_config_drive_speed(drive, speed);
51} 51}
@@ -89,15 +89,15 @@ static int tc86c001_timer_expiry(ide_drive_t *drive)
89 "attempting recovery...\n", drive->name); 89 "attempting recovery...\n", drive->name);
90 90
91 /* Stop DMA */ 91 /* Stop DMA */
92 hwif->OUTB(dma_cmd & ~0x01, hwif->dma_command); 92 outb(dma_cmd & ~0x01, hwif->dma_command);
93 93
94 /* Setup the dummy DMA transfer */ 94 /* Setup the dummy DMA transfer */
95 hwif->OUTW(0, sc_base + 0x0a); /* Sector Count */ 95 outw(0, sc_base + 0x0a); /* Sector Count */
96 hwif->OUTW(0, twcr_port); /* Transfer Word Count 1 or 2 */ 96 outw(0, twcr_port); /* Transfer Word Count 1 or 2 */
97 97
98 /* Start the dummy DMA transfer */ 98 /* Start the dummy DMA transfer */
99 hwif->OUTB(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */ 99 outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
100 hwif->OUTB(0x01, hwif->dma_command); /* set START_STOPBM */ 100 outb(0x01, hwif->dma_command); /* set START_STOPBM */
101 101
102 /* 102 /*
103 * If an interrupt was pending, it should come thru shortly. 103 * If an interrupt was pending, it should come thru shortly.
@@ -128,8 +128,8 @@ static void tc86c001_dma_start(ide_drive_t *drive)
128 * the appropriate system control registers for DMA to work 128 * the appropriate system control registers for DMA to work
129 * with LBA48 and ATAPI devices... 129 * with LBA48 and ATAPI devices...
130 */ 130 */
131 hwif->OUTW(nsectors, sc_base + 0x0a); /* Sector Count */ 131 outw(nsectors, sc_base + 0x0a); /* Sector Count */
132 hwif->OUTW(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */ 132 outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
133 133
134 /* Install our timeout expiry hook, saving the current handler... */ 134 /* Install our timeout expiry hook, saving the current handler... */
135 ide_set_hwifdata(hwif, hwgroup->expiry); 135 ide_set_hwifdata(hwif, hwgroup->expiry);
@@ -168,7 +168,7 @@ static int tc86c001_busproc(ide_drive_t *drive, int state)
168 } 168 }
169 169
170 /* System Control 1 Register bit 11 (ATA Hard Reset) write */ 170 /* System Control 1 Register bit 11 (ATA Hard Reset) write */
171 hwif->OUTW(scr1, sc_base + 0x00); 171 outw(scr1, sc_base + 0x00);
172 return 0; 172 return 0;
173} 173}
174 174
@@ -204,13 +204,13 @@ static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
204 u16 scr1 = hwif->INW(sc_base + 0x00);; 204 u16 scr1 = hwif->INW(sc_base + 0x00);;
205 205
206 /* System Control 1 Register bit 15 (Soft Reset) set */ 206 /* System Control 1 Register bit 15 (Soft Reset) set */
207 hwif->OUTW(scr1 | 0x8000, sc_base + 0x00); 207 outw(scr1 | 0x8000, sc_base + 0x00);
208 208
209 /* System Control 1 Register bit 14 (FIFO Reset) set */ 209 /* System Control 1 Register bit 14 (FIFO Reset) set */
210 hwif->OUTW(scr1 | 0x4000, sc_base + 0x00); 210 outw(scr1 | 0x4000, sc_base + 0x00);
211 211
212 /* System Control 1 Register: reset clear */ 212 /* System Control 1 Register: reset clear */
213 hwif->OUTW(scr1 & ~0xc000, sc_base + 0x00); 213 outw(scr1 & ~0xc000, sc_base + 0x00);
214 214
215 /* Store the system control register base for convenience... */ 215 /* Store the system control register base for convenience... */
216 hwif->config_data = sc_base; 216 hwif->config_data = sc_base;
@@ -228,7 +228,7 @@ static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
228 * Sector Count Control Register bits 0 and 1 set: 228 * Sector Count Control Register bits 0 and 1 set:
229 * software sets Sector Count Register for master and slave device 229 * software sets Sector Count Register for master and slave device
230 */ 230 */
231 hwif->OUTW(0x0003, sc_base + 0x0c); 231 outw(0x0003, sc_base + 0x0c);
232 232
233 /* Sector Count Register limit */ 233 /* Sector Count Register limit */
234 hwif->rqsize = 0xffff; 234 hwif->rqsize = 0xffff;
diff --git a/drivers/ide/pci/trm290.c b/drivers/ide/pci/trm290.c
index 5eb98893810c..cbb1b11119a5 100644
--- a/drivers/ide/pci/trm290.c
+++ b/drivers/ide/pci/trm290.c
@@ -157,16 +157,16 @@ static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
157 if (reg != hwif->select_data) { 157 if (reg != hwif->select_data) {
158 hwif->select_data = reg; 158 hwif->select_data = reg;
159 /* set PIO/DMA */ 159 /* set PIO/DMA */
160 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1); 160 outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
161 hwif->OUTW(reg & 0xff, hwif->config_data); 161 outw(reg & 0xff, hwif->config_data);
162 } 162 }
163 163
164 /* enable IRQ if not probing */ 164 /* enable IRQ if not probing */
165 if (drive->present) { 165 if (drive->present) {
166 reg = hwif->INW(hwif->config_data + 3); 166 reg = inw(hwif->config_data + 3);
167 reg &= 0x13; 167 reg &= 0x13;
168 reg &= ~(1 << hwif->channel); 168 reg &= ~(1 << hwif->channel);
169 hwif->OUTW(reg, hwif->config_data+3); 169 outw(reg, hwif->config_data + 3);
170 } 170 }
171 171
172 local_irq_restore(flags); 172 local_irq_restore(flags);
@@ -179,12 +179,10 @@ static void trm290_selectproc (ide_drive_t *drive)
179 179
180static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command) 180static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
181{ 181{
182 ide_hwif_t *hwif = HWIF(drive);
183
184 BUG_ON(HWGROUP(drive)->handler != NULL); /* paranoia check */ 182 BUG_ON(HWGROUP(drive)->handler != NULL); /* paranoia check */
185 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL); 183 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
186 /* issue cmd to drive */ 184 /* issue cmd to drive */
187 hwif->OUTB(command, IDE_COMMAND_REG); 185 outb(command, IDE_COMMAND_REG);
188} 186}
189 187
190static int trm290_ide_dma_setup(ide_drive_t *drive) 188static int trm290_ide_dma_setup(ide_drive_t *drive)
@@ -210,10 +208,10 @@ static int trm290_ide_dma_setup(ide_drive_t *drive)
210 } 208 }
211 /* select DMA xfer */ 209 /* select DMA xfer */
212 trm290_prepare_drive(drive, 1); 210 trm290_prepare_drive(drive, 1);
213 hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command); 211 outl(hwif->dmatable_dma | rw, hwif->dma_command);
214 drive->waiting_for_dma = 1; 212 drive->waiting_for_dma = 1;
215 /* start DMA */ 213 /* start DMA */
216 hwif->OUTW((count * 2) - 1, hwif->dma_status); 214 outw((count * 2) - 1, hwif->dma_status);
217 return 0; 215 return 0;
218} 216}
219 217
@@ -229,7 +227,7 @@ static int trm290_ide_dma_end (ide_drive_t *drive)
229 drive->waiting_for_dma = 0; 227 drive->waiting_for_dma = 0;
230 /* purge DMA mappings */ 228 /* purge DMA mappings */
231 ide_destroy_dmatable(drive); 229 ide_destroy_dmatable(drive);
232 status = hwif->INW(hwif->dma_status); 230 status = inw(hwif->dma_status);
233 return (status != 0x00ff); 231 return (status != 0x00ff);
234} 232}
235 233
@@ -238,7 +236,7 @@ static int trm290_ide_dma_test_irq (ide_drive_t *drive)
238 ide_hwif_t *hwif = HWIF(drive); 236 ide_hwif_t *hwif = HWIF(drive);
239 u16 status = 0; 237 u16 status = 0;
240 238
241 status = hwif->INW(hwif->dma_status); 239 status = inw(hwif->dma_status);
242 return (status == 0x00ff); 240 return (status == 0x00ff);
243} 241}
244 242
@@ -267,15 +265,15 @@ static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
267 265
268 local_irq_save(flags); 266 local_irq_save(flags);
269 /* put config reg into first byte of hwif->select_data */ 267 /* put config reg into first byte of hwif->select_data */
270 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1); 268 outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
271 /* select PIO as default */ 269 /* select PIO as default */
272 hwif->select_data = 0x21; 270 hwif->select_data = 0x21;
273 hwif->OUTB(hwif->select_data, hwif->config_data); 271 outb(hwif->select_data, hwif->config_data);
274 /* get IRQ info */ 272 /* get IRQ info */
275 reg = hwif->INB(hwif->config_data+3); 273 reg = inb(hwif->config_data + 3);
276 /* mask IRQs for both ports */ 274 /* mask IRQs for both ports */
277 reg = (reg & 0x10) | 0x03; 275 reg = (reg & 0x10) | 0x03;
278 hwif->OUTB(reg, hwif->config_data+3); 276 outb(reg, hwif->config_data + 3);
279 local_irq_restore(flags); 277 local_irq_restore(flags);
280 278
281 if ((reg & 0x10)) 279 if ((reg & 0x10))
@@ -308,16 +306,16 @@ static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
308 static u16 next_offset = 0; 306 static u16 next_offset = 0;
309 u8 old_mask; 307 u8 old_mask;
310 308
311 hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1); 309 outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);
312 old = hwif->INW(hwif->config_data); 310 old = inw(hwif->config_data);
313 old &= ~1; 311 old &= ~1;
314 old_mask = hwif->INB(old+2); 312 old_mask = inb(old + 2);
315 if (old != compat && old_mask == 0xff) { 313 if (old != compat && old_mask == 0xff) {
316 /* leave lower 10 bits untouched */ 314 /* leave lower 10 bits untouched */
317 compat += (next_offset += 0x400); 315 compat += (next_offset += 0x400);
318 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2; 316 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
319 hwif->OUTW(compat|1, hwif->config_data); 317 outw(compat | 1, hwif->config_data);
320 new = hwif->INW(hwif->config_data); 318 new = inw(hwif->config_data);
321 printk(KERN_INFO "%s: control basereg workaround: " 319 printk(KERN_INFO "%s: control basereg workaround: "
322 "old=0x%04x, new=0x%04x\n", 320 "old=0x%04x, new=0x%04x\n",
323 hwif->name, old, new & ~1); 321 hwif->name, old, new & ~1);
diff --git a/drivers/ide/ppc/scc_pata.c b/drivers/ide/ppc/scc_pata.c
index 0ab26ea5a35a..de9110803745 100644
--- a/drivers/ide/ppc/scc_pata.c
+++ b/drivers/ide/ppc/scc_pata.c
@@ -132,12 +132,6 @@ static u16 scc_ide_inw(unsigned long port)
132 return (u16)data; 132 return (u16)data;
133} 133}
134 134
135static u32 scc_ide_inl(unsigned long port)
136{
137 u32 data = in_be32((void*)port);
138 return data;
139}
140
141static void scc_ide_insw(unsigned long port, void *addr, u32 count) 135static void scc_ide_insw(unsigned long port, void *addr, u32 count)
142{ 136{
143 u16 *ptr = (u16 *)addr; 137 u16 *ptr = (u16 *)addr;
@@ -165,11 +159,6 @@ static void scc_ide_outw(u16 addr, unsigned long port)
165 out_be32((void*)port, addr); 159 out_be32((void*)port, addr);
166} 160}
167 161
168static void scc_ide_outl(u32 addr, unsigned long port)
169{
170 out_be32((void*)port, addr);
171}
172
173static void 162static void
174scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port) 163scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
175{ 164{
@@ -258,16 +247,16 @@ static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted)
258 break; 247 break;
259 } 248 }
260 249
261 reg = hwif->INL(cckctrl_port); 250 reg = in_be32((void __iomem *)cckctrl_port);
262 if (reg & CCKCTRL_ATACLKOEN) { 251 if (reg & CCKCTRL_ATACLKOEN) {
263 offset = 1; /* 133MHz */ 252 offset = 1; /* 133MHz */
264 } else { 253 } else {
265 offset = 0; /* 100MHz */ 254 offset = 0; /* 100MHz */
266 } 255 }
267 reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted]; 256 reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted];
268 hwif->OUTL(reg, piosht_port); 257 out_be32((void __iomem *)piosht_port, reg);
269 reg = JCHCTtbl[offset][mode_wanted]; 258 reg = JCHCTtbl[offset][mode_wanted];
270 hwif->OUTL(reg, pioct_port); 259 out_be32((void __iomem *)pioct_port, reg);
271 260
272 ide_config_drive_speed(drive, speed); 261 ide_config_drive_speed(drive, speed);
273} 262}
@@ -299,7 +288,7 @@ static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
299 unsigned long reg; 288 unsigned long reg;
300 unsigned long jcactsel; 289 unsigned long jcactsel;
301 290
302 reg = hwif->INL(cckctrl_port); 291 reg = in_be32((void __iomem *)cckctrl_port);
303 if (reg & CCKCTRL_ATACLKOEN) { 292 if (reg & CCKCTRL_ATACLKOEN) {
304 offset = 1; /* 133MHz */ 293 offset = 1; /* 133MHz */
305 } else { 294 } else {
@@ -334,17 +323,17 @@ static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
334 323
335 jcactsel = JCACTSELtbl[offset][idx]; 324 jcactsel = JCACTSELtbl[offset][idx];
336 if (is_slave) { 325 if (is_slave) {
337 hwif->OUTL(JCHDCTxtbl[offset][idx], sdmact_port); 326 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
338 hwif->OUTL(JCSTWTxtbl[offset][idx], scrcst_port); 327 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
339 jcactsel = jcactsel << 2 ; 328 jcactsel = jcactsel << 2;
340 hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_SLAVE) | jcactsel, tdvhsel_port ); 329 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
341 } else { 330 } else {
342 hwif->OUTL(JCHDCTxtbl[offset][idx], mdmact_port); 331 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
343 hwif->OUTL(JCSTWTxtbl[offset][idx], mcrcst_port); 332 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
344 hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_MASTER) | jcactsel, tdvhsel_port ); 333 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
345 } 334 }
346 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]; 335 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
347 hwif->OUTL(reg, udenvt_port); 336 out_be32((void __iomem *)udenvt_port, reg);
348 337
349 return ide_config_drive_speed(drive, speed); 338 return ide_config_drive_speed(drive, speed);
350} 339}
@@ -395,6 +384,51 @@ static int scc_config_drive_for_dma(ide_drive_t *drive)
395} 384}
396 385
397/** 386/**
387 * scc_ide_dma_setup - begin a DMA phase
388 * @drive: target device
389 *
390 * Build an IDE DMA PRD (IDE speak for scatter gather table)
391 * and then set up the DMA transfer registers.
392 *
393 * Returns 0 on success. If a PIO fallback is required then 1
394 * is returned.
395 */
396
397static int scc_dma_setup(ide_drive_t *drive)
398{
399 ide_hwif_t *hwif = drive->hwif;
400 struct request *rq = HWGROUP(drive)->rq;
401 unsigned int reading;
402 u8 dma_stat;
403
404 if (rq_data_dir(rq))
405 reading = 0;
406 else
407 reading = 1 << 3;
408
409 /* fall back to pio! */
410 if (!ide_build_dmatable(drive, rq)) {
411 ide_map_sg(drive, rq);
412 return 1;
413 }
414
415 /* PRD table */
416 out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
417
418 /* specify r/w */
419 out_be32((void __iomem *)hwif->dma_command, reading);
420
421 /* read dma_status for INTR & ERROR flags */
422 dma_stat = in_be32((void __iomem *)hwif->dma_status);
423
424 /* clear INTR & ERROR flags */
425 out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
426 drive->waiting_for_dma = 1;
427 return 0;
428}
429
430
431/**
398 * scc_ide_dma_end - Stop DMA 432 * scc_ide_dma_end - Stop DMA
399 * @drive: IDE drive 433 * @drive: IDE drive
400 * 434 *
@@ -409,14 +443,13 @@ static int scc_ide_dma_end(ide_drive_t * drive)
409 u32 reg; 443 u32 reg;
410 444
411 while (1) { 445 while (1) {
412 reg = hwif->INL(intsts_port); 446 reg = in_be32((void __iomem *)intsts_port);
413 447
414 if (reg & INTSTS_SERROR) { 448 if (reg & INTSTS_SERROR) {
415 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); 449 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
416 hwif->OUTL(INTSTS_SERROR|INTSTS_BMSINT, intsts_port); 450 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
417 451
418 hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS, 452 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
419 hwif->dma_command);
420 continue; 453 continue;
421 } 454 }
422 455
@@ -424,56 +457,53 @@ static int scc_ide_dma_end(ide_drive_t * drive)
424 u32 maea0, maec0; 457 u32 maea0, maec0;
425 unsigned long ctl_base = hwif->config_data; 458 unsigned long ctl_base = hwif->config_data;
426 459
427 maea0 = hwif->INL(ctl_base + 0xF50); 460 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
428 maec0 = hwif->INL(ctl_base + 0xF54); 461 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
429 462
430 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0); 463 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
431 464
432 hwif->OUTL(INTSTS_PRERR|INTSTS_BMSINT, intsts_port); 465 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
433 466
434 hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS, 467 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
435 hwif->dma_command);
436 continue; 468 continue;
437 } 469 }
438 470
439 if (reg & INTSTS_RERR) { 471 if (reg & INTSTS_RERR) {
440 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); 472 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
441 hwif->OUTL(INTSTS_RERR|INTSTS_BMSINT, intsts_port); 473 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
442 474
443 hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS, 475 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
444 hwif->dma_command);
445 continue; 476 continue;
446 } 477 }
447 478
448 if (reg & INTSTS_ICERR) { 479 if (reg & INTSTS_ICERR) {
449 hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS, 480 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
450 hwif->dma_command);
451 481
452 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); 482 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
453 hwif->OUTL(INTSTS_ICERR|INTSTS_BMSINT, intsts_port); 483 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
454 continue; 484 continue;
455 } 485 }
456 486
457 if (reg & INTSTS_BMSINT) { 487 if (reg & INTSTS_BMSINT) {
458 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME); 488 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
459 hwif->OUTL(INTSTS_BMSINT, intsts_port); 489 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
460 490
461 ide_do_reset(drive); 491 ide_do_reset(drive);
462 continue; 492 continue;
463 } 493 }
464 494
465 if (reg & INTSTS_BMHE) { 495 if (reg & INTSTS_BMHE) {
466 hwif->OUTL(INTSTS_BMHE, intsts_port); 496 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
467 continue; 497 continue;
468 } 498 }
469 499
470 if (reg & INTSTS_ACTEINT) { 500 if (reg & INTSTS_ACTEINT) {
471 hwif->OUTL(INTSTS_ACTEINT, intsts_port); 501 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
472 continue; 502 continue;
473 } 503 }
474 504
475 if (reg & INTSTS_IOIRQS) { 505 if (reg & INTSTS_IOIRQS) {
476 hwif->OUTL(INTSTS_IOIRQS, intsts_port); 506 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
477 continue; 507 continue;
478 } 508 }
479 break; 509 break;
@@ -617,13 +647,11 @@ static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
617 647
618 hwif->INB = scc_ide_inb; 648 hwif->INB = scc_ide_inb;
619 hwif->INW = scc_ide_inw; 649 hwif->INW = scc_ide_inw;
620 hwif->INL = scc_ide_inl;
621 hwif->INSW = scc_ide_insw; 650 hwif->INSW = scc_ide_insw;
622 hwif->INSL = scc_ide_insl; 651 hwif->INSL = scc_ide_insl;
623 hwif->OUTB = scc_ide_outb; 652 hwif->OUTB = scc_ide_outb;
624 hwif->OUTBSYNC = scc_ide_outbsync; 653 hwif->OUTBSYNC = scc_ide_outbsync;
625 hwif->OUTW = scc_ide_outw; 654 hwif->OUTW = scc_ide_outw;
626 hwif->OUTL = scc_ide_outl;
627 hwif->OUTSW = scc_ide_outsw; 655 hwif->OUTSW = scc_ide_outsw;
628 hwif->OUTSL = scc_ide_outsl; 656 hwif->OUTSL = scc_ide_outsl;
629 657
@@ -679,8 +707,10 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif)
679 hwif->dma_status = hwif->dma_base + 0x04; 707 hwif->dma_status = hwif->dma_base + 0x04;
680 hwif->dma_prdtable = hwif->dma_base + 0x08; 708 hwif->dma_prdtable = hwif->dma_base + 0x08;
681 709
682 hwif->OUTL(hwif->dmatable_dma, (hwif->dma_base + 0x018)); /* PTERADD */ 710 /* PTERADD */
711 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
683 712
713 hwif->dma_setup = scc_dma_setup;
684 hwif->ide_dma_end = scc_ide_dma_end; 714 hwif->ide_dma_end = scc_ide_dma_end;
685 hwif->speedproc = scc_tune_chipset; 715 hwif->speedproc = scc_tune_chipset;
686 hwif->tuneproc = scc_tuneproc; 716 hwif->tuneproc = scc_tuneproc;
@@ -689,7 +719,7 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif)
689 hwif->drives[0].autotune = IDE_TUNE_AUTO; 719 hwif->drives[0].autotune = IDE_TUNE_AUTO;
690 hwif->drives[1].autotune = IDE_TUNE_AUTO; 720 hwif->drives[1].autotune = IDE_TUNE_AUTO;
691 721
692 if (hwif->INL(hwif->config_data + 0xff0) & CCKCTRL_ATACLKOEN) { 722 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
693 hwif->ultra_mask = 0x7f; /* 133MHz */ 723 hwif->ultra_mask = 0x7f; /* 133MHz */
694 } else { 724 } else {
695 hwif->ultra_mask = 0x3f; /* 100MHz */ 725 hwif->ultra_mask = 0x3f; /* 100MHz */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 12:08:48 -0500