diff options
author | Olof Johansson <olof@lixom.net> | 2014-07-08 00:10:17 -0400 |
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committer | Olof Johansson <olof@lixom.net> | 2014-07-08 00:10:17 -0400 |
commit | 069c70cb07105521a095655e707ce9c20bcc6154 (patch) | |
tree | 1ca8130ee071dd01fae618c7f04c84a24a2e0f09 /drivers | |
parent | 8b5ca6495358872d495eb7223fc6d737ee2b9b2c (diff) | |
parent | 35e75645f16c86918f26df1bfc2c24ad8ebb5a17 (diff) |
Merge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Merge "Samsung fixes-2 for v3.16" from Kukjin Kim:
- fix the check for SMP configuration with using CONFIG_SMP
not just SMP
- fix the number of pwm-cells for exynos4 pwm
- fix ftrace for exynos_mct
- register exynos_mct for stable udely
- fix secondary boot addr for secure mode for exynos SoCs
* tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Update secondary boot addr for secure mode
clocksource: exynos_mct: Register the timer for stable udelay
clocksource: exynos_mct: Fix ftrace
ARM: dts: fix pwm-cells in pwm node for exynos4
ARM: EXYNOS: Fix the check for non-smp configuration
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clocksource/exynos_mct.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index f71d55f5e6e5..ab51bf20a3ed 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c | |||
@@ -162,7 +162,7 @@ static void exynos4_mct_frc_start(void) | |||
162 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); | 162 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); |
163 | } | 163 | } |
164 | 164 | ||
165 | static cycle_t exynos4_frc_read(struct clocksource *cs) | 165 | static cycle_t notrace _exynos4_frc_read(void) |
166 | { | 166 | { |
167 | unsigned int lo, hi; | 167 | unsigned int lo, hi; |
168 | u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); | 168 | u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); |
@@ -176,6 +176,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs) | |||
176 | return ((cycle_t)hi << 32) | lo; | 176 | return ((cycle_t)hi << 32) | lo; |
177 | } | 177 | } |
178 | 178 | ||
179 | static cycle_t exynos4_frc_read(struct clocksource *cs) | ||
180 | { | ||
181 | return _exynos4_frc_read(); | ||
182 | } | ||
183 | |||
179 | static void exynos4_frc_resume(struct clocksource *cs) | 184 | static void exynos4_frc_resume(struct clocksource *cs) |
180 | { | 185 | { |
181 | exynos4_mct_frc_start(); | 186 | exynos4_mct_frc_start(); |
@@ -192,13 +197,24 @@ struct clocksource mct_frc = { | |||
192 | 197 | ||
193 | static u64 notrace exynos4_read_sched_clock(void) | 198 | static u64 notrace exynos4_read_sched_clock(void) |
194 | { | 199 | { |
195 | return exynos4_frc_read(&mct_frc); | 200 | return _exynos4_frc_read(); |
201 | } | ||
202 | |||
203 | static struct delay_timer exynos4_delay_timer; | ||
204 | |||
205 | static cycles_t exynos4_read_current_timer(void) | ||
206 | { | ||
207 | return _exynos4_frc_read(); | ||
196 | } | 208 | } |
197 | 209 | ||
198 | static void __init exynos4_clocksource_init(void) | 210 | static void __init exynos4_clocksource_init(void) |
199 | { | 211 | { |
200 | exynos4_mct_frc_start(); | 212 | exynos4_mct_frc_start(); |
201 | 213 | ||
214 | exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; | ||
215 | exynos4_delay_timer.freq = clk_rate; | ||
216 | register_current_timer_delay(&exynos4_delay_timer); | ||
217 | |||
202 | if (clocksource_register_hz(&mct_frc, clk_rate)) | 218 | if (clocksource_register_hz(&mct_frc, clk_rate)) |
203 | panic("%s: can't register clocksource\n", mct_frc.name); | 219 | panic("%s: can't register clocksource\n", mct_frc.name); |
204 | 220 | ||