drm/i915: Save and restore the GM45 FBC regs on suspend and resume.

This hasn't fixed the regressions we were testing against, but clearly
should be required.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

2 files changed, 19 insertions, 8 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 17be01e351b3..1254c4b80e30 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -342,6 +342,7 @@ typedef struct drm_i915_private {
         u32 savePFIT_CONTROL;
         u32 save_palette_a[256];
         u32 save_palette_b[256];
+        u32 saveDPFC_CB_BASE;
         u32 saveFBC_CFB_BASE;
         u32 saveFBC_LL_BASE;
         u32 saveFBC_CONTROL;
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bd6d8d91ca9f..660c5f36424b 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -437,10 +437,14 @@ void i915_save_display(struct drm_device *dev)
         /* FIXME: save TV & SDVO state */
 
         /* FBC state */
-        dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
-        dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
-        dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
-        dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
+        if (IS_GM45(dev)) {
+                dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
+        } else {
+                dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
+                dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
+                dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
+                dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
+        }
 
         /* VGA state */
         dev_priv->saveVGA0 = I915_READ(VGA0);
@@ -511,10 +515,16 @@ void i915_restore_display(struct drm_device *dev)
         /* FIXME: restore TV & SDVO state */
 
         /* FBC info */
-        I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
-        I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
-        I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
-        I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
+        if (IS_GM45(dev)) {
+                g4x_disable_fbc(dev);
+                I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
+        } else {
+                i8xx_disable_fbc(dev);
+                I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
+                I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
+                I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
+                I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
+        }
 
         /* VGA state */
         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);