diff options
author | Alexander Shiyan <shc_work@mail.ru> | 2014-05-08 03:56:40 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-06-19 20:43:34 -0400 |
commit | f80b2581a7068907076ca92c43866f36f446c039 (patch) | |
tree | 8b98431b0debc428c33bfde35fe310a89fbd63b4 /drivers/w1 | |
parent | b7ce0b5d03f303cba0fff3f9df17f400d4e7a2d8 (diff) |
w1: mxc_w1: Optimize mxc_w1_ds2_touch_bit()
According to the i.MX reference manual, the read/write bit operations
takes from 60 us to 120 us.
This patch optimizes mxc_w1_ds2_touch_bit() function to use proper
value for such delay. Nevertheless, a small margin for the timeout has
been added for the case if clock frequency is inaccurate.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/w1')
-rw-r--r-- | drivers/w1/masters/mxc_w1.c | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c index 741d2bb400ae..da3d0f0ad63c 100644 --- a/drivers/w1/masters/mxc_w1.c +++ b/drivers/w1/masters/mxc_w1.c | |||
@@ -75,22 +75,25 @@ static u8 mxc_w1_ds2_reset_bus(void *data) | |||
75 | */ | 75 | */ |
76 | static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit) | 76 | static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit) |
77 | { | 77 | { |
78 | struct mxc_w1_device *mdev = data; | 78 | struct mxc_w1_device *dev = data; |
79 | void __iomem *ctrl_addr = mdev->regs + MXC_W1_CONTROL; | 79 | unsigned long timeout; |
80 | unsigned int timeout_cnt = 400; /* Takes max. 120us according to | 80 | |
81 | * datasheet. | 81 | writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL); |
82 | */ | 82 | |
83 | /* Wait for read/write bit (60us, Max 120us), use 200us for sure */ | ||
84 | timeout = jiffies + usecs_to_jiffies(200); | ||
83 | 85 | ||
84 | writeb(MXC_W1_CONTROL_WR(bit), ctrl_addr); | 86 | udelay(60); |
85 | 87 | ||
86 | while (timeout_cnt--) { | 88 | do { |
87 | if (!(readb(ctrl_addr) & MXC_W1_CONTROL_WR(bit))) | 89 | u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); |
88 | break; | ||
89 | 90 | ||
90 | udelay(1); | 91 | /* RDST bit is valid after the WR1/RD bit is self-cleared */ |
91 | } | 92 | if (!(ctrl & MXC_W1_CONTROL_WR(bit))) |
93 | return !!(ctrl & MXC_W1_CONTROL_RDST); | ||
94 | } while (time_is_after_jiffies(timeout)); | ||
92 | 95 | ||
93 | return !!(readb(ctrl_addr) & MXC_W1_CONTROL_RDST); | 96 | return 0; |
94 | } | 97 | } |
95 | 98 | ||
96 | static int mxc_w1_probe(struct platform_device *pdev) | 99 | static int mxc_w1_probe(struct platform_device *pdev) |