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authorDave Jones <davej@redhat.com>2006-04-18 18:19:55 -0400
committerDave Jones <davej@redhat.com>2006-04-18 18:19:55 -0400
commitf1f76afd71e0f17af9a35fcb649f4bab53304a4d (patch)
treea56257b13a0eda4a9b7e950c3b85adad16341b80 /drivers/video
parent530515a06f90c0831732709efee4a99497bd2b7c (diff)
parent385910f2b275a636238f70844f1b6da9fda6f2da (diff)
Merge ../linus
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/Kconfig14
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/aty/aty128fb.c7
-rw-r--r--drivers/video/aty/atyfb_base.c9
-rw-r--r--drivers/video/aty/radeon_pm.c4
-rw-r--r--drivers/video/backlight/Kconfig4
-rw-r--r--drivers/video/backlight/backlight.c84
-rw-r--r--drivers/video/backlight/corgi_bl.c124
-rw-r--r--drivers/video/backlight/hp680_bl.c139
-rw-r--r--drivers/video/cfbimgblt.c2
-rw-r--r--drivers/video/cirrusfb.c4
-rw-r--r--drivers/video/console/fbcon.c11
-rw-r--r--drivers/video/console/sticore.c22
-rw-r--r--drivers/video/fbmem.c7
-rw-r--r--drivers/video/matrox/matroxfb_base.c3
-rw-r--r--drivers/video/nvidia/nvidia.c5
-rw-r--r--drivers/video/pxafb.c8
-rw-r--r--drivers/video/radeonfb.c3167
-rw-r--r--drivers/video/riva/fbdev.c9
-rw-r--r--drivers/video/sticore.h37
-rw-r--r--drivers/video/stifb.c95
-rw-r--r--drivers/video/vesafb.c27
-rw-r--r--drivers/video/w100fb.c162
-rw-r--r--drivers/video/w100fb.h748
24 files changed, 859 insertions, 3834 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 22e9d696fdd2..9060e7137441 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -904,18 +904,6 @@ config FB_MATROX_MULTIHEAD
904 There is no need for enabling 'Matrox multihead support' if you have 904 There is no need for enabling 'Matrox multihead support' if you have
905 only one Matrox card in the box. 905 only one Matrox card in the box.
906 906
907config FB_RADEON_OLD
908 tristate "ATI Radeon display support (Old driver)"
909 depends on FB && PCI
910 select FB_CFB_FILLRECT
911 select FB_CFB_COPYAREA
912 select FB_CFB_IMAGEBLIT
913 select FB_MACMODES if PPC
914 help
915 Choose this option if you want to use an ATI Radeon graphics card as
916 a framebuffer device. There are both PCI and AGP versions. You
917 don't need to choose this to run the Radeon in plain VGA mode.
918
919config FB_RADEON 907config FB_RADEON
920 tristate "ATI Radeon display support" 908 tristate "ATI Radeon display support"
921 depends on FB && PCI 909 depends on FB && PCI
@@ -973,7 +961,7 @@ config FB_ATY128
973 961
974config FB_ATY 962config FB_ATY
975 tristate "ATI Mach64 display support" if PCI || ATARI 963 tristate "ATI Mach64 display support" if PCI || ATARI
976 depends on FB 964 depends on FB && !SPARC32
977 select FB_CFB_FILLRECT 965 select FB_CFB_FILLRECT
978 select FB_CFB_COPYAREA 966 select FB_CFB_COPYAREA
979 select FB_CFB_IMAGEBLIT 967 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index cb90218515ac..23de3b2c7856 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -39,7 +39,6 @@ obj-$(CONFIG_FB_KYRO) += kyro/
39obj-$(CONFIG_FB_SAVAGE) += savage/ 39obj-$(CONFIG_FB_SAVAGE) += savage/
40obj-$(CONFIG_FB_GEODE) += geode/ 40obj-$(CONFIG_FB_GEODE) += geode/
41obj-$(CONFIG_FB_I810) += vgastate.o 41obj-$(CONFIG_FB_I810) += vgastate.o
42obj-$(CONFIG_FB_RADEON_OLD) += radeonfb.o
43obj-$(CONFIG_FB_NEOMAGIC) += neofb.o vgastate.o 42obj-$(CONFIG_FB_NEOMAGIC) += neofb.o vgastate.o
44obj-$(CONFIG_FB_VIRGE) += virgefb.o 43obj-$(CONFIG_FB_VIRGE) += virgefb.o
45obj-$(CONFIG_FB_3DFX) += tdfxfb.o 44obj-$(CONFIG_FB_3DFX) += tdfxfb.o
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c
index 821c6da8e42c..f7bbff4ddc6a 100644
--- a/drivers/video/aty/aty128fb.c
+++ b/drivers/video/aty/aty128fb.c
@@ -67,6 +67,7 @@
67#include <asm/io.h> 67#include <asm/io.h>
68 68
69#ifdef CONFIG_PPC_PMAC 69#ifdef CONFIG_PPC_PMAC
70#include <asm/machdep.h>
70#include <asm/pmac_feature.h> 71#include <asm/pmac_feature.h>
71#include <asm/prom.h> 72#include <asm/prom.h>
72#include <asm/pci-bridge.h> 73#include <asm/pci-bridge.h>
@@ -1748,7 +1749,7 @@ static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *
1748 1749
1749 var = default_var; 1750 var = default_var;
1750#ifdef CONFIG_PPC_PMAC 1751#ifdef CONFIG_PPC_PMAC
1751 if (_machine == _MACH_Pmac) { 1752 if (machine_is(powermac)) {
1752 /* Indicate sleep capability */ 1753 /* Indicate sleep capability */
1753 if (par->chip_gen == rage_M3) { 1754 if (par->chip_gen == rage_M3) {
1754 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); 1755 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
@@ -2011,7 +2012,7 @@ static int aty128fb_blank(int blank, struct fb_info *fb)
2011 return 0; 2012 return 0;
2012 2013
2013#ifdef CONFIG_PMAC_BACKLIGHT 2014#ifdef CONFIG_PMAC_BACKLIGHT
2014 if ((_machine == _MACH_Pmac) && blank) 2015 if (machine_is(powermac) && blank)
2015 set_backlight_enable(0); 2016 set_backlight_enable(0);
2016#endif /* CONFIG_PMAC_BACKLIGHT */ 2017#endif /* CONFIG_PMAC_BACKLIGHT */
2017 2018
@@ -2029,7 +2030,7 @@ static int aty128fb_blank(int blank, struct fb_info *fb)
2029 aty128_set_lcd_enable(par, par->lcd_on && !blank); 2030 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2030 } 2031 }
2031#ifdef CONFIG_PMAC_BACKLIGHT 2032#ifdef CONFIG_PMAC_BACKLIGHT
2032 if ((_machine == _MACH_Pmac) && !blank) 2033 if (machine_is(powermac) && !blank)
2033 set_backlight_enable(1); 2034 set_backlight_enable(1);
2034#endif /* CONFIG_PMAC_BACKLIGHT */ 2035#endif /* CONFIG_PMAC_BACKLIGHT */
2035 return 0; 2036 return 0;
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c
index e799fcca365a..d9d7d3c4cae2 100644
--- a/drivers/video/aty/atyfb_base.c
+++ b/drivers/video/aty/atyfb_base.c
@@ -75,6 +75,7 @@
75#include "ati_ids.h" 75#include "ati_ids.h"
76 76
77#ifdef __powerpc__ 77#ifdef __powerpc__
78#include <asm/machdep.h>
78#include <asm/prom.h> 79#include <asm/prom.h>
79#include "../macmodes.h" 80#include "../macmodes.h"
80#endif 81#endif
@@ -2518,7 +2519,7 @@ static int __init aty_init(struct fb_info *info, const char *name)
2518 2519
2519 memset(&var, 0, sizeof(var)); 2520 memset(&var, 0, sizeof(var));
2520#ifdef CONFIG_PPC 2521#ifdef CONFIG_PPC
2521 if (_machine == _MACH_Pmac) { 2522 if (machine_is(powermac)) {
2522 /* 2523 /*
2523 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it 2524 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2524 * applies to all Mac video cards 2525 * applies to all Mac video cards
@@ -2673,7 +2674,7 @@ static int atyfb_blank(int blank, struct fb_info *info)
2673 return 0; 2674 return 0;
2674 2675
2675#ifdef CONFIG_PMAC_BACKLIGHT 2676#ifdef CONFIG_PMAC_BACKLIGHT
2676 if ((_machine == _MACH_Pmac) && blank > FB_BLANK_NORMAL) 2677 if (machine_is(powermac) && blank > FB_BLANK_NORMAL)
2677 set_backlight_enable(0); 2678 set_backlight_enable(0);
2678#elif defined(CONFIG_FB_ATY_GENERIC_LCD) 2679#elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2679 if (par->lcd_table && blank > FB_BLANK_NORMAL && 2680 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
@@ -2705,7 +2706,7 @@ static int atyfb_blank(int blank, struct fb_info *info)
2705 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par); 2706 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2706 2707
2707#ifdef CONFIG_PMAC_BACKLIGHT 2708#ifdef CONFIG_PMAC_BACKLIGHT
2708 if ((_machine == _MACH_Pmac) && blank <= FB_BLANK_NORMAL) 2709 if (machine_is(powermac) && blank <= FB_BLANK_NORMAL)
2709 set_backlight_enable(1); 2710 set_backlight_enable(1);
2710#elif defined(CONFIG_FB_ATY_GENERIC_LCD) 2711#elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2711 if (par->lcd_table && blank <= FB_BLANK_NORMAL && 2712 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
@@ -3399,7 +3400,7 @@ static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_devi
3399 struct atyfb_par *par; 3400 struct atyfb_par *par;
3400 int i, rc = -ENOMEM; 3401 int i, rc = -ENOMEM;
3401 3402
3402 for (i = ARRAY_SIZE(aty_chips); i >= 0; i--) 3403 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3403 if (pdev->device == aty_chips[i].pci_id) 3404 if (pdev->device == aty_chips[i].pci_id)
3404 break; 3405 break;
3405 3406
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c
index 5886a2f1323e..c7091761cef4 100644
--- a/drivers/video/aty/radeon_pm.c
+++ b/drivers/video/aty/radeon_pm.c
@@ -20,7 +20,7 @@
20#include <linux/agp_backend.h> 20#include <linux/agp_backend.h>
21 21
22#ifdef CONFIG_PPC_PMAC 22#ifdef CONFIG_PPC_PMAC
23#include <asm/processor.h> 23#include <asm/machdep.h>
24#include <asm/prom.h> 24#include <asm/prom.h>
25#include <asm/pmac_feature.h> 25#include <asm/pmac_feature.h>
26#endif 26#endif
@@ -2745,7 +2745,7 @@ void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk)
2745 rinfo->pm_mode |= radeon_pm_off; 2745 rinfo->pm_mode |= radeon_pm_off;
2746 } 2746 }
2747#if defined(CONFIG_PPC_PMAC) 2747#if defined(CONFIG_PPC_PMAC)
2748 if (_machine == _MACH_Pmac && rinfo->of_node) { 2748 if (machine_is(powermac) && rinfo->of_node) {
2749 if (rinfo->is_mobility && rinfo->pm_reg && 2749 if (rinfo->is_mobility && rinfo->pm_reg &&
2750 rinfo->family <= CHIP_FAMILY_RV250) 2750 rinfo->family <= CHIP_FAMILY_RV250)
2751 rinfo->pm_mode |= radeon_pm_d2; 2751 rinfo->pm_mode |= radeon_pm_d2;
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 9d996f2c10d5..b895eaaa73fd 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -43,11 +43,11 @@ config LCD_DEVICE
43 default y 43 default y
44 44
45config BACKLIGHT_CORGI 45config BACKLIGHT_CORGI
46 tristate "Sharp Corgi Backlight Driver (SL-C7xx Series)" 46 tristate "Sharp Corgi Backlight Driver (SL Series)"
47 depends on BACKLIGHT_DEVICE && PXA_SHARPSL 47 depends on BACKLIGHT_DEVICE && PXA_SHARPSL
48 default y 48 default y
49 help 49 help
50 If you have a Sharp Zaurus SL-C7xx, say y to enable the 50 If you have a Sharp Zaurus SL-C7xx, SL-Cxx00 or SL-6000x say y to enable the
51 backlight driver. 51 backlight driver.
52 52
53config BACKLIGHT_HP680 53config BACKLIGHT_HP680
diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c
index 151fda8dded0..334b1db1bd7c 100644
--- a/drivers/video/backlight/backlight.c
+++ b/drivers/video/backlight/backlight.c
@@ -16,14 +16,12 @@
16 16
17static ssize_t backlight_show_power(struct class_device *cdev, char *buf) 17static ssize_t backlight_show_power(struct class_device *cdev, char *buf)
18{ 18{
19 int rc; 19 int rc = -ENXIO;
20 struct backlight_device *bd = to_backlight_device(cdev); 20 struct backlight_device *bd = to_backlight_device(cdev);
21 21
22 down(&bd->sem); 22 down(&bd->sem);
23 if (likely(bd->props && bd->props->get_power)) 23 if (likely(bd->props))
24 rc = sprintf(buf, "%d\n", bd->props->get_power(bd)); 24 rc = sprintf(buf, "%d\n", bd->props->power);
25 else
26 rc = -ENXIO;
27 up(&bd->sem); 25 up(&bd->sem);
28 26
29 return rc; 27 return rc;
@@ -31,7 +29,7 @@ static ssize_t backlight_show_power(struct class_device *cdev, char *buf)
31 29
32static ssize_t backlight_store_power(struct class_device *cdev, const char *buf, size_t count) 30static ssize_t backlight_store_power(struct class_device *cdev, const char *buf, size_t count)
33{ 31{
34 int rc, power; 32 int rc = -ENXIO, power;
35 char *endp; 33 char *endp;
36 struct backlight_device *bd = to_backlight_device(cdev); 34 struct backlight_device *bd = to_backlight_device(cdev);
37 35
@@ -40,12 +38,13 @@ static ssize_t backlight_store_power(struct class_device *cdev, const char *buf,
40 return -EINVAL; 38 return -EINVAL;
41 39
42 down(&bd->sem); 40 down(&bd->sem);
43 if (likely(bd->props && bd->props->set_power)) { 41 if (likely(bd->props)) {
44 pr_debug("backlight: set power to %d\n", power); 42 pr_debug("backlight: set power to %d\n", power);
45 bd->props->set_power(bd, power); 43 bd->props->power = power;
44 if (likely(bd->props->update_status))
45 bd->props->update_status(bd);
46 rc = count; 46 rc = count;
47 } else 47 }
48 rc = -ENXIO;
49 up(&bd->sem); 48 up(&bd->sem);
50 49
51 return rc; 50 return rc;
@@ -53,14 +52,12 @@ static ssize_t backlight_store_power(struct class_device *cdev, const char *buf,
53 52
54static ssize_t backlight_show_brightness(struct class_device *cdev, char *buf) 53static ssize_t backlight_show_brightness(struct class_device *cdev, char *buf)
55{ 54{
56 int rc; 55 int rc = -ENXIO;
57 struct backlight_device *bd = to_backlight_device(cdev); 56 struct backlight_device *bd = to_backlight_device(cdev);
58 57
59 down(&bd->sem); 58 down(&bd->sem);
60 if (likely(bd->props && bd->props->get_brightness)) 59 if (likely(bd->props))
61 rc = sprintf(buf, "%d\n", bd->props->get_brightness(bd)); 60 rc = sprintf(buf, "%d\n", bd->props->brightness);
62 else
63 rc = -ENXIO;
64 up(&bd->sem); 61 up(&bd->sem);
65 62
66 return rc; 63 return rc;
@@ -68,7 +65,7 @@ static ssize_t backlight_show_brightness(struct class_device *cdev, char *buf)
68 65
69static ssize_t backlight_store_brightness(struct class_device *cdev, const char *buf, size_t count) 66static ssize_t backlight_store_brightness(struct class_device *cdev, const char *buf, size_t count)
70{ 67{
71 int rc, brightness; 68 int rc = -ENXIO, brightness;
72 char *endp; 69 char *endp;
73 struct backlight_device *bd = to_backlight_device(cdev); 70 struct backlight_device *bd = to_backlight_device(cdev);
74 71
@@ -77,12 +74,18 @@ static ssize_t backlight_store_brightness(struct class_device *cdev, const char
77 return -EINVAL; 74 return -EINVAL;
78 75
79 down(&bd->sem); 76 down(&bd->sem);
80 if (likely(bd->props && bd->props->set_brightness)) { 77 if (likely(bd->props)) {
81 pr_debug("backlight: set brightness to %d\n", brightness); 78 if (brightness > bd->props->max_brightness)
82 bd->props->set_brightness(bd, brightness); 79 rc = -EINVAL;
83 rc = count; 80 else {
84 } else 81 pr_debug("backlight: set brightness to %d\n",
85 rc = -ENXIO; 82 brightness);
83 bd->props->brightness = brightness;
84 if (likely(bd->props->update_status))
85 bd->props->update_status(bd);
86 rc = count;
87 }
88 }
86 up(&bd->sem); 89 up(&bd->sem);
87 90
88 return rc; 91 return rc;
@@ -90,14 +93,26 @@ static ssize_t backlight_store_brightness(struct class_device *cdev, const char
90 93
91static ssize_t backlight_show_max_brightness(struct class_device *cdev, char *buf) 94static ssize_t backlight_show_max_brightness(struct class_device *cdev, char *buf)
92{ 95{
93 int rc; 96 int rc = -ENXIO;
94 struct backlight_device *bd = to_backlight_device(cdev); 97 struct backlight_device *bd = to_backlight_device(cdev);
95 98
96 down(&bd->sem); 99 down(&bd->sem);
97 if (likely(bd->props)) 100 if (likely(bd->props))
98 rc = sprintf(buf, "%d\n", bd->props->max_brightness); 101 rc = sprintf(buf, "%d\n", bd->props->max_brightness);
99 else 102 up(&bd->sem);
100 rc = -ENXIO; 103
104 return rc;
105}
106
107static ssize_t backlight_show_actual_brightness(struct class_device *cdev,
108 char *buf)
109{
110 int rc = -ENXIO;
111 struct backlight_device *bd = to_backlight_device(cdev);
112
113 down(&bd->sem);
114 if (likely(bd->props && bd->props->get_brightness))
115 rc = sprintf(buf, "%d\n", bd->props->get_brightness(bd));
101 up(&bd->sem); 116 up(&bd->sem);
102 117
103 return rc; 118 return rc;
@@ -123,7 +138,10 @@ static struct class backlight_class = {
123 138
124static struct class_device_attribute bl_class_device_attributes[] = { 139static struct class_device_attribute bl_class_device_attributes[] = {
125 DECLARE_ATTR(power, 0644, backlight_show_power, backlight_store_power), 140 DECLARE_ATTR(power, 0644, backlight_show_power, backlight_store_power),
126 DECLARE_ATTR(brightness, 0644, backlight_show_brightness, backlight_store_brightness), 141 DECLARE_ATTR(brightness, 0644, backlight_show_brightness,
142 backlight_store_brightness),
143 DECLARE_ATTR(actual_brightness, 0444, backlight_show_actual_brightness,
144 NULL),
127 DECLARE_ATTR(max_brightness, 0444, backlight_show_max_brightness, NULL), 145 DECLARE_ATTR(max_brightness, 0444, backlight_show_max_brightness, NULL),
128}; 146};
129 147
@@ -144,8 +162,12 @@ static int fb_notifier_callback(struct notifier_block *self,
144 bd = container_of(self, struct backlight_device, fb_notif); 162 bd = container_of(self, struct backlight_device, fb_notif);
145 down(&bd->sem); 163 down(&bd->sem);
146 if (bd->props) 164 if (bd->props)
147 if (!bd->props->check_fb || bd->props->check_fb(evdata->info)) 165 if (!bd->props->check_fb ||
148 bd->props->set_power(bd, *(int *)evdata->data); 166 bd->props->check_fb(evdata->info)) {
167 bd->props->fb_blank = *(int *)evdata->data;
168 if (likely(bd->props && bd->props->update_status))
169 bd->props->update_status(bd);
170 }
149 up(&bd->sem); 171 up(&bd->sem);
150 return 0; 172 return 0;
151} 173}
@@ -231,6 +253,12 @@ void backlight_device_unregister(struct backlight_device *bd)
231 &bl_class_device_attributes[i]); 253 &bl_class_device_attributes[i]);
232 254
233 down(&bd->sem); 255 down(&bd->sem);
256 if (likely(bd->props && bd->props->update_status)) {
257 bd->props->brightness = 0;
258 bd->props->power = 0;
259 bd->props->update_status(bd);
260 }
261
234 bd->props = NULL; 262 bd->props = NULL;
235 up(&bd->sem); 263 up(&bd->sem);
236 264
diff --git a/drivers/video/backlight/corgi_bl.c b/drivers/video/backlight/corgi_bl.c
index d0aaf450e8c7..2ebbfd95145f 100644
--- a/drivers/video/backlight/corgi_bl.c
+++ b/drivers/video/backlight/corgi_bl.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Backlight Driver for Sharp Corgi 2 * Backlight Driver for Sharp Zaurus Handhelds (various models)
3 * 3 *
4 * Copyright (c) 2004-2005 Richard Purdie 4 * Copyright (c) 2004-2006 Richard Purdie
5 * 5 *
6 * Based on Sharp's 2.4 Backlight Driver 6 * Based on Sharp's 2.4 Backlight Driver
7 * 7 *
@@ -15,80 +15,63 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/spinlock.h> 18#include <linux/mutex.h>
19#include <linux/fb.h> 19#include <linux/fb.h>
20#include <linux/backlight.h> 20#include <linux/backlight.h>
21
22#include <asm/arch/sharpsl.h> 21#include <asm/arch/sharpsl.h>
23#include <asm/hardware/sharpsl_pm.h> 22#include <asm/hardware/sharpsl_pm.h>
24 23
25#define CORGI_DEFAULT_INTENSITY 0x1f 24static int corgibl_intensity;
26#define CORGI_LIMIT_MASK 0x0b 25static DEFINE_MUTEX(bl_mutex);
27
28static int corgibl_powermode = FB_BLANK_UNBLANK;
29static int current_intensity = 0;
30static int corgibl_limit = 0;
31static void (*corgibl_mach_set_intensity)(int intensity);
32static spinlock_t bl_lock = SPIN_LOCK_UNLOCKED;
33static struct backlight_properties corgibl_data; 26static struct backlight_properties corgibl_data;
27static struct backlight_device *corgi_backlight_device;
28static struct corgibl_machinfo *bl_machinfo;
34 29
35static void corgibl_send_intensity(int intensity) 30static unsigned long corgibl_flags;
31#define CORGIBL_SUSPENDED 0x01
32#define CORGIBL_BATTLOW 0x02
33
34static int corgibl_send_intensity(struct backlight_device *bd)
36{ 35{
37 unsigned long flags;
38 void (*corgi_kick_batt)(void); 36 void (*corgi_kick_batt)(void);
37 int intensity = bd->props->brightness;
39 38
40 if (corgibl_powermode != FB_BLANK_UNBLANK) { 39 if (bd->props->power != FB_BLANK_UNBLANK)
41 intensity = 0; 40 intensity = 0;
42 } else { 41 if (bd->props->fb_blank != FB_BLANK_UNBLANK)
43 if (corgibl_limit) 42 intensity = 0;
44 intensity &= CORGI_LIMIT_MASK; 43 if (corgibl_flags & CORGIBL_SUSPENDED)
45 } 44 intensity = 0;
46 45 if (corgibl_flags & CORGIBL_BATTLOW)
47 spin_lock_irqsave(&bl_lock, flags); 46 intensity &= bl_machinfo->limit_mask;
48 47
49 corgibl_mach_set_intensity(intensity); 48 mutex_lock(&bl_mutex);
49 bl_machinfo->set_bl_intensity(intensity);
50 mutex_unlock(&bl_mutex);
50 51
51 spin_unlock_irqrestore(&bl_lock, flags); 52 corgibl_intensity = intensity;
52 53
53 corgi_kick_batt = symbol_get(sharpsl_battery_kick); 54 corgi_kick_batt = symbol_get(sharpsl_battery_kick);
54 if (corgi_kick_batt) { 55 if (corgi_kick_batt) {
55 corgi_kick_batt(); 56 corgi_kick_batt();
56 symbol_put(sharpsl_battery_kick); 57 symbol_put(sharpsl_battery_kick);
57 } 58 }
58}
59 59
60static void corgibl_blank(int blank) 60 return 0;
61{
62 switch(blank) {
63
64 case FB_BLANK_NORMAL:
65 case FB_BLANK_VSYNC_SUSPEND:
66 case FB_BLANK_HSYNC_SUSPEND:
67 case FB_BLANK_POWERDOWN:
68 if (corgibl_powermode == FB_BLANK_UNBLANK) {
69 corgibl_send_intensity(0);
70 corgibl_powermode = blank;
71 }
72 break;
73 case FB_BLANK_UNBLANK:
74 if (corgibl_powermode != FB_BLANK_UNBLANK) {
75 corgibl_powermode = blank;
76 corgibl_send_intensity(current_intensity);
77 }
78 break;
79 }
80} 61}
81 62
82#ifdef CONFIG_PM 63#ifdef CONFIG_PM
83static int corgibl_suspend(struct platform_device *dev, pm_message_t state) 64static int corgibl_suspend(struct platform_device *dev, pm_message_t state)
84{ 65{
85 corgibl_blank(FB_BLANK_POWERDOWN); 66 corgibl_flags |= CORGIBL_SUSPENDED;
67 corgibl_send_intensity(corgi_backlight_device);
86 return 0; 68 return 0;
87} 69}
88 70
89static int corgibl_resume(struct platform_device *dev) 71static int corgibl_resume(struct platform_device *dev)
90{ 72{
91 corgibl_blank(FB_BLANK_UNBLANK); 73 corgibl_flags &= ~CORGIBL_SUSPENDED;
74 corgibl_send_intensity(corgi_backlight_device);
92 return 0; 75 return 0;
93} 76}
94#else 77#else
@@ -96,68 +79,55 @@ static int corgibl_resume(struct platform_device *dev)
96#define corgibl_resume NULL 79#define corgibl_resume NULL
97#endif 80#endif
98 81
99 82static int corgibl_get_intensity(struct backlight_device *bd)
100static int corgibl_set_power(struct backlight_device *bd, int state)
101{
102 corgibl_blank(state);
103 return 0;
104}
105
106static int corgibl_get_power(struct backlight_device *bd)
107{ 83{
108 return corgibl_powermode; 84 return corgibl_intensity;
109} 85}
110 86
111static int corgibl_set_intensity(struct backlight_device *bd, int intensity) 87static int corgibl_set_intensity(struct backlight_device *bd)
112{ 88{
113 if (intensity > corgibl_data.max_brightness) 89 corgibl_send_intensity(corgi_backlight_device);
114 intensity = corgibl_data.max_brightness;
115 corgibl_send_intensity(intensity);
116 current_intensity=intensity;
117 return 0; 90 return 0;
118} 91}
119 92
120static int corgibl_get_intensity(struct backlight_device *bd)
121{
122 return current_intensity;
123}
124
125/* 93/*
126 * Called when the battery is low to limit the backlight intensity. 94 * Called when the battery is low to limit the backlight intensity.
127 * If limit==0 clear any limit, otherwise limit the intensity 95 * If limit==0 clear any limit, otherwise limit the intensity
128 */ 96 */
129void corgibl_limit_intensity(int limit) 97void corgibl_limit_intensity(int limit)
130{ 98{
131 corgibl_limit = (limit ? 1 : 0); 99 if (limit)
132 corgibl_send_intensity(current_intensity); 100 corgibl_flags |= CORGIBL_BATTLOW;
101 else
102 corgibl_flags &= ~CORGIBL_BATTLOW;
103 corgibl_send_intensity(corgi_backlight_device);
133} 104}
134EXPORT_SYMBOL(corgibl_limit_intensity); 105EXPORT_SYMBOL(corgibl_limit_intensity);
135 106
136 107
137static struct backlight_properties corgibl_data = { 108static struct backlight_properties corgibl_data = {
138 .owner = THIS_MODULE, 109 .owner = THIS_MODULE,
139 .get_power = corgibl_get_power,
140 .set_power = corgibl_set_power,
141 .get_brightness = corgibl_get_intensity, 110 .get_brightness = corgibl_get_intensity,
142 .set_brightness = corgibl_set_intensity, 111 .update_status = corgibl_set_intensity,
143}; 112};
144 113
145static struct backlight_device *corgi_backlight_device;
146
147static int __init corgibl_probe(struct platform_device *pdev) 114static int __init corgibl_probe(struct platform_device *pdev)
148{ 115{
149 struct corgibl_machinfo *machinfo = pdev->dev.platform_data; 116 struct corgibl_machinfo *machinfo = pdev->dev.platform_data;
150 117
118 bl_machinfo = machinfo;
151 corgibl_data.max_brightness = machinfo->max_intensity; 119 corgibl_data.max_brightness = machinfo->max_intensity;
152 corgibl_mach_set_intensity = machinfo->set_bl_intensity; 120 if (!machinfo->limit_mask)
121 machinfo->limit_mask = -1;
153 122
154 corgi_backlight_device = backlight_device_register ("corgi-bl", 123 corgi_backlight_device = backlight_device_register ("corgi-bl",
155 NULL, &corgibl_data); 124 NULL, &corgibl_data);
156 if (IS_ERR (corgi_backlight_device)) 125 if (IS_ERR (corgi_backlight_device))
157 return PTR_ERR (corgi_backlight_device); 126 return PTR_ERR (corgi_backlight_device);
158 127
159 corgibl_set_intensity(NULL, CORGI_DEFAULT_INTENSITY); 128 corgibl_data.power = FB_BLANK_UNBLANK;
160 corgibl_limit_intensity(0); 129 corgibl_data.brightness = machinfo->default_intensity;
130 corgibl_send_intensity(corgi_backlight_device);
161 131
162 printk("Corgi Backlight Driver Initialized.\n"); 132 printk("Corgi Backlight Driver Initialized.\n");
163 return 0; 133 return 0;
@@ -167,8 +137,6 @@ static int corgibl_remove(struct platform_device *dev)
167{ 137{
168 backlight_device_unregister(corgi_backlight_device); 138 backlight_device_unregister(corgi_backlight_device);
169 139
170 corgibl_set_intensity(NULL, 0);
171
172 printk("Corgi Backlight Driver Unloaded\n"); 140 printk("Corgi Backlight Driver Unloaded\n");
173 return 0; 141 return 0;
174} 142}
diff --git a/drivers/video/backlight/hp680_bl.c b/drivers/video/backlight/hp680_bl.c
index 95da4c9ed1f1..a71e984c93d4 100644
--- a/drivers/video/backlight/hp680_bl.c
+++ b/drivers/video/backlight/hp680_bl.c
@@ -13,7 +13,7 @@
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/device.h> 16#include <linux/platform_device.h>
17#include <linux/spinlock.h> 17#include <linux/spinlock.h>
18#include <linux/fb.h> 18#include <linux/fb.h>
19#include <linux/backlight.h> 19#include <linux/backlight.h>
@@ -25,66 +25,58 @@
25#define HP680_MAX_INTENSITY 255 25#define HP680_MAX_INTENSITY 255
26#define HP680_DEFAULT_INTENSITY 10 26#define HP680_DEFAULT_INTENSITY 10
27 27
28static int hp680bl_powermode = FB_BLANK_UNBLANK; 28static int hp680bl_suspended;
29static int current_intensity = 0; 29static int current_intensity = 0;
30static spinlock_t bl_lock = SPIN_LOCK_UNLOCKED; 30static spinlock_t bl_lock = SPIN_LOCK_UNLOCKED;
31static struct backlight_device *hp680_backlight_device;
31 32
32static void hp680bl_send_intensity(int intensity) 33static void hp680bl_send_intensity(struct backlight_device *bd)
33{ 34{
34 unsigned long flags; 35 unsigned long flags;
36 u16 v;
37 int intensity = bd->props->brightness;
35 38
36 if (hp680bl_powermode != FB_BLANK_UNBLANK) 39 if (bd->props->power != FB_BLANK_UNBLANK)
40 intensity = 0;
41 if (bd->props->fb_blank != FB_BLANK_UNBLANK)
42 intensity = 0;
43 if (hp680bl_suspended)
37 intensity = 0; 44 intensity = 0;
38 45
39 spin_lock_irqsave(&bl_lock, flags); 46 spin_lock_irqsave(&bl_lock, flags);
40 sh_dac_output(255-(u8)intensity, DAC_LCD_BRIGHTNESS); 47 if (intensity && current_intensity == 0) {
48 sh_dac_enable(DAC_LCD_BRIGHTNESS);
49 v = inw(HD64461_GPBDR);
50 v &= ~HD64461_GPBDR_LCDOFF;
51 outw(v, HD64461_GPBDR);
52 sh_dac_output(255-(u8)intensity, DAC_LCD_BRIGHTNESS);
53 } else if (intensity == 0 && current_intensity != 0) {
54 sh_dac_output(255-(u8)intensity, DAC_LCD_BRIGHTNESS);
55 sh_dac_disable(DAC_LCD_BRIGHTNESS);
56 v = inw(HD64461_GPBDR);
57 v |= HD64461_GPBDR_LCDOFF;
58 outw(v, HD64461_GPBDR);
59 } else if (intensity) {
60 sh_dac_output(255-(u8)intensity, DAC_LCD_BRIGHTNESS);
61 }
41 spin_unlock_irqrestore(&bl_lock, flags); 62 spin_unlock_irqrestore(&bl_lock, flags);
42}
43 63
44static void hp680bl_blank(int blank) 64 current_intensity = intensity;
45{
46 u16 v;
47
48 switch(blank) {
49
50 case FB_BLANK_NORMAL:
51 case FB_BLANK_VSYNC_SUSPEND:
52 case FB_BLANK_HSYNC_SUSPEND:
53 case FB_BLANK_POWERDOWN:
54 if (hp680bl_powermode == FB_BLANK_UNBLANK) {
55 hp680bl_send_intensity(0);
56 hp680bl_powermode = blank;
57 sh_dac_disable(DAC_LCD_BRIGHTNESS);
58 v = inw(HD64461_GPBDR);
59 v |= HD64461_GPBDR_LCDOFF;
60 outw(v, HD64461_GPBDR);
61 }
62 break;
63 case FB_BLANK_UNBLANK:
64 if (hp680bl_powermode != FB_BLANK_UNBLANK) {
65 sh_dac_enable(DAC_LCD_BRIGHTNESS);
66 v = inw(HD64461_GPBDR);
67 v &= ~HD64461_GPBDR_LCDOFF;
68 outw(v, HD64461_GPBDR);
69 hp680bl_powermode = blank;
70 hp680bl_send_intensity(current_intensity);
71 }
72 break;
73 }
74} 65}
75 66
67
76#ifdef CONFIG_PM 68#ifdef CONFIG_PM
77static int hp680bl_suspend(struct device *dev, pm_message_t state, u32 level) 69static int hp680bl_suspend(struct platform_device *dev, pm_message_t state)
78{ 70{
79 if (level == SUSPEND_POWER_DOWN) 71 hp680bl_suspended = 1;
80 hp680bl_blank(FB_BLANK_POWERDOWN); 72 hp680bl_send_intensity(hp680_backlight_device);
81 return 0; 73 return 0;
82} 74}
83 75
84static int hp680bl_resume(struct device *dev, u32 level) 76static int hp680bl_resume(struct platform_device *dev)
85{ 77{
86 if (level == RESUME_POWER_ON) 78 hp680bl_suspended = 0;
87 hp680bl_blank(FB_BLANK_UNBLANK); 79 hp680bl_send_intensity(hp680_backlight_device);
88 return 0; 80 return 0;
89} 81}
90#else 82#else
@@ -92,24 +84,9 @@ static int hp680bl_resume(struct device *dev, u32 level)
92#define hp680bl_resume NULL 84#define hp680bl_resume NULL
93#endif 85#endif
94 86
95 87static int hp680bl_set_intensity(struct backlight_device *bd)
96static int hp680bl_set_power(struct backlight_device *bd, int state)
97{ 88{
98 hp680bl_blank(state); 89 hp680bl_send_intensity(bd);
99 return 0;
100}
101
102static int hp680bl_get_power(struct backlight_device *bd)
103{
104 return hp680bl_powermode;
105}
106
107static int hp680bl_set_intensity(struct backlight_device *bd, int intensity)
108{
109 if (intensity > HP680_MAX_INTENSITY)
110 intensity = HP680_MAX_INTENSITY;
111 hp680bl_send_intensity(intensity);
112 current_intensity = intensity;
113 return 0; 90 return 0;
114} 91}
115 92
@@ -120,65 +97,67 @@ static int hp680bl_get_intensity(struct backlight_device *bd)
120 97
121static struct backlight_properties hp680bl_data = { 98static struct backlight_properties hp680bl_data = {
122 .owner = THIS_MODULE, 99 .owner = THIS_MODULE,
123 .get_power = hp680bl_get_power,
124 .set_power = hp680bl_set_power,
125 .max_brightness = HP680_MAX_INTENSITY, 100 .max_brightness = HP680_MAX_INTENSITY,
126 .get_brightness = hp680bl_get_intensity, 101 .get_brightness = hp680bl_get_intensity,
127 .set_brightness = hp680bl_set_intensity, 102 .update_status = hp680bl_set_intensity,
128}; 103};
129 104
130static struct backlight_device *hp680_backlight_device; 105static int __init hp680bl_probe(struct platform_device *dev)
131
132static int __init hp680bl_probe(struct device *dev)
133{ 106{
134 hp680_backlight_device = backlight_device_register ("hp680-bl", 107 hp680_backlight_device = backlight_device_register ("hp680-bl",
135 NULL, &hp680bl_data); 108 NULL, &hp680bl_data);
136 if (IS_ERR (hp680_backlight_device)) 109 if (IS_ERR (hp680_backlight_device))
137 return PTR_ERR (hp680_backlight_device); 110 return PTR_ERR (hp680_backlight_device);
138 111
139 hp680bl_set_intensity(NULL, HP680_DEFAULT_INTENSITY); 112 hp680_backlight_device->props->brightness = HP680_DEFAULT_INTENSITY;
113 hp680bl_send_intensity(hp680_backlight_device);
140 114
141 return 0; 115 return 0;
142} 116}
143 117
144static int hp680bl_remove(struct device *dev) 118static int hp680bl_remove(struct platform_device *dev)
145{ 119{
146 backlight_device_unregister(hp680_backlight_device); 120 backlight_device_unregister(hp680_backlight_device);
147 121
148 return 0; 122 return 0;
149} 123}
150 124
151static struct device_driver hp680bl_driver = { 125static struct platform_driver hp680bl_driver = {
152 .name = "hp680-bl",
153 .bus = &platform_bus_type,
154 .probe = hp680bl_probe, 126 .probe = hp680bl_probe,
155 .remove = hp680bl_remove, 127 .remove = hp680bl_remove,
156 .suspend = hp680bl_suspend, 128 .suspend = hp680bl_suspend,
157 .resume = hp680bl_resume, 129 .resume = hp680bl_resume,
130 .driver = {
131 .name = "hp680-bl",
132 },
158}; 133};
159 134
160static struct platform_device hp680bl_device = { 135static struct platform_device *hp680bl_device;
161 .name = "hp680-bl",
162 .id = -1,
163};
164 136
165static int __init hp680bl_init(void) 137static int __init hp680bl_init(void)
166{ 138{
167 int ret; 139 int ret;
168 140
169 ret=driver_register(&hp680bl_driver); 141 ret = platform_driver_register(&hp680bl_driver);
170 if (!ret) { 142 if (!ret) {
171 ret = platform_device_register(&hp680bl_device); 143 hp680bl_device = platform_device_alloc("hp680-bl", -1);
172 if (ret) 144 if (!hp680bl_device)
173 driver_unregister(&hp680bl_driver); 145 return -ENOMEM;
146
147 ret = platform_device_add(hp680bl_device);
148
149 if (ret) {
150 platform_device_put(hp680bl_device);
151 platform_driver_unregister(&hp680bl_driver);
152 }
174 } 153 }
175 return ret; 154 return ret;
176} 155}
177 156
178static void __exit hp680bl_exit(void) 157static void __exit hp680bl_exit(void)
179{ 158{
180 platform_device_unregister(&hp680bl_device); 159 platform_device_unregister(hp680bl_device);
181 driver_unregister(&hp680bl_driver); 160 platform_driver_unregister(&hp680bl_driver);
182} 161}
183 162
184module_init(hp680bl_init); 163module_init(hp680bl_init);
diff --git a/drivers/video/cfbimgblt.c b/drivers/video/cfbimgblt.c
index 910e2338a27e..8ba6152db2fd 100644
--- a/drivers/video/cfbimgblt.c
+++ b/drivers/video/cfbimgblt.c
@@ -169,7 +169,7 @@ static inline void slow_imageblit(const struct fb_image *image, struct fb_info *
169 169
170 while (j--) { 170 while (j--) {
171 l--; 171 l--;
172 color = (*s & 1 << (FB_BIT_NR(l))) ? fgcolor : bgcolor; 172 color = (*s & (1 << l)) ? fgcolor : bgcolor;
173 val |= FB_SHIFT_HIGH(color, shift); 173 val |= FB_SHIFT_HIGH(color, shift);
174 174
175 /* Did the bitshift spill bits to the next long? */ 175 /* Did the bitshift spill bits to the next long? */
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c
index 66d6f2f0a219..1103010af54a 100644
--- a/drivers/video/cirrusfb.c
+++ b/drivers/video/cirrusfb.c
@@ -60,8 +60,8 @@
60#include <asm/amigahw.h> 60#include <asm/amigahw.h>
61#endif 61#endif
62#ifdef CONFIG_PPC_PREP 62#ifdef CONFIG_PPC_PREP
63#include <asm/processor.h> 63#include <asm/machdep.h>
64#define isPReP (_machine == _MACH_prep) 64#define isPReP (machine_is(prep))
65#else 65#else
66#define isPReP 0 66#define isPReP 0
67#endif 67#endif
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index 041d06987861..ca020719d20b 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -466,7 +466,7 @@ static int __init fb_console_setup(char *this_opt)
466 int i, j; 466 int i, j;
467 467
468 if (!this_opt || !*this_opt) 468 if (!this_opt || !*this_opt)
469 return 0; 469 return 1;
470 470
471 while ((options = strsep(&this_opt, ",")) != NULL) { 471 while ((options = strsep(&this_opt, ",")) != NULL) {
472 if (!strncmp(options, "font:", 5)) 472 if (!strncmp(options, "font:", 5))
@@ -481,10 +481,10 @@ static int __init fb_console_setup(char *this_opt)
481 options++; 481 options++;
482 } 482 }
483 if (*options != ',') 483 if (*options != ',')
484 return 0; 484 return 1;
485 options++; 485 options++;
486 } else 486 } else
487 return 0; 487 return 1;
488 } 488 }
489 489
490 if (!strncmp(options, "map:", 4)) { 490 if (!strncmp(options, "map:", 4)) {
@@ -496,7 +496,7 @@ static int __init fb_console_setup(char *this_opt)
496 con2fb_map_boot[i] = 496 con2fb_map_boot[i] =
497 (options[j++]-'0') % FB_MAX; 497 (options[j++]-'0') % FB_MAX;
498 } 498 }
499 return 0; 499 return 1;
500 } 500 }
501 501
502 if (!strncmp(options, "vc:", 3)) { 502 if (!strncmp(options, "vc:", 3)) {
@@ -518,7 +518,7 @@ static int __init fb_console_setup(char *this_opt)
518 rotate = 0; 518 rotate = 0;
519 } 519 }
520 } 520 }
521 return 0; 521 return 1;
522} 522}
523 523
524__setup("fbcon=", fb_console_setup); 524__setup("fbcon=", fb_console_setup);
@@ -1142,6 +1142,7 @@ static void fbcon_init(struct vc_data *vc, int init)
1142 set_blitting_type(vc, info); 1142 set_blitting_type(vc, info);
1143 } 1143 }
1144 1144
1145 ops->p = &fb_display[fg_console];
1145} 1146}
1146 1147
1147static void fbcon_deinit(struct vc_data *vc) 1148static void fbcon_deinit(struct vc_data *vc)
diff --git a/drivers/video/console/sticore.c b/drivers/video/console/sticore.c
index 0339f5640a78..74ac2acaf72c 100644
--- a/drivers/video/console/sticore.c
+++ b/drivers/video/console/sticore.c
@@ -275,7 +275,7 @@ static int __init sti_setup(char *str)
275 if (str) 275 if (str)
276 strlcpy (default_sti_path, str, sizeof (default_sti_path)); 276 strlcpy (default_sti_path, str, sizeof (default_sti_path));
277 277
278 return 0; 278 return 1;
279} 279}
280 280
281/* Assuming the machine has multiple STI consoles (=graphic cards) which 281/* Assuming the machine has multiple STI consoles (=graphic cards) which
@@ -321,7 +321,7 @@ static int __init sti_font_setup(char *str)
321 i++; 321 i++;
322 } 322 }
323 323
324 return 0; 324 return 1;
325} 325}
326 326
327/* The optional linux kernel parameter "sti_font" defines which font 327/* The optional linux kernel parameter "sti_font" defines which font
@@ -373,7 +373,7 @@ sti_dump_globcfg(struct sti_glob_cfg *glob_cfg, unsigned int sti_mem_request)
373 glob_cfg->save_addr)); 373 glob_cfg->save_addr));
374 374
375 /* dump extended cfg */ 375 /* dump extended cfg */
376 cfg = PTR_STI(glob_cfg->ext_ptr); 376 cfg = PTR_STI((unsigned long)glob_cfg->ext_ptr);
377 DPRINTK(( KERN_INFO 377 DPRINTK(( KERN_INFO
378 "monitor %d\n" 378 "monitor %d\n"
379 "in friendly mode: %d\n" 379 "in friendly mode: %d\n"
@@ -453,25 +453,11 @@ sti_init_glob_cfg(struct sti_struct *sti,
453 sti->regions_phys[i] = 453 sti->regions_phys[i] =
454 REGION_OFFSET_TO_PHYS(sti->regions[i], newhpa); 454 REGION_OFFSET_TO_PHYS(sti->regions[i], newhpa);
455 455
456 /* remap virtually */
457 /* FIXME: add BTLB support if btlb==1 */
458 len = sti->regions[i].region_desc.length * 4096; 456 len = sti->regions[i].region_desc.length * 4096;
459
460/* XXX: Enabling IOREMAP debugging causes a crash, so we must be passing
461 * a virtual address to something expecting a physical address that doesn't
462 * go through a readX macro */
463#if 0
464 if (len)
465 glob_cfg->region_ptrs[i] = (unsigned long) (
466 sti->regions[i].region_desc.cache ?
467 ioremap(sti->regions_phys[i], len) :
468 ioremap_nocache(sti->regions_phys[i], len) );
469#else
470 if (len) 457 if (len)
471 glob_cfg->region_ptrs[i] = sti->regions_phys[i]; 458 glob_cfg->region_ptrs[i] = sti->regions_phys[i];
472#endif
473 459
474 DPRINTK(("region #%d: phys %08lx, virt %08x, len=%lukB, " 460 DPRINTK(("region #%d: phys %08lx, region_ptr %08x, len=%lukB, "
475 "btlb=%d, sysonly=%d, cache=%d, last=%d\n", 461 "btlb=%d, sysonly=%d, cache=%d, last=%d\n",
476 i, sti->regions_phys[i], glob_cfg->region_ptrs[i], 462 i, sti->regions_phys[i], glob_cfg->region_ptrs[i],
477 len/1024, 463 len/1024,
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index b1a8dca76430..8d8eadb64853 100644
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -435,6 +435,11 @@ int fb_prepare_logo(struct fb_info *info, int rotate)
435 depth = info->var.green.length; 435 depth = info->var.green.length;
436 } 436 }
437 437
438 if (info->fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) {
439 /* assume console colormap */
440 depth = 4;
441 }
442
438 if (depth >= 8) { 443 if (depth >= 8) {
439 switch (info->fix.visual) { 444 switch (info->fix.visual) {
440 case FB_VISUAL_TRUECOLOR: 445 case FB_VISUAL_TRUECOLOR:
@@ -1588,7 +1593,7 @@ static int __init video_setup(char *options)
1588 } 1593 }
1589 } 1594 }
1590 1595
1591 return 0; 1596 return 1;
1592} 1597}
1593__setup("video=", video_setup); 1598__setup("video=", video_setup);
1594#endif 1599#endif
diff --git a/drivers/video/matrox/matroxfb_base.c b/drivers/video/matrox/matroxfb_base.c
index 951c9974a1d3..23c1827b2d0b 100644
--- a/drivers/video/matrox/matroxfb_base.c
+++ b/drivers/video/matrox/matroxfb_base.c
@@ -115,6 +115,7 @@
115#include <asm/uaccess.h> 115#include <asm/uaccess.h>
116 116
117#ifdef CONFIG_PPC_PMAC 117#ifdef CONFIG_PPC_PMAC
118#include <asm/machdep.h>
118unsigned char nvram_read_byte(int); 119unsigned char nvram_read_byte(int);
119static int default_vmode = VMODE_NVRAM; 120static int default_vmode = VMODE_NVRAM;
120static int default_cmode = CMODE_NVRAM; 121static int default_cmode = CMODE_NVRAM;
@@ -1833,7 +1834,7 @@ static int initMatrox2(WPMINFO struct board* b){
1833 /* FIXME: Where to move this?! */ 1834 /* FIXME: Where to move this?! */
1834#if defined(CONFIG_PPC_PMAC) 1835#if defined(CONFIG_PPC_PMAC)
1835#ifndef MODULE 1836#ifndef MODULE
1836 if (_machine == _MACH_Pmac) { 1837 if (machine_is(powermac)) {
1837 struct fb_var_screeninfo var; 1838 struct fb_var_screeninfo var;
1838 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 1839 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1839 default_vmode = VMODE_640_480_60; 1840 default_vmode = VMODE_640_480_60;
diff --git a/drivers/video/nvidia/nvidia.c b/drivers/video/nvidia/nvidia.c
index 6d3e4890cb43..093ab9977c7c 100644
--- a/drivers/video/nvidia/nvidia.c
+++ b/drivers/video/nvidia/nvidia.c
@@ -30,6 +30,7 @@
30#include <asm/pci-bridge.h> 30#include <asm/pci-bridge.h>
31#endif 31#endif
32#ifdef CONFIG_PMAC_BACKLIGHT 32#ifdef CONFIG_PMAC_BACKLIGHT
33#include <asm/machdep.h>
33#include <asm/backlight.h> 34#include <asm/backlight.h>
34#endif 35#endif
35 36
@@ -1355,7 +1356,7 @@ static int nvidiafb_blank(int blank, struct fb_info *info)
1355 NVWriteCrtc(par, 0x1a, vesa); 1356 NVWriteCrtc(par, 0x1a, vesa);
1356 1357
1357#ifdef CONFIG_PMAC_BACKLIGHT 1358#ifdef CONFIG_PMAC_BACKLIGHT
1358 if (par->FlatPanel && _machine == _MACH_Pmac) { 1359 if (par->FlatPanel && machine_is(powermac)) {
1359 set_backlight_enable(!blank); 1360 set_backlight_enable(!blank);
1360 } 1361 }
1361#endif 1362#endif
@@ -1741,7 +1742,7 @@ static int __devinit nvidiafb_probe(struct pci_dev *pd,
1741 info->fix.id, 1742 info->fix.id,
1742 par->FbMapSize / (1024 * 1024), info->fix.smem_start); 1743 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1743#ifdef CONFIG_PMAC_BACKLIGHT 1744#ifdef CONFIG_PMAC_BACKLIGHT
1744 if (par->FlatPanel && _machine == _MACH_Pmac) 1745 if (par->FlatPanel && machine_is(powermac))
1745 register_backlight_controller(&nvidia_backlight_controller, 1746 register_backlight_controller(&nvidia_backlight_controller,
1746 par, "mnca"); 1747 par, "mnca");
1747#endif 1748#endif
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 53ad61f1038c..809fc5eefc15 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -232,9 +232,9 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
232 if (var->yres < MIN_YRES) 232 if (var->yres < MIN_YRES)
233 var->yres = MIN_YRES; 233 var->yres = MIN_YRES;
234 if (var->xres > fbi->max_xres) 234 if (var->xres > fbi->max_xres)
235 var->xres = fbi->max_xres; 235 return -EINVAL;
236 if (var->yres > fbi->max_yres) 236 if (var->yres > fbi->max_yres)
237 var->yres = fbi->max_yres; 237 return -EINVAL;
238 var->xres_virtual = 238 var->xres_virtual =
239 max(var->xres_virtual, var->xres); 239 max(var->xres_virtual, var->xres);
240 var->yres_virtual = 240 var->yres_virtual =
@@ -781,7 +781,7 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
781 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ 781 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
782 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */ 782 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
783 783
784 schedule_timeout(20 * HZ / 1000); 784 schedule_timeout(200 * HZ / 1000);
785 remove_wait_queue(&fbi->ctrlr_wait, &wait); 785 remove_wait_queue(&fbi->ctrlr_wait, &wait);
786 786
787 /* disable LCD controller clock */ 787 /* disable LCD controller clock */
@@ -1274,7 +1274,7 @@ int __init pxafb_probe(struct platform_device *dev)
1274 struct pxafb_mach_info *inf; 1274 struct pxafb_mach_info *inf;
1275 int ret; 1275 int ret;
1276 1276
1277 dev_dbg(dev, "pxafb_probe\n"); 1277 dev_dbg(&dev->dev, "pxafb_probe\n");
1278 1278
1279 inf = dev->dev.platform_data; 1279 inf = dev->dev.platform_data;
1280 ret = -ENOMEM; 1280 ret = -ENOMEM;
diff --git a/drivers/video/radeonfb.c b/drivers/video/radeonfb.c
deleted file mode 100644
index 24982adb3aa2..000000000000
--- a/drivers/video/radeonfb.c
+++ /dev/null
@@ -1,3167 +0,0 @@
1/*
2 * drivers/video/radeonfb.c
3 * framebuffer driver for ATI Radeon chipset video boards
4 *
5 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
6 *
7 *
8 * ChangeLog:
9 * 2000-08-03 initial version 0.0.1
10 * 2000-09-10 more bug fixes, public release 0.0.5
11 * 2001-02-19 mode bug fixes, 0.0.7
12 * 2001-07-05 fixed scrolling issues, engine initialization,
13 * and minor mode tweaking, 0.0.9
14 * 2001-09-07 Radeon VE support, Nick Kurshev
15 * blanking, pan_display, and cmap fixes, 0.1.0
16 * 2001-10-10 Radeon 7500 and 8500 support, and experimental
17 * flat panel support, 0.1.1
18 * 2001-11-17 Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
19 * 2001-11-18 DFP fixes, Kevin Hendricks, 0.1.3
20 * 2001-11-29 more cmap, backlight fixes, Benjamin Herrenschmidt
21 * 2002-01-18 DFP panel detection via BIOS, Michael Clark, 0.1.4
22 * 2002-06-02 console switching, mode set fixes, accel fixes
23 * 2002-06-03 MTRR support, Peter Horton, 0.1.5
24 * 2002-09-21 rv250, r300, m9 initial support,
25 * added mirror option, 0.1.6
26 *
27 * Special thanks to ATI DevRel team for their hardware donations.
28 *
29 */
30
31
32#define RADEON_VERSION "0.1.6"
33
34
35#include <linux/config.h>
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/errno.h>
39#include <linux/string.h>
40#include <linux/mm.h>
41#include <linux/tty.h>
42#include <linux/slab.h>
43#include <linux/delay.h>
44#include <linux/fb.h>
45#include <linux/ioport.h>
46#include <linux/init.h>
47#include <linux/pci.h>
48#include <linux/vmalloc.h>
49
50#include <asm/io.h>
51#include <asm/uaccess.h>
52#if defined(__powerpc__)
53#include <asm/prom.h>
54#include <asm/pci-bridge.h>
55#include "macmodes.h"
56
57#ifdef CONFIG_NVRAM
58#include <linux/nvram.h>
59#endif
60
61#ifdef CONFIG_PMAC_BACKLIGHT
62#include <asm/backlight.h>
63#endif
64
65#ifdef CONFIG_BOOTX_TEXT
66#include <asm/btext.h>
67#endif
68
69#ifdef CONFIG_ADB_PMU
70#include <linux/adb.h>
71#include <linux/pmu.h>
72#endif
73
74#endif /* __powerpc__ */
75
76#ifdef CONFIG_MTRR
77#include <asm/mtrr.h>
78#endif
79
80#include <video/radeon.h>
81#include <linux/radeonfb.h>
82
83#define DEBUG 0
84
85#if DEBUG
86#define RTRACE printk
87#else
88#define RTRACE if(0) printk
89#endif
90
91// XXX
92#undef CONFIG_PMAC_PBOOK
93
94
95enum radeon_chips {
96 RADEON_QD,
97 RADEON_QE,
98 RADEON_QF,
99 RADEON_QG,
100 RADEON_QY,
101 RADEON_QZ,
102 RADEON_LW,
103 RADEON_LX,
104 RADEON_LY,
105 RADEON_LZ,
106 RADEON_QL,
107 RADEON_QN,
108 RADEON_QO,
109 RADEON_Ql,
110 RADEON_BB,
111 RADEON_QW,
112 RADEON_QX,
113 RADEON_Id,
114 RADEON_Ie,
115 RADEON_If,
116 RADEON_Ig,
117 RADEON_Ya,
118 RADEON_Yd,
119 RADEON_Ld,
120 RADEON_Le,
121 RADEON_Lf,
122 RADEON_Lg,
123 RADEON_ND,
124 RADEON_NE,
125 RADEON_NF,
126 RADEON_NG,
127 RADEON_QM
128};
129
130enum radeon_arch {
131 RADEON_R100,
132 RADEON_RV100,
133 RADEON_R200,
134 RADEON_RV200,
135 RADEON_RV250,
136 RADEON_R300,
137 RADEON_M6,
138 RADEON_M7,
139 RADEON_M9
140};
141
142static struct radeon_chip_info {
143 const char *name;
144 unsigned char arch;
145} radeon_chip_info[] __devinitdata = {
146 { "QD", RADEON_R100 },
147 { "QE", RADEON_R100 },
148 { "QF", RADEON_R100 },
149 { "QG", RADEON_R100 },
150 { "VE QY", RADEON_RV100 },
151 { "VE QZ", RADEON_RV100 },
152 { "M7 LW", RADEON_M7 },
153 { "M7 LX", RADEON_M7 },
154 { "M6 LY", RADEON_M6 },
155 { "M6 LZ", RADEON_M6 },
156 { "8500 QL", RADEON_R200 },
157 { "8500 QN", RADEON_R200 },
158 { "8500 QO", RADEON_R200 },
159 { "8500 Ql", RADEON_R200 },
160 { "8500 BB", RADEON_R200 },
161 { "7500 QW", RADEON_RV200 },
162 { "7500 QX", RADEON_RV200 },
163 { "9000 Id", RADEON_RV250 },
164 { "9000 Ie", RADEON_RV250 },
165 { "9000 If", RADEON_RV250 },
166 { "9000 Ig", RADEON_RV250 },
167 { "M9 Ld", RADEON_M9 },
168 { "M9 Le", RADEON_M9 },
169 { "M9 Lf", RADEON_M9 },
170 { "M9 Lg", RADEON_M9 },
171 { "9700 ND", RADEON_R300 },
172 { "9700 NE", RADEON_R300 },
173 { "9700 NF", RADEON_R300 },
174 { "9700 NG", RADEON_R300 },
175 { "9100 QM", RADEON_R200 }
176};
177
178
179enum radeon_montype
180{
181 MT_NONE,
182 MT_CRT, /* CRT */
183 MT_LCD, /* LCD */
184 MT_DFP, /* DVI */
185 MT_CTV, /* composite TV */
186 MT_STV /* S-Video out */
187};
188
189
190static struct pci_device_id radeonfb_pci_table[] = {
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
192 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
194 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
196 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
198 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX},
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
200 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
202 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN},
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO},
204 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql},
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB},
206 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX},
208 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id},
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie},
210 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If},
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig},
212 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ya, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ya},
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Yd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Yd},
214 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld},
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le},
216 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf},
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg},
218 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND},
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE},
220 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF},
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NG},
222 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM},
223 { 0, }
224};
225MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
226
227
228typedef struct {
229 u16 reg;
230 u32 val;
231} reg_val;
232
233
234/* these common regs are cleared before mode setting so they do not
235 * interfere with anything
236 */
237static reg_val common_regs[] = {
238 { OVR_CLR, 0 },
239 { OVR_WID_LEFT_RIGHT, 0 },
240 { OVR_WID_TOP_BOTTOM, 0 },
241 { OV0_SCALE_CNTL, 0 },
242 { SUBPIC_CNTL, 0 },
243 { VIPH_CONTROL, 0 },
244 { I2C_CNTL_1, 0 },
245 { GEN_INT_CNTL, 0 },
246 { CAP0_TRIG_CNTL, 0 },
247};
248
249static reg_val common_regs_m6[] = {
250 { OVR_CLR, 0 },
251 { OVR_WID_LEFT_RIGHT, 0 },
252 { OVR_WID_TOP_BOTTOM, 0 },
253 { OV0_SCALE_CNTL, 0 },
254 { SUBPIC_CNTL, 0 },
255 { GEN_INT_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 }
257};
258
259typedef struct {
260 u8 clock_chip_type;
261 u8 struct_size;
262 u8 accelerator_entry;
263 u8 VGA_entry;
264 u16 VGA_table_offset;
265 u16 POST_table_offset;
266 u16 XCLK;
267 u16 MCLK;
268 u8 num_PLL_blocks;
269 u8 size_PLL_blocks;
270 u16 PCLK_ref_freq;
271 u16 PCLK_ref_divider;
272 u32 PCLK_min_freq;
273 u32 PCLK_max_freq;
274 u16 MCLK_ref_freq;
275 u16 MCLK_ref_divider;
276 u32 MCLK_min_freq;
277 u32 MCLK_max_freq;
278 u16 XCLK_ref_freq;
279 u16 XCLK_ref_divider;
280 u32 XCLK_min_freq;
281 u32 XCLK_max_freq;
282} __attribute__ ((packed)) PLL_BLOCK;
283
284
285struct pll_info {
286 int ppll_max;
287 int ppll_min;
288 int xclk;
289 int ref_div;
290 int ref_clk;
291};
292
293
294struct ram_info {
295 int ml;
296 int mb;
297 int trcd;
298 int trp;
299 int twr;
300 int cl;
301 int tr2w;
302 int loop_latency;
303 int rloop;
304};
305
306
307struct radeon_regs {
308 /* CRTC regs */
309 u32 crtc_h_total_disp;
310 u32 crtc_h_sync_strt_wid;
311 u32 crtc_v_total_disp;
312 u32 crtc_v_sync_strt_wid;
313 u32 crtc_pitch;
314 u32 crtc_gen_cntl;
315 u32 crtc_ext_cntl;
316 u32 dac_cntl;
317
318 u32 flags;
319 u32 pix_clock;
320 int xres, yres;
321
322 /* DDA regs */
323 u32 dda_config;
324 u32 dda_on_off;
325
326 /* PLL regs */
327 u32 ppll_div_3;
328 u32 ppll_ref_div;
329 u32 vclk_ecp_cntl;
330
331 /* Flat panel regs */
332 u32 fp_crtc_h_total_disp;
333 u32 fp_crtc_v_total_disp;
334 u32 fp_gen_cntl;
335 u32 fp_h_sync_strt_wid;
336 u32 fp_horz_stretch;
337 u32 fp_panel_cntl;
338 u32 fp_v_sync_strt_wid;
339 u32 fp_vert_stretch;
340 u32 lvds_gen_cntl;
341 u32 lvds_pll_cntl;
342 u32 tmds_crc;
343 u32 tmds_transmitter_cntl;
344
345#if defined(__BIG_ENDIAN)
346 u32 surface_cntl;
347#endif
348};
349
350
351struct radeonfb_info {
352 struct fb_info info;
353
354 struct radeon_regs state;
355 struct radeon_regs init_state;
356
357 char name[32];
358 char ram_type[12];
359
360 unsigned long mmio_base_phys;
361 unsigned long fb_base_phys;
362
363 void __iomem *mmio_base;
364 void __iomem *fb_base;
365
366 struct pci_dev *pdev;
367
368 unsigned char *EDID;
369 unsigned char __iomem *bios_seg;
370
371 u32 pseudo_palette[17];
372 struct { u8 red, green, blue, pad; } palette[256];
373
374 int chipset;
375 unsigned char arch;
376 int video_ram;
377 u8 rev;
378 int pitch, bpp, depth;
379 int xres, yres, pixclock;
380 int xres_virtual, yres_virtual;
381 u32 accel_flags;
382
383 int use_default_var;
384 int got_dfpinfo;
385
386 int hasCRTC2;
387 int crtDisp_type;
388 int dviDisp_type;
389
390 int panel_xres, panel_yres;
391 int clock;
392 int hOver_plus, hSync_width, hblank;
393 int vOver_plus, vSync_width, vblank;
394 int hAct_high, vAct_high, interlaced;
395 int synct, misc;
396
397 u32 dp_gui_master_cntl;
398
399 struct pll_info pll;
400 int pll_output_freq, post_div, fb_div;
401
402 struct ram_info ram;
403
404 int mtrr_hdl;
405
406#ifdef CONFIG_PMAC_PBOOK
407 int pm_reg;
408 u32 save_regs[64];
409 u32 mdll, mdll2;
410#endif /* CONFIG_PMAC_PBOOK */
411 int asleep;
412
413 struct radeonfb_info *next;
414};
415
416
417static struct fb_var_screeninfo radeonfb_default_var = {
418 640, 480, 640, 480, 0, 0, 8, 0,
419 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
420 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
421 0, FB_VMODE_NONINTERLACED
422};
423
424/*
425 * IO macros
426 */
427
428#define INREG8(addr) readb((rinfo->mmio_base)+addr)
429#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
430#define INREG(addr) readl((rinfo->mmio_base)+addr)
431#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
432
433#define OUTPLL(addr,val) \
434 do { \
435 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
436 OUTREG(CLOCK_CNTL_DATA, val); \
437 } while(0)
438
439#define OUTPLLP(addr,val,mask) \
440 do { \
441 unsigned int _tmp = INPLL(addr); \
442 _tmp &= (mask); \
443 _tmp |= (val); \
444 OUTPLL(addr, _tmp); \
445 } while (0)
446
447#define OUTREGP(addr,val,mask) \
448 do { \
449 unsigned int _tmp = INREG(addr); \
450 _tmp &= (mask); \
451 _tmp |= (val); \
452 OUTREG(addr, _tmp); \
453 } while (0)
454
455
456static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
457{
458 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
459 return (INREG(CLOCK_CNTL_DATA));
460}
461
462#define INPLL(addr) _INPLL(rinfo, addr)
463
464#define PRIMARY_MONITOR(rinfo) ((rinfo->dviDisp_type != MT_NONE) && \
465 (rinfo->dviDisp_type != MT_STV) && \
466 (rinfo->dviDisp_type != MT_CTV) ? \
467 rinfo->dviDisp_type : rinfo->crtDisp_type)
468
469static char *GET_MON_NAME(int type)
470{
471 char *pret = NULL;
472
473 switch (type) {
474 case MT_NONE:
475 pret = "no";
476 break;
477 case MT_CRT:
478 pret = "CRT";
479 break;
480 case MT_DFP:
481 pret = "DFP";
482 break;
483 case MT_LCD:
484 pret = "LCD";
485 break;
486 case MT_CTV:
487 pret = "CTV";
488 break;
489 case MT_STV:
490 pret = "STV";
491 break;
492 }
493
494 return pret;
495}
496
497
498/*
499 * 2D engine routines
500 */
501
502static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
503{
504 int i;
505
506 /* initiate flush */
507 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
508 ~RB2D_DC_FLUSH_ALL);
509
510 for (i=0; i < 2000000; i++) {
511 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
512 break;
513 }
514}
515
516
517static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
518{
519 int i;
520
521 for (i=0; i<2000000; i++)
522 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
523 return;
524}
525
526
527static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
528{
529 int i;
530
531 /* ensure FIFO is empty before waiting for idle */
532 _radeon_fifo_wait (rinfo, 64);
533
534 for (i=0; i<2000000; i++) {
535 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
536 radeon_engine_flush (rinfo);
537 return;
538 }
539 }
540}
541
542
543#define radeon_engine_idle() _radeon_engine_idle(rinfo)
544#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
545
546
547
548/*
549 * helper routines
550 */
551
552static __inline__ u32 radeon_get_dstbpp(u16 depth)
553{
554 switch (depth) {
555 case 8:
556 return DST_8BPP;
557 case 15:
558 return DST_15BPP;
559 case 16:
560 return DST_16BPP;
561 case 32:
562 return DST_32BPP;
563 default:
564 return 0;
565 }
566}
567
568
569static inline int var_to_depth(const struct fb_var_screeninfo *var)
570{
571 if (var->bits_per_pixel != 16)
572 return var->bits_per_pixel;
573 return (var->green.length == 6) ? 16 : 15;
574}
575
576
577static void _radeon_engine_reset(struct radeonfb_info *rinfo)
578{
579 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
580
581 radeon_engine_flush (rinfo);
582
583 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
584 mclk_cntl = INPLL(MCLK_CNTL);
585
586 OUTPLL(MCLK_CNTL, (mclk_cntl |
587 FORCEON_MCLKA |
588 FORCEON_MCLKB |
589 FORCEON_YCLKA |
590 FORCEON_YCLKB |
591 FORCEON_MC |
592 FORCEON_AIC));
593 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
594
595 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
596 SOFT_RESET_CP |
597 SOFT_RESET_HI |
598 SOFT_RESET_SE |
599 SOFT_RESET_RE |
600 SOFT_RESET_PP |
601 SOFT_RESET_E2 |
602 SOFT_RESET_RB);
603 INREG(RBBM_SOFT_RESET);
604 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
605 ~(SOFT_RESET_CP |
606 SOFT_RESET_HI |
607 SOFT_RESET_SE |
608 SOFT_RESET_RE |
609 SOFT_RESET_PP |
610 SOFT_RESET_E2 |
611 SOFT_RESET_RB));
612 INREG(RBBM_SOFT_RESET);
613
614 OUTPLL(MCLK_CNTL, mclk_cntl);
615 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
616 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
617
618 return;
619}
620
621#define radeon_engine_reset() _radeon_engine_reset(rinfo)
622
623
624static __inline__ int round_div(int num, int den)
625{
626 return (num + (den / 2)) / den;
627}
628
629
630
631static __inline__ int min_bits_req(int val)
632{
633 int bits_req = 0;
634
635 if (val == 0)
636 bits_req = 1;
637
638 while (val) {
639 val >>= 1;
640 bits_req++;
641 }
642
643 return (bits_req);
644}
645
646
647static __inline__ int _max(int val1, int val2)
648{
649 if (val1 >= val2)
650 return val1;
651 else
652 return val2;
653}
654
655
656
657/*
658 * globals
659 */
660
661#ifndef MODULE
662static char *mode_option;
663#endif
664
665static char noaccel = 0;
666static char mirror = 0;
667static int panel_yres = 0;
668static char force_dfp = 0;
669static struct radeonfb_info *board_list = NULL;
670static char nomtrr = 0;
671
672/*
673 * prototypes
674 */
675
676static void radeon_save_state (struct radeonfb_info *rinfo,
677 struct radeon_regs *save);
678static void radeon_engine_init (struct radeonfb_info *rinfo);
679static void radeon_write_mode (struct radeonfb_info *rinfo,
680 struct radeon_regs *mode);
681static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
682static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
683static int radeon_init_disp_var (struct radeonfb_info *rinfo, struct fb_var_screeninfo *var);
684static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo);
685static void radeon_get_pllinfo(struct radeonfb_info *rinfo, void __iomem *bios_seg);
686static void radeon_get_moninfo (struct radeonfb_info *rinfo);
687static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
688static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
689static void radeon_get_EDID(struct radeonfb_info *rinfo);
690static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
691static void radeon_update_default_var(struct radeonfb_info *rinfo);
692
693#ifdef CONFIG_PPC_OF
694
695static int radeon_read_OF (struct radeonfb_info *rinfo);
696static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
697extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
698
699#ifdef CONFIG_PMAC_PBOOK
700int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
701static struct pmu_sleep_notifier radeon_sleep_notifier = {
702 radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
703};
704#endif /* CONFIG_PMAC_PBOOK */
705#ifdef CONFIG_PMAC_BACKLIGHT
706static int radeon_set_backlight_enable(int on, int level, void *data);
707static int radeon_set_backlight_level(int level, void *data);
708static struct backlight_controller radeon_backlight_controller = {
709 radeon_set_backlight_enable,
710 radeon_set_backlight_level
711};
712#endif /* CONFIG_PMAC_BACKLIGHT */
713
714#endif /* CONFIG_PPC_OF */
715
716
717static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo)
718{
719#if defined(__i386__)
720 u32 segstart;
721 char __iomem *rom_base;
722 char __iomem *rom;
723 int stage;
724 int i,j;
725 char aty_rom_sig[] = "761295520";
726 char *radeon_sig[] = {
727 "RG6",
728 "RADEON"
729 };
730
731 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
732
733 stage = 1;
734
735 rom_base = ioremap(segstart, 0x1000);
736
737 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
738 stage = 2;
739
740
741 if (stage != 2) {
742 iounmap(rom_base);
743 continue;
744 }
745
746 rom = rom_base;
747
748 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
749 if (aty_rom_sig[0] == *rom)
750 if (strncmp(aty_rom_sig, rom,
751 strlen(aty_rom_sig)) == 0)
752 stage = 3;
753 rom++;
754 }
755 if (stage != 3) {
756 iounmap(rom_base);
757 continue;
758 }
759 rom = rom_base;
760
761 for (i = 0; (i < 512) && (stage != 4); i++) {
762 for (j = 0; j < ARRAY_SIZE(radeon_sig); j++) {
763 if (radeon_sig[j][0] == *rom)
764 if (strncmp(radeon_sig[j], rom,
765 strlen(radeon_sig[j])) == 0) {
766 stage = 4;
767 break;
768 }
769 }
770 rom++;
771 }
772 if (stage != 4) {
773 iounmap(rom_base);
774 continue;
775 }
776
777 return rom_base;
778 }
779#endif
780 return NULL;
781}
782
783
784
785
786static void radeon_get_pllinfo(struct radeonfb_info *rinfo, void __iomem *bios_seg)
787{
788 void __iomem *bios_header;
789 void __iomem *header_ptr;
790 u16 bios_header_offset, pll_info_offset;
791 PLL_BLOCK pll;
792
793 if (bios_seg) {
794 bios_header = bios_seg + 0x48L;
795 header_ptr = bios_header;
796
797 bios_header_offset = readw(header_ptr);
798 bios_header = bios_seg + bios_header_offset;
799 bios_header += 0x30;
800
801 header_ptr = bios_header;
802 pll_info_offset = readw(header_ptr);
803 header_ptr = bios_seg + pll_info_offset;
804
805 memcpy_fromio(&pll, header_ptr, 50);
806
807 rinfo->pll.xclk = (u32)pll.XCLK;
808 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
809 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
810 rinfo->pll.ppll_min = pll.PCLK_min_freq;
811 rinfo->pll.ppll_max = pll.PCLK_max_freq;
812
813 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
814 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
815 } else {
816#ifdef CONFIG_PPC_OF
817 if (radeon_read_OF(rinfo)) {
818 unsigned int tmp, Nx, M, ref_div, xclk;
819
820 tmp = INPLL(M_SPLL_REF_FB_DIV);
821 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
822
823 Nx = (tmp & 0xff00) >> 8;
824 M = (tmp & 0xff);
825 xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
826 (2 * M)));
827
828 rinfo->pll.xclk = xclk;
829 rinfo->pll.ref_div = ref_div;
830 rinfo->pll.ppll_min = 12000;
831 rinfo->pll.ppll_max = 35000;
832
833 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
834 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
835
836 return;
837 }
838#endif
839 /* no BIOS or BIOS not found, use defaults */
840 switch (rinfo->chipset) {
841 case PCI_DEVICE_ID_ATI_RADEON_QW:
842 case PCI_DEVICE_ID_ATI_RADEON_QX:
843 rinfo->pll.ppll_max = 35000;
844 rinfo->pll.ppll_min = 12000;
845 rinfo->pll.xclk = 23000;
846 rinfo->pll.ref_div = 12;
847 rinfo->pll.ref_clk = 2700;
848 break;
849 case PCI_DEVICE_ID_ATI_RADEON_QL:
850 case PCI_DEVICE_ID_ATI_RADEON_QN:
851 case PCI_DEVICE_ID_ATI_RADEON_QO:
852 case PCI_DEVICE_ID_ATI_RADEON_Ql:
853 case PCI_DEVICE_ID_ATI_RADEON_BB:
854 rinfo->pll.ppll_max = 35000;
855 rinfo->pll.ppll_min = 12000;
856 rinfo->pll.xclk = 27500;
857 rinfo->pll.ref_div = 12;
858 rinfo->pll.ref_clk = 2700;
859 break;
860 case PCI_DEVICE_ID_ATI_RADEON_Id:
861 case PCI_DEVICE_ID_ATI_RADEON_Ie:
862 case PCI_DEVICE_ID_ATI_RADEON_If:
863 case PCI_DEVICE_ID_ATI_RADEON_Ig:
864 rinfo->pll.ppll_max = 35000;
865 rinfo->pll.ppll_min = 12000;
866 rinfo->pll.xclk = 25000;
867 rinfo->pll.ref_div = 12;
868 rinfo->pll.ref_clk = 2700;
869 break;
870 case PCI_DEVICE_ID_ATI_RADEON_ND:
871 case PCI_DEVICE_ID_ATI_RADEON_NE:
872 case PCI_DEVICE_ID_ATI_RADEON_NF:
873 case PCI_DEVICE_ID_ATI_RADEON_NG:
874 rinfo->pll.ppll_max = 40000;
875 rinfo->pll.ppll_min = 20000;
876 rinfo->pll.xclk = 27000;
877 rinfo->pll.ref_div = 12;
878 rinfo->pll.ref_clk = 2700;
879 break;
880 case PCI_DEVICE_ID_ATI_RADEON_QD:
881 case PCI_DEVICE_ID_ATI_RADEON_QE:
882 case PCI_DEVICE_ID_ATI_RADEON_QF:
883 case PCI_DEVICE_ID_ATI_RADEON_QG:
884 default:
885 rinfo->pll.ppll_max = 35000;
886 rinfo->pll.ppll_min = 12000;
887 rinfo->pll.xclk = 16600;
888 rinfo->pll.ref_div = 67;
889 rinfo->pll.ref_clk = 2700;
890 break;
891 }
892
893 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
894 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
895 }
896}
897
898
899static void radeon_get_moninfo (struct radeonfb_info *rinfo)
900{
901 unsigned int tmp;
902
903 if (force_dfp) {
904 rinfo->dviDisp_type = MT_DFP;
905 return;
906 }
907
908 tmp = INREG(BIOS_4_SCRATCH);
909 printk(KERN_DEBUG "radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
910
911 if (rinfo->hasCRTC2) {
912 /* primary DVI port */
913 if (tmp & 0x08)
914 rinfo->dviDisp_type = MT_DFP;
915 else if (tmp & 0x4)
916 rinfo->dviDisp_type = MT_LCD;
917 else if (tmp & 0x200)
918 rinfo->dviDisp_type = MT_CRT;
919 else if (tmp & 0x10)
920 rinfo->dviDisp_type = MT_CTV;
921 else if (tmp & 0x20)
922 rinfo->dviDisp_type = MT_STV;
923
924 /* secondary CRT port */
925 if (tmp & 0x2)
926 rinfo->crtDisp_type = MT_CRT;
927 else if (tmp & 0x800)
928 rinfo->crtDisp_type = MT_DFP;
929 else if (tmp & 0x400)
930 rinfo->crtDisp_type = MT_LCD;
931 else if (tmp & 0x1000)
932 rinfo->crtDisp_type = MT_CTV;
933 else if (tmp & 0x2000)
934 rinfo->crtDisp_type = MT_STV;
935 } else {
936 rinfo->dviDisp_type = MT_NONE;
937
938 tmp = INREG(FP_GEN_CNTL);
939
940 if (tmp & FP_EN_TMDS)
941 rinfo->crtDisp_type = MT_DFP;
942 else
943 rinfo->crtDisp_type = MT_CRT;
944 }
945}
946
947
948
949static void radeon_get_EDID(struct radeonfb_info *rinfo)
950{
951#ifdef CONFIG_PPC_OF
952 if (!radeon_get_EDID_OF(rinfo))
953 RTRACE("radeonfb: could not retrieve EDID from OF\n");
954#else
955 /* XXX use other methods later */
956#endif
957}
958
959
960#ifdef CONFIG_PPC_OF
961static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
962{
963 struct device_node *dp;
964 unsigned char *pedid = NULL;
965 static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
966 int i;
967
968 dp = pci_device_to_OF_node(rinfo->pdev);
969 while (dp != NULL) {
970 for (i = 0; propnames[i] != NULL; ++i) {
971 pedid = (unsigned char *)
972 get_property(dp, propnames[i], NULL);
973 if (pedid != NULL) {
974 rinfo->EDID = pedid;
975 return 1;
976 }
977 }
978 dp = dp->child;
979 }
980 return 0;
981}
982#endif /* CONFIG_PPC_OF */
983
984
985static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
986{
987 unsigned char *block = rinfo->EDID;
988
989 if (!block)
990 return 0;
991
992 /* jump to the detailed timing block section */
993 block += 54;
994
995 rinfo->clock = (block[0] + (block[1] << 8));
996 rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
997 rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
998 rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
999 rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1000 rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1001 rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1002 rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1003 rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1004 rinfo->interlaced = ((block[17] & 0x80) >> 7);
1005 rinfo->synct = ((block[17] & 0x18) >> 3);
1006 rinfo->misc = ((block[17] & 0x06) >> 1);
1007 rinfo->hAct_high = rinfo->vAct_high = 0;
1008 if (rinfo->synct == 3) {
1009 if (rinfo->misc & 2)
1010 rinfo->hAct_high = 1;
1011 if (rinfo->misc & 1)
1012 rinfo->vAct_high = 1;
1013 }
1014
1015 printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
1016 rinfo->panel_xres, rinfo->panel_yres);
1017
1018 rinfo->got_dfpinfo = 1;
1019
1020 return 1;
1021}
1022
1023
1024static void radeon_update_default_var(struct radeonfb_info *rinfo)
1025{
1026 struct fb_var_screeninfo *var = &radeonfb_default_var;
1027
1028 var->xres = rinfo->panel_xres;
1029 var->yres = rinfo->panel_yres;
1030 var->xres_virtual = rinfo->panel_xres;
1031 var->yres_virtual = rinfo->panel_yres;
1032 var->xoffset = var->yoffset = 0;
1033 var->bits_per_pixel = 8;
1034 var->pixclock = 100000000 / rinfo->clock;
1035 var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
1036 var->right_margin = rinfo->hOver_plus;
1037 var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
1038 var->lower_margin = rinfo->vOver_plus;
1039 var->hsync_len = rinfo->hSync_width;
1040 var->vsync_len = rinfo->vSync_width;
1041 var->sync = 0;
1042 if (rinfo->synct == 3) {
1043 if (rinfo->hAct_high)
1044 var->sync |= FB_SYNC_HOR_HIGH_ACT;
1045 if (rinfo->vAct_high)
1046 var->sync |= FB_SYNC_VERT_HIGH_ACT;
1047 }
1048
1049 var->vmode = 0;
1050 if (rinfo->interlaced)
1051 var->vmode |= FB_VMODE_INTERLACED;
1052
1053 rinfo->use_default_var = 1;
1054}
1055
1056
1057static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
1058{
1059 char __iomem *fpbiosstart, *tmp, *tmp0;
1060 char stmp[30];
1061 int i;
1062
1063 if (!rinfo->bios_seg)
1064 return 0;
1065
1066 if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
1067 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1068 return 0;
1069 }
1070
1071 if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
1072 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1073 return 0;
1074 }
1075
1076 for(i=0; i<24; i++)
1077 stmp[i] = readb(tmp+i+1);
1078 stmp[24] = 0;
1079 printk("radeonfb: panel ID string: %s\n", stmp);
1080 rinfo->panel_xres = readw(tmp + 25);
1081 rinfo->panel_yres = readw(tmp + 27);
1082 printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
1083 rinfo->panel_xres, rinfo->panel_yres);
1084
1085 for(i=0; i<32; i++) {
1086 tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
1087 if (tmp0 == 0)
1088 break;
1089 if ((readw(tmp0) == rinfo->panel_xres) &&
1090 (readw(tmp0+2) == rinfo->panel_yres)) {
1091 rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
1092 rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
1093 rinfo->hSync_width = readb(tmp0+23) * 8;
1094 rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
1095 rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
1096 rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
1097 rinfo->clock = readw(tmp0+9);
1098
1099 rinfo->got_dfpinfo = 1;
1100 return 1;
1101 }
1102 }
1103
1104 return 0;
1105}
1106
1107
1108
1109static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
1110{
1111 unsigned int tmp;
1112 unsigned short a, b;
1113
1114 if (radeon_get_dfpinfo_BIOS(rinfo))
1115 radeon_update_default_var(rinfo);
1116
1117 if (radeon_dfp_parse_EDID(rinfo))
1118 radeon_update_default_var(rinfo);
1119
1120 if (!rinfo->got_dfpinfo) {
1121 /*
1122 * it seems all else has failed now and we
1123 * resort to probing registers for our DFP info
1124 */
1125 if (panel_yres) {
1126 rinfo->panel_yres = panel_yres;
1127 } else {
1128 tmp = INREG(FP_VERT_STRETCH);
1129 tmp &= 0x00fff000;
1130 rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
1131 }
1132
1133 switch (rinfo->panel_yres) {
1134 case 480:
1135 rinfo->panel_xres = 640;
1136 break;
1137 case 600:
1138 rinfo->panel_xres = 800;
1139 break;
1140 case 768:
1141#if defined(__powerpc__)
1142 if (rinfo->dviDisp_type == MT_LCD)
1143 rinfo->panel_xres = 1152;
1144 else
1145#endif
1146 rinfo->panel_xres = 1024;
1147 break;
1148 case 1024:
1149 rinfo->panel_xres = 1280;
1150 break;
1151 case 1050:
1152 rinfo->panel_xres = 1400;
1153 break;
1154 case 1200:
1155 rinfo->panel_xres = 1600;
1156 break;
1157 default:
1158 printk("radeonfb: Failed to detect DFP panel size\n");
1159 return 0;
1160 }
1161
1162 printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
1163 rinfo->panel_xres, rinfo->panel_yres);
1164
1165 tmp = INREG(FP_CRTC_H_TOTAL_DISP);
1166 a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
1167 b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
1168 rinfo->hblank = (a - b + 1) * 8;
1169
1170 tmp = INREG(FP_H_SYNC_STRT_WID);
1171 rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
1172 FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
1173 rinfo->hOver_plus *= 8;
1174 rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
1175 FP_H_SYNC_WID_SHIFT);
1176 rinfo->hSync_width *= 8;
1177 tmp = INREG(FP_CRTC_V_TOTAL_DISP);
1178 a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
1179 b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
1180 rinfo->vblank = a - b /* + 24 */ ;
1181
1182 tmp = INREG(FP_V_SYNC_STRT_WID);
1183 rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
1184 - b + 1;
1185 rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
1186 FP_V_SYNC_WID_SHIFT);
1187
1188 return 1;
1189 }
1190
1191 return 1;
1192}
1193
1194
1195#ifdef CONFIG_PPC_OF
1196static int radeon_read_OF (struct radeonfb_info *rinfo)
1197{
1198 struct device_node *dp;
1199 unsigned int *xtal;
1200
1201 dp = pci_device_to_OF_node(rinfo->pdev);
1202
1203 xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", NULL);
1204
1205 rinfo->pll.ref_clk = *xtal / 10;
1206
1207 if (*xtal)
1208 return 1;
1209 else
1210 return 0;
1211}
1212#endif
1213
1214
1215static void radeon_engine_init (struct radeonfb_info *rinfo)
1216{
1217 u32 temp;
1218
1219 /* disable 3D engine */
1220 OUTREG(RB3D_CNTL, 0);
1221
1222 radeon_engine_reset ();
1223
1224 radeon_fifo_wait (1);
1225 OUTREG(RB2D_DSTCACHE_MODE, 0);
1226
1227 radeon_fifo_wait (1);
1228 temp = INREG(DEFAULT_PITCH_OFFSET);
1229 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
1230 (rinfo->pitch << 0x16)));
1231
1232 radeon_fifo_wait (1);
1233 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
1234
1235 radeon_fifo_wait (1);
1236 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
1237 DEFAULT_SC_BOTTOM_MAX));
1238
1239 temp = radeon_get_dstbpp(rinfo->depth);
1240 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
1241 radeon_fifo_wait (1);
1242 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
1243 GMC_BRUSH_SOLID_COLOR |
1244 GMC_SRC_DATATYPE_COLOR));
1245
1246 radeon_fifo_wait (7);
1247
1248 /* clear line drawing regs */
1249 OUTREG(DST_LINE_START, 0);
1250 OUTREG(DST_LINE_END, 0);
1251
1252 /* set brush color regs */
1253 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
1254 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
1255
1256 /* set source color regs */
1257 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
1258 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
1259
1260 /* default write mask */
1261 OUTREG(DP_WRITE_MSK, 0xffffffff);
1262
1263 radeon_engine_idle ();
1264}
1265
1266
1267static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
1268{
1269 struct fb_info *info = &rinfo->info;
1270 struct fb_var_screeninfo var;
1271
1272 var = radeonfb_default_var;
1273 if ((radeon_init_disp_var(rinfo, &var)) < 0)
1274 return -1;
1275
1276 rinfo->depth = var_to_depth(&var);
1277 rinfo->bpp = var.bits_per_pixel;
1278
1279 info->var = var;
1280 fb_alloc_cmap(&info->cmap, 256, 0);
1281
1282 var.activate = FB_ACTIVATE_NOW;
1283 return 0;
1284}
1285
1286
1287static int radeon_init_disp_var (struct radeonfb_info *rinfo,
1288 struct fb_var_screeninfo *var)
1289{
1290#ifndef MODULE
1291 if (mode_option)
1292 fb_find_mode (var, &rinfo->info, mode_option,
1293 NULL, 0, NULL, 8);
1294 else
1295#endif
1296 if (rinfo->use_default_var)
1297 /* We will use the modified default far */
1298 *var = radeonfb_default_var;
1299 else
1300
1301 fb_find_mode (var, &rinfo->info, "640x480-8@60",
1302 NULL, 0, NULL, 0);
1303
1304 if (noaccel)
1305 var->accel_flags &= ~FB_ACCELF_TEXT;
1306 else
1307 var->accel_flags |= FB_ACCELF_TEXT;
1308
1309 return 0;
1310}
1311
1312
1313static int radeon_do_maximize(struct radeonfb_info *rinfo,
1314 struct fb_var_screeninfo *var,
1315 struct fb_var_screeninfo *v,
1316 int nom, int den)
1317{
1318 static struct {
1319 int xres, yres;
1320 } modes[] = {
1321 {1600, 1280},
1322 {1280, 1024},
1323 {1024, 768},
1324 {800, 600},
1325 {640, 480},
1326 {-1, -1}
1327 };
1328 int i;
1329
1330 /* use highest possible virtual resolution */
1331 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
1332 printk("radeonfb: using max available virtual resolution\n");
1333 for (i=0; modes[i].xres != -1; i++) {
1334 if (modes[i].xres * nom / den * modes[i].yres <
1335 rinfo->video_ram / 2)
1336 break;
1337 }
1338 if (modes[i].xres == -1) {
1339 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
1340 return -EINVAL;
1341 }
1342 v->xres_virtual = modes[i].xres;
1343 v->yres_virtual = modes[i].yres;
1344
1345 printk("radeonfb: virtual resolution set to max of %dx%d\n",
1346 v->xres_virtual, v->yres_virtual);
1347 } else if (v->xres_virtual == -1) {
1348 v->xres_virtual = (rinfo->video_ram * den /
1349 (nom * v->yres_virtual * 2)) & ~15;
1350 } else if (v->yres_virtual == -1) {
1351 v->xres_virtual = (v->xres_virtual + 15) & ~15;
1352 v->yres_virtual = rinfo->video_ram * den /
1353 (nom * v->xres_virtual *2);
1354 } else {
1355 if (v->xres_virtual * nom / den * v->yres_virtual >
1356 rinfo->video_ram) {
1357 return -EINVAL;
1358 }
1359 }
1360
1361 if (v->xres_virtual * nom / den >= 8192) {
1362 v->xres_virtual = 8192 * den / nom - 16;
1363 }
1364
1365 if (v->xres_virtual < v->xres)
1366 return -EINVAL;
1367
1368 if (v->yres_virtual < v->yres)
1369 return -EINVAL;
1370
1371 return 0;
1372}
1373
1374
1375static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
1376{
1377 struct radeonfb_info *rinfo = (struct radeonfb_info *) info->par;
1378 struct fb_var_screeninfo v;
1379 int nom, den;
1380
1381 memcpy (&v, var, sizeof (v));
1382
1383 switch (v.bits_per_pixel) {
1384 case 0 ... 8:
1385 v.bits_per_pixel = 8;
1386 break;
1387 case 9 ... 16:
1388 v.bits_per_pixel = 16;
1389 break;
1390 case 17 ... 24:
1391#if 0 /* Doesn't seem to work */
1392 v.bits_per_pixel = 24;
1393 break;
1394#endif
1395 return -EINVAL;
1396 case 25 ... 32:
1397 v.bits_per_pixel = 32;
1398 break;
1399 default:
1400 return -EINVAL;
1401 }
1402
1403 switch (var_to_depth(&v)) {
1404 case 8:
1405 nom = den = 1;
1406 v.red.offset = v.green.offset = v.blue.offset = 0;
1407 v.red.length = v.green.length = v.blue.length = 8;
1408 v.transp.offset = v.transp.length = 0;
1409 break;
1410 case 15:
1411 nom = 2;
1412 den = 1;
1413 v.red.offset = 10;
1414 v.green.offset = 5;
1415 v.blue.offset = 0;
1416 v.red.length = v.green.length = v.blue.length = 5;
1417 v.transp.offset = v.transp.length = 0;
1418 break;
1419 case 16:
1420 nom = 2;
1421 den = 1;
1422 v.red.offset = 11;
1423 v.green.offset = 5;
1424 v.blue.offset = 0;
1425 v.red.length = 5;
1426 v.green.length = 6;
1427 v.blue.length = 5;
1428 v.transp.offset = v.transp.length = 0;
1429 break;
1430 case 24:
1431 nom = 4;
1432 den = 1;
1433 v.red.offset = 16;
1434 v.green.offset = 8;
1435 v.blue.offset = 0;
1436 v.red.length = v.blue.length = v.green.length = 8;
1437 v.transp.offset = v.transp.length = 0;
1438 break;
1439 case 32:
1440 nom = 4;
1441 den = 1;
1442 v.red.offset = 16;
1443 v.green.offset = 8;
1444 v.blue.offset = 0;
1445 v.red.length = v.blue.length = v.green.length = 8;
1446 v.transp.offset = 24;
1447 v.transp.length = 8;
1448 break;
1449 default:
1450 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
1451 var->xres, var->yres, var->bits_per_pixel);
1452 return -EINVAL;
1453 }
1454
1455 if (radeon_do_maximize(rinfo, var, &v, nom, den) < 0)
1456 return -EINVAL;
1457
1458 if (v.xoffset < 0)
1459 v.xoffset = 0;
1460 if (v.yoffset < 0)
1461 v.yoffset = 0;
1462
1463 if (v.xoffset > v.xres_virtual - v.xres)
1464 v.xoffset = v.xres_virtual - v.xres - 1;
1465
1466 if (v.yoffset > v.yres_virtual - v.yres)
1467 v.yoffset = v.yres_virtual - v.yres - 1;
1468
1469 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
1470 v.transp.offset = v.transp.length =
1471 v.transp.msb_right = 0;
1472
1473 if (noaccel)
1474 v.accel_flags = 0;
1475
1476 memcpy(var, &v, sizeof(v));
1477
1478 return 0;
1479}
1480
1481
1482static int radeonfb_pan_display (struct fb_var_screeninfo *var,
1483 struct fb_info *info)
1484{
1485 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1486
1487 if ((var->xoffset + var->xres > var->xres_virtual)
1488 || (var->yoffset + var->yres > var->yres_virtual))
1489 return -EINVAL;
1490
1491 if (rinfo->asleep)
1492 return 0;
1493
1494 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
1495 * var->bits_per_pixel / 8) & ~7);
1496 return 0;
1497}
1498
1499
1500static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
1501 unsigned long arg)
1502{
1503 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1504 unsigned int tmp;
1505 u32 value = 0;
1506 int rc;
1507
1508 switch (cmd) {
1509 /*
1510 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
1511 */
1512 case FBIO_RADEON_SET_MIRROR:
1513 switch (rinfo->arch) {
1514 case RADEON_R100:
1515 case RADEON_RV100:
1516 case RADEON_R200:
1517 case RADEON_RV200:
1518 case RADEON_RV250:
1519 case RADEON_R300:
1520 return -EINVAL;
1521 default:
1522 /* RADEON M6, RADEON_M7, RADEON_M9 */
1523 break;
1524 }
1525
1526 rc = get_user(value, (__u32 __user *)arg);
1527
1528 if (rc)
1529 return rc;
1530
1531 if (value & 0x01) {
1532 tmp = INREG(LVDS_GEN_CNTL);
1533
1534 tmp |= (LVDS_ON | LVDS_BLON);
1535 } else {
1536 tmp = INREG(LVDS_GEN_CNTL);
1537
1538 tmp &= ~(LVDS_ON | LVDS_BLON);
1539 }
1540
1541 OUTREG(LVDS_GEN_CNTL, tmp);
1542
1543 if (value & 0x02) {
1544 tmp = INREG(CRTC_EXT_CNTL);
1545 tmp |= CRTC_CRT_ON;
1546
1547 mirror = 1;
1548 } else {
1549 tmp = INREG(CRTC_EXT_CNTL);
1550 tmp &= ~CRTC_CRT_ON;
1551
1552 mirror = 0;
1553 }
1554
1555 OUTREG(CRTC_EXT_CNTL, tmp);
1556
1557 break;
1558 case FBIO_RADEON_GET_MIRROR:
1559 switch (rinfo->arch) {
1560 case RADEON_R100:
1561 case RADEON_RV100:
1562 case RADEON_R200:
1563 case RADEON_RV200:
1564 case RADEON_RV250:
1565 case RADEON_R300:
1566 return -EINVAL;
1567 default:
1568 /* RADEON M6, RADEON_M7, RADEON_M9 */
1569 break;
1570 }
1571
1572 tmp = INREG(LVDS_GEN_CNTL);
1573 if ((LVDS_ON | LVDS_BLON) & tmp)
1574 value |= 0x01;
1575
1576 tmp = INREG(CRTC_EXT_CNTL);
1577 if (CRTC_CRT_ON & tmp)
1578 value |= 0x02;
1579
1580 return put_user(value, (__u32 __user *)arg);
1581 default:
1582 return -EINVAL;
1583 }
1584
1585 return -EINVAL;
1586}
1587
1588
1589static int radeonfb_blank (int blank, struct fb_info *info)
1590{
1591 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1592 u32 val = INREG(CRTC_EXT_CNTL);
1593 u32 val2 = INREG(LVDS_GEN_CNTL);
1594
1595 if (rinfo->asleep)
1596 return 0;
1597
1598#ifdef CONFIG_PMAC_BACKLIGHT
1599 if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
1600 set_backlight_enable(!blank);
1601 return 0;
1602 }
1603#endif
1604
1605 /* reset it */
1606 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1607 CRTC_VSYNC_DIS);
1608 val2 &= ~(LVDS_DISPLAY_DIS);
1609
1610 switch (blank) {
1611 case FB_BLANK_UNBLANK:
1612 case FB_BLANK_NORMAL:
1613 break;
1614 case FB_BLANK_VSYNC_SUSPEND:
1615 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1616 break;
1617 case FB_BLANK_HSYNC_SUSPEND:
1618 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1619 break;
1620 case FB_BLANK_POWERDOWN:
1621 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1622 CRTC_HSYNC_DIS);
1623 val2 |= (LVDS_DISPLAY_DIS);
1624 break;
1625 }
1626
1627 switch (rinfo->dviDisp_type) {
1628 case MT_LCD:
1629 OUTREG(LVDS_GEN_CNTL, val2);
1630 break;
1631 case MT_CRT:
1632 default:
1633 OUTREG(CRTC_EXT_CNTL, val);
1634 break;
1635 }
1636
1637 /* let fbcon do a soft blank for us */
1638 return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1639}
1640
1641
1642static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1643 unsigned blue, unsigned transp, struct fb_info *info)
1644{
1645 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1646 u32 pindex, vclk_cntl;
1647 unsigned int i;
1648
1649 if (regno > 255)
1650 return 1;
1651
1652 red >>= 8;
1653 green >>= 8;
1654 blue >>= 8;
1655 rinfo->palette[regno].red = red;
1656 rinfo->palette[regno].green = green;
1657 rinfo->palette[regno].blue = blue;
1658
1659 /* default */
1660 pindex = regno;
1661
1662 if (!rinfo->asleep) {
1663 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1664 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1665
1666 if (rinfo->bpp == 16) {
1667 pindex = regno * 8;
1668
1669 if (rinfo->depth == 16 && regno > 63)
1670 return 1;
1671 if (rinfo->depth == 15 && regno > 31)
1672 return 1;
1673
1674 /* For 565, the green component is mixed one order below */
1675 if (rinfo->depth == 16) {
1676 OUTREG(PALETTE_INDEX, pindex>>1);
1677 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1678 (green << 8) | (rinfo->palette[regno>>1].blue));
1679 green = rinfo->palette[regno<<1].green;
1680 }
1681 }
1682
1683 if (rinfo->depth != 16 || regno < 32) {
1684 OUTREG(PALETTE_INDEX, pindex);
1685 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1686 }
1687
1688 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1689 }
1690 if (regno < 16) {
1691 switch (rinfo->depth) {
1692 case 15:
1693 ((u16 *) (info->pseudo_palette))[regno] =
1694 (regno << 10) | (regno << 5) | regno;
1695 break;
1696 case 16:
1697 ((u16 *) (info->pseudo_palette))[regno] =
1698 (regno << 11) | (regno << 6) | regno;
1699 break;
1700 case 24:
1701 ((u32 *) (info->pseudo_palette))[regno] =
1702 (regno << 16) | (regno << 8) | regno;
1703 break;
1704 case 32:
1705 i = (regno << 8) | regno;
1706 ((u32 *) (info->pseudo_palette))[regno] =
1707 (i << 16) | i;
1708 break;
1709 }
1710 }
1711 return 0;
1712}
1713
1714
1715
1716static void radeon_save_state (struct radeonfb_info *rinfo,
1717 struct radeon_regs *save)
1718{
1719 /* CRTC regs */
1720 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1721 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1722 save->dac_cntl = INREG(DAC_CNTL);
1723 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1724 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1725 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1726 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1727 save->crtc_pitch = INREG(CRTC_PITCH);
1728#if defined(__BIG_ENDIAN)
1729 save->surface_cntl = INREG(SURFACE_CNTL);
1730#endif
1731
1732 /* FP regs */
1733 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1734 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1735 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1736 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1737 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1738 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1739 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1740 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1741 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1742 save->tmds_crc = INREG(TMDS_CRC);
1743 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1744 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1745}
1746
1747
1748
1749static int radeonfb_set_par (struct fb_info *info)
1750{
1751 struct radeonfb_info *rinfo = (struct radeonfb_info *)info->par;
1752 struct fb_var_screeninfo *mode = &info->var;
1753 struct radeon_regs newmode;
1754 int hTotal, vTotal, hSyncStart, hSyncEnd,
1755 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1756 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1757 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1758 u32 dotClock = 1000000000 / mode->pixclock,
1759 sync, h_sync_pol, v_sync_pol;
1760 int freq = dotClock / 10; /* x 100 */
1761 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
1762 int useable_precision, roff, ron;
1763 int min_bits, format = 0;
1764 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1765 int primary_mon = PRIMARY_MONITOR(rinfo);
1766 int depth = var_to_depth(mode);
1767 int accel = (mode->accel_flags & FB_ACCELF_TEXT) != 0;
1768
1769 rinfo->xres = mode->xres;
1770 rinfo->yres = mode->yres;
1771 rinfo->xres_virtual = mode->xres_virtual;
1772 rinfo->yres_virtual = mode->yres_virtual;
1773 rinfo->pixclock = mode->pixclock;
1774
1775 hSyncStart = mode->xres + mode->right_margin;
1776 hSyncEnd = hSyncStart + mode->hsync_len;
1777 hTotal = hSyncEnd + mode->left_margin;
1778
1779 vSyncStart = mode->yres + mode->lower_margin;
1780 vSyncEnd = vSyncStart + mode->vsync_len;
1781 vTotal = vSyncEnd + mode->upper_margin;
1782
1783 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1784 if (rinfo->panel_xres < mode->xres)
1785 rinfo->xres = mode->xres = rinfo->panel_xres;
1786 if (rinfo->panel_yres < mode->yres)
1787 rinfo->yres = mode->yres = rinfo->panel_yres;
1788
1789 hTotal = mode->xres + rinfo->hblank;
1790 hSyncStart = mode->xres + rinfo->hOver_plus;
1791 hSyncEnd = hSyncStart + rinfo->hSync_width;
1792
1793 vTotal = mode->yres + rinfo->vblank;
1794 vSyncStart = mode->yres + rinfo->vOver_plus;
1795 vSyncEnd = vSyncStart + rinfo->vSync_width;
1796 }
1797
1798 sync = mode->sync;
1799 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1800 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1801
1802 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1803 hSyncStart, hSyncEnd, hTotal);
1804 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1805 vSyncStart, vSyncEnd, vTotal);
1806
1807 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1808 vsync_wid = vSyncEnd - vSyncStart;
1809 if (hsync_wid == 0)
1810 hsync_wid = 1;
1811 else if (hsync_wid > 0x3f) /* max */
1812 hsync_wid = 0x3f;
1813
1814 if (vsync_wid == 0)
1815 vsync_wid = 1;
1816 else if (vsync_wid > 0x1f) /* max */
1817 vsync_wid = 0x1f;
1818
1819 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1820 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1821
1822 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1823
1824 format = radeon_get_dstbpp(depth);
1825 bytpp = mode->bits_per_pixel >> 3;
1826
1827 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1828 hsync_fudge = hsync_fudge_fp[format-1];
1829 else
1830 hsync_fudge = hsync_adj_tab[format-1];
1831
1832 hsync_start = hSyncStart - 8 + hsync_fudge;
1833
1834 newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1835 (format << 8);
1836
1837 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1838 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1839 if (mirror)
1840 newmode.crtc_ext_cntl |= CRTC_CRT_ON;
1841
1842 newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1843 CRTC_INTERLACE_EN);
1844 } else {
1845 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1846 CRTC_CRT_ON;
1847 }
1848
1849 newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1850 DAC_8BIT_EN;
1851
1852 newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1853 (((mode->xres / 8) - 1) << 16));
1854
1855 newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1856 (hsync_wid << 16) | (h_sync_pol << 23));
1857
1858 newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1859 ((mode->yres - 1) << 16);
1860
1861 newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1862 (vsync_wid << 16) | (v_sync_pol << 23));
1863
1864 if (accel) {
1865 /* We first calculate the engine pitch */
1866 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1867 & ~(0x3f)) >> 6;
1868
1869 /* Then, re-multiply it to get the CRTC pitch */
1870 newmode.crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1871 } else
1872 newmode.crtc_pitch = (mode->xres_virtual >> 3);
1873 newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
1874
1875#if defined(__BIG_ENDIAN)
1876 /*
1877 * It looks like recent chips have a problem with SURFACE_CNTL,
1878 * setting SURF_TRANSLATION_DIS completely disables the
1879 * swapper as well, so we leave it unset now.
1880 */
1881 newmode.surface_cntl = 0;
1882
1883 /* Setup swapping on both apertures, though we currently
1884 * only use aperture 0, enabling swapper on aperture 1
1885 * won't harm
1886 */
1887 switch (mode->bits_per_pixel) {
1888 case 16:
1889 newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
1890 newmode.surface_cntl |= NONSURF_AP1_SWP_16BPP;
1891 break;
1892 case 24:
1893 case 32:
1894 newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
1895 newmode.surface_cntl |= NONSURF_AP1_SWP_32BPP;
1896 break;
1897 }
1898#endif
1899
1900 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1901 & ~(0x3f)) / 64;
1902
1903 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1904 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
1905 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1906 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
1907
1908 newmode.xres = mode->xres;
1909 newmode.yres = mode->yres;
1910
1911 rinfo->bpp = mode->bits_per_pixel;
1912 rinfo->depth = depth;
1913
1914 if (freq > rinfo->pll.ppll_max)
1915 freq = rinfo->pll.ppll_max;
1916 if (freq*12 < rinfo->pll.ppll_min)
1917 freq = rinfo->pll.ppll_min / 12;
1918
1919 {
1920 struct {
1921 int divider;
1922 int bitvalue;
1923 } *post_div,
1924 post_divs[] = {
1925 { 1, 0 },
1926 { 2, 1 },
1927 { 4, 2 },
1928 { 8, 3 },
1929 { 3, 4 },
1930 { 16, 5 },
1931 { 6, 6 },
1932 { 12, 7 },
1933 { 0, 0 },
1934 };
1935
1936 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1937 rinfo->pll_output_freq = post_div->divider * freq;
1938 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
1939 rinfo->pll_output_freq <= rinfo->pll.ppll_max)
1940 break;
1941 }
1942
1943 rinfo->post_div = post_div->divider;
1944 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
1945 rinfo->pll.ref_clk);
1946 newmode.ppll_ref_div = rinfo->pll.ref_div;
1947 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
1948 }
1949 newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1950
1951#ifdef CONFIG_PPC_OF
1952 /* Gross hack for iBook with M7 until I find out a proper fix */
1953 if (machine_is_compatible("PowerBook4,3") && rinfo->arch == RADEON_M7)
1954 newmode.ppll_div_3 = 0x000600ad;
1955#endif /* CONFIG_PPC_OF */
1956
1957 RTRACE("post div = 0x%x\n", rinfo->post_div);
1958 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
1959 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
1960
1961 /* DDA */
1962 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
1963 rinfo->pll.ref_div * rinfo->post_div);
1964 xclk_freq = rinfo->pll.xclk;
1965
1966 xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
1967
1968 min_bits = min_bits_req(xclk_per_trans);
1969 useable_precision = min_bits + 1;
1970
1971 xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
1972 vclk_freq * mode->bits_per_pixel);
1973
1974 ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
1975 2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
1976 xclk_per_trans) << (11 - useable_precision);
1977 roff = xclk_per_trans_precise * (32 - 4);
1978
1979 RTRACE("ron = %d, roff = %d\n", ron, roff);
1980 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
1981
1982 if ((ron + rinfo->ram.rloop) >= roff) {
1983 printk("radeonfb: error ron out of range\n");
1984 return -EINVAL;
1985 }
1986
1987 newmode.dda_config = (xclk_per_trans_precise |
1988 (useable_precision << 16) |
1989 (rinfo->ram.rloop << 20));
1990 newmode.dda_on_off = (ron << 16) | roff;
1991
1992 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1993 unsigned int hRatio, vRatio;
1994
1995 /* We force the pixel clock to be always enabled. Allowing it
1996 * to be power managed during blanking would save power, but has
1997 * nasty interactions with the 2D engine & sleep code that haven't
1998 * been solved yet. --BenH
1999 */
2000 newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
2001
2002 if (mode->xres > rinfo->panel_xres)
2003 mode->xres = rinfo->panel_xres;
2004 if (mode->yres > rinfo->panel_yres)
2005 mode->yres = rinfo->panel_yres;
2006
2007 newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
2008 << HORZ_PANEL_SHIFT);
2009 newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
2010 << VERT_PANEL_SHIFT);
2011
2012 if (mode->xres != rinfo->panel_xres) {
2013 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
2014 rinfo->panel_xres);
2015 newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
2016 (newmode.fp_horz_stretch &
2017 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
2018 HORZ_AUTO_RATIO_INC)));
2019 newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
2020 HORZ_STRETCH_ENABLE);
2021 }
2022 newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
2023
2024 if (mode->yres != rinfo->panel_yres) {
2025 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
2026 rinfo->panel_yres);
2027 newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
2028 (newmode.fp_vert_stretch &
2029 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
2030 newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
2031 VERT_STRETCH_ENABLE);
2032 }
2033 newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
2034
2035 newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
2036 ~(FP_SEL_CRTC2 |
2037 FP_RMX_HVSYNC_CONTROL_EN |
2038 FP_DFP_SYNC_SEL |
2039 FP_CRT_SYNC_SEL |
2040 FP_CRTC_LOCK_8DOT |
2041 FP_USE_SHADOW_EN |
2042 FP_CRTC_USE_SHADOW_VEND |
2043 FP_CRT_SYNC_ALT));
2044
2045 newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
2046 FP_CRTC_DONT_SHADOW_HEND);
2047
2048 newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
2049 newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
2050 newmode.tmds_crc = rinfo->init_state.tmds_crc;
2051 newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
2052
2053 if (primary_mon == MT_LCD) {
2054 newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
2055 newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
2056 } else {
2057 /* DFP */
2058 newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
2059 newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
2060 TMDS_ICHCSEL | TMDS_PLL_EN) &
2061 ~(TMDS_PLLRST);
2062 newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
2063 }
2064
2065 newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) |
2066 (((mode->xres / 8) - 1) << 16));
2067 newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) |
2068 ((mode->yres - 1) << 16);
2069 newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) |
2070 (hsync_wid << 16) | (h_sync_pol << 23));
2071 newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) |
2072 (vsync_wid << 16) | (v_sync_pol << 23));
2073 }
2074
2075 /* do it! */
2076 if (!rinfo->asleep) {
2077 radeon_write_mode (rinfo, &newmode);
2078 /* (re)initialize the engine */
2079 if (noaccel)
2080 radeon_engine_init (rinfo);
2081
2082 }
2083 /* Update fix */
2084 if (accel)
2085 info->fix.line_length = rinfo->pitch*64;
2086 else
2087 info->fix.line_length = mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8);
2088 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
2089
2090#ifdef CONFIG_BOOTX_TEXT
2091 /* Update debug text engine */
2092 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
2093 rinfo->depth, info->fix.line_length);
2094#endif
2095
2096 return 0;
2097}
2098
2099
2100static void radeon_write_mode (struct radeonfb_info *rinfo,
2101 struct radeon_regs *mode)
2102{
2103 int i;
2104 int primary_mon = PRIMARY_MONITOR(rinfo);
2105
2106 radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
2107
2108
2109 if (rinfo->arch == RADEON_M6) {
2110 for (i=0; i<7; i++)
2111 OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);
2112 } else {
2113 for (i=0; i<9; i++)
2114 OUTREG(common_regs[i].reg, common_regs[i].val);
2115 }
2116
2117 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
2118 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
2119 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2120 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
2121 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
2122 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
2123 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
2124 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
2125 OUTREG(CRTC_OFFSET, 0);
2126 OUTREG(CRTC_OFFSET_CNTL, 0);
2127 OUTREG(CRTC_PITCH, mode->crtc_pitch);
2128
2129#if defined(__BIG_ENDIAN)
2130 OUTREG(SURFACE_CNTL, mode->surface_cntl);
2131#endif
2132
2133 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
2134 PPLL_DIV_SEL_MASK) {
2135 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
2136 }
2137
2138 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
2139
2140 while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
2141 (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
2142 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
2143 }
2144
2145 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
2146 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
2147 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
2148 }
2149
2150 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
2151 (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
2152 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
2153 }
2154
2155 OUTPLL(HTOTAL_CNTL, 0);
2156
2157 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
2158
2159// OUTREG(DDA_CONFIG, mode->dda_config);
2160// OUTREG(DDA_ON_OFF, mode->dda_on_off);
2161
2162 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2163 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
2164 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
2165 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
2166 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
2167 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
2168 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
2169 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
2170 OUTREG(TMDS_CRC, mode->tmds_crc);
2171 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
2172
2173 if (primary_mon == MT_LCD) {
2174 unsigned int tmp = INREG(LVDS_GEN_CNTL);
2175
2176 mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
2177 mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
2178
2179 if ((tmp & (LVDS_ON | LVDS_BLON)) ==
2180 (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
2181 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2182 } else {
2183 if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
2184 udelay(1000);
2185 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2186 } else {
2187 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
2188 LVDS_BLON);
2189 udelay(1000);
2190 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2191 }
2192 }
2193 }
2194 }
2195
2196 radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
2197
2198 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
2199
2200 return;
2201}
2202
2203static struct fb_ops radeonfb_ops = {
2204 .owner = THIS_MODULE,
2205 .fb_check_var = radeonfb_check_var,
2206 .fb_set_par = radeonfb_set_par,
2207 .fb_setcolreg = radeonfb_setcolreg,
2208 .fb_pan_display = radeonfb_pan_display,
2209 .fb_blank = radeonfb_blank,
2210 .fb_ioctl = radeonfb_ioctl,
2211#if 0
2212 .fb_fillrect = radeonfb_fillrect,
2213 .fb_copyarea = radeonfb_copyarea,
2214 .fb_imageblit = radeonfb_imageblit,
2215 .fb_rasterimg = radeonfb_rasterimg,
2216#else
2217 .fb_fillrect = cfb_fillrect,
2218 .fb_copyarea = cfb_copyarea,
2219 .fb_imageblit = cfb_imageblit,
2220#endif
2221};
2222
2223
2224static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
2225{
2226 struct fb_info *info;
2227
2228 info = &rinfo->info;
2229
2230 info->par = rinfo;
2231 info->pseudo_palette = rinfo->pseudo_palette;
2232 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
2233 info->fbops = &radeonfb_ops;
2234 info->screen_base = rinfo->fb_base;
2235
2236 /* Fill fix common fields */
2237 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
2238 info->fix.smem_start = rinfo->fb_base_phys;
2239 info->fix.smem_len = rinfo->video_ram;
2240 info->fix.type = FB_TYPE_PACKED_PIXELS;
2241 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
2242 info->fix.xpanstep = 8;
2243 info->fix.ypanstep = 1;
2244 info->fix.ywrapstep = 0;
2245 info->fix.type_aux = 0;
2246 info->fix.mmio_start = rinfo->mmio_base_phys;
2247 info->fix.mmio_len = RADEON_REGSIZE;
2248 if (noaccel)
2249 info->fix.accel = FB_ACCEL_NONE;
2250 else
2251 info->fix.accel = FB_ACCEL_ATI_RADEON;
2252
2253 if (radeon_init_disp (rinfo) < 0)
2254 return -1;
2255
2256 return 0;
2257}
2258
2259
2260#ifdef CONFIG_PMAC_BACKLIGHT
2261
2262/* TODO: Dbl check these tables, we don't go up to full ON backlight
2263 * in these, possibly because we noticed MacOS doesn't, but I'd prefer
2264 * having some more official numbers from ATI
2265 */
2266static int backlight_conv_m6[] = {
2267 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2268 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2269};
2270static int backlight_conv_m7[] = {
2271 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
2272 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
2273};
2274
2275#define BACKLIGHT_LVDS_OFF
2276#undef BACKLIGHT_DAC_OFF
2277
2278/* We turn off the LCD completely instead of just dimming the backlight.
2279 * This provides some greater power saving and the display is useless
2280 * without backlight anyway.
2281 */
2282
2283static int radeon_set_backlight_enable(int on, int level, void *data)
2284{
2285 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
2286 unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2287 int* conv_table;
2288
2289 /* Pardon me for that hack... maybe some day we can figure
2290 * out in what direction backlight should work on a given
2291 * panel ?
2292 */
2293 if ((rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9)
2294 && !machine_is_compatible("PowerBook4,3"))
2295 conv_table = backlight_conv_m7;
2296 else
2297 conv_table = backlight_conv_m6;
2298
2299 lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
2300 if (on && (level > BACKLIGHT_OFF)) {
2301 lvds_gen_cntl |= LVDS_DIGON;
2302 if (!(lvds_gen_cntl & LVDS_ON)) {
2303 lvds_gen_cntl &= ~LVDS_BLON;
2304 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2305 (void)INREG(LVDS_GEN_CNTL);
2306 mdelay(10);
2307 lvds_gen_cntl |= LVDS_BLON;
2308 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2309 }
2310 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2311 lvds_gen_cntl |= (conv_table[level] <<
2312 LVDS_BL_MOD_LEVEL_SHIFT);
2313 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
2314 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
2315 } else {
2316 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2317 lvds_gen_cntl |= (conv_table[0] <<
2318 LVDS_BL_MOD_LEVEL_SHIFT);
2319 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2320 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2321 udelay(10);
2322 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
2323 }
2324
2325 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2326 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2327 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2328
2329 return 0;
2330}
2331
2332static int radeon_set_backlight_level(int level, void *data)
2333{
2334 return radeon_set_backlight_enable(1, level, data);
2335}
2336#endif /* CONFIG_PMAC_BACKLIGHT */
2337
2338
2339#ifdef CONFIG_PMAC_PBOOK
2340
2341static u32 dbg_clk;
2342
2343/*
2344 * Radeon M6 Power Management code. This code currently only supports
2345 * the mobile chips, it's based from some informations provided by ATI
2346 * along with hours of tracing of MacOS drivers
2347 */
2348
2349static void radeon_pm_save_regs(struct radeonfb_info *rinfo)
2350{
2351 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
2352 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
2353 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
2354 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
2355 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
2356 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
2357 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
2358 rinfo->save_regs[7] = INPLL(MCLK_MISC);
2359 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
2360
2361 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
2362 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
2363 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
2364 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
2365 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
2366 rinfo->save_regs[14] = INREG(BUS_CNTL1);
2367 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
2368 rinfo->save_regs[16] = INREG(AGP_CNTL);
2369 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2370 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2371 rinfo->save_regs[19] = INREG(GPIOPAD_A);
2372 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
2373 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
2374 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
2375 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
2376 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
2377 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
2378 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
2379 rinfo->save_regs[27] = INREG(GPIO_MONID);
2380 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
2381
2382 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
2383 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
2384 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
2385 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
2386 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
2387}
2388
2389static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
2390{
2391 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
2392
2393 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2394 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2395 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
2396 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
2397 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2398 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
2399 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
2400 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
2401
2402 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2403 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
2404 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
2405 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
2406 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
2407 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
2408 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
2409 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2410 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
2411 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
2412
2413 // wait VBL before that one ?
2414 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
2415
2416 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2417 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2418 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2419 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
2420 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
2421 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
2422 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
2423 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
2424 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
2425 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
2426}
2427
2428static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
2429{
2430 OUTREG(GPIOPAD_MASK, 0x0001ffff);
2431 OUTREG(GPIOPAD_EN, 0x00000400);
2432 OUTREG(GPIOPAD_A, 0x00000000);
2433 OUTREG(ZV_LCDPAD_MASK, 0x00000000);
2434 OUTREG(ZV_LCDPAD_EN, 0x00000000);
2435 OUTREG(ZV_LCDPAD_A, 0x00000000);
2436 OUTREG(GPIO_VGA_DDC, 0x00030000);
2437 OUTREG(GPIO_DVI_DDC, 0x00000000);
2438 OUTREG(GPIO_MONID, 0x00030000);
2439 OUTREG(GPIO_CRT2_DDC, 0x00000000);
2440}
2441
2442static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
2443{
2444//
2445// u32 reg;
2446//
2447// OUTPLL(P2PLL_REF_DIV, 0x0c);
2448//
2449// .../... figure out what macos does here
2450}
2451
2452static void radeon_pm_low_current(struct radeonfb_info *rinfo)
2453{
2454 u32 reg;
2455
2456 reg = INREG(BUS_CNTL1);
2457 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
2458 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
2459 OUTREG(BUS_CNTL1, reg);
2460
2461 reg = INPLL(PLL_PWRMGT_CNTL);
2462 reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
2463 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
2464 reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2465 reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
2466 OUTPLL(PLL_PWRMGT_CNTL, reg);
2467
2468// reg = INPLL(TV_PLL_CNTL1);
2469// reg |= TV_PLL_CNTL1__TVPLL_RESET | TV_PLL_CNTL1__TVPLL_SLEEP;
2470// OUTPLL(TV_PLL_CNTL1, reg);
2471
2472 reg = INREG(TV_DAC_CNTL);
2473 reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
2474 reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
2475 TV_DAC_CNTL_BDACPD |
2476 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
2477 OUTREG(TV_DAC_CNTL, reg);
2478
2479 reg = INREG(TMDS_TRANSMITTER_CNTL);
2480 reg &= ~(TMDS_PLL_EN |TMDS_PLLRST);
2481 OUTREG(TMDS_TRANSMITTER_CNTL, reg);
2482
2483// lvds_pll_cntl = regr32(g, LVDS_PLL_CNTL);
2484// lvds_pll_cntl &= ~LVDS_PLL_CNTL__LVDS_PLL_EN;
2485// lvds_pll_cntl |= LVDS_PLL_CNTL__LVDS_PLL_RESET;
2486// regw32(g, LVDS_PLL_CNTL, lvds_pll_cntl);
2487
2488 reg = INREG(DAC_CNTL);
2489 reg &= ~DAC_CMP_EN;
2490 OUTREG(DAC_CNTL, reg);
2491
2492 reg = INREG(DAC_CNTL2);
2493 reg &= ~DAC2_CMP_EN;
2494 OUTREG(DAC_CNTL2, reg);
2495
2496 reg = INREG(TV_DAC_CNTL);
2497 reg &= ~TV_DAC_CNTL_DETECT;
2498 OUTREG(TV_DAC_CNTL, reg);
2499}
2500
2501static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
2502{
2503 /* This code is disabled. It does what is in the pm_init
2504 * function of the MacOS driver code ATI sent me. However,
2505 * it doesn't fix my sleep problem, and is causing other issues
2506 * on wakeup (bascially the machine dying when switching consoles
2507 * I haven't had time to investigate this yet
2508 */
2509#if 0
2510 u32 disp_misc_cntl;
2511 u32 disp_pwr_man;
2512 u32 temp;
2513
2514 // set SPLL, MPLL, PPLL, P2PLL, TVPLL, SCLK, MCLK, PCLK, P2CLK,
2515 // TCLK and TEST_MODE to 0
2516 temp = INPLL(CLK_PWRMGT_CNTL);
2517 OUTPLL(CLK_PWRMGT_CNTL , temp & ~0xc00002ff);
2518
2519 // Turn on Power Management
2520 temp = INPLL(CLK_PWRMGT_CNTL);
2521 OUTPLL(CLK_PWRMGT_CNTL , temp | 0x00000400);
2522
2523 // Turn off display clock if using mobile chips
2524 temp = INPLL(CLK_PWRMGT_CNTL);
2525 OUTREG(CLK_PWRMGT_CNTL , temp | 0x00100000);
2526
2527 // Force PIXCLK_ALWAYS_ON and PIXCLK_DAC_ALWAYS_ON
2528 temp = INPLL(VCLK_ECP_CNTL);
2529 OUTPLL(VCLK_ECP_CNTL, temp & ~0x000000c0);
2530
2531 // Force ECP_FORCE_ON to 1
2532 temp = INPLL(VCLK_ECP_CNTL);
2533 OUTPLL(VCLK_ECP_CNTL, temp | 0x00040000);
2534
2535 // Force PIXCLK_BLEND_ALWAYS_ON and PIXCLK_GV_ALWAYS_ON
2536 temp = INPLL(PIXCLKS_CNTL);
2537 OUTPLL(PIXCLKS_CNTL, temp & ~0x00001800);
2538
2539 // Forcing SCLK_CNTL to ON
2540 OUTPLL(SCLK_CNTL, (INPLL(SCLK_CNTL)& 0x00000007) | 0xffff8000 );
2541
2542 // Set PM control over XTALIN pad
2543 temp = INPLL(CLK_PIN_CNTL);
2544 OUTPLL(CLK_PIN_CNTL, temp | 0x00080000);
2545
2546 // Force MCLK and YCLK and MC as dynamic
2547 temp = INPLL(MCLK_CNTL);
2548 OUTPLL(MCLK_CNTL, temp & 0xffeaffff);
2549
2550 // PLL_TURNOFF
2551 temp = INPLL(PLL_PWRMGT_CNTL);
2552 OUTPLL(PLL_PWRMGT_CNTL, temp | 0x0000001f);
2553
2554 // set MOBILE_SU to 1 if M6 or DDR64 is detected
2555 temp = INPLL(PLL_PWRMGT_CNTL);
2556 OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00010000);
2557
2558 // select PM access mode (PM_MODE_SEL) (use ACPI mode)
2559// temp = INPLL(PLL_PWRMGT_CNTL);
2560// OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00002000);
2561 temp = INPLL(PLL_PWRMGT_CNTL);
2562 OUTPLL(PLL_PWRMGT_CNTL, temp & ~0x00002000);
2563
2564 // set DISP_MISC_CNTL register
2565 disp_misc_cntl = INREG(DISP_MISC_CNTL);
2566 disp_misc_cntl &= ~( DISP_MISC_CNTL_SOFT_RESET_GRPH_PP |
2567 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP |
2568 DISP_MISC_CNTL_SOFT_RESET_OV0_PP |
2569 DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK |
2570 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK |
2571 DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK |
2572 DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP |
2573 DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK |
2574 DISP_MISC_CNTL_SOFT_RESET_LVDS |
2575 DISP_MISC_CNTL_SOFT_RESET_TMDS |
2576 DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS |
2577 DISP_MISC_CNTL_SOFT_RESET_TV);
2578 OUTREG(DISP_MISC_CNTL, disp_misc_cntl);
2579
2580 // set DISP_PWR_MAN register
2581 disp_pwr_man = INREG(DISP_PWR_MAN);
2582 // clau - 9.29.2000 - changes made to bit23:18 to set to 1 as requested by George
2583 disp_pwr_man |= (DISP_PWR_MAN_DIG_TMDS_ENABLE_RST |
2584 DISP_PWR_MAN_TV_ENABLE_RST |
2585 // DISP_PWR_MAN_AUTO_PWRUP_EN |
2586 DISP_PWR_MAN_DISP_D3_GRPH_RST |
2587 DISP_PWR_MAN_DISP_D3_SUBPIC_RST |
2588 DISP_PWR_MAN_DISP_D3_OV0_RST |
2589 DISP_PWR_MAN_DISP_D1D2_GRPH_RST |
2590 DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST |
2591 DISP_PWR_MAN_DISP_D1D2_OV0_RST);
2592 disp_pwr_man &= ~(DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN |
2593 DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN|
2594 DISP_PWR_MAN_DISP_D3_RST |
2595 DISP_PWR_MAN_DISP_D3_REG_RST);
2596 OUTREG(DISP_PWR_MAN, disp_pwr_man);
2597
2598 // clau - 10.24.2000
2599 // - add in setting for BUS_CNTL1 b27:26 = 0x01 and b31 = 0x1
2600 // - add in setting for AGP_CNTL b7:0 = 0x20
2601 // - add in setting for DVI_DDC_DATA_OUT_EN b17:16 = 0x0
2602
2603 // the following settings (two lines) are applied at a later part of this function, only on mobile platform
2604 // requres -mobile flag
2605 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & 0xf3ffffff) | 0x04000000);
2606 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | 0x80000000);
2607 OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & 0xffffff00) | 0x20);
2608 OUTREG(GPIO_DVI_DDC, INREG(GPIO_DVI_DDC) & 0xfffcffff);
2609
2610 // yulee - 12.12.2000
2611 // A12 only
2612 // EN_MCLK_TRISTATE_IN_SUSPEND@MCLK_MISC = 1
2613 // ACCESS_REGS_IN_SUSPEND@CLK_PIN_CNTL = 0
2614 // only on mobile platform
2615 OUTPLL(MCLK_MISC, INPLL(MCLK_MISC) | 0x00040000 );
2616
2617 // yulee -12.12.2000
2618 // AGPCLK_VALID@BUS_CNTL1 = 1
2619 // MOBILE_PLATFORM_SEL@BUS_CNTL1 = 01
2620 // CRTC_STEREO_SYNC_OUT_EN@CRTC_OFFSET_CNTL = 0
2621 // CG_CLK_TO_OUTPIN@CLK_PIN_CNTL = 0
2622 // only on mobile platform
2623 OUTPLL(CLK_PIN_CNTL, INPLL(CLK_PIN_CNTL ) & 0xFFFFF7FF );
2624 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1 ) & 0xF3FFFFFF) | 0x84000000 );
2625 OUTREG(CRTC_OFFSET_CNTL, INREG(CRTC_OFFSET_CNTL ) & 0xFFEFFFFF );
2626
2627 mdelay(100);
2628#endif
2629
2630 /* Disable CRTCs */
2631 OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
2632 OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2633 (void)INREG(CRTC2_GEN_CNTL);
2634 mdelay(17);
2635}
2636
2637static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2638{
2639 u16 pwr_cmd;
2640
2641 if (!rinfo->pm_reg)
2642 return;
2643
2644 /* Set the chip into appropriate suspend mode (we use D2,
2645 * D3 would require a compete re-initialization of the chip,
2646 * including PCI config registers, clocks, AGP conf, ...)
2647 */
2648 if (suspend) {
2649 /* According to ATI, we should program V2CLK here, I have
2650 * to verify what's up exactly
2651 */
2652 /* Save some registers */
2653 radeon_pm_save_regs(rinfo);
2654
2655 /* Check that on M7 too, might work might not. M7 may also
2656 * need explicit enabling of PM
2657 */
2658 if (rinfo->arch == RADEON_M6) {
2659 /* Program V2CLK */
2660 radeon_pm_program_v2clk(rinfo);
2661
2662 /* Disable IO PADs */
2663 radeon_pm_disable_iopad(rinfo);
2664
2665 /* Set low current */
2666 radeon_pm_low_current(rinfo);
2667
2668 /* Prepare chip for power management */
2669 radeon_pm_setup_for_suspend(rinfo);
2670
2671 /* Reset the MDLL */
2672 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
2673 (void)INPLL(MDLL_RDCKA);
2674 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2675 (void)INPLL(MDLL_RDCKA);
2676 }
2677
2678 /* Switch PCI power managment to D2. */
2679 for (;;) {
2680 pci_read_config_word(
2681 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2682 &pwr_cmd);
2683 if (pwr_cmd & 2)
2684 break;
2685 pci_write_config_word(
2686 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2687 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2688 mdelay(500);
2689 }
2690 } else {
2691 /* Switch back PCI powermanagment to D0 */
2692 mdelay(200);
2693 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2694 mdelay(500);
2695
2696 dbg_clk = INPLL(1);
2697
2698 /* Do we need that on M7 ? */
2699 if (rinfo->arch == RADEON_M6) {
2700 /* Restore the MDLL */
2701 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2702 (void)INPLL(MDLL_CKO);
2703 }
2704
2705 /* Restore some registers */
2706 radeon_pm_restore_regs(rinfo);
2707 }
2708}
2709
2710/*
2711 * Save the contents of the framebuffer when we go to sleep,
2712 * and restore it when we wake up again.
2713 */
2714
2715int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
2716{
2717 struct radeonfb_info *rinfo;
2718
2719 for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
2720 struct fb_fix_screeninfo fix;
2721 int nb;
2722 struct display *disp;
2723
2724 disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
2725
2726 switch (rinfo->arch) {
2727 case RADEON_M6:
2728 case RADEON_M7:
2729 case RADEON_M9:
2730 break;
2731 default:
2732 return PBOOK_SLEEP_REFUSE;
2733 }
2734
2735 radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
2736 nb = fb_display[fg_console].var.yres * fix.line_length;
2737
2738 switch (when) {
2739 case PBOOK_SLEEP_NOW:
2740 acquire_console_sem();
2741 disp->dispsw = &fbcon_dummy;
2742
2743 if (!noaccel) {
2744 /* Make sure engine is reset */
2745 radeon_engine_reset();
2746 radeon_engine_idle();
2747 }
2748
2749 /* Blank display and LCD */
2750 radeonfb_blank(VESA_POWERDOWN+1,
2751 (struct fb_info *)rinfo);
2752
2753 /* Sleep */
2754 rinfo->asleep = 1;
2755 radeon_set_suspend(rinfo, 1);
2756 release_console_sem();
2757
2758 break;
2759 case PBOOK_WAKE:
2760 acquire_console_sem();
2761 /* Wakeup */
2762 radeon_set_suspend(rinfo, 0);
2763
2764 if (!noaccel)
2765 radeon_engine_init(rinfo);
2766 rinfo->asleep = 0;
2767 radeon_set_dispsw(rinfo, disp);
2768 radeon_load_video_mode(rinfo, &disp->var);
2769 do_install_cmap(rinfo->currcon < 0 ? 0 : rinfo->currcon,
2770 (struct fb_info *)rinfo);
2771
2772 radeonfb_blank(0, (struct fb_info *)rinfo);
2773 release_console_sem();
2774 printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
2775 break;
2776 }
2777 }
2778
2779 return PBOOK_SLEEP_OK;
2780}
2781
2782#endif /* CONFIG_PMAC_PBOOK */
2783
2784static int radeonfb_pci_register (struct pci_dev *pdev,
2785 const struct pci_device_id *ent)
2786{
2787 struct radeonfb_info *rinfo;
2788 struct radeon_chip_info *rci = &radeon_chip_info[ent->driver_data];
2789 u32 tmp;
2790
2791 RTRACE("radeonfb_pci_register BEGIN\n");
2792
2793 /* Enable device in PCI config */
2794 if (pci_enable_device(pdev) != 0) {
2795 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2796 return -ENODEV;
2797 }
2798
2799 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
2800 if (!rinfo) {
2801 printk ("radeonfb: could not allocate memory\n");
2802 return -ENODEV;
2803 }
2804
2805 memset (rinfo, 0, sizeof (struct radeonfb_info));
2806 //info = &rinfo->info;
2807 rinfo->pdev = pdev;
2808 strcpy(rinfo->name, rci->name);
2809 rinfo->arch = rci->arch;
2810
2811 /* Set base addrs */
2812 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2813 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2814
2815 /* request the mem regions */
2816 if (!request_mem_region (rinfo->fb_base_phys,
2817 pci_resource_len(pdev, 0), "radeonfb")) {
2818 printk ("radeonfb: cannot reserve FB region\n");
2819 kfree (rinfo);
2820 return -ENODEV;
2821 }
2822
2823 if (!request_mem_region (rinfo->mmio_base_phys,
2824 pci_resource_len(pdev, 2), "radeonfb")) {
2825 printk ("radeonfb: cannot reserve MMIO region\n");
2826 release_mem_region (rinfo->fb_base_phys,
2827 pci_resource_len(pdev, 0));
2828 kfree (rinfo);
2829 return -ENODEV;
2830 }
2831
2832 /* map the regions */
2833 rinfo->mmio_base = ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
2834 if (!rinfo->mmio_base) {
2835 printk ("radeonfb: cannot map MMIO\n");
2836 release_mem_region (rinfo->mmio_base_phys,
2837 pci_resource_len(pdev, 2));
2838 release_mem_region (rinfo->fb_base_phys,
2839 pci_resource_len(pdev, 0));
2840 kfree (rinfo);
2841 return -ENODEV;
2842 }
2843
2844 rinfo->chipset = pdev->device;
2845
2846 switch (rinfo->arch) {
2847 case RADEON_R100:
2848 rinfo->hasCRTC2 = 0;
2849 break;
2850 default:
2851 /* all the rest have it */
2852 rinfo->hasCRTC2 = 1;
2853 break;
2854 }
2855#if 0
2856 if (rinfo->arch == RADEON_M7) {
2857 /*
2858 * Noticed some errors in accel with M7, will have to work these out...
2859 */
2860 noaccel = 1;
2861 }
2862#endif
2863 if (mirror)
2864 printk("radeonfb: mirroring display to CRT\n");
2865
2866 /* framebuffer size */
2867 tmp = INREG(CONFIG_MEMSIZE);
2868
2869 /* mem size is bits [28:0], mask off the rest */
2870 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2871
2872 /* ram type */
2873 tmp = INREG(MEM_SDRAM_MODE_REG);
2874 switch ((MEM_CFG_TYPE & tmp) >> 30) {
2875 case 0:
2876 /* SDR SGRAM (2:1) */
2877 strcpy(rinfo->ram_type, "SDR SGRAM");
2878 rinfo->ram.ml = 4;
2879 rinfo->ram.mb = 4;
2880 rinfo->ram.trcd = 1;
2881 rinfo->ram.trp = 2;
2882 rinfo->ram.twr = 1;
2883 rinfo->ram.cl = 2;
2884 rinfo->ram.loop_latency = 16;
2885 rinfo->ram.rloop = 16;
2886
2887 break;
2888 case 1:
2889 /* DDR SGRAM */
2890 strcpy(rinfo->ram_type, "DDR SGRAM");
2891 rinfo->ram.ml = 4;
2892 rinfo->ram.mb = 4;
2893 rinfo->ram.trcd = 3;
2894 rinfo->ram.trp = 3;
2895 rinfo->ram.twr = 2;
2896 rinfo->ram.cl = 3;
2897 rinfo->ram.tr2w = 1;
2898 rinfo->ram.loop_latency = 16;
2899 rinfo->ram.rloop = 16;
2900
2901 break;
2902 default:
2903 /* 64-bit SDR SGRAM */
2904 strcpy(rinfo->ram_type, "SDR SGRAM 64");
2905 rinfo->ram.ml = 4;
2906 rinfo->ram.mb = 8;
2907 rinfo->ram.trcd = 3;
2908 rinfo->ram.trp = 3;
2909 rinfo->ram.twr = 1;
2910 rinfo->ram.cl = 3;
2911 rinfo->ram.tr2w = 1;
2912 rinfo->ram.loop_latency = 17;
2913 rinfo->ram.rloop = 17;
2914
2915 break;
2916 }
2917
2918 rinfo->bios_seg = radeon_find_rom(rinfo);
2919 radeon_get_pllinfo(rinfo, rinfo->bios_seg);
2920
2921 /*
2922 * Hack to get around some busted production M6's
2923 * reporting no ram
2924 */
2925 if (rinfo->video_ram == 0) {
2926 switch (pdev->device) {
2927 case PCI_DEVICE_ID_ATI_RADEON_LY:
2928 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2929 rinfo->video_ram = 8192 * 1024;
2930 break;
2931 default:
2932 break;
2933 }
2934 }
2935
2936
2937 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2938
2939#if !defined(__powerpc__)
2940 radeon_get_moninfo(rinfo);
2941#else
2942 switch (pdev->device) {
2943 case PCI_DEVICE_ID_ATI_RADEON_LW:
2944 case PCI_DEVICE_ID_ATI_RADEON_LX:
2945 case PCI_DEVICE_ID_ATI_RADEON_LY:
2946 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2947 rinfo->dviDisp_type = MT_LCD;
2948 break;
2949 default:
2950 radeon_get_moninfo(rinfo);
2951 break;
2952 }
2953#endif
2954
2955 radeon_get_EDID(rinfo);
2956
2957 if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
2958 (rinfo->crtDisp_type == MT_DFP)) {
2959 if (!radeon_get_dfpinfo(rinfo)) {
2960 iounmap(rinfo->mmio_base);
2961 release_mem_region (rinfo->mmio_base_phys,
2962 pci_resource_len(pdev, 2));
2963 release_mem_region (rinfo->fb_base_phys,
2964 pci_resource_len(pdev, 0));
2965 kfree (rinfo);
2966 return -ENODEV;
2967 }
2968 }
2969
2970 rinfo->fb_base = ioremap (rinfo->fb_base_phys, rinfo->video_ram);
2971 if (!rinfo->fb_base) {
2972 printk ("radeonfb: cannot map FB\n");
2973 iounmap(rinfo->mmio_base);
2974 release_mem_region (rinfo->mmio_base_phys,
2975 pci_resource_len(pdev, 2));
2976 release_mem_region (rinfo->fb_base_phys,
2977 pci_resource_len(pdev, 0));
2978 kfree (rinfo);
2979 return -ENODEV;
2980 }
2981
2982 /* I SHOULD FIX THAT CRAP ! I should probably mimmic XFree DRI
2983 * driver setup here.
2984 *
2985 * On PPC, OF based cards setup the internal memory
2986 * mapping in strange ways. We change it so that the
2987 * framebuffer is mapped at 0 and given half of the card's
2988 * address space (2Gb). AGP is mapped high (0xe0000000) and
2989 * can use up to 512Mb. Once DRI is fully implemented, we
2990 * will have to setup the PCI remapper to remap the agp_special_page
2991 * memory page somewhere between those regions so that the card
2992 * use a normal PCI bus master cycle to access the ring read ptr.
2993 * --BenH.
2994 */
2995#ifdef CONFIG_ALL_PPC
2996 if (rinfo->hasCRTC2)
2997 OUTREG(CRTC2_GEN_CNTL,
2998 (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2999 OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
3000 OUTREG(MC_FB_LOCATION, 0x7fff0000);
3001 OUTREG(MC_AGP_LOCATION, 0xffffe000);
3002 OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
3003 if (rinfo->hasCRTC2)
3004 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
3005 OUTREG(SRC_OFFSET, 0x00000000);
3006 OUTREG(DST_OFFSET, 0x00000000);
3007 mdelay(10);
3008 OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
3009#endif /* CONFIG_ALL_PPC */
3010
3011 /* save current mode regs before we switch into the new one
3012 * so we can restore this upon __exit
3013 */
3014 radeon_save_state (rinfo, &rinfo->init_state);
3015
3016 /* set all the vital stuff */
3017 radeon_set_fbinfo (rinfo);
3018
3019 pci_set_drvdata(pdev, rinfo);
3020 rinfo->next = board_list;
3021 board_list = rinfo;
3022 ((struct fb_info *) rinfo)->device = &pdev->dev;
3023 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
3024 printk ("radeonfb: could not register framebuffer\n");
3025 iounmap(rinfo->fb_base);
3026 iounmap(rinfo->mmio_base);
3027 release_mem_region (rinfo->mmio_base_phys,
3028 pci_resource_len(pdev, 2));
3029 release_mem_region (rinfo->fb_base_phys,
3030 pci_resource_len(pdev, 0));
3031 kfree (rinfo);
3032 return -ENODEV;
3033 }
3034
3035#ifdef CONFIG_MTRR
3036 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
3037 rinfo->video_ram,
3038 MTRR_TYPE_WRCOMB, 1);
3039#endif
3040
3041#ifdef CONFIG_PMAC_BACKLIGHT
3042 if (rinfo->dviDisp_type == MT_LCD)
3043 register_backlight_controller(&radeon_backlight_controller,
3044 rinfo, "ati");
3045#endif
3046
3047#ifdef CONFIG_PMAC_PBOOK
3048 if (rinfo->dviDisp_type == MT_LCD) {
3049 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
3050 pmu_register_sleep_notifier(&radeon_sleep_notifier);
3051 }
3052#endif
3053
3054 printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type,
3055 (rinfo->video_ram/(1024*1024)));
3056
3057 if (rinfo->hasCRTC2) {
3058 printk("radeonfb: DVI port %s monitor connected\n",
3059 GET_MON_NAME(rinfo->dviDisp_type));
3060 printk("radeonfb: CRT port %s monitor connected\n",
3061 GET_MON_NAME(rinfo->crtDisp_type));
3062 } else {
3063 printk("radeonfb: CRT port %s monitor connected\n",
3064 GET_MON_NAME(rinfo->crtDisp_type));
3065 }
3066
3067 RTRACE("radeonfb_pci_register END\n");
3068
3069 return 0;
3070}
3071
3072
3073
3074static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
3075{
3076 struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
3077
3078 if (!rinfo)
3079 return;
3080
3081 /* restore original state
3082 *
3083 * Doesn't quite work yet, possibly because of the PPC hacking
3084 * I do on startup, disable for now. --BenH
3085 */
3086 radeon_write_mode (rinfo, &rinfo->init_state);
3087
3088#ifdef CONFIG_MTRR
3089 if (rinfo->mtrr_hdl >= 0)
3090 mtrr_del(rinfo->mtrr_hdl, 0, 0);
3091#endif
3092
3093 unregister_framebuffer ((struct fb_info *) rinfo);
3094
3095 iounmap(rinfo->mmio_base);
3096 iounmap(rinfo->fb_base);
3097
3098 release_mem_region (rinfo->mmio_base_phys,
3099 pci_resource_len(pdev, 2));
3100 release_mem_region (rinfo->fb_base_phys,
3101 pci_resource_len(pdev, 0));
3102
3103 kfree (rinfo);
3104}
3105
3106
3107static struct pci_driver radeonfb_driver = {
3108 .name = "radeonfb",
3109 .id_table = radeonfb_pci_table,
3110 .probe = radeonfb_pci_register,
3111 .remove = __devexit_p(radeonfb_pci_unregister),
3112};
3113
3114#ifndef MODULE
3115static int __init radeonfb_old_setup (char *options)
3116{
3117 char *this_opt;
3118
3119 if (!options || !*options)
3120 return 0;
3121
3122 while ((this_opt = strsep (&options, ",")) != NULL) {
3123 if (!*this_opt)
3124 continue;
3125 if (!strncmp(this_opt, "noaccel", 7)) {
3126 noaccel = 1;
3127 } else if (!strncmp(this_opt, "mirror", 6)) {
3128 mirror = 1;
3129 } else if (!strncmp(this_opt, "dfp", 3)) {
3130 force_dfp = 1;
3131 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
3132 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
3133 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3134 nomtrr = 1;
3135 } else
3136 mode_option = this_opt;
3137 }
3138
3139 return 0;
3140}
3141#endif /* MODULE */
3142
3143static int __init radeonfb_old_init (void)
3144{
3145#ifndef MODULE
3146 char *option = NULL;
3147
3148 if (fb_get_options("radeonfb_old", &option))
3149 return -ENODEV;
3150 radeonfb_old_setup(option);
3151#endif
3152 return pci_register_driver (&radeonfb_driver);
3153}
3154
3155
3156static void __exit radeonfb_old_exit (void)
3157{
3158 pci_unregister_driver (&radeonfb_driver);
3159}
3160
3161module_init(radeonfb_old_init);
3162module_exit(radeonfb_old_exit);
3163
3164
3165MODULE_AUTHOR("Ani Joshi");
3166MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
3167MODULE_LICENSE("GPL");
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c
index f841f013b96f..3e9308f0f165 100644
--- a/drivers/video/riva/fbdev.c
+++ b/drivers/video/riva/fbdev.c
@@ -49,6 +49,7 @@
49#include <asm/pci-bridge.h> 49#include <asm/pci-bridge.h>
50#endif 50#endif
51#ifdef CONFIG_PMAC_BACKLIGHT 51#ifdef CONFIG_PMAC_BACKLIGHT
52#include <asm/machdep.h>
52#include <asm/backlight.h> 53#include <asm/backlight.h>
53#endif 54#endif
54 55
@@ -1247,7 +1248,7 @@ static int rivafb_blank(int blank, struct fb_info *info)
1247 CRTCout(par, 0x1a, vesa); 1248 CRTCout(par, 0x1a, vesa);
1248 1249
1249#ifdef CONFIG_PMAC_BACKLIGHT 1250#ifdef CONFIG_PMAC_BACKLIGHT
1250 if ( par->FlatPanel && _machine == _MACH_Pmac) { 1251 if ( par->FlatPanel && machine_is(powermac)) {
1251 set_backlight_enable(!blank); 1252 set_backlight_enable(!blank);
1252 } 1253 }
1253#endif 1254#endif
@@ -2037,9 +2038,9 @@ static int __devinit rivafb_probe(struct pci_dev *pd,
2037 info->fix.smem_len / (1024 * 1024), 2038 info->fix.smem_len / (1024 * 1024),
2038 info->fix.smem_start); 2039 info->fix.smem_start);
2039#ifdef CONFIG_PMAC_BACKLIGHT 2040#ifdef CONFIG_PMAC_BACKLIGHT
2040 if (default_par->FlatPanel && _machine == _MACH_Pmac) 2041 if (default_par->FlatPanel && machine_is(powermac))
2041 register_backlight_controller(&riva_backlight_controller, 2042 register_backlight_controller(&riva_backlight_controller,
2042 default_par, "mnca"); 2043 default_par, "mnca");
2043#endif 2044#endif
2044 NVTRACE_LEAVE(); 2045 NVTRACE_LEAVE();
2045 return 0; 2046 return 0;
diff --git a/drivers/video/sticore.h b/drivers/video/sticore.h
index dc93336af557..1a9a60c74be3 100644
--- a/drivers/video/sticore.h
+++ b/drivers/video/sticore.h
@@ -34,36 +34,20 @@
34 * for them to fix it and steal their solution. prumpf 34 * for them to fix it and steal their solution. prumpf
35 */ 35 */
36 36
37#define STI_WAIT 1 37#include <asm/io.h>
38
39#include <asm/io.h> /* for USE_HPPA_IOREMAP */
40
41#if USE_HPPA_IOREMAP
42 38
43#define STI_PTR(p) (p) 39#define STI_WAIT 1
44#define PTR_STI(p) (p)
45static inline int STI_CALL( unsigned long func,
46 void *flags, void *inptr, void *outptr, void *glob_cfg )
47{
48 int (*f)(void *,void *,void *,void *);
49 f = (void*)func;
50 return f(flags, inptr, outptr, glob_cfg);
51}
52
53#else /* !USE_HPPA_IOREMAP */
54 40
55#define STI_PTR(p) ( virt_to_phys(p) ) 41#define STI_PTR(p) ( virt_to_phys(p) )
56#define PTR_STI(p) ( phys_to_virt((long)p) ) 42#define PTR_STI(p) ( phys_to_virt((unsigned long)p) )
57#define STI_CALL(func, flags, inptr, outptr, glob_cfg) \ 43#define STI_CALL(func, flags, inptr, outptr, glob_cfg) \
58 ({ \ 44 ({ \
59 pdc_sti_call( func, (unsigned long)STI_PTR(flags), \ 45 pdc_sti_call( func, STI_PTR(flags), \
60 (unsigned long)STI_PTR(inptr), \ 46 STI_PTR(inptr), \
61 (unsigned long)STI_PTR(outptr), \ 47 STI_PTR(outptr), \
62 (unsigned long)STI_PTR(glob_cfg)); \ 48 STI_PTR(glob_cfg)); \
63 }) 49 })
64 50
65#endif /* USE_HPPA_IOREMAP */
66
67 51
68#define sti_onscreen_x(sti) (sti->glob_cfg->onscreen_x) 52#define sti_onscreen_x(sti) (sti->glob_cfg->onscreen_x)
69#define sti_onscreen_y(sti) (sti->glob_cfg->onscreen_y) 53#define sti_onscreen_y(sti) (sti->glob_cfg->onscreen_y)
@@ -352,8 +336,9 @@ struct sti_struct {
352 struct sti_conf_outptr outptr; /* configuration */ 336 struct sti_conf_outptr outptr; /* configuration */
353 struct sti_conf_outptr_ext outptr_ext; 337 struct sti_conf_outptr_ext outptr_ext;
354 338
355 /* PCI data structures (pg. 17ff from sti.pdf) */
356 struct pci_dev *pd; 339 struct pci_dev *pd;
340
341 /* PCI data structures (pg. 17ff from sti.pdf) */
357 u8 rm_entry[16]; /* pci region mapper array == pci config space offset */ 342 u8 rm_entry[16]; /* pci region mapper array == pci config space offset */
358 343
359 /* pointer to the fb_info where this STI device is used */ 344 /* pointer to the fb_info where this STI device is used */
diff --git a/drivers/video/stifb.c b/drivers/video/stifb.c
index 56d71d6e9a72..4a292aae6eb2 100644
--- a/drivers/video/stifb.c
+++ b/drivers/video/stifb.c
@@ -3,7 +3,7 @@
3 * Low level Frame buffer driver for HP workstations with 3 * Low level Frame buffer driver for HP workstations with
4 * STI (standard text interface) video firmware. 4 * STI (standard text interface) video firmware.
5 * 5 *
6 * Copyright (C) 2001-2005 Helge Deller <deller@gmx.de> 6 * Copyright (C) 2001-2006 Helge Deller <deller@gmx.de>
7 * Portions Copyright (C) 2001 Thomas Bogendoerfer <tsbogend@alpha.franken.de> 7 * Portions Copyright (C) 2001 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
8 * 8 *
9 * Based on: 9 * Based on:
@@ -514,7 +514,7 @@ rattlerSetupPlanes(struct stifb_info *fb)
514 SETUP_HW(fb); 514 SETUP_HW(fb);
515 WRITE_BYTE(1, fb, REG_16b1); 515 WRITE_BYTE(1, fb, REG_16b1);
516 516
517 fb_memset(fb->info.fix.smem_start, 0xff, 517 fb_memset((void*)fb->info.fix.smem_start, 0xff,
518 fb->info.var.yres*fb->info.fix.line_length); 518 fb->info.var.yres*fb->info.fix.line_length);
519 519
520 CRX24_SET_OVLY_MASK(fb); 520 CRX24_SET_OVLY_MASK(fb);
@@ -908,83 +908,6 @@ SETUP_HCRX(struct stifb_info *fb)
908 908
909/* ------------------- driver specific functions --------------------------- */ 909/* ------------------- driver specific functions --------------------------- */
910 910
911#define TMPBUFLEN 2048
912
913static ssize_t
914stifb_read(struct file *file, char *buf, size_t count, loff_t *ppos)
915{
916 unsigned long p = *ppos;
917 struct inode *inode = file->f_dentry->d_inode;
918 int fbidx = iminor(inode);
919 struct fb_info *info = registered_fb[fbidx];
920 char tmpbuf[TMPBUFLEN];
921
922 if (!info || ! info->screen_base)
923 return -ENODEV;
924
925 if (p >= info->fix.smem_len)
926 return 0;
927 if (count >= info->fix.smem_len)
928 count = info->fix.smem_len;
929 if (count + p > info->fix.smem_len)
930 count = info->fix.smem_len - p;
931 if (count > sizeof(tmpbuf))
932 count = sizeof(tmpbuf);
933 if (count) {
934 char *base_addr;
935
936 base_addr = info->screen_base;
937 memcpy_fromio(&tmpbuf, base_addr+p, count);
938 count -= copy_to_user(buf, &tmpbuf, count);
939 if (!count)
940 return -EFAULT;
941 *ppos += count;
942 }
943 return count;
944}
945
946static ssize_t
947stifb_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
948{
949 struct inode *inode = file->f_dentry->d_inode;
950 int fbidx = iminor(inode);
951 struct fb_info *info = registered_fb[fbidx];
952 unsigned long p = *ppos;
953 size_t c;
954 int err;
955 char tmpbuf[TMPBUFLEN];
956
957 if (!info || !info->screen_base)
958 return -ENODEV;
959
960 if (p > info->fix.smem_len)
961 return -ENOSPC;
962 if (count >= info->fix.smem_len)
963 count = info->fix.smem_len;
964 err = 0;
965 if (count + p > info->fix.smem_len) {
966 count = info->fix.smem_len - p;
967 err = -ENOSPC;
968 }
969
970 p += (unsigned long)info->screen_base;
971 c = count;
972 while (c) {
973 int len = c > sizeof(tmpbuf) ? sizeof(tmpbuf) : c;
974 err = -EFAULT;
975 if (copy_from_user(&tmpbuf, buf, len))
976 break;
977 memcpy_toio(p, &tmpbuf, len);
978 c -= len;
979 p += len;
980 buf += len;
981 *ppos += len;
982 }
983 if (count-c)
984 return (count-c);
985 return err;
986}
987
988static int 911static int
989stifb_setcolreg(u_int regno, u_int red, u_int green, 912stifb_setcolreg(u_int regno, u_int red, u_int green,
990 u_int blue, u_int transp, struct fb_info *info) 913 u_int blue, u_int transp, struct fb_info *info)
@@ -1137,8 +1060,6 @@ stifb_init_display(struct stifb_info *fb)
1137 1060
1138static struct fb_ops stifb_ops = { 1061static struct fb_ops stifb_ops = {
1139 .owner = THIS_MODULE, 1062 .owner = THIS_MODULE,
1140 .fb_read = stifb_read,
1141 .fb_write = stifb_write,
1142 .fb_setcolreg = stifb_setcolreg, 1063 .fb_setcolreg = stifb_setcolreg,
1143 .fb_blank = stifb_blank, 1064 .fb_blank = stifb_blank,
1144 .fb_fillrect = cfb_fillrect, 1065 .fb_fillrect = cfb_fillrect,
@@ -1162,7 +1083,7 @@ stifb_init_fb(struct sti_struct *sti, int bpp_pref)
1162 char *dev_name; 1083 char *dev_name;
1163 int bpp, xres, yres; 1084 int bpp, xres, yres;
1164 1085
1165 fb = kmalloc(sizeof(*fb), GFP_ATOMIC); 1086 fb = kzalloc(sizeof(*fb), GFP_ATOMIC);
1166 if (!fb) { 1087 if (!fb) {
1167 printk(KERN_ERR "stifb: Could not allocate stifb structure\n"); 1088 printk(KERN_ERR "stifb: Could not allocate stifb structure\n");
1168 return -ENODEV; 1089 return -ENODEV;
@@ -1171,7 +1092,6 @@ stifb_init_fb(struct sti_struct *sti, int bpp_pref)
1171 info = &fb->info; 1092 info = &fb->info;
1172 1093
1173 /* set struct to a known state */ 1094 /* set struct to a known state */
1174 memset(fb, 0, sizeof(*fb));
1175 fix = &info->fix; 1095 fix = &info->fix;
1176 var = &info->var; 1096 var = &info->var;
1177 1097
@@ -1234,7 +1154,7 @@ stifb_init_fb(struct sti_struct *sti, int bpp_pref)
1234 case S9000_ID_TOMCAT: /* Dual CRX, behaves else like a CRX */ 1154 case S9000_ID_TOMCAT: /* Dual CRX, behaves else like a CRX */
1235 /* FIXME: TomCat supports two heads: 1155 /* FIXME: TomCat supports two heads:
1236 * fb.iobase = REGION_BASE(fb_info,3); 1156 * fb.iobase = REGION_BASE(fb_info,3);
1237 * fb.screen_base = (void*) REGION_BASE(fb_info,2); 1157 * fb.screen_base = ioremap_nocache(REGION_BASE(fb_info,2),xxx);
1238 * for now we only support the left one ! */ 1158 * for now we only support the left one ! */
1239 xres = fb->ngle_rom.x_size_visible; 1159 xres = fb->ngle_rom.x_size_visible;
1240 yres = fb->ngle_rom.y_size_visible; 1160 yres = fb->ngle_rom.y_size_visible;
@@ -1327,7 +1247,8 @@ stifb_init_fb(struct sti_struct *sti, int bpp_pref)
1327 1247
1328 strcpy(fix->id, "stifb"); 1248 strcpy(fix->id, "stifb");
1329 info->fbops = &stifb_ops; 1249 info->fbops = &stifb_ops;
1330 info->screen_base = (void*) REGION_BASE(fb,1); 1250 info->screen_base = ioremap_nocache(REGION_BASE(fb,1), fix->smem_len);
1251 info->screen_size = fix->smem_len;
1331 info->flags = FBINFO_DEFAULT; 1252 info->flags = FBINFO_DEFAULT;
1332 info->pseudo_palette = &fb->pseudo_palette; 1253 info->pseudo_palette = &fb->pseudo_palette;
1333 1254
@@ -1457,7 +1378,7 @@ stifb_setup(char *options)
1457 int i; 1378 int i;
1458 1379
1459 if (!options || !*options) 1380 if (!options || !*options)
1460 return 0; 1381 return 1;
1461 1382
1462 if (strncmp(options, "off", 3) == 0) { 1383 if (strncmp(options, "off", 3) == 0) {
1463 stifb_disabled = 1; 1384 stifb_disabled = 1;
@@ -1472,7 +1393,7 @@ stifb_setup(char *options)
1472 stifb_bpp_pref[i] = simple_strtoul(options, &options, 10); 1393 stifb_bpp_pref[i] = simple_strtoul(options, &options, 10);
1473 } 1394 }
1474 } 1395 }
1475 return 0; 1396 return 1;
1476} 1397}
1477 1398
1478__setup("stifb=", stifb_setup); 1399__setup("stifb=", stifb_setup);
diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c
index 8982e540214c..b0b9acfdd430 100644
--- a/drivers/video/vesafb.c
+++ b/drivers/video/vesafb.c
@@ -57,7 +57,7 @@ static unsigned short *pmi_base = NULL;
57static void (*pmi_start)(void); 57static void (*pmi_start)(void);
58static void (*pmi_pal)(void); 58static void (*pmi_pal)(void);
59static int depth; 59static int depth;
60 60static int vga_compat;
61/* --------------------------------------------------------------------- */ 61/* --------------------------------------------------------------------- */
62 62
63static int vesafb_pan_display(struct fb_var_screeninfo *var, 63static int vesafb_pan_display(struct fb_var_screeninfo *var,
@@ -83,9 +83,10 @@ static int vesafb_pan_display(struct fb_var_screeninfo *var,
83static void vesa_setpalette(int regno, unsigned red, unsigned green, 83static void vesa_setpalette(int regno, unsigned red, unsigned green,
84 unsigned blue) 84 unsigned blue)
85{ 85{
86 int shift = 16 - depth;
87
86#ifdef __i386__ 88#ifdef __i386__
87 struct { u_char blue, green, red, pad; } entry; 89 struct { u_char blue, green, red, pad; } entry;
88 int shift = 16 - depth;
89 90
90 if (pmi_setpal) { 91 if (pmi_setpal) {
91 entry.red = red >> shift; 92 entry.red = red >> shift;
@@ -101,14 +102,20 @@ static void vesa_setpalette(int regno, unsigned red, unsigned green,
101 "d" (regno), /* EDX */ 102 "d" (regno), /* EDX */
102 "D" (&entry), /* EDI */ 103 "D" (&entry), /* EDI */
103 "S" (&pmi_pal)); /* ESI */ 104 "S" (&pmi_pal)); /* ESI */
104 } else { 105 return;
105 /* without protected mode interface, try VGA registers... */ 106 }
107#endif
108
109/*
110 * without protected mode interface and if VGA compatible,
111 * try VGA registers...
112 */
113 if (vga_compat) {
106 outb_p(regno, dac_reg); 114 outb_p(regno, dac_reg);
107 outb_p(red >> shift, dac_val); 115 outb_p(red >> shift, dac_val);
108 outb_p(green >> shift, dac_val); 116 outb_p(green >> shift, dac_val);
109 outb_p(blue >> shift, dac_val); 117 outb_p(blue >> shift, dac_val);
110 } 118 }
111#endif
112} 119}
113 120
114static int vesafb_setcolreg(unsigned regno, unsigned red, unsigned green, 121static int vesafb_setcolreg(unsigned regno, unsigned red, unsigned green,
@@ -214,6 +221,7 @@ static int __init vesafb_probe(struct platform_device *dev)
214 if (screen_info.orig_video_isVGA != VIDEO_TYPE_VLFB) 221 if (screen_info.orig_video_isVGA != VIDEO_TYPE_VLFB)
215 return -ENODEV; 222 return -ENODEV;
216 223
224 vga_compat = (screen_info.capabilities & 2) ? 0 : 1;
217 vesafb_fix.smem_start = screen_info.lfb_base; 225 vesafb_fix.smem_start = screen_info.lfb_base;
218 vesafb_defined.bits_per_pixel = screen_info.lfb_depth; 226 vesafb_defined.bits_per_pixel = screen_info.lfb_depth;
219 if (15 == vesafb_defined.bits_per_pixel) 227 if (15 == vesafb_defined.bits_per_pixel)
@@ -318,6 +326,12 @@ static int __init vesafb_probe(struct platform_device *dev)
318 } 326 }
319 } 327 }
320 328
329 if (vesafb_defined.bits_per_pixel == 8 && !pmi_setpal && !vga_compat) {
330 printk(KERN_WARNING "vesafb: hardware palette is unchangeable,\n"
331 " colors may be incorrect\n");
332 vesafb_fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
333 }
334
321 vesafb_defined.xres_virtual = vesafb_defined.xres; 335 vesafb_defined.xres_virtual = vesafb_defined.xres;
322 vesafb_defined.yres_virtual = vesafb_fix.smem_len / vesafb_fix.line_length; 336 vesafb_defined.yres_virtual = vesafb_fix.smem_len / vesafb_fix.line_length;
323 if (ypan && vesafb_defined.yres_virtual > vesafb_defined.yres) { 337 if (ypan && vesafb_defined.yres_virtual > vesafb_defined.yres) {
@@ -354,7 +368,8 @@ static int __init vesafb_probe(struct platform_device *dev)
354 printk(KERN_INFO "vesafb: %s: " 368 printk(KERN_INFO "vesafb: %s: "
355 "size=%d:%d:%d:%d, shift=%d:%d:%d:%d\n", 369 "size=%d:%d:%d:%d, shift=%d:%d:%d:%d\n",
356 (vesafb_defined.bits_per_pixel > 8) ? 370 (vesafb_defined.bits_per_pixel > 8) ?
357 "Truecolor" : "Pseudocolor", 371 "Truecolor" : (vga_compat || pmi_setpal) ?
372 "Pseudocolor" : "Static Pseudocolor",
358 screen_info.rsvd_size, 373 screen_info.rsvd_size,
359 screen_info.red_size, 374 screen_info.red_size,
360 screen_info.green_size, 375 screen_info.green_size,
diff --git a/drivers/video/w100fb.c b/drivers/video/w100fb.c
index f6e24ee85f07..5fc86ea20692 100644
--- a/drivers/video/w100fb.c
+++ b/drivers/video/w100fb.c
@@ -4,8 +4,9 @@
4 * Frame Buffer Device for ATI Imageon w100 (Wallaby) 4 * Frame Buffer Device for ATI Imageon w100 (Wallaby)
5 * 5 *
6 * Copyright (C) 2002, ATI Corp. 6 * Copyright (C) 2002, ATI Corp.
7 * Copyright (C) 2004-2005 Richard Purdie 7 * Copyright (C) 2004-2006 Richard Purdie
8 * Copyright (c) 2005 Ian Molton 8 * Copyright (c) 2005 Ian Molton
9 * Copyright (c) 2006 Alberto Mardegan
9 * 10 *
10 * Rewritten for 2.6 by Richard Purdie <rpurdie@rpsys.net> 11 * Rewritten for 2.6 by Richard Purdie <rpurdie@rpsys.net>
11 * 12 *
@@ -14,6 +15,9 @@
14 * 15 *
15 * w32xx support by Ian Molton 16 * w32xx support by Ian Molton
16 * 17 *
18 * Hardware acceleration support by Alberto Mardegan
19 * <mardy@users.sourceforge.net>
20 *
17 * This program is free software; you can redistribute it and/or modify 21 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as 22 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation. 23 * published by the Free Software Foundation.
@@ -47,6 +51,7 @@ static void w100_set_dispregs(struct w100fb_par*);
47static void w100_update_enable(void); 51static void w100_update_enable(void);
48static void w100_update_disable(void); 52static void w100_update_disable(void);
49static void calc_hsync(struct w100fb_par *par); 53static void calc_hsync(struct w100fb_par *par);
54static void w100_init_graphic_engine(struct w100fb_par *par);
50struct w100_pll_info *w100_get_xtal_table(unsigned int freq); 55struct w100_pll_info *w100_get_xtal_table(unsigned int freq);
51 56
52/* Pseudo palette size */ 57/* Pseudo palette size */
@@ -248,6 +253,152 @@ static int w100fb_blank(int blank_mode, struct fb_info *info)
248} 253}
249 254
250 255
256static void w100_fifo_wait(int entries)
257{
258 union rbbm_status_u status;
259 int i;
260
261 for (i = 0; i < 2000000; i++) {
262 status.val = readl(remapped_regs + mmRBBM_STATUS);
263 if (status.f.cmdfifo_avail >= entries)
264 return;
265 udelay(1);
266 }
267 printk(KERN_ERR "w100fb: FIFO Timeout!\n");
268}
269
270
271static int w100fb_sync(struct fb_info *info)
272{
273 union rbbm_status_u status;
274 int i;
275
276 for (i = 0; i < 2000000; i++) {
277 status.val = readl(remapped_regs + mmRBBM_STATUS);
278 if (!status.f.gui_active)
279 return 0;
280 udelay(1);
281 }
282 printk(KERN_ERR "w100fb: Graphic engine timeout!\n");
283 return -EBUSY;
284}
285
286
287static void w100_init_graphic_engine(struct w100fb_par *par)
288{
289 union dp_gui_master_cntl_u gmc;
290 union dp_mix_u dp_mix;
291 union dp_datatype_u dp_datatype;
292 union dp_cntl_u dp_cntl;
293
294 w100_fifo_wait(4);
295 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET);
296 writel(par->xres, remapped_regs + mmDST_PITCH);
297 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET);
298 writel(par->xres, remapped_regs + mmSRC_PITCH);
299
300 w100_fifo_wait(3);
301 writel(0, remapped_regs + mmSC_TOP_LEFT);
302 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT);
303 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT);
304
305 w100_fifo_wait(4);
306 dp_cntl.val = 0;
307 dp_cntl.f.dst_x_dir = 1;
308 dp_cntl.f.dst_y_dir = 1;
309 dp_cntl.f.src_x_dir = 1;
310 dp_cntl.f.src_y_dir = 1;
311 dp_cntl.f.dst_major_x = 1;
312 dp_cntl.f.src_major_x = 1;
313 writel(dp_cntl.val, remapped_regs + mmDP_CNTL);
314
315 gmc.val = 0;
316 gmc.f.gmc_src_pitch_offset_cntl = 1;
317 gmc.f.gmc_dst_pitch_offset_cntl = 1;
318 gmc.f.gmc_src_clipping = 1;
319 gmc.f.gmc_dst_clipping = 1;
320 gmc.f.gmc_brush_datatype = GMC_BRUSH_NONE;
321 gmc.f.gmc_dst_datatype = 3; /* from DstType_16Bpp_444 */
322 gmc.f.gmc_src_datatype = SRC_DATATYPE_EQU_DST;
323 gmc.f.gmc_byte_pix_order = 1;
324 gmc.f.gmc_default_sel = 0;
325 gmc.f.gmc_rop3 = ROP3_SRCCOPY;
326 gmc.f.gmc_dp_src_source = DP_SRC_MEM_RECTANGULAR;
327 gmc.f.gmc_clr_cmp_fcn_dis = 1;
328 gmc.f.gmc_wr_msk_dis = 1;
329 gmc.f.gmc_dp_op = DP_OP_ROP;
330 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
331
332 dp_datatype.val = dp_mix.val = 0;
333 dp_datatype.f.dp_dst_datatype = gmc.f.gmc_dst_datatype;
334 dp_datatype.f.dp_brush_datatype = gmc.f.gmc_brush_datatype;
335 dp_datatype.f.dp_src2_type = 0;
336 dp_datatype.f.dp_src2_datatype = gmc.f.gmc_src_datatype;
337 dp_datatype.f.dp_src_datatype = gmc.f.gmc_src_datatype;
338 dp_datatype.f.dp_byte_pix_order = gmc.f.gmc_byte_pix_order;
339 writel(dp_datatype.val, remapped_regs + mmDP_DATATYPE);
340
341 dp_mix.f.dp_src_source = gmc.f.gmc_dp_src_source;
342 dp_mix.f.dp_src2_source = 1;
343 dp_mix.f.dp_rop3 = gmc.f.gmc_rop3;
344 dp_mix.f.dp_op = gmc.f.gmc_dp_op;
345 writel(dp_mix.val, remapped_regs + mmDP_MIX);
346}
347
348
349static void w100fb_fillrect(struct fb_info *info,
350 const struct fb_fillrect *rect)
351{
352 union dp_gui_master_cntl_u gmc;
353
354 if (info->state != FBINFO_STATE_RUNNING)
355 return;
356 if (info->flags & FBINFO_HWACCEL_DISABLED) {
357 cfb_fillrect(info, rect);
358 return;
359 }
360
361 gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
362 gmc.f.gmc_rop3 = ROP3_PATCOPY;
363 gmc.f.gmc_brush_datatype = GMC_BRUSH_SOLID_COLOR;
364 w100_fifo_wait(2);
365 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
366 writel(rect->color, remapped_regs + mmDP_BRUSH_FRGD_CLR);
367
368 w100_fifo_wait(2);
369 writel((rect->dy << 16) | (rect->dx & 0xffff), remapped_regs + mmDST_Y_X);
370 writel((rect->width << 16) | (rect->height & 0xffff),
371 remapped_regs + mmDST_WIDTH_HEIGHT);
372}
373
374
375static void w100fb_copyarea(struct fb_info *info,
376 const struct fb_copyarea *area)
377{
378 u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
379 u32 h = area->height, w = area->width;
380 union dp_gui_master_cntl_u gmc;
381
382 if (info->state != FBINFO_STATE_RUNNING)
383 return;
384 if (info->flags & FBINFO_HWACCEL_DISABLED) {
385 cfb_copyarea(info, area);
386 return;
387 }
388
389 gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
390 gmc.f.gmc_rop3 = ROP3_SRCCOPY;
391 gmc.f.gmc_brush_datatype = GMC_BRUSH_NONE;
392 w100_fifo_wait(1);
393 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
394
395 w100_fifo_wait(3);
396 writel((sy << 16) | (sx & 0xffff), remapped_regs + mmSRC_Y_X);
397 writel((dy << 16) | (dx & 0xffff), remapped_regs + mmDST_Y_X);
398 writel((w << 16) | (h & 0xffff), remapped_regs + mmDST_WIDTH_HEIGHT);
399}
400
401
251/* 402/*
252 * Change the resolution by calling the appropriate hardware functions 403 * Change the resolution by calling the appropriate hardware functions
253 */ 404 */
@@ -265,6 +416,7 @@ static void w100fb_activate_var(struct w100fb_par *par)
265 w100_init_lcd(par); 416 w100_init_lcd(par);
266 w100_set_dispregs(par); 417 w100_set_dispregs(par);
267 w100_update_enable(); 418 w100_update_enable();
419 w100_init_graphic_engine(par);
268 420
269 calc_hsync(par); 421 calc_hsync(par);
270 422
@@ -394,9 +546,10 @@ static struct fb_ops w100fb_ops = {
394 .fb_set_par = w100fb_set_par, 546 .fb_set_par = w100fb_set_par,
395 .fb_setcolreg = w100fb_setcolreg, 547 .fb_setcolreg = w100fb_setcolreg,
396 .fb_blank = w100fb_blank, 548 .fb_blank = w100fb_blank,
397 .fb_fillrect = cfb_fillrect, 549 .fb_fillrect = w100fb_fillrect,
398 .fb_copyarea = cfb_copyarea, 550 .fb_copyarea = w100fb_copyarea,
399 .fb_imageblit = cfb_imageblit, 551 .fb_imageblit = cfb_imageblit,
552 .fb_sync = w100fb_sync,
400}; 553};
401 554
402#ifdef CONFIG_PM 555#ifdef CONFIG_PM
@@ -543,7 +696,8 @@ int __init w100fb_probe(struct platform_device *pdev)
543 } 696 }
544 697
545 info->fbops = &w100fb_ops; 698 info->fbops = &w100fb_ops;
546 info->flags = FBINFO_DEFAULT; 699 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
700 FBINFO_HWACCEL_FILLRECT;
547 info->node = -1; 701 info->node = -1;
548 info->screen_base = remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE); 702 info->screen_base = remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE);
549 info->screen_size = REMAPPED_FB_LEN; 703 info->screen_size = REMAPPED_FB_LEN;
diff --git a/drivers/video/w100fb.h b/drivers/video/w100fb.h
index 7a58a1e3e427..fffae7b4f6e9 100644
--- a/drivers/video/w100fb.h
+++ b/drivers/video/w100fb.h
@@ -122,15 +122,32 @@
122/* Block DISPLAY End: */ 122/* Block DISPLAY End: */
123 123
124/* Block GFX Start: */ 124/* Block GFX Start: */
125#define mmDST_OFFSET 0x1004
126#define mmDST_PITCH 0x1008
127#define mmDST_Y_X 0x1038
128#define mmDST_WIDTH_HEIGHT 0x1198
129#define mmDP_GUI_MASTER_CNTL 0x106C
125#define mmBRUSH_OFFSET 0x108C 130#define mmBRUSH_OFFSET 0x108C
126#define mmBRUSH_Y_X 0x1074 131#define mmBRUSH_Y_X 0x1074
132#define mmDP_BRUSH_FRGD_CLR 0x107C
133#define mmSRC_OFFSET 0x11AC
134#define mmSRC_PITCH 0x11B0
135#define mmSRC_Y_X 0x1034
127#define mmDEFAULT_PITCH_OFFSET 0x10A0 136#define mmDEFAULT_PITCH_OFFSET 0x10A0
128#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8 137#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
129#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC 138#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
139#define mmSC_TOP_LEFT 0x11BC
140#define mmSC_BOTTOM_RIGHT 0x11C0
141#define mmSRC_SC_BOTTOM_RIGHT 0x11C4
130#define mmGLOBAL_ALPHA 0x1210 142#define mmGLOBAL_ALPHA 0x1210
131#define mmFILTER_COEF 0x1214 143#define mmFILTER_COEF 0x1214
132#define mmMVC_CNTL_START 0x11E0 144#define mmMVC_CNTL_START 0x11E0
133#define mmE2_ARITHMETIC_CNTL 0x1220 145#define mmE2_ARITHMETIC_CNTL 0x1220
146#define mmDP_CNTL 0x11C8
147#define mmDP_CNTL_DST_DIR 0x11CC
148#define mmDP_DATATYPE 0x12C4
149#define mmDP_MIX 0x12C8
150#define mmDP_WRITE_MSK 0x12CC
134#define mmENG_CNTL 0x13E8 151#define mmENG_CNTL 0x13E8
135#define mmENG_PERF_CNT 0x13F0 152#define mmENG_PERF_CNT 0x13F0
136/* Block GFX End: */ 153/* Block GFX End: */
@@ -179,6 +196,7 @@
179/* Block RBBM Start: */ 196/* Block RBBM Start: */
180#define mmWAIT_UNTIL 0x1400 197#define mmWAIT_UNTIL 0x1400
181#define mmISYNC_CNTL 0x1404 198#define mmISYNC_CNTL 0x1404
199#define mmRBBM_STATUS 0x0140
182#define mmRBBM_CNTL 0x0144 200#define mmRBBM_CNTL 0x0144
183#define mmNQWAIT_UNTIL 0x0150 201#define mmNQWAIT_UNTIL 0x0150
184/* Block RBBM End: */ 202/* Block RBBM End: */
@@ -225,147 +243,147 @@
225/* Register structure definitions */ 243/* Register structure definitions */
226 244
227struct wrap_top_dir_t { 245struct wrap_top_dir_t {
228 unsigned long top_addr : 23; 246 u32 top_addr : 23;
229 unsigned long : 9; 247 u32 : 9;
230} __attribute__((packed)); 248} __attribute__((packed));
231 249
232union wrap_top_dir_u { 250union wrap_top_dir_u {
233 unsigned long val : 32; 251 u32 val : 32;
234 struct wrap_top_dir_t f; 252 struct wrap_top_dir_t f;
235} __attribute__((packed)); 253} __attribute__((packed));
236 254
237struct wrap_start_dir_t { 255struct wrap_start_dir_t {
238 unsigned long start_addr : 23; 256 u32 start_addr : 23;
239 unsigned long : 9; 257 u32 : 9;
240} __attribute__((packed)); 258} __attribute__((packed));
241 259
242union wrap_start_dir_u { 260union wrap_start_dir_u {
243 unsigned long val : 32; 261 u32 val : 32;
244 struct wrap_start_dir_t f; 262 struct wrap_start_dir_t f;
245} __attribute__((packed)); 263} __attribute__((packed));
246 264
247struct cif_cntl_t { 265struct cif_cntl_t {
248 unsigned long swap_reg : 2; 266 u32 swap_reg : 2;
249 unsigned long swap_fbuf_1 : 2; 267 u32 swap_fbuf_1 : 2;
250 unsigned long swap_fbuf_2 : 2; 268 u32 swap_fbuf_2 : 2;
251 unsigned long swap_fbuf_3 : 2; 269 u32 swap_fbuf_3 : 2;
252 unsigned long pmi_int_disable : 1; 270 u32 pmi_int_disable : 1;
253 unsigned long pmi_schmen_disable : 1; 271 u32 pmi_schmen_disable : 1;
254 unsigned long intb_oe : 1; 272 u32 intb_oe : 1;
255 unsigned long en_wait_to_compensate_dq_prop_dly : 1; 273 u32 en_wait_to_compensate_dq_prop_dly : 1;
256 unsigned long compensate_wait_rd_size : 2; 274 u32 compensate_wait_rd_size : 2;
257 unsigned long wait_asserted_timeout_val : 2; 275 u32 wait_asserted_timeout_val : 2;
258 unsigned long wait_masked_val : 2; 276 u32 wait_masked_val : 2;
259 unsigned long en_wait_timeout : 1; 277 u32 en_wait_timeout : 1;
260 unsigned long en_one_clk_setup_before_wait : 1; 278 u32 en_one_clk_setup_before_wait : 1;
261 unsigned long interrupt_active_high : 1; 279 u32 interrupt_active_high : 1;
262 unsigned long en_overwrite_straps : 1; 280 u32 en_overwrite_straps : 1;
263 unsigned long strap_wait_active_hi : 1; 281 u32 strap_wait_active_hi : 1;
264 unsigned long lat_busy_count : 2; 282 u32 lat_busy_count : 2;
265 unsigned long lat_rd_pm4_sclk_busy : 1; 283 u32 lat_rd_pm4_sclk_busy : 1;
266 unsigned long dis_system_bits : 1; 284 u32 dis_system_bits : 1;
267 unsigned long dis_mr : 1; 285 u32 dis_mr : 1;
268 unsigned long cif_spare_1 : 4; 286 u32 cif_spare_1 : 4;
269} __attribute__((packed)); 287} __attribute__((packed));
270 288
271union cif_cntl_u { 289union cif_cntl_u {
272 unsigned long val : 32; 290 u32 val : 32;
273 struct cif_cntl_t f; 291 struct cif_cntl_t f;
274} __attribute__((packed)); 292} __attribute__((packed));
275 293
276struct cfgreg_base_t { 294struct cfgreg_base_t {
277 unsigned long cfgreg_base : 24; 295 u32 cfgreg_base : 24;
278 unsigned long : 8; 296 u32 : 8;
279} __attribute__((packed)); 297} __attribute__((packed));
280 298
281union cfgreg_base_u { 299union cfgreg_base_u {
282 unsigned long val : 32; 300 u32 val : 32;
283 struct cfgreg_base_t f; 301 struct cfgreg_base_t f;
284} __attribute__((packed)); 302} __attribute__((packed));
285 303
286struct cif_io_t { 304struct cif_io_t {
287 unsigned long dq_srp : 1; 305 u32 dq_srp : 1;
288 unsigned long dq_srn : 1; 306 u32 dq_srn : 1;
289 unsigned long dq_sp : 4; 307 u32 dq_sp : 4;
290 unsigned long dq_sn : 4; 308 u32 dq_sn : 4;
291 unsigned long waitb_srp : 1; 309 u32 waitb_srp : 1;
292 unsigned long waitb_srn : 1; 310 u32 waitb_srn : 1;
293 unsigned long waitb_sp : 4; 311 u32 waitb_sp : 4;
294 unsigned long waitb_sn : 4; 312 u32 waitb_sn : 4;
295 unsigned long intb_srp : 1; 313 u32 intb_srp : 1;
296 unsigned long intb_srn : 1; 314 u32 intb_srn : 1;
297 unsigned long intb_sp : 4; 315 u32 intb_sp : 4;
298 unsigned long intb_sn : 4; 316 u32 intb_sn : 4;
299 unsigned long : 2; 317 u32 : 2;
300} __attribute__((packed)); 318} __attribute__((packed));
301 319
302union cif_io_u { 320union cif_io_u {
303 unsigned long val : 32; 321 u32 val : 32;
304 struct cif_io_t f; 322 struct cif_io_t f;
305} __attribute__((packed)); 323} __attribute__((packed));
306 324
307struct cif_read_dbg_t { 325struct cif_read_dbg_t {
308 unsigned long unpacker_pre_fetch_trig_gen : 2; 326 u32 unpacker_pre_fetch_trig_gen : 2;
309 unsigned long dly_second_rd_fetch_trig : 1; 327 u32 dly_second_rd_fetch_trig : 1;
310 unsigned long rst_rd_burst_id : 1; 328 u32 rst_rd_burst_id : 1;
311 unsigned long dis_rd_burst_id : 1; 329 u32 dis_rd_burst_id : 1;
312 unsigned long en_block_rd_when_packer_is_not_emp : 1; 330 u32 en_block_rd_when_packer_is_not_emp : 1;
313 unsigned long dis_pre_fetch_cntl_sm : 1; 331 u32 dis_pre_fetch_cntl_sm : 1;
314 unsigned long rbbm_chrncy_dis : 1; 332 u32 rbbm_chrncy_dis : 1;
315 unsigned long rbbm_rd_after_wr_lat : 2; 333 u32 rbbm_rd_after_wr_lat : 2;
316 unsigned long dis_be_during_rd : 1; 334 u32 dis_be_during_rd : 1;
317 unsigned long one_clk_invalidate_pulse : 1; 335 u32 one_clk_invalidate_pulse : 1;
318 unsigned long dis_chnl_priority : 1; 336 u32 dis_chnl_priority : 1;
319 unsigned long rst_read_path_a_pls : 1; 337 u32 rst_read_path_a_pls : 1;
320 unsigned long rst_read_path_b_pls : 1; 338 u32 rst_read_path_b_pls : 1;
321 unsigned long dis_reg_rd_fetch_trig : 1; 339 u32 dis_reg_rd_fetch_trig : 1;
322 unsigned long dis_rd_fetch_trig_from_ind_addr : 1; 340 u32 dis_rd_fetch_trig_from_ind_addr : 1;
323 unsigned long dis_rd_same_byte_to_trig_fetch : 1; 341 u32 dis_rd_same_byte_to_trig_fetch : 1;
324 unsigned long dis_dir_wrap : 1; 342 u32 dis_dir_wrap : 1;
325 unsigned long dis_ring_buf_to_force_dec : 1; 343 u32 dis_ring_buf_to_force_dec : 1;
326 unsigned long dis_addr_comp_in_16bit : 1; 344 u32 dis_addr_comp_in_16bit : 1;
327 unsigned long clr_w : 1; 345 u32 clr_w : 1;
328 unsigned long err_rd_tag_is_3 : 1; 346 u32 err_rd_tag_is_3 : 1;
329 unsigned long err_load_when_ful_a : 1; 347 u32 err_load_when_ful_a : 1;
330 unsigned long err_load_when_ful_b : 1; 348 u32 err_load_when_ful_b : 1;
331 unsigned long : 7; 349 u32 : 7;
332} __attribute__((packed)); 350} __attribute__((packed));
333 351
334union cif_read_dbg_u { 352union cif_read_dbg_u {
335 unsigned long val : 32; 353 u32 val : 32;
336 struct cif_read_dbg_t f; 354 struct cif_read_dbg_t f;
337} __attribute__((packed)); 355} __attribute__((packed));
338 356
339struct cif_write_dbg_t { 357struct cif_write_dbg_t {
340 unsigned long packer_timeout_count : 2; 358 u32 packer_timeout_count : 2;
341 unsigned long en_upper_load_cond : 1; 359 u32 en_upper_load_cond : 1;
342 unsigned long en_chnl_change_cond : 1; 360 u32 en_chnl_change_cond : 1;
343 unsigned long dis_addr_comp_cond : 1; 361 u32 dis_addr_comp_cond : 1;
344 unsigned long dis_load_same_byte_addr_cond : 1; 362 u32 dis_load_same_byte_addr_cond : 1;
345 unsigned long dis_timeout_cond : 1; 363 u32 dis_timeout_cond : 1;
346 unsigned long dis_timeout_during_rbbm : 1; 364 u32 dis_timeout_during_rbbm : 1;
347 unsigned long dis_packer_ful_during_rbbm_timeout : 1; 365 u32 dis_packer_ful_during_rbbm_timeout : 1;
348 unsigned long en_dword_split_to_rbbm : 1; 366 u32 en_dword_split_to_rbbm : 1;
349 unsigned long en_dummy_val : 1; 367 u32 en_dummy_val : 1;
350 unsigned long dummy_val_sel : 1; 368 u32 dummy_val_sel : 1;
351 unsigned long mask_pm4_wrptr_dec : 1; 369 u32 mask_pm4_wrptr_dec : 1;
352 unsigned long dis_mc_clean_cond : 1; 370 u32 dis_mc_clean_cond : 1;
353 unsigned long err_two_reqi_during_ful : 1; 371 u32 err_two_reqi_during_ful : 1;
354 unsigned long err_reqi_during_idle_clk : 1; 372 u32 err_reqi_during_idle_clk : 1;
355 unsigned long err_global : 1; 373 u32 err_global : 1;
356 unsigned long en_wr_buf_dbg_load : 1; 374 u32 en_wr_buf_dbg_load : 1;
357 unsigned long en_wr_buf_dbg_path : 1; 375 u32 en_wr_buf_dbg_path : 1;
358 unsigned long sel_wr_buf_byte : 3; 376 u32 sel_wr_buf_byte : 3;
359 unsigned long dis_rd_flush_wr : 1; 377 u32 dis_rd_flush_wr : 1;
360 unsigned long dis_packer_ful_cond : 1; 378 u32 dis_packer_ful_cond : 1;
361 unsigned long dis_invalidate_by_ops_chnl : 1; 379 u32 dis_invalidate_by_ops_chnl : 1;
362 unsigned long en_halt_when_reqi_err : 1; 380 u32 en_halt_when_reqi_err : 1;
363 unsigned long cif_spare_2 : 5; 381 u32 cif_spare_2 : 5;
364 unsigned long : 1; 382 u32 : 1;
365} __attribute__((packed)); 383} __attribute__((packed));
366 384
367union cif_write_dbg_u { 385union cif_write_dbg_u {
368 unsigned long val : 32; 386 u32 val : 32;
369 struct cif_write_dbg_t f; 387 struct cif_write_dbg_t f;
370} __attribute__((packed)); 388} __attribute__((packed));
371 389
@@ -403,327 +421,327 @@ union cpu_defaults_u {
403} __attribute__((packed)); 421} __attribute__((packed));
404 422
405struct crtc_total_t { 423struct crtc_total_t {
406 unsigned long crtc_h_total : 10; 424 u32 crtc_h_total : 10;
407 unsigned long : 6; 425 u32 : 6;
408 unsigned long crtc_v_total : 10; 426 u32 crtc_v_total : 10;
409 unsigned long : 6; 427 u32 : 6;
410} __attribute__((packed)); 428} __attribute__((packed));
411 429
412union crtc_total_u { 430union crtc_total_u {
413 unsigned long val : 32; 431 u32 val : 32;
414 struct crtc_total_t f; 432 struct crtc_total_t f;
415} __attribute__((packed)); 433} __attribute__((packed));
416 434
417struct crtc_ss_t { 435struct crtc_ss_t {
418 unsigned long ss_start : 10; 436 u32 ss_start : 10;
419 unsigned long : 6; 437 u32 : 6;
420 unsigned long ss_end : 10; 438 u32 ss_end : 10;
421 unsigned long : 2; 439 u32 : 2;
422 unsigned long ss_align : 1; 440 u32 ss_align : 1;
423 unsigned long ss_pol : 1; 441 u32 ss_pol : 1;
424 unsigned long ss_run_mode : 1; 442 u32 ss_run_mode : 1;
425 unsigned long ss_en : 1; 443 u32 ss_en : 1;
426} __attribute__((packed)); 444} __attribute__((packed));
427 445
428union crtc_ss_u { 446union crtc_ss_u {
429 unsigned long val : 32; 447 u32 val : 32;
430 struct crtc_ss_t f; 448 struct crtc_ss_t f;
431} __attribute__((packed)); 449} __attribute__((packed));
432 450
433struct active_h_disp_t { 451struct active_h_disp_t {
434 unsigned long active_h_start : 10; 452 u32 active_h_start : 10;
435 unsigned long : 6; 453 u32 : 6;
436 unsigned long active_h_end : 10; 454 u32 active_h_end : 10;
437 unsigned long : 6; 455 u32 : 6;
438} __attribute__((packed)); 456} __attribute__((packed));
439 457
440union active_h_disp_u { 458union active_h_disp_u {
441 unsigned long val : 32; 459 u32 val : 32;
442 struct active_h_disp_t f; 460 struct active_h_disp_t f;
443} __attribute__((packed)); 461} __attribute__((packed));
444 462
445struct active_v_disp_t { 463struct active_v_disp_t {
446 unsigned long active_v_start : 10; 464 u32 active_v_start : 10;
447 unsigned long : 6; 465 u32 : 6;
448 unsigned long active_v_end : 10; 466 u32 active_v_end : 10;
449 unsigned long : 6; 467 u32 : 6;
450} __attribute__((packed)); 468} __attribute__((packed));
451 469
452union active_v_disp_u { 470union active_v_disp_u {
453 unsigned long val : 32; 471 u32 val : 32;
454 struct active_v_disp_t f; 472 struct active_v_disp_t f;
455} __attribute__((packed)); 473} __attribute__((packed));
456 474
457struct graphic_h_disp_t { 475struct graphic_h_disp_t {
458 unsigned long graphic_h_start : 10; 476 u32 graphic_h_start : 10;
459 unsigned long : 6; 477 u32 : 6;
460 unsigned long graphic_h_end : 10; 478 u32 graphic_h_end : 10;
461 unsigned long : 6; 479 u32 : 6;
462} __attribute__((packed)); 480} __attribute__((packed));
463 481
464union graphic_h_disp_u { 482union graphic_h_disp_u {
465 unsigned long val : 32; 483 u32 val : 32;
466 struct graphic_h_disp_t f; 484 struct graphic_h_disp_t f;
467} __attribute__((packed)); 485} __attribute__((packed));
468 486
469struct graphic_v_disp_t { 487struct graphic_v_disp_t {
470 unsigned long graphic_v_start : 10; 488 u32 graphic_v_start : 10;
471 unsigned long : 6; 489 u32 : 6;
472 unsigned long graphic_v_end : 10; 490 u32 graphic_v_end : 10;
473 unsigned long : 6; 491 u32 : 6;
474} __attribute__((packed)); 492} __attribute__((packed));
475 493
476union graphic_v_disp_u{ 494union graphic_v_disp_u{
477 unsigned long val : 32; 495 u32 val : 32;
478 struct graphic_v_disp_t f; 496 struct graphic_v_disp_t f;
479} __attribute__((packed)); 497} __attribute__((packed));
480 498
481struct graphic_ctrl_t_w100 { 499struct graphic_ctrl_t_w100 {
482 unsigned long color_depth : 3; 500 u32 color_depth : 3;
483 unsigned long portrait_mode : 2; 501 u32 portrait_mode : 2;
484 unsigned long low_power_on : 1; 502 u32 low_power_on : 1;
485 unsigned long req_freq : 4; 503 u32 req_freq : 4;
486 unsigned long en_crtc : 1; 504 u32 en_crtc : 1;
487 unsigned long en_graphic_req : 1; 505 u32 en_graphic_req : 1;
488 unsigned long en_graphic_crtc : 1; 506 u32 en_graphic_crtc : 1;
489 unsigned long total_req_graphic : 9; 507 u32 total_req_graphic : 9;
490 unsigned long lcd_pclk_on : 1; 508 u32 lcd_pclk_on : 1;
491 unsigned long lcd_sclk_on : 1; 509 u32 lcd_sclk_on : 1;
492 unsigned long pclk_running : 1; 510 u32 pclk_running : 1;
493 unsigned long sclk_running : 1; 511 u32 sclk_running : 1;
494 unsigned long : 6; 512 u32 : 6;
495} __attribute__((packed)); 513} __attribute__((packed));
496 514
497struct graphic_ctrl_t_w32xx { 515struct graphic_ctrl_t_w32xx {
498 unsigned long color_depth : 3; 516 u32 color_depth : 3;
499 unsigned long portrait_mode : 2; 517 u32 portrait_mode : 2;
500 unsigned long low_power_on : 1; 518 u32 low_power_on : 1;
501 unsigned long req_freq : 4; 519 u32 req_freq : 4;
502 unsigned long en_crtc : 1; 520 u32 en_crtc : 1;
503 unsigned long en_graphic_req : 1; 521 u32 en_graphic_req : 1;
504 unsigned long en_graphic_crtc : 1; 522 u32 en_graphic_crtc : 1;
505 unsigned long total_req_graphic : 10; 523 u32 total_req_graphic : 10;
506 unsigned long lcd_pclk_on : 1; 524 u32 lcd_pclk_on : 1;
507 unsigned long lcd_sclk_on : 1; 525 u32 lcd_sclk_on : 1;
508 unsigned long pclk_running : 1; 526 u32 pclk_running : 1;
509 unsigned long sclk_running : 1; 527 u32 sclk_running : 1;
510 unsigned long : 5; 528 u32 : 5;
511} __attribute__((packed)); 529} __attribute__((packed));
512 530
513union graphic_ctrl_u { 531union graphic_ctrl_u {
514 unsigned long val : 32; 532 u32 val : 32;
515 struct graphic_ctrl_t_w100 f_w100; 533 struct graphic_ctrl_t_w100 f_w100;
516 struct graphic_ctrl_t_w32xx f_w32xx; 534 struct graphic_ctrl_t_w32xx f_w32xx;
517} __attribute__((packed)); 535} __attribute__((packed));
518 536
519struct video_ctrl_t { 537struct video_ctrl_t {
520 unsigned long video_mode : 1; 538 u32 video_mode : 1;
521 unsigned long keyer_en : 1; 539 u32 keyer_en : 1;
522 unsigned long en_video_req : 1; 540 u32 en_video_req : 1;
523 unsigned long en_graphic_req_video : 1; 541 u32 en_graphic_req_video : 1;
524 unsigned long en_video_crtc : 1; 542 u32 en_video_crtc : 1;
525 unsigned long video_hor_exp : 2; 543 u32 video_hor_exp : 2;
526 unsigned long video_ver_exp : 2; 544 u32 video_ver_exp : 2;
527 unsigned long uv_combine : 1; 545 u32 uv_combine : 1;
528 unsigned long total_req_video : 9; 546 u32 total_req_video : 9;
529 unsigned long video_ch_sel : 1; 547 u32 video_ch_sel : 1;
530 unsigned long video_portrait : 2; 548 u32 video_portrait : 2;
531 unsigned long yuv2rgb_en : 1; 549 u32 yuv2rgb_en : 1;
532 unsigned long yuv2rgb_option : 1; 550 u32 yuv2rgb_option : 1;
533 unsigned long video_inv_hor : 1; 551 u32 video_inv_hor : 1;
534 unsigned long video_inv_ver : 1; 552 u32 video_inv_ver : 1;
535 unsigned long gamma_sel : 2; 553 u32 gamma_sel : 2;
536 unsigned long dis_limit : 1; 554 u32 dis_limit : 1;
537 unsigned long en_uv_hblend : 1; 555 u32 en_uv_hblend : 1;
538 unsigned long rgb_gamma_sel : 2; 556 u32 rgb_gamma_sel : 2;
539} __attribute__((packed)); 557} __attribute__((packed));
540 558
541union video_ctrl_u { 559union video_ctrl_u {
542 unsigned long val : 32; 560 u32 val : 32;
543 struct video_ctrl_t f; 561 struct video_ctrl_t f;
544} __attribute__((packed)); 562} __attribute__((packed));
545 563
546struct disp_db_buf_cntl_rd_t { 564struct disp_db_buf_cntl_rd_t {
547 unsigned long en_db_buf : 1; 565 u32 en_db_buf : 1;
548 unsigned long update_db_buf_done : 1; 566 u32 update_db_buf_done : 1;
549 unsigned long db_buf_cntl : 6; 567 u32 db_buf_cntl : 6;
550 unsigned long : 24; 568 u32 : 24;
551} __attribute__((packed)); 569} __attribute__((packed));
552 570
553union disp_db_buf_cntl_rd_u { 571union disp_db_buf_cntl_rd_u {
554 unsigned long val : 32; 572 u32 val : 32;
555 struct disp_db_buf_cntl_rd_t f; 573 struct disp_db_buf_cntl_rd_t f;
556} __attribute__((packed)); 574} __attribute__((packed));
557 575
558struct disp_db_buf_cntl_wr_t { 576struct disp_db_buf_cntl_wr_t {
559 unsigned long en_db_buf : 1; 577 u32 en_db_buf : 1;
560 unsigned long update_db_buf : 1; 578 u32 update_db_buf : 1;
561 unsigned long db_buf_cntl : 6; 579 u32 db_buf_cntl : 6;
562 unsigned long : 24; 580 u32 : 24;
563} __attribute__((packed)); 581} __attribute__((packed));
564 582
565union disp_db_buf_cntl_wr_u { 583union disp_db_buf_cntl_wr_u {
566 unsigned long val : 32; 584 u32 val : 32;
567 struct disp_db_buf_cntl_wr_t f; 585 struct disp_db_buf_cntl_wr_t f;
568} __attribute__((packed)); 586} __attribute__((packed));
569 587
570struct gamma_value1_t { 588struct gamma_value1_t {
571 unsigned long gamma1 : 8; 589 u32 gamma1 : 8;
572 unsigned long gamma2 : 8; 590 u32 gamma2 : 8;
573 unsigned long gamma3 : 8; 591 u32 gamma3 : 8;
574 unsigned long gamma4 : 8; 592 u32 gamma4 : 8;
575} __attribute__((packed)); 593} __attribute__((packed));
576 594
577union gamma_value1_u { 595union gamma_value1_u {
578 unsigned long val : 32; 596 u32 val : 32;
579 struct gamma_value1_t f; 597 struct gamma_value1_t f;
580} __attribute__((packed)); 598} __attribute__((packed));
581 599
582struct gamma_value2_t { 600struct gamma_value2_t {
583 unsigned long gamma5 : 8; 601 u32 gamma5 : 8;
584 unsigned long gamma6 : 8; 602 u32 gamma6 : 8;
585 unsigned long gamma7 : 8; 603 u32 gamma7 : 8;
586 unsigned long gamma8 : 8; 604 u32 gamma8 : 8;
587} __attribute__((packed)); 605} __attribute__((packed));
588 606
589union gamma_value2_u { 607union gamma_value2_u {
590 unsigned long val : 32; 608 u32 val : 32;
591 struct gamma_value2_t f; 609 struct gamma_value2_t f;
592} __attribute__((packed)); 610} __attribute__((packed));
593 611
594struct gamma_slope_t { 612struct gamma_slope_t {
595 unsigned long slope1 : 3; 613 u32 slope1 : 3;
596 unsigned long slope2 : 3; 614 u32 slope2 : 3;
597 unsigned long slope3 : 3; 615 u32 slope3 : 3;
598 unsigned long slope4 : 3; 616 u32 slope4 : 3;
599 unsigned long slope5 : 3; 617 u32 slope5 : 3;
600 unsigned long slope6 : 3; 618 u32 slope6 : 3;
601 unsigned long slope7 : 3; 619 u32 slope7 : 3;
602 unsigned long slope8 : 3; 620 u32 slope8 : 3;
603 unsigned long : 8; 621 u32 : 8;
604} __attribute__((packed)); 622} __attribute__((packed));
605 623
606union gamma_slope_u { 624union gamma_slope_u {
607 unsigned long val : 32; 625 u32 val : 32;
608 struct gamma_slope_t f; 626 struct gamma_slope_t f;
609} __attribute__((packed)); 627} __attribute__((packed));
610 628
611struct mc_ext_mem_location_t { 629struct mc_ext_mem_location_t {
612 unsigned long mc_ext_mem_start : 16; 630 u32 mc_ext_mem_start : 16;
613 unsigned long mc_ext_mem_top : 16; 631 u32 mc_ext_mem_top : 16;
614} __attribute__((packed)); 632} __attribute__((packed));
615 633
616union mc_ext_mem_location_u { 634union mc_ext_mem_location_u {
617 unsigned long val : 32; 635 u32 val : 32;
618 struct mc_ext_mem_location_t f; 636 struct mc_ext_mem_location_t f;
619} __attribute__((packed)); 637} __attribute__((packed));
620 638
621struct mc_fb_location_t { 639struct mc_fb_location_t {
622 unsigned long mc_fb_start : 16; 640 u32 mc_fb_start : 16;
623 unsigned long mc_fb_top : 16; 641 u32 mc_fb_top : 16;
624} __attribute__((packed)); 642} __attribute__((packed));
625 643
626union mc_fb_location_u { 644union mc_fb_location_u {
627 unsigned long val : 32; 645 u32 val : 32;
628 struct mc_fb_location_t f; 646 struct mc_fb_location_t f;
629} __attribute__((packed)); 647} __attribute__((packed));
630 648
631struct clk_pin_cntl_t { 649struct clk_pin_cntl_t {
632 unsigned long osc_en : 1; 650 u32 osc_en : 1;
633 unsigned long osc_gain : 5; 651 u32 osc_gain : 5;
634 unsigned long dont_use_xtalin : 1; 652 u32 dont_use_xtalin : 1;
635 unsigned long xtalin_pm_en : 1; 653 u32 xtalin_pm_en : 1;
636 unsigned long xtalin_dbl_en : 1; 654 u32 xtalin_dbl_en : 1;
637 unsigned long : 7; 655 u32 : 7;
638 unsigned long cg_debug : 16; 656 u32 cg_debug : 16;
639} __attribute__((packed)); 657} __attribute__((packed));
640 658
641union clk_pin_cntl_u { 659union clk_pin_cntl_u {
642 unsigned long val : 32; 660 u32 val : 32;
643 struct clk_pin_cntl_t f; 661 struct clk_pin_cntl_t f;
644} __attribute__((packed)); 662} __attribute__((packed));
645 663
646struct pll_ref_fb_div_t { 664struct pll_ref_fb_div_t {
647 unsigned long pll_ref_div : 4; 665 u32 pll_ref_div : 4;
648 unsigned long : 4; 666 u32 : 4;
649 unsigned long pll_fb_div_int : 6; 667 u32 pll_fb_div_int : 6;
650 unsigned long : 2; 668 u32 : 2;
651 unsigned long pll_fb_div_frac : 3; 669 u32 pll_fb_div_frac : 3;
652 unsigned long : 1; 670 u32 : 1;
653 unsigned long pll_reset_time : 4; 671 u32 pll_reset_time : 4;
654 unsigned long pll_lock_time : 8; 672 u32 pll_lock_time : 8;
655} __attribute__((packed)); 673} __attribute__((packed));
656 674
657union pll_ref_fb_div_u { 675union pll_ref_fb_div_u {
658 unsigned long val : 32; 676 u32 val : 32;
659 struct pll_ref_fb_div_t f; 677 struct pll_ref_fb_div_t f;
660} __attribute__((packed)); 678} __attribute__((packed));
661 679
662struct pll_cntl_t { 680struct pll_cntl_t {
663 unsigned long pll_pwdn : 1; 681 u32 pll_pwdn : 1;
664 unsigned long pll_reset : 1; 682 u32 pll_reset : 1;
665 unsigned long pll_pm_en : 1; 683 u32 pll_pm_en : 1;
666 unsigned long pll_mode : 1; 684 u32 pll_mode : 1;
667 unsigned long pll_refclk_sel : 1; 685 u32 pll_refclk_sel : 1;
668 unsigned long pll_fbclk_sel : 1; 686 u32 pll_fbclk_sel : 1;
669 unsigned long pll_tcpoff : 1; 687 u32 pll_tcpoff : 1;
670 unsigned long pll_pcp : 3; 688 u32 pll_pcp : 3;
671 unsigned long pll_pvg : 3; 689 u32 pll_pvg : 3;
672 unsigned long pll_vcofr : 1; 690 u32 pll_vcofr : 1;
673 unsigned long pll_ioffset : 2; 691 u32 pll_ioffset : 2;
674 unsigned long pll_pecc_mode : 2; 692 u32 pll_pecc_mode : 2;
675 unsigned long pll_pecc_scon : 2; 693 u32 pll_pecc_scon : 2;
676 unsigned long pll_dactal : 4; 694 u32 pll_dactal : 4;
677 unsigned long pll_cp_clip : 2; 695 u32 pll_cp_clip : 2;
678 unsigned long pll_conf : 3; 696 u32 pll_conf : 3;
679 unsigned long pll_mbctrl : 2; 697 u32 pll_mbctrl : 2;
680 unsigned long pll_ring_off : 1; 698 u32 pll_ring_off : 1;
681} __attribute__((packed)); 699} __attribute__((packed));
682 700
683union pll_cntl_u { 701union pll_cntl_u {
684 unsigned long val : 32; 702 u32 val : 32;
685 struct pll_cntl_t f; 703 struct pll_cntl_t f;
686} __attribute__((packed)); 704} __attribute__((packed));
687 705
688struct sclk_cntl_t { 706struct sclk_cntl_t {
689 unsigned long sclk_src_sel : 2; 707 u32 sclk_src_sel : 2;
690 unsigned long : 2; 708 u32 : 2;
691 unsigned long sclk_post_div_fast : 4; 709 u32 sclk_post_div_fast : 4;
692 unsigned long sclk_clkon_hys : 3; 710 u32 sclk_clkon_hys : 3;
693 unsigned long sclk_post_div_slow : 4; 711 u32 sclk_post_div_slow : 4;
694 unsigned long disp_cg_ok2switch_en : 1; 712 u32 disp_cg_ok2switch_en : 1;
695 unsigned long sclk_force_reg : 1; 713 u32 sclk_force_reg : 1;
696 unsigned long sclk_force_disp : 1; 714 u32 sclk_force_disp : 1;
697 unsigned long sclk_force_mc : 1; 715 u32 sclk_force_mc : 1;
698 unsigned long sclk_force_extmc : 1; 716 u32 sclk_force_extmc : 1;
699 unsigned long sclk_force_cp : 1; 717 u32 sclk_force_cp : 1;
700 unsigned long sclk_force_e2 : 1; 718 u32 sclk_force_e2 : 1;
701 unsigned long sclk_force_e3 : 1; 719 u32 sclk_force_e3 : 1;
702 unsigned long sclk_force_idct : 1; 720 u32 sclk_force_idct : 1;
703 unsigned long sclk_force_bist : 1; 721 u32 sclk_force_bist : 1;
704 unsigned long busy_extend_cp : 1; 722 u32 busy_extend_cp : 1;
705 unsigned long busy_extend_e2 : 1; 723 u32 busy_extend_e2 : 1;
706 unsigned long busy_extend_e3 : 1; 724 u32 busy_extend_e3 : 1;
707 unsigned long busy_extend_idct : 1; 725 u32 busy_extend_idct : 1;
708 unsigned long : 3; 726 u32 : 3;
709} __attribute__((packed)); 727} __attribute__((packed));
710 728
711union sclk_cntl_u { 729union sclk_cntl_u {
712 unsigned long val : 32; 730 u32 val : 32;
713 struct sclk_cntl_t f; 731 struct sclk_cntl_t f;
714} __attribute__((packed)); 732} __attribute__((packed));
715 733
716struct pclk_cntl_t { 734struct pclk_cntl_t {
717 unsigned long pclk_src_sel : 2; 735 u32 pclk_src_sel : 2;
718 unsigned long : 2; 736 u32 : 2;
719 unsigned long pclk_post_div : 4; 737 u32 pclk_post_div : 4;
720 unsigned long : 8; 738 u32 : 8;
721 unsigned long pclk_force_disp : 1; 739 u32 pclk_force_disp : 1;
722 unsigned long : 15; 740 u32 : 15;
723} __attribute__((packed)); 741} __attribute__((packed));
724 742
725union pclk_cntl_u { 743union pclk_cntl_u {
726 unsigned long val : 32; 744 u32 val : 32;
727 struct pclk_cntl_t f; 745 struct pclk_cntl_t f;
728} __attribute__((packed)); 746} __attribute__((packed));
729 747
@@ -735,36 +753,176 @@ union pclk_cntl_u {
735#define TESTCLK_SRC_XTAL 0x06 753#define TESTCLK_SRC_XTAL 0x06
736 754
737struct clk_test_cntl_t { 755struct clk_test_cntl_t {
738 unsigned long testclk_sel : 4; 756 u32 testclk_sel : 4;
739 unsigned long : 3; 757 u32 : 3;
740 unsigned long start_check_freq : 1; 758 u32 start_check_freq : 1;
741 unsigned long tstcount_rst : 1; 759 u32 tstcount_rst : 1;
742 unsigned long : 15; 760 u32 : 15;
743 unsigned long test_count : 8; 761 u32 test_count : 8;
744} __attribute__((packed)); 762} __attribute__((packed));
745 763
746union clk_test_cntl_u { 764union clk_test_cntl_u {
747 unsigned long val : 32; 765 u32 val : 32;
748 struct clk_test_cntl_t f; 766 struct clk_test_cntl_t f;
749} __attribute__((packed)); 767} __attribute__((packed));
750 768
751struct pwrmgt_cntl_t { 769struct pwrmgt_cntl_t {
752 unsigned long pwm_enable : 1; 770 u32 pwm_enable : 1;
753 unsigned long : 1; 771 u32 : 1;
754 unsigned long pwm_mode_req : 2; 772 u32 pwm_mode_req : 2;
755 unsigned long pwm_wakeup_cond : 2; 773 u32 pwm_wakeup_cond : 2;
756 unsigned long pwm_fast_noml_hw_en : 1; 774 u32 pwm_fast_noml_hw_en : 1;
757 unsigned long pwm_noml_fast_hw_en : 1; 775 u32 pwm_noml_fast_hw_en : 1;
758 unsigned long pwm_fast_noml_cond : 4; 776 u32 pwm_fast_noml_cond : 4;
759 unsigned long pwm_noml_fast_cond : 4; 777 u32 pwm_noml_fast_cond : 4;
760 unsigned long pwm_idle_timer : 8; 778 u32 pwm_idle_timer : 8;
761 unsigned long pwm_busy_timer : 8; 779 u32 pwm_busy_timer : 8;
762} __attribute__((packed)); 780} __attribute__((packed));
763 781
764union pwrmgt_cntl_u { 782union pwrmgt_cntl_u {
765 unsigned long val : 32; 783 u32 val : 32;
766 struct pwrmgt_cntl_t f; 784 struct pwrmgt_cntl_t f;
767} __attribute__((packed)); 785} __attribute__((packed));
768 786
787#define SRC_DATATYPE_EQU_DST 3
788
789#define ROP3_SRCCOPY 0xcc
790#define ROP3_PATCOPY 0xf0
791
792#define GMC_BRUSH_SOLID_COLOR 13
793#define GMC_BRUSH_NONE 15
794
795#define DP_SRC_MEM_RECTANGULAR 2
796
797#define DP_OP_ROP 0
798
799struct dp_gui_master_cntl_t {
800 u32 gmc_src_pitch_offset_cntl : 1;
801 u32 gmc_dst_pitch_offset_cntl : 1;
802 u32 gmc_src_clipping : 1;
803 u32 gmc_dst_clipping : 1;
804 u32 gmc_brush_datatype : 4;
805 u32 gmc_dst_datatype : 4;
806 u32 gmc_src_datatype : 3;
807 u32 gmc_byte_pix_order : 1;
808 u32 gmc_default_sel : 1;
809 u32 gmc_rop3 : 8;
810 u32 gmc_dp_src_source : 3;
811 u32 gmc_clr_cmp_fcn_dis : 1;
812 u32 : 1;
813 u32 gmc_wr_msk_dis : 1;
814 u32 gmc_dp_op : 1;
815} __attribute__((packed));
816
817union dp_gui_master_cntl_u {
818 u32 val : 32;
819 struct dp_gui_master_cntl_t f;
820} __attribute__((packed));
821
822struct rbbm_status_t {
823 u32 cmdfifo_avail : 7;
824 u32 : 1;
825 u32 hirq_on_rbb : 1;
826 u32 cprq_on_rbb : 1;
827 u32 cfrq_on_rbb : 1;
828 u32 hirq_in_rtbuf : 1;
829 u32 cprq_in_rtbuf : 1;
830 u32 cfrq_in_rtbuf : 1;
831 u32 cf_pipe_busy : 1;
832 u32 eng_ev_busy : 1;
833 u32 cp_cmdstrm_busy : 1;
834 u32 e2_busy : 1;
835 u32 rb2d_busy : 1;
836 u32 rb3d_busy : 1;
837 u32 se_busy : 1;
838 u32 re_busy : 1;
839 u32 tam_busy : 1;
840 u32 tdm_busy : 1;
841 u32 pb_busy : 1;
842 u32 : 6;
843 u32 gui_active : 1;
844} __attribute__((packed));
845
846union rbbm_status_u {
847 u32 val : 32;
848 struct rbbm_status_t f;
849} __attribute__((packed));
850
851struct dp_datatype_t {
852 u32 dp_dst_datatype : 4;
853 u32 : 4;
854 u32 dp_brush_datatype : 4;
855 u32 dp_src2_type : 1;
856 u32 dp_src2_datatype : 3;
857 u32 dp_src_datatype : 3;
858 u32 : 11;
859 u32 dp_byte_pix_order : 1;
860 u32 : 1;
861} __attribute__((packed));
862
863union dp_datatype_u {
864 u32 val : 32;
865 struct dp_datatype_t f;
866} __attribute__((packed));
867
868struct dp_mix_t {
869 u32 : 8;
870 u32 dp_src_source : 3;
871 u32 dp_src2_source : 3;
872 u32 : 2;
873 u32 dp_rop3 : 8;
874 u32 dp_op : 1;
875 u32 : 7;
876} __attribute__((packed));
877
878union dp_mix_u {
879 u32 val : 32;
880 struct dp_mix_t f;
881} __attribute__((packed));
882
883struct eng_cntl_t {
884 u32 erc_reg_rd_ws : 1;
885 u32 erc_reg_wr_ws : 1;
886 u32 erc_idle_reg_wr : 1;
887 u32 dis_engine_triggers : 1;
888 u32 dis_rop_src_uses_dst_w_h : 1;
889 u32 dis_src_uses_dst_dirmaj : 1;
890 u32 : 6;
891 u32 force_3dclk_when_2dclk : 1;
892 u32 : 19;
893} __attribute__((packed));
894
895union eng_cntl_u {
896 u32 val : 32;
897 struct eng_cntl_t f;
898} __attribute__((packed));
899
900struct dp_cntl_t {
901 u32 dst_x_dir : 1;
902 u32 dst_y_dir : 1;
903 u32 src_x_dir : 1;
904 u32 src_y_dir : 1;
905 u32 dst_major_x : 1;
906 u32 src_major_x : 1;
907 u32 : 26;
908} __attribute__((packed));
909
910union dp_cntl_u {
911 u32 val : 32;
912 struct dp_cntl_t f;
913} __attribute__((packed));
914
915struct dp_cntl_dst_dir_t {
916 u32 : 15;
917 u32 dst_y_dir : 1;
918 u32 : 15;
919 u32 dst_x_dir : 1;
920} __attribute__((packed));
921
922union dp_cntl_dst_dir_u {
923 u32 val : 32;
924 struct dp_cntl_dst_dir_t f;
925} __attribute__((packed));
926
769#endif 927#endif
770 928
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 00:30:20 -0500