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authorArchit Taneja <archit@ti.com>2012-02-10 01:15:52 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-02-23 03:29:08 -0500
commita247ce78ca3fa041f3e6b1187c4ae96c7016e83a (patch)
tree56febb09d0817a380c3a9c725f01afe3928048fb /drivers/video
parentd65b4e98d7ea3038b767b70fe8be959b2913f16d (diff)
OMAPDSS: HACK: Ensure DSS clock domain gets out of idle when HDMI is enabled
For DSS clock domain to transition from idle to active state. It's necessary to enable the optional clock DSS_FCLK before we enable the module using the MODULEMODE bits in the clock domain's CM_DSS_DSS_CLKCTRL register. This sequence was not followed correctly for the 'dss_hdmi' hwmod and it led to DSS clock domain not getting out of idle when pm_runtime_get_sync() was called for hdmi's platform device. Since the clock domain failed to change it's state to active, the hwmod code disables any clocks it had enabled before for this hwmod. This led to the clock 'dss_48mhz_clk' gettind disabled. When hdmi's runtime_resume() op is called, the call to dss_runtime_get() correctly enables the DSS clock domain this time. However, the clock 'dss_48mhz_clk' is needed for HDMI's PHY to function correctly. Since it was disabled previously, the driver fails when it tries to enable HDMI's PHY. Fix this for now by ensuring that dss_runtime_get() is called before we call pm_runtime_get_sync() for hdmi's platform device. A correct fix for later would be to modify the DSS related hwmod's mainclks, and also some changes in how opt clocks are handled in the DSS driver. This fixes the issue of HDMI not working when it's the default display. The issue is not seen if any other display is already enabled as the first display would have correctly enabled the DSS clockdomain. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/omap2/dss/hdmi.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index d7aa3b056529..a36b934b2db4 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -165,9 +165,25 @@ static int hdmi_runtime_get(void)
165 165
166 DSSDBG("hdmi_runtime_get\n"); 166 DSSDBG("hdmi_runtime_get\n");
167 167
168 /*
169 * HACK: Add dss_runtime_get() to ensure DSS clock domain is enabled.
170 * This should be removed later.
171 */
172 r = dss_runtime_get();
173 if (r < 0)
174 goto err_get_dss;
175
168 r = pm_runtime_get_sync(&hdmi.pdev->dev); 176 r = pm_runtime_get_sync(&hdmi.pdev->dev);
169 WARN_ON(r < 0); 177 WARN_ON(r < 0);
170 return r < 0 ? r : 0; 178 if (r < 0)
179 goto err_get_hdmi;
180
181 return 0;
182
183err_get_hdmi:
184 dss_runtime_put();
185err_get_dss:
186 return r;
171} 187}
172 188
173static void hdmi_runtime_put(void) 189static void hdmi_runtime_put(void)
@@ -178,6 +194,12 @@ static void hdmi_runtime_put(void)
178 194
179 r = pm_runtime_put_sync(&hdmi.pdev->dev); 195 r = pm_runtime_put_sync(&hdmi.pdev->dev);
180 WARN_ON(r < 0); 196 WARN_ON(r < 0);
197
198 /*
199 * HACK: This is added to complement the dss_runtime_get() call in
200 * hdmi_runtime_get(). This should be removed later.
201 */
202 dss_runtime_put();
181} 203}
182 204
183int hdmi_init_display(struct omap_dss_device *dssdev) 205int hdmi_init_display(struct omap_dss_device *dssdev)