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authorMythri P K <mythripk@ti.com>2011-09-22 04:07:43 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-09-30 09:17:31 -0400
commit31ec732e8fdae66df39335a9c56623498eb76953 (patch)
treec4b6152f037788971f2d0d25ae0106ff3310cefe /drivers/video
parent050958b97b43e1121a9d0ba3cc3cf788594d57b5 (diff)
OMAPDSS: HDMI: Replace hdmi_reg struct with u16
Remove usage of hdmi_reg struct to use u16 instead in the HDMI IP header file. hdmi_reg struct is not really needed, and the same change was also made for dispc earlier. Signed-off-by: Mythri P K <mythripk@ti.com> [tomi.valkeinen@ti.com: updated the description] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c10
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h262
2 files changed, 134 insertions, 138 deletions
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index da7fe50fc127..5f22d2e5979e 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -32,15 +32,15 @@
32#include "dss.h" 32#include "dss.h"
33 33
34static inline void hdmi_write_reg(void __iomem *base_addr, 34static inline void hdmi_write_reg(void __iomem *base_addr,
35 const struct hdmi_reg idx, u32 val) 35 const u16 idx, u32 val)
36{ 36{
37 __raw_writel(val, base_addr + idx.idx); 37 __raw_writel(val, base_addr + idx);
38} 38}
39 39
40static inline u32 hdmi_read_reg(void __iomem *base_addr, 40static inline u32 hdmi_read_reg(void __iomem *base_addr,
41 const struct hdmi_reg idx) 41 const u16 idx)
42{ 42{
43 return __raw_readl(base_addr + idx.idx); 43 return __raw_readl(base_addr + idx);
44} 44}
45 45
46static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data) 46static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
@@ -69,7 +69,7 @@ static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
69} 69}
70 70
71static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, 71static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
72 const struct hdmi_reg idx, 72 const u16 idx,
73 int b2, int b1, u32 val) 73 int b2, int b1, u32 val)
74{ 74{
75 u32 t = 0; 75 u32 t = 0;
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index de1e19956012..694888af9726 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -30,142 +30,138 @@
30#include <sound/pcm_params.h> 30#include <sound/pcm_params.h>
31#endif 31#endif
32 32
33struct hdmi_reg { u16 idx; };
34
35#define HDMI_REG(idx) ((const struct hdmi_reg) { idx })
36
37/* HDMI Wrapper */ 33/* HDMI Wrapper */
38 34
39#define HDMI_WP_REVISION HDMI_REG(0x0) 35#define HDMI_WP_REVISION 0x0
40#define HDMI_WP_SYSCONFIG HDMI_REG(0x10) 36#define HDMI_WP_SYSCONFIG 0x10
41#define HDMI_WP_IRQSTATUS_RAW HDMI_REG(0x24) 37#define HDMI_WP_IRQSTATUS_RAW 0x24
42#define HDMI_WP_IRQSTATUS HDMI_REG(0x28) 38#define HDMI_WP_IRQSTATUS 0x28
43#define HDMI_WP_PWR_CTRL HDMI_REG(0x40) 39#define HDMI_WP_PWR_CTRL 0x40
44#define HDMI_WP_IRQENABLE_SET HDMI_REG(0x2C) 40#define HDMI_WP_IRQENABLE_SET 0x2C
45#define HDMI_WP_VIDEO_CFG HDMI_REG(0x50) 41#define HDMI_WP_VIDEO_CFG 0x50
46#define HDMI_WP_VIDEO_SIZE HDMI_REG(0x60) 42#define HDMI_WP_VIDEO_SIZE 0x60
47#define HDMI_WP_VIDEO_TIMING_H HDMI_REG(0x68) 43#define HDMI_WP_VIDEO_TIMING_H 0x68
48#define HDMI_WP_VIDEO_TIMING_V HDMI_REG(0x6C) 44#define HDMI_WP_VIDEO_TIMING_V 0x6C
49#define HDMI_WP_WP_CLK HDMI_REG(0x70) 45#define HDMI_WP_WP_CLK 0x70
50#define HDMI_WP_AUDIO_CFG HDMI_REG(0x80) 46#define HDMI_WP_AUDIO_CFG 0x80
51#define HDMI_WP_AUDIO_CFG2 HDMI_REG(0x84) 47#define HDMI_WP_AUDIO_CFG2 0x84
52#define HDMI_WP_AUDIO_CTRL HDMI_REG(0x88) 48#define HDMI_WP_AUDIO_CTRL 0x88
53#define HDMI_WP_AUDIO_DATA HDMI_REG(0x8C) 49#define HDMI_WP_AUDIO_DATA 0x8C
54 50
55/* HDMI IP Core System */ 51/* HDMI IP Core System */
56 52
57#define HDMI_CORE_SYS_VND_IDL HDMI_REG(0x0) 53#define HDMI_CORE_SYS_VND_IDL 0x0
58#define HDMI_CORE_SYS_DEV_IDL HDMI_REG(0x8) 54#define HDMI_CORE_SYS_DEV_IDL 0x8
59#define HDMI_CORE_SYS_DEV_IDH HDMI_REG(0xC) 55#define HDMI_CORE_SYS_DEV_IDH 0xC
60#define HDMI_CORE_SYS_DEV_REV HDMI_REG(0x10) 56#define HDMI_CORE_SYS_DEV_REV 0x10
61#define HDMI_CORE_SYS_SRST HDMI_REG(0x14) 57#define HDMI_CORE_SYS_SRST 0x14
62#define HDMI_CORE_CTRL1 HDMI_REG(0x20) 58#define HDMI_CORE_CTRL1 0x20
63#define HDMI_CORE_SYS_SYS_STAT HDMI_REG(0x24) 59#define HDMI_CORE_SYS_SYS_STAT 0x24
64#define HDMI_CORE_SYS_VID_ACEN HDMI_REG(0x124) 60#define HDMI_CORE_SYS_VID_ACEN 0x124
65#define HDMI_CORE_SYS_VID_MODE HDMI_REG(0x128) 61#define HDMI_CORE_SYS_VID_MODE 0x128
66#define HDMI_CORE_SYS_INTR_STATE HDMI_REG(0x1C0) 62#define HDMI_CORE_SYS_INTR_STATE 0x1C0
67#define HDMI_CORE_SYS_INTR1 HDMI_REG(0x1C4) 63#define HDMI_CORE_SYS_INTR1 0x1C4
68#define HDMI_CORE_SYS_INTR2 HDMI_REG(0x1C8) 64#define HDMI_CORE_SYS_INTR2 0x1C8
69#define HDMI_CORE_SYS_INTR3 HDMI_REG(0x1CC) 65#define HDMI_CORE_SYS_INTR3 0x1CC
70#define HDMI_CORE_SYS_INTR4 HDMI_REG(0x1D0) 66#define HDMI_CORE_SYS_INTR4 0x1D0
71#define HDMI_CORE_SYS_UMASK1 HDMI_REG(0x1D4) 67#define HDMI_CORE_SYS_UMASK1 0x1D4
72#define HDMI_CORE_SYS_TMDS_CTRL HDMI_REG(0x208) 68#define HDMI_CORE_SYS_TMDS_CTRL 0x208
73#define HDMI_CORE_SYS_DE_DLY HDMI_REG(0xC8) 69#define HDMI_CORE_SYS_DE_DLY 0xC8
74#define HDMI_CORE_SYS_DE_CTRL HDMI_REG(0xCC) 70#define HDMI_CORE_SYS_DE_CTRL 0xCC
75#define HDMI_CORE_SYS_DE_TOP HDMI_REG(0xD0) 71#define HDMI_CORE_SYS_DE_TOP 0xD0
76#define HDMI_CORE_SYS_DE_CNTL HDMI_REG(0xD8) 72#define HDMI_CORE_SYS_DE_CNTL 0xD8
77#define HDMI_CORE_SYS_DE_CNTH HDMI_REG(0xDC) 73#define HDMI_CORE_SYS_DE_CNTH 0xDC
78#define HDMI_CORE_SYS_DE_LINL HDMI_REG(0xE0) 74#define HDMI_CORE_SYS_DE_LINL 0xE0
79#define HDMI_CORE_SYS_DE_LINH_1 HDMI_REG(0xE4) 75#define HDMI_CORE_SYS_DE_LINH_1 0xE4
80#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1 76#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
81#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1 77#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
82#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1 78#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
83#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1 79#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
84 80
85/* HDMI DDC E-DID */ 81/* HDMI DDC E-DID */
86#define HDMI_CORE_DDC_CMD HDMI_REG(0x3CC) 82#define HDMI_CORE_DDC_CMD 0x3CC
87#define HDMI_CORE_DDC_STATUS HDMI_REG(0x3C8) 83#define HDMI_CORE_DDC_STATUS 0x3C8
88#define HDMI_CORE_DDC_ADDR HDMI_REG(0x3B4) 84#define HDMI_CORE_DDC_ADDR 0x3B4
89#define HDMI_CORE_DDC_OFFSET HDMI_REG(0x3BC) 85#define HDMI_CORE_DDC_OFFSET 0x3BC
90#define HDMI_CORE_DDC_COUNT1 HDMI_REG(0x3C0) 86#define HDMI_CORE_DDC_COUNT1 0x3C0
91#define HDMI_CORE_DDC_COUNT2 HDMI_REG(0x3C4) 87#define HDMI_CORE_DDC_COUNT2 0x3C4
92#define HDMI_CORE_DDC_DATA HDMI_REG(0x3D0) 88#define HDMI_CORE_DDC_DATA 0x3D0
93#define HDMI_CORE_DDC_SEGM HDMI_REG(0x3B8) 89#define HDMI_CORE_DDC_SEGM 0x3B8
94 90
95/* HDMI IP Core Audio Video */ 91/* HDMI IP Core Audio Video */
96 92
97#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC) 93#define HDMI_CORE_AV_HDMI_CTRL 0xBC
98#define HDMI_CORE_AV_DPD HDMI_REG(0xF4) 94#define HDMI_CORE_AV_DPD 0xF4
99#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8) 95#define HDMI_CORE_AV_PB_CTRL1 0xF8
100#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC) 96#define HDMI_CORE_AV_PB_CTRL2 0xFC
101#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100) 97#define HDMI_CORE_AV_AVI_TYPE 0x100
102#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104) 98#define HDMI_CORE_AV_AVI_VERS 0x104
103#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108) 99#define HDMI_CORE_AV_AVI_LEN 0x108
104#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C) 100#define HDMI_CORE_AV_AVI_CHSUM 0x10C
105#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_REG(n * 4 + 0x110) 101#define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110)
106#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_REG(15) 102#define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15
107#define HDMI_CORE_AV_SPD_DBYTE HDMI_REG(0x190) 103#define HDMI_CORE_AV_SPD_DBYTE 0x190
108#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_REG(27) 104#define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27
109#define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_REG(n * 4 + 0x210) 105#define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210)
110#define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_REG(10) 106#define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10
111#define HDMI_CORE_AV_MPEG_DBYTE HDMI_REG(0x290) 107#define HDMI_CORE_AV_MPEG_DBYTE 0x290
112#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_REG(27) 108#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27
113#define HDMI_CORE_AV_GEN_DBYTE HDMI_REG(0x300) 109#define HDMI_CORE_AV_GEN_DBYTE 0x300
114#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_REG(31) 110#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31
115#define HDMI_CORE_AV_GEN2_DBYTE HDMI_REG(0x380) 111#define HDMI_CORE_AV_GEN2_DBYTE 0x380
116#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_REG(31) 112#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31
117#define HDMI_CORE_AV_ACR_CTRL HDMI_REG(0x4) 113#define HDMI_CORE_AV_ACR_CTRL 0x4
118#define HDMI_CORE_AV_FREQ_SVAL HDMI_REG(0x8) 114#define HDMI_CORE_AV_FREQ_SVAL 0x8
119#define HDMI_CORE_AV_N_SVAL1 HDMI_REG(0xC) 115#define HDMI_CORE_AV_N_SVAL1 0xC
120#define HDMI_CORE_AV_N_SVAL2 HDMI_REG(0x10) 116#define HDMI_CORE_AV_N_SVAL2 0x10
121#define HDMI_CORE_AV_N_SVAL3 HDMI_REG(0x14) 117#define HDMI_CORE_AV_N_SVAL3 0x14
122#define HDMI_CORE_AV_CTS_SVAL1 HDMI_REG(0x18) 118#define HDMI_CORE_AV_CTS_SVAL1 0x18
123#define HDMI_CORE_AV_CTS_SVAL2 HDMI_REG(0x1C) 119#define HDMI_CORE_AV_CTS_SVAL2 0x1C
124#define HDMI_CORE_AV_CTS_SVAL3 HDMI_REG(0x20) 120#define HDMI_CORE_AV_CTS_SVAL3 0x20
125#define HDMI_CORE_AV_CTS_HVAL1 HDMI_REG(0x24) 121#define HDMI_CORE_AV_CTS_HVAL1 0x24
126#define HDMI_CORE_AV_CTS_HVAL2 HDMI_REG(0x28) 122#define HDMI_CORE_AV_CTS_HVAL2 0x28
127#define HDMI_CORE_AV_CTS_HVAL3 HDMI_REG(0x2C) 123#define HDMI_CORE_AV_CTS_HVAL3 0x2C
128#define HDMI_CORE_AV_AUD_MODE HDMI_REG(0x50) 124#define HDMI_CORE_AV_AUD_MODE 0x50
129#define HDMI_CORE_AV_SPDIF_CTRL HDMI_REG(0x54) 125#define HDMI_CORE_AV_SPDIF_CTRL 0x54
130#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_REG(0x60) 126#define HDMI_CORE_AV_HW_SPDIF_FS 0x60
131#define HDMI_CORE_AV_SWAP_I2S HDMI_REG(0x64) 127#define HDMI_CORE_AV_SWAP_I2S 0x64
132#define HDMI_CORE_AV_SPDIF_ERTH HDMI_REG(0x6C) 128#define HDMI_CORE_AV_SPDIF_ERTH 0x6C
133#define HDMI_CORE_AV_I2S_IN_MAP HDMI_REG(0x70) 129#define HDMI_CORE_AV_I2S_IN_MAP 0x70
134#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_REG(0x74) 130#define HDMI_CORE_AV_I2S_IN_CTRL 0x74
135#define HDMI_CORE_AV_I2S_CHST0 HDMI_REG(0x78) 131#define HDMI_CORE_AV_I2S_CHST0 0x78
136#define HDMI_CORE_AV_I2S_CHST1 HDMI_REG(0x7C) 132#define HDMI_CORE_AV_I2S_CHST1 0x7C
137#define HDMI_CORE_AV_I2S_CHST2 HDMI_REG(0x80) 133#define HDMI_CORE_AV_I2S_CHST2 0x80
138#define HDMI_CORE_AV_I2S_CHST4 HDMI_REG(0x84) 134#define HDMI_CORE_AV_I2S_CHST4 0x84
139#define HDMI_CORE_AV_I2S_CHST5 HDMI_REG(0x88) 135#define HDMI_CORE_AV_I2S_CHST5 0x88
140#define HDMI_CORE_AV_ASRC HDMI_REG(0x8C) 136#define HDMI_CORE_AV_ASRC 0x8C
141#define HDMI_CORE_AV_I2S_IN_LEN HDMI_REG(0x90) 137#define HDMI_CORE_AV_I2S_IN_LEN 0x90
142#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC) 138#define HDMI_CORE_AV_HDMI_CTRL 0xBC
143#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_REG(0xC0) 139#define HDMI_CORE_AV_AUDO_TXSTAT 0xC0
144#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_REG(0xCC) 140#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 0xCC
145#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_REG(0xD0) 141#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 0xD0
146#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_REG(0xD4) 142#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 0xD4
147#define HDMI_CORE_AV_TEST_TXCTRL HDMI_REG(0xF0) 143#define HDMI_CORE_AV_TEST_TXCTRL 0xF0
148#define HDMI_CORE_AV_DPD HDMI_REG(0xF4) 144#define HDMI_CORE_AV_DPD 0xF4
149#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8) 145#define HDMI_CORE_AV_PB_CTRL1 0xF8
150#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC) 146#define HDMI_CORE_AV_PB_CTRL2 0xFC
151#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100) 147#define HDMI_CORE_AV_AVI_TYPE 0x100
152#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104) 148#define HDMI_CORE_AV_AVI_VERS 0x104
153#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108) 149#define HDMI_CORE_AV_AVI_LEN 0x108
154#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C) 150#define HDMI_CORE_AV_AVI_CHSUM 0x10C
155#define HDMI_CORE_AV_SPD_TYPE HDMI_REG(0x180) 151#define HDMI_CORE_AV_SPD_TYPE 0x180
156#define HDMI_CORE_AV_SPD_VERS HDMI_REG(0x184) 152#define HDMI_CORE_AV_SPD_VERS 0x184
157#define HDMI_CORE_AV_SPD_LEN HDMI_REG(0x188) 153#define HDMI_CORE_AV_SPD_LEN 0x188
158#define HDMI_CORE_AV_SPD_CHSUM HDMI_REG(0x18C) 154#define HDMI_CORE_AV_SPD_CHSUM 0x18C
159#define HDMI_CORE_AV_AUDIO_TYPE HDMI_REG(0x200) 155#define HDMI_CORE_AV_AUDIO_TYPE 0x200
160#define HDMI_CORE_AV_AUDIO_VERS HDMI_REG(0x204) 156#define HDMI_CORE_AV_AUDIO_VERS 0x204
161#define HDMI_CORE_AV_AUDIO_LEN HDMI_REG(0x208) 157#define HDMI_CORE_AV_AUDIO_LEN 0x208
162#define HDMI_CORE_AV_AUDIO_CHSUM HDMI_REG(0x20C) 158#define HDMI_CORE_AV_AUDIO_CHSUM 0x20C
163#define HDMI_CORE_AV_MPEG_TYPE HDMI_REG(0x280) 159#define HDMI_CORE_AV_MPEG_TYPE 0x280
164#define HDMI_CORE_AV_MPEG_VERS HDMI_REG(0x284) 160#define HDMI_CORE_AV_MPEG_VERS 0x284
165#define HDMI_CORE_AV_MPEG_LEN HDMI_REG(0x288) 161#define HDMI_CORE_AV_MPEG_LEN 0x288
166#define HDMI_CORE_AV_MPEG_CHSUM HDMI_REG(0x28C) 162#define HDMI_CORE_AV_MPEG_CHSUM 0x28C
167#define HDMI_CORE_AV_CP_BYTE1 HDMI_REG(0x37C) 163#define HDMI_CORE_AV_CP_BYTE1 0x37C
168#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_REG(0x3FC) 164#define HDMI_CORE_AV_CEC_ADDR_ID 0x3FC
169#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4 165#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
170#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4 166#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
171#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4 167#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
@@ -173,20 +169,20 @@ struct hdmi_reg { u16 idx; };
173 169
174/* PLL */ 170/* PLL */
175 171
176#define PLLCTRL_PLL_CONTROL HDMI_REG(0x0) 172#define PLLCTRL_PLL_CONTROL 0x0
177#define PLLCTRL_PLL_STATUS HDMI_REG(0x4) 173#define PLLCTRL_PLL_STATUS 0x4
178#define PLLCTRL_PLL_GO HDMI_REG(0x8) 174#define PLLCTRL_PLL_GO 0x8
179#define PLLCTRL_CFG1 HDMI_REG(0xC) 175#define PLLCTRL_CFG1 0xC
180#define PLLCTRL_CFG2 HDMI_REG(0x10) 176#define PLLCTRL_CFG2 0x10
181#define PLLCTRL_CFG3 HDMI_REG(0x14) 177#define PLLCTRL_CFG3 0x14
182#define PLLCTRL_CFG4 HDMI_REG(0x20) 178#define PLLCTRL_CFG4 0x20
183 179
184/* HDMI PHY */ 180/* HDMI PHY */
185 181
186#define HDMI_TXPHY_TX_CTRL HDMI_REG(0x0) 182#define HDMI_TXPHY_TX_CTRL 0x0
187#define HDMI_TXPHY_DIGITAL_CTRL HDMI_REG(0x4) 183#define HDMI_TXPHY_DIGITAL_CTRL 0x4
188#define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8) 184#define HDMI_TXPHY_POWER_CTRL 0x8
189#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC) 185#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
190 186
191#define REG_FLD_MOD(base, idx, val, start, end) \ 187#define REG_FLD_MOD(base, idx, val, start, end) \
192 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ 188 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\