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authorLinus Torvalds <torvalds@linux-foundation.org>2008-12-30 20:36:49 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2008-12-30 20:36:49 -0500
commit14a3c4ab0e58d143c7928c9eb2f2610205e13bf2 (patch)
tree885992999d7a1a2fd3586efcf32ebcbcbc3a72aa /drivers/video
parent1af237a099a3b8ff56aa384f605c6a68af7bf288 (diff)
parent47992cbdaef2f18a47871b2ed01ad27f568c8b73 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (407 commits) [ARM] pxafb: add support for overlay1 and overlay2 as framebuffer devices [ARM] pxafb: cleanup of the timing checking code [ARM] pxafb: cleanup of the color format manipulation code [ARM] pxafb: add palette format support for LCCR4_PAL_FOR_3 [ARM] pxafb: add support for FBIOPAN_DISPLAY by dma braching [ARM] pxafb: allow pxafb_set_par() to start from arbitrary yoffset [ARM] pxafb: allow video memory size to be configurable [ARM] pxa: add document on the MFP design and how to use it [ARM] sa1100_wdt: don't assume CLOCK_TICK_RATE to be a constant [ARM] rtc-sa1100: don't assume CLOCK_TICK_RATE to be a constant [ARM] pxa/tavorevb: update board support (smartpanel LCD + keypad) [ARM] pxa: Update eseries defconfig [ARM] 5352/1: add w90p910-plat config file [ARM] s3c: S3C options should depend on PLAT_S3C [ARM] mv78xx0: implement GPIO and GPIO interrupt support [ARM] Kirkwood: implement GPIO and GPIO interrupt support [ARM] Orion: share GPIO IRQ handling code [ARM] Orion: share GPIO handling code [ARM] s3c: define __io using the typesafe version [ARM] S3C64XX: Ensure CPU_V6 is selected ...
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/Kconfig7
-rw-r--r--drivers/video/amba-clcd.c4
-rw-r--r--drivers/video/imxfb.c468
-rw-r--r--drivers/video/imxfb.h73
-rw-r--r--drivers/video/pxafb.c981
-rw-r--r--drivers/video/pxafb.h82
-rw-r--r--drivers/video/sa1100fb.c2
7 files changed, 993 insertions, 624 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d0c821992a99..6372f8b17b45 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -362,7 +362,7 @@ endchoice
362 362
363config FB_ACORN 363config FB_ACORN
364 bool "Acorn VIDC support" 364 bool "Acorn VIDC support"
365 depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500) 365 depends on (FB = y) && ARM && ARCH_ACORN
366 select FB_CFB_FILLRECT 366 select FB_CFB_FILLRECT
367 select FB_CFB_COPYAREA 367 select FB_CFB_COPYAREA
368 select FB_CFB_IMAGEBLIT 368 select FB_CFB_IMAGEBLIT
@@ -1817,6 +1817,11 @@ config FB_PXA
1817 1817
1818 If unsure, say N. 1818 If unsure, say N.
1819 1819
1820config FB_PXA_OVERLAY
1821 bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
1822 default n
1823 depends on FB_PXA && (PXA27x || PXA3xx)
1824
1820config FB_PXA_SMARTPANEL 1825config FB_PXA_SMARTPANEL
1821 bool "PXA Smartpanel LCD support" 1826 bool "PXA Smartpanel LCD support"
1822 default n 1827 default n
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index a7a1c891bfa2..2ac52fd8cc11 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -343,14 +343,14 @@ static int clcdfb_register(struct clcd_fb *fb)
343{ 343{
344 int ret; 344 int ret;
345 345
346 fb->clk = clk_get(&fb->dev->dev, "CLCDCLK"); 346 fb->clk = clk_get(&fb->dev->dev, NULL);
347 if (IS_ERR(fb->clk)) { 347 if (IS_ERR(fb->clk)) {
348 ret = PTR_ERR(fb->clk); 348 ret = PTR_ERR(fb->clk);
349 goto out; 349 goto out;
350 } 350 }
351 351
352 fb->fb.fix.mmio_start = fb->dev->res.start; 352 fb->fb.fix.mmio_start = fb->dev->res.start;
353 fb->fb.fix.mmio_len = SZ_4K; 353 fb->fb.fix.mmio_len = 4096;
354 354
355 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len); 355 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
356 if (!fb->regs) { 356 if (!fb->regs) {
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index ccd986140c95..d58c68cd456e 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * linux/drivers/video/imxfb.c
3 *
4 * Freescale i.MX Frame Buffer device driver 2 * Freescale i.MX Frame Buffer device driver
5 * 3 *
6 * Copyright (C) 2004 Sascha Hauer, Pengutronix 4 * Copyright (C) 2004 Sascha Hauer, Pengutronix
@@ -16,7 +14,6 @@
16 * linux-arm-kernel@lists.arm.linux.org.uk 14 * linux-arm-kernel@lists.arm.linux.org.uk
17 */ 15 */
18 16
19//#define DEBUG 1
20 17
21#include <linux/module.h> 18#include <linux/module.h>
22#include <linux/kernel.h> 19#include <linux/kernel.h>
@@ -32,9 +29,8 @@
32#include <linux/cpufreq.h> 29#include <linux/cpufreq.h>
33#include <linux/platform_device.h> 30#include <linux/platform_device.h>
34#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
32#include <linux/io.h>
35 33
36#include <mach/hardware.h>
37#include <asm/io.h>
38#include <mach/imxfb.h> 34#include <mach/imxfb.h>
39 35
40/* 36/*
@@ -42,23 +38,150 @@
42 */ 38 */
43#define DEBUG_VAR 1 39#define DEBUG_VAR 1
44 40
45#include "imxfb.h" 41#define DRIVER_NAME "imx-fb"
42
43#define LCDC_SSA 0x00
44
45#define LCDC_SIZE 0x04
46#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
47#define SIZE_YMAX(y) ((y) & 0x1ff)
48
49#define LCDC_VPW 0x08
50#define VPW_VPW(x) ((x) & 0x3ff)
51
52#define LCDC_CPOS 0x0C
53#define CPOS_CC1 (1<<31)
54#define CPOS_CC0 (1<<30)
55#define CPOS_OP (1<<28)
56#define CPOS_CXP(x) (((x) & 3ff) << 16)
57#define CPOS_CYP(y) ((y) & 0x1ff)
58
59#define LCDC_LCWHB 0x10
60#define LCWHB_BK_EN (1<<31)
61#define LCWHB_CW(w) (((w) & 0x1f) << 24)
62#define LCWHB_CH(h) (((h) & 0x1f) << 16)
63#define LCWHB_BD(x) ((x) & 0xff)
64
65#define LCDC_LCHCC 0x14
66#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
67#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
68#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
69
70#define LCDC_PCR 0x18
71
72#define LCDC_HCR 0x1C
73#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
74#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
75#define HCR_H_WAIT_2(x) ((x) & 0xff)
76
77#define LCDC_VCR 0x20
78#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
79#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
80#define VCR_V_WAIT_2(x) ((x) & 0xff)
81
82#define LCDC_POS 0x24
83#define POS_POS(x) ((x) & 1f)
84
85#define LCDC_LSCR1 0x28
86/* bit fields in imxfb.h */
87
88#define LCDC_PWMR 0x2C
89/* bit fields in imxfb.h */
90
91#define LCDC_DMACR 0x30
92/* bit fields in imxfb.h */
93
94#define LCDC_RMCR 0x34
95#define RMCR_LCDC_EN (1<<1)
96#define RMCR_SELF_REF (1<<0)
97
98#define LCDC_LCDICR 0x38
99#define LCDICR_INT_SYN (1<<2)
100#define LCDICR_INT_CON (1)
101
102#define LCDC_LCDISR 0x40
103#define LCDISR_UDR_ERR (1<<3)
104#define LCDISR_ERR_RES (1<<2)
105#define LCDISR_EOF (1<<1)
106#define LCDISR_BOF (1<<0)
107
108/*
109 * These are the bitfields for each
110 * display depth that we support.
111 */
112struct imxfb_rgb {
113 struct fb_bitfield red;
114 struct fb_bitfield green;
115 struct fb_bitfield blue;
116 struct fb_bitfield transp;
117};
118
119struct imxfb_info {
120 struct platform_device *pdev;
121 void __iomem *regs;
46 122
47static struct imxfb_rgb def_rgb_16 = { 123 u_int max_bpp;
48 .red = { .offset = 8, .length = 4, }, 124 u_int max_xres;
49 .green = { .offset = 4, .length = 4, }, 125 u_int max_yres;
50 .blue = { .offset = 0, .length = 4, }, 126
51 .transp = { .offset = 0, .length = 0, }, 127 /*
128 * These are the addresses we mapped
129 * the framebuffer memory region to.
130 */
131 dma_addr_t map_dma;
132 u_char *map_cpu;
133 u_int map_size;
134
135 u_char *screen_cpu;
136 dma_addr_t screen_dma;
137 u_int palette_size;
138
139 dma_addr_t dbar1;
140 dma_addr_t dbar2;
141
142 u_int pcr;
143 u_int pwmr;
144 u_int lscr1;
145 u_int dmacr;
146 u_int cmap_inverse:1,
147 cmap_static:1,
148 unused:30;
149
150 void (*lcd_power)(int);
151 void (*backlight_power)(int);
152};
153
154#define IMX_NAME "IMX"
155
156/*
157 * Minimum X and Y resolutions
158 */
159#define MIN_XRES 64
160#define MIN_YRES 64
161
162static struct imxfb_rgb def_rgb_16_tft = {
163 .red = {.offset = 11, .length = 5,},
164 .green = {.offset = 5, .length = 6,},
165 .blue = {.offset = 0, .length = 5,},
166 .transp = {.offset = 0, .length = 0,},
167};
168
169static struct imxfb_rgb def_rgb_16_stn = {
170 .red = {.offset = 8, .length = 4,},
171 .green = {.offset = 4, .length = 4,},
172 .blue = {.offset = 0, .length = 4,},
173 .transp = {.offset = 0, .length = 0,},
52}; 174};
53 175
54static struct imxfb_rgb def_rgb_8 = { 176static struct imxfb_rgb def_rgb_8 = {
55 .red = { .offset = 0, .length = 8, }, 177 .red = {.offset = 0, .length = 8,},
56 .green = { .offset = 0, .length = 8, }, 178 .green = {.offset = 0, .length = 8,},
57 .blue = { .offset = 0, .length = 8, }, 179 .blue = {.offset = 0, .length = 8,},
58 .transp = { .offset = 0, .length = 0, }, 180 .transp = {.offset = 0, .length = 0,},
59}; 181};
60 182
61static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info); 183static int imxfb_activate_var(struct fb_var_screeninfo *var,
184 struct fb_info *info);
62 185
63static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 186static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
64{ 187{
@@ -67,10 +190,8 @@ static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
67 return chan << bf->offset; 190 return chan << bf->offset;
68} 191}
69 192
70#define LCDC_PALETTE(x) __REG2(IMX_LCDC_BASE+0x800, (x)<<2) 193static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
71static int 194 u_int trans, struct fb_info *info)
72imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
73 u_int trans, struct fb_info *info)
74{ 195{
75 struct imxfb_info *fbi = info->par; 196 struct imxfb_info *fbi = info->par;
76 u_int val, ret = 1; 197 u_int val, ret = 1;
@@ -81,14 +202,13 @@ imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
81 (CNVT_TOHW(green,4) << 4) | 202 (CNVT_TOHW(green,4) << 4) |
82 CNVT_TOHW(blue, 4); 203 CNVT_TOHW(blue, 4);
83 204
84 LCDC_PALETTE(regno) = val; 205 writel(val, fbi->regs + 0x800 + (regno << 2));
85 ret = 0; 206 ret = 0;
86 } 207 }
87 return ret; 208 return ret;
88} 209}
89 210
90static int 211static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
91imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
92 u_int trans, struct fb_info *info) 212 u_int trans, struct fb_info *info)
93{ 213{
94 struct imxfb_info *fbi = info->par; 214 struct imxfb_info *fbi = info->par;
@@ -148,11 +268,10 @@ imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
148 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 268 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
149 * bitfields, horizontal timing, vertical timing. 269 * bitfields, horizontal timing, vertical timing.
150 */ 270 */
151static int 271static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
152imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
153{ 272{
154 struct imxfb_info *fbi = info->par; 273 struct imxfb_info *fbi = info->par;
155 int rgbidx; 274 struct imxfb_rgb *rgb;
156 275
157 if (var->xres < MIN_XRES) 276 if (var->xres < MIN_XRES)
158 var->xres = MIN_XRES; 277 var->xres = MIN_XRES;
@@ -168,23 +287,25 @@ imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
168 pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); 287 pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
169 switch (var->bits_per_pixel) { 288 switch (var->bits_per_pixel) {
170 case 16: 289 case 16:
171 rgbidx = RGB_16; 290 default:
291 if (readl(fbi->regs + LCDC_PCR) & PCR_TFT)
292 rgb = &def_rgb_16_tft;
293 else
294 rgb = &def_rgb_16_stn;
172 break; 295 break;
173 case 8: 296 case 8:
174 rgbidx = RGB_8; 297 rgb = &def_rgb_8;
175 break; 298 break;
176 default:
177 rgbidx = RGB_16;
178 } 299 }
179 300
180 /* 301 /*
181 * Copy the RGB parameters for this display 302 * Copy the RGB parameters for this display
182 * from the machine specific parameters. 303 * from the machine specific parameters.
183 */ 304 */
184 var->red = fbi->rgb[rgbidx]->red; 305 var->red = rgb->red;
185 var->green = fbi->rgb[rgbidx]->green; 306 var->green = rgb->green;
186 var->blue = fbi->rgb[rgbidx]->blue; 307 var->blue = rgb->blue;
187 var->transp = fbi->rgb[rgbidx]->transp; 308 var->transp = rgb->transp;
188 309
189 pr_debug("RGBT length = %d:%d:%d:%d\n", 310 pr_debug("RGBT length = %d:%d:%d:%d\n",
190 var->red.length, var->green.length, var->blue.length, 311 var->red.length, var->green.length, var->blue.length,
@@ -221,8 +342,7 @@ static int imxfb_set_par(struct fb_info *info)
221 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 342 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
222 } 343 }
223 344
224 info->fix.line_length = var->xres_virtual * 345 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
225 var->bits_per_pixel / 8;
226 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; 346 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
227 347
228 imxfb_activate_var(var, info); 348 imxfb_activate_var(var, info);
@@ -235,22 +355,27 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
235 pr_debug("Enabling LCD controller\n"); 355 pr_debug("Enabling LCD controller\n");
236 356
237 /* initialize LCDC */ 357 /* initialize LCDC */
238 LCDC_RMCR &= ~RMCR_LCDC_EN; /* just to be safe... */ 358 writel(readl(fbi->regs + LCDC_RMCR) & ~RMCR_LCDC_EN,
359 fbi->regs + LCDC_RMCR); /* just to be safe... */
360
361 writel(fbi->screen_dma, fbi->regs + LCDC_SSA);
239 362
240 LCDC_SSA = fbi->screen_dma;
241 /* physical screen start address */ 363 /* physical screen start address */
242 LCDC_VPW = VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4); 364 writel(VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4),
365 fbi->regs + LCDC_VPW);
243 366
244 LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */ 367 /* panning offset 0 (0 pixel offset) */
368 writel(0x00000000, fbi->regs + LCDC_POS);
245 369
246 /* disable hardware cursor */ 370 /* disable hardware cursor */
247 LCDC_CPOS &= ~(CPOS_CC0 | CPOS_CC1); 371 writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
372 fbi->regs + LCDC_CPOS);
248 373
249 LCDC_RMCR = RMCR_LCDC_EN; 374 writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
250 375
251 if(fbi->backlight_power) 376 if (fbi->backlight_power)
252 fbi->backlight_power(1); 377 fbi->backlight_power(1);
253 if(fbi->lcd_power) 378 if (fbi->lcd_power)
254 fbi->lcd_power(1); 379 fbi->lcd_power(1);
255} 380}
256 381
@@ -258,12 +383,12 @@ static void imxfb_disable_controller(struct imxfb_info *fbi)
258{ 383{
259 pr_debug("Disabling LCD controller\n"); 384 pr_debug("Disabling LCD controller\n");
260 385
261 if(fbi->backlight_power) 386 if (fbi->backlight_power)
262 fbi->backlight_power(0); 387 fbi->backlight_power(0);
263 if(fbi->lcd_power) 388 if (fbi->lcd_power)
264 fbi->lcd_power(0); 389 fbi->lcd_power(0);
265 390
266 LCDC_RMCR = 0; 391 writel(0, fbi->regs + LCDC_RMCR);
267} 392}
268 393
269static int imxfb_blank(int blank, struct fb_info *info) 394static int imxfb_blank(int blank, struct fb_info *info)
@@ -340,74 +465,26 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
340 info->fix.id, var->lower_margin); 465 info->fix.id, var->lower_margin);
341#endif 466#endif
342 467
343 LCDC_HCR = HCR_H_WIDTH(var->hsync_len) | 468 writel(HCR_H_WIDTH(var->hsync_len) |
344 HCR_H_WAIT_1(var->left_margin) | 469 HCR_H_WAIT_1(var->right_margin) |
345 HCR_H_WAIT_2(var->right_margin); 470 HCR_H_WAIT_2(var->left_margin),
471 fbi->regs + LCDC_HCR);
346 472
347 LCDC_VCR = VCR_V_WIDTH(var->vsync_len) | 473 writel(VCR_V_WIDTH(var->vsync_len) |
348 VCR_V_WAIT_1(var->upper_margin) | 474 VCR_V_WAIT_1(var->lower_margin) |
349 VCR_V_WAIT_2(var->lower_margin); 475 VCR_V_WAIT_2(var->upper_margin),
476 fbi->regs + LCDC_VCR);
350 477
351 LCDC_SIZE = SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres); 478 writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres),
352 LCDC_PCR = fbi->pcr; 479 fbi->regs + LCDC_SIZE);
353 LCDC_PWMR = fbi->pwmr; 480 writel(fbi->pcr, fbi->regs + LCDC_PCR);
354 LCDC_LSCR1 = fbi->lscr1; 481 writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
355 LCDC_DMACR = fbi->dmacr; 482 writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
483 writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
356 484
357 return 0; 485 return 0;
358} 486}
359 487
360static void imxfb_setup_gpio(struct imxfb_info *fbi)
361{
362 int width;
363
364 LCDC_RMCR &= ~(RMCR_LCDC_EN | RMCR_SELF_REF);
365
366 if( fbi->pcr & PCR_TFT )
367 width = 16;
368 else
369 width = 1 << ((fbi->pcr >> 28) & 0x3);
370
371 switch(width) {
372 case 16:
373 imx_gpio_mode(PD30_PF_LD15);
374 imx_gpio_mode(PD29_PF_LD14);
375 imx_gpio_mode(PD28_PF_LD13);
376 imx_gpio_mode(PD27_PF_LD12);
377 imx_gpio_mode(PD26_PF_LD11);
378 imx_gpio_mode(PD25_PF_LD10);
379 imx_gpio_mode(PD24_PF_LD9);
380 imx_gpio_mode(PD23_PF_LD8);
381 case 8:
382 imx_gpio_mode(PD22_PF_LD7);
383 imx_gpio_mode(PD21_PF_LD6);
384 imx_gpio_mode(PD20_PF_LD5);
385 imx_gpio_mode(PD19_PF_LD4);
386 case 4:
387 imx_gpio_mode(PD18_PF_LD3);
388 imx_gpio_mode(PD17_PF_LD2);
389 case 2:
390 imx_gpio_mode(PD16_PF_LD1);
391 case 1:
392 imx_gpio_mode(PD15_PF_LD0);
393 }
394
395 /* initialize GPIOs */
396 imx_gpio_mode(PD6_PF_LSCLK);
397 imx_gpio_mode(PD11_PF_CONTRAST);
398 imx_gpio_mode(PD14_PF_FLM_VSYNC);
399 imx_gpio_mode(PD13_PF_LP_HSYNC);
400 imx_gpio_mode(PD12_PF_ACD_OE);
401
402 /* These are only needed for Sharp HR TFT displays */
403 if (fbi->pcr & PCR_SHARP) {
404 imx_gpio_mode(PD7_PF_REV);
405 imx_gpio_mode(PD8_PF_CLS);
406 imx_gpio_mode(PD9_PF_PS);
407 imx_gpio_mode(PD10_PF_SPL_SPR);
408 }
409}
410
411#ifdef CONFIG_PM 488#ifdef CONFIG_PM
412/* 489/*
413 * Power management hooks. Note that we won't be called from IRQ context, 490 * Power management hooks. Note that we won't be called from IRQ context,
@@ -416,7 +493,8 @@ static void imxfb_setup_gpio(struct imxfb_info *fbi)
416static int imxfb_suspend(struct platform_device *dev, pm_message_t state) 493static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
417{ 494{
418 struct imxfb_info *fbi = platform_get_drvdata(dev); 495 struct imxfb_info *fbi = platform_get_drvdata(dev);
419 pr_debug("%s\n",__func__); 496
497 pr_debug("%s\n", __func__);
420 498
421 imxfb_disable_controller(fbi); 499 imxfb_disable_controller(fbi);
422 return 0; 500 return 0;
@@ -425,7 +503,8 @@ static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
425static int imxfb_resume(struct platform_device *dev) 503static int imxfb_resume(struct platform_device *dev)
426{ 504{
427 struct imxfb_info *fbi = platform_get_drvdata(dev); 505 struct imxfb_info *fbi = platform_get_drvdata(dev);
428 pr_debug("%s\n",__func__); 506
507 pr_debug("%s\n", __func__);
429 508
430 imxfb_enable_controller(fbi); 509 imxfb_enable_controller(fbi);
431 return 0; 510 return 0;
@@ -435,149 +514,136 @@ static int imxfb_resume(struct platform_device *dev)
435#define imxfb_resume NULL 514#define imxfb_resume NULL
436#endif 515#endif
437 516
438static int __init imxfb_init_fbinfo(struct device *dev) 517static int __init imxfb_init_fbinfo(struct platform_device *pdev)
439{ 518{
440 struct imxfb_mach_info *inf = dev->platform_data; 519 struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
441 struct fb_info *info = dev_get_drvdata(dev); 520 struct fb_info *info = dev_get_drvdata(&pdev->dev);
442 struct imxfb_info *fbi = info->par; 521 struct imxfb_info *fbi = info->par;
443 522
444 pr_debug("%s\n",__func__); 523 pr_debug("%s\n",__func__);
445 524
446 info->pseudo_palette = kmalloc( sizeof(u32) * 16, GFP_KERNEL); 525 info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
447 if (!info->pseudo_palette) 526 if (!info->pseudo_palette)
448 return -ENOMEM; 527 return -ENOMEM;
449 528
450 memset(fbi, 0, sizeof(struct imxfb_info)); 529 memset(fbi, 0, sizeof(struct imxfb_info));
451 fbi->dev = dev;
452 530
453 strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); 531 strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
454 532
455 info->fix.type = FB_TYPE_PACKED_PIXELS; 533 info->fix.type = FB_TYPE_PACKED_PIXELS;
456 info->fix.type_aux = 0; 534 info->fix.type_aux = 0;
457 info->fix.xpanstep = 0; 535 info->fix.xpanstep = 0;
458 info->fix.ypanstep = 0; 536 info->fix.ypanstep = 0;
459 info->fix.ywrapstep = 0; 537 info->fix.ywrapstep = 0;
460 info->fix.accel = FB_ACCEL_NONE; 538 info->fix.accel = FB_ACCEL_NONE;
461 539
462 info->var.nonstd = 0; 540 info->var.nonstd = 0;
463 info->var.activate = FB_ACTIVATE_NOW; 541 info->var.activate = FB_ACTIVATE_NOW;
464 info->var.height = -1; 542 info->var.height = -1;
465 info->var.width = -1; 543 info->var.width = -1;
466 info->var.accel_flags = 0; 544 info->var.accel_flags = 0;
467 info->var.vmode = FB_VMODE_NONINTERLACED; 545 info->var.vmode = FB_VMODE_NONINTERLACED;
468 546
469 info->fbops = &imxfb_ops; 547 info->fbops = &imxfb_ops;
470 info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; 548 info->flags = FBINFO_FLAG_DEFAULT |
471 549 FBINFO_READS_FAST;
472 fbi->rgb[RGB_16] = &def_rgb_16; 550
473 fbi->rgb[RGB_8] = &def_rgb_8; 551 fbi->max_xres = pdata->xres;
474 552 info->var.xres = pdata->xres;
475 fbi->max_xres = inf->xres; 553 info->var.xres_virtual = pdata->xres;
476 info->var.xres = inf->xres; 554 fbi->max_yres = pdata->yres;
477 info->var.xres_virtual = inf->xres; 555 info->var.yres = pdata->yres;
478 fbi->max_yres = inf->yres; 556 info->var.yres_virtual = pdata->yres;
479 info->var.yres = inf->yres; 557 fbi->max_bpp = pdata->bpp;
480 info->var.yres_virtual = inf->yres; 558 info->var.bits_per_pixel = pdata->bpp;
481 fbi->max_bpp = inf->bpp; 559 info->var.nonstd = pdata->nonstd;
482 info->var.bits_per_pixel = inf->bpp; 560 info->var.pixclock = pdata->pixclock;
483 info->var.nonstd = inf->nonstd; 561 info->var.hsync_len = pdata->hsync_len;
484 info->var.pixclock = inf->pixclock; 562 info->var.left_margin = pdata->left_margin;
485 info->var.hsync_len = inf->hsync_len; 563 info->var.right_margin = pdata->right_margin;
486 info->var.left_margin = inf->left_margin; 564 info->var.vsync_len = pdata->vsync_len;
487 info->var.right_margin = inf->right_margin; 565 info->var.upper_margin = pdata->upper_margin;
488 info->var.vsync_len = inf->vsync_len; 566 info->var.lower_margin = pdata->lower_margin;
489 info->var.upper_margin = inf->upper_margin; 567 info->var.sync = pdata->sync;
490 info->var.lower_margin = inf->lower_margin; 568 info->var.grayscale = pdata->cmap_greyscale;
491 info->var.sync = inf->sync; 569 fbi->cmap_inverse = pdata->cmap_inverse;
492 info->var.grayscale = inf->cmap_greyscale; 570 fbi->cmap_static = pdata->cmap_static;
493 fbi->cmap_inverse = inf->cmap_inverse; 571 fbi->pcr = pdata->pcr;
494 fbi->cmap_static = inf->cmap_static; 572 fbi->lscr1 = pdata->lscr1;
495 fbi->pcr = inf->pcr; 573 fbi->dmacr = pdata->dmacr;
496 fbi->lscr1 = inf->lscr1; 574 fbi->pwmr = pdata->pwmr;
497 fbi->dmacr = inf->dmacr; 575 fbi->lcd_power = pdata->lcd_power;
498 fbi->pwmr = inf->pwmr; 576 fbi->backlight_power = pdata->backlight_power;
499 fbi->lcd_power = inf->lcd_power;
500 fbi->backlight_power = inf->backlight_power;
501 info->fix.smem_len = fbi->max_xres * fbi->max_yres * 577 info->fix.smem_len = fbi->max_xres * fbi->max_yres *
502 fbi->max_bpp / 8; 578 fbi->max_bpp / 8;
503 579
504 return 0; 580 return 0;
505} 581}
506 582
507/*
508 * Allocates the DRAM memory for the frame buffer. This buffer is
509 * remapped into a non-cached, non-buffered, memory region to
510 * allow pixel writes to occur without flushing the cache.
511 * Once this area is remapped, all virtual memory access to the
512 * video memory should occur at the new region.
513 */
514static int __init imxfb_map_video_memory(struct fb_info *info)
515{
516 struct imxfb_info *fbi = info->par;
517
518 fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
519 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
520 &fbi->map_dma,GFP_KERNEL);
521
522 if (fbi->map_cpu) {
523 info->screen_base = fbi->map_cpu;
524 fbi->screen_cpu = fbi->map_cpu;
525 fbi->screen_dma = fbi->map_dma;
526 info->fix.smem_start = fbi->screen_dma;
527 }
528
529 return fbi->map_cpu ? 0 : -ENOMEM;
530}
531
532static int __init imxfb_probe(struct platform_device *pdev) 583static int __init imxfb_probe(struct platform_device *pdev)
533{ 584{
534 struct imxfb_info *fbi; 585 struct imxfb_info *fbi;
535 struct fb_info *info; 586 struct fb_info *info;
536 struct imxfb_mach_info *inf; 587 struct imx_fb_platform_data *pdata;
537 struct resource *res; 588 struct resource *res;
538 int ret; 589 int ret;
539 590
540 printk("i.MX Framebuffer driver\n"); 591 printk("i.MX Framebuffer driver\n");
541 592
542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 593 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 if(!res) 594 if (!res)
544 return -ENODEV; 595 return -ENODEV;
545 596
546 inf = pdev->dev.platform_data; 597 pdata = pdev->dev.platform_data;
547 if(!inf) { 598 if (!pdata) {
548 dev_err(&pdev->dev,"No platform_data available\n"); 599 dev_err(&pdev->dev,"No platform_data available\n");
549 return -ENOMEM; 600 return -ENOMEM;
550 } 601 }
551 602
552 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); 603 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
553 if(!info) 604 if (!info)
554 return -ENOMEM; 605 return -ENOMEM;
555 606
556 fbi = info->par; 607 fbi = info->par;
557 608
558 platform_set_drvdata(pdev, info); 609 platform_set_drvdata(pdev, info);
559 610
560 ret = imxfb_init_fbinfo(&pdev->dev); 611 ret = imxfb_init_fbinfo(pdev);
561 if( ret < 0 ) 612 if (ret < 0)
562 goto failed_init; 613 goto failed_init;
563 614
564 res = request_mem_region(res->start, res->end - res->start + 1, "IMXFB"); 615 res = request_mem_region(res->start, resource_size(res),
616 DRIVER_NAME);
565 if (!res) { 617 if (!res) {
566 ret = -EBUSY; 618 ret = -EBUSY;
567 goto failed_regs; 619 goto failed_req;
620 }
621
622 fbi->regs = ioremap(res->start, resource_size(res));
623 if (fbi->regs == NULL) {
624 printk(KERN_ERR"Cannot map frame buffer registers\n");
625 goto failed_ioremap;
568 } 626 }
569 627
570 if (!inf->fixed_screen_cpu) { 628 if (!pdata->fixed_screen_cpu) {
571 ret = imxfb_map_video_memory(info); 629 fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
572 if (ret) { 630 fbi->map_cpu = dma_alloc_writecombine(&pdev->dev,
631 fbi->map_size, &fbi->map_dma, GFP_KERNEL);
632
633 if (!fbi->map_cpu) {
573 dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret); 634 dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
574 ret = -ENOMEM; 635 ret = -ENOMEM;
575 goto failed_map; 636 goto failed_map;
576 } 637 }
638
639 info->screen_base = fbi->map_cpu;
640 fbi->screen_cpu = fbi->map_cpu;
641 fbi->screen_dma = fbi->map_dma;
642 info->fix.smem_start = fbi->screen_dma;
577 } else { 643 } else {
578 /* Fixed framebuffer mapping enables location of the screen in eSRAM */ 644 /* Fixed framebuffer mapping enables location of the screen in eSRAM */
579 fbi->map_cpu = inf->fixed_screen_cpu; 645 fbi->map_cpu = pdata->fixed_screen_cpu;
580 fbi->map_dma = inf->fixed_screen_dma; 646 fbi->map_dma = pdata->fixed_screen_dma;
581 info->screen_base = fbi->map_cpu; 647 info->screen_base = fbi->map_cpu;
582 fbi->screen_cpu = fbi->map_cpu; 648 fbi->screen_cpu = fbi->map_cpu;
583 fbi->screen_dma = fbi->map_dma; 649 fbi->screen_dma = fbi->map_dma;
@@ -590,12 +656,10 @@ static int __init imxfb_probe(struct platform_device *pdev)
590 */ 656 */
591 imxfb_check_var(&info->var, info); 657 imxfb_check_var(&info->var, info);
592 658
593 ret = fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0); 659 ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
594 if (ret < 0) 660 if (ret < 0)
595 goto failed_cmap; 661 goto failed_cmap;
596 662
597 imxfb_setup_gpio(fbi);
598
599 imxfb_set_par(info); 663 imxfb_set_par(info);
600 ret = register_framebuffer(info); 664 ret = register_framebuffer(info);
601 if (ret < 0) { 665 if (ret < 0) {
@@ -610,20 +674,22 @@ static int __init imxfb_probe(struct platform_device *pdev)
610failed_register: 674failed_register:
611 fb_dealloc_cmap(&info->cmap); 675 fb_dealloc_cmap(&info->cmap);
612failed_cmap: 676failed_cmap:
613 if (!inf->fixed_screen_cpu) 677 if (!pdata->fixed_screen_cpu)
614 dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, 678 dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu,
615 fbi->map_dma); 679 fbi->map_dma);
616failed_map: 680failed_map:
617 kfree(info->pseudo_palette); 681 iounmap(fbi->regs);
618failed_regs: 682failed_ioremap:
619 release_mem_region(res->start, res->end - res->start); 683 release_mem_region(res->start, res->end - res->start);
684failed_req:
685 kfree(info->pseudo_palette);
620failed_init: 686failed_init:
621 platform_set_drvdata(pdev, NULL); 687 platform_set_drvdata(pdev, NULL);
622 framebuffer_release(info); 688 framebuffer_release(info);
623 return ret; 689 return ret;
624} 690}
625 691
626static int imxfb_remove(struct platform_device *pdev) 692static int __devexit imxfb_remove(struct platform_device *pdev)
627{ 693{
628 struct fb_info *info = platform_get_drvdata(pdev); 694 struct fb_info *info = platform_get_drvdata(pdev);
629 struct imxfb_info *fbi = info->par; 695 struct imxfb_info *fbi = info->par;
@@ -639,6 +705,7 @@ static int imxfb_remove(struct platform_device *pdev)
639 kfree(info->pseudo_palette); 705 kfree(info->pseudo_palette);
640 framebuffer_release(info); 706 framebuffer_release(info);
641 707
708 iounmap(fbi->regs);
642 release_mem_region(res->start, res->end - res->start + 1); 709 release_mem_region(res->start, res->end - res->start + 1);
643 platform_set_drvdata(pdev, NULL); 710 platform_set_drvdata(pdev, NULL);
644 711
@@ -653,19 +720,18 @@ void imxfb_shutdown(struct platform_device * dev)
653} 720}
654 721
655static struct platform_driver imxfb_driver = { 722static struct platform_driver imxfb_driver = {
656 .probe = imxfb_probe,
657 .suspend = imxfb_suspend, 723 .suspend = imxfb_suspend,
658 .resume = imxfb_resume, 724 .resume = imxfb_resume,
659 .remove = imxfb_remove, 725 .remove = __devexit_p(imxfb_remove),
660 .shutdown = imxfb_shutdown, 726 .shutdown = imxfb_shutdown,
661 .driver = { 727 .driver = {
662 .name = "imx-fb", 728 .name = DRIVER_NAME,
663 }, 729 },
664}; 730};
665 731
666int __init imxfb_init(void) 732int __init imxfb_init(void)
667{ 733{
668 return platform_driver_register(&imxfb_driver); 734 return platform_driver_probe(&imxfb_driver, imxfb_probe);
669} 735}
670 736
671static void __exit imxfb_cleanup(void) 737static void __exit imxfb_cleanup(void)
diff --git a/drivers/video/imxfb.h b/drivers/video/imxfb.h
deleted file mode 100644
index e837a8b48eb8..000000000000
--- a/drivers/video/imxfb.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * linux/drivers/video/imxfb.h
3 *
4 * Freescale i.MX Frame Buffer device driver
5 *
6 * Copyright (C) 2004 S.Hauer, Pengutronix
7 *
8 * Copyright (C) 1999 Eric A. Thomas
9 * Based on acornfb.c Copyright (C) Russell King.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16/*
17 * These are the bitfields for each
18 * display depth that we support.
19 */
20struct imxfb_rgb {
21 struct fb_bitfield red;
22 struct fb_bitfield green;
23 struct fb_bitfield blue;
24 struct fb_bitfield transp;
25};
26
27#define RGB_16 (0)
28#define RGB_8 (1)
29#define NR_RGB 2
30
31struct imxfb_info {
32 struct device *dev;
33 struct imxfb_rgb *rgb[NR_RGB];
34
35 u_int max_bpp;
36 u_int max_xres;
37 u_int max_yres;
38
39 /*
40 * These are the addresses we mapped
41 * the framebuffer memory region to.
42 */
43 dma_addr_t map_dma;
44 u_char * map_cpu;
45 u_int map_size;
46
47 u_char * screen_cpu;
48 dma_addr_t screen_dma;
49 u_int palette_size;
50
51 dma_addr_t dbar1;
52 dma_addr_t dbar2;
53
54 u_int pcr;
55 u_int pwmr;
56 u_int lscr1;
57 u_int dmacr;
58 u_int cmap_inverse:1,
59 cmap_static:1,
60 unused:30;
61
62 void (*lcd_power)(int);
63 void (*backlight_power)(int);
64};
65
66#define IMX_NAME "IMX"
67
68/*
69 * Minimum X and Y resolutions
70 */
71#define MIN_XRES 64
72#define MIN_YRES 64
73
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index cc59c52e1103..48ff701d3a72 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -20,6 +20,16 @@
20 * 20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk 21 * linux-arm-kernel@lists.arm.linux.org.uk
22 * 22 *
23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24 *
25 * Copyright (C) 2004, Intel Corporation
26 *
27 * 2003/08/27: <yu.tang@intel.com>
28 * 2004/03/10: <stanley.cai@intel.com>
29 * 2004/10/28: <yan.yin@intel.com>
30 *
31 * Copyright (C) 2006-2008 Marvell International Ltd.
32 * All Rights Reserved
23 */ 33 */
24 34
25#include <linux/module.h> 35#include <linux/module.h>
@@ -50,7 +60,6 @@
50#include <asm/irq.h> 60#include <asm/irq.h>
51#include <asm/div64.h> 61#include <asm/div64.h>
52#include <mach/pxa-regs.h> 62#include <mach/pxa-regs.h>
53#include <mach/pxa2xx-gpio.h>
54#include <mach/bitfield.h> 63#include <mach/bitfield.h>
55#include <mach/pxafb.h> 64#include <mach/pxafb.h>
56 65
@@ -67,14 +76,16 @@
67 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) 76 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
68 77
69#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ 78#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
70 LCCR3_PCD | LCCR3_BPP) 79 LCCR3_PCD | LCCR3_BPP(0xf))
71
72static void (*pxafb_backlight_power)(int);
73static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
74 80
75static int pxafb_activate_var(struct fb_var_screeninfo *var, 81static int pxafb_activate_var(struct fb_var_screeninfo *var,
76 struct pxafb_info *); 82 struct pxafb_info *);
77static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); 83static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
84static void setup_base_frame(struct pxafb_info *fbi, int branch);
85static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
86 unsigned long offset, size_t size);
87
88static unsigned long video_mem_size = 0;
78 89
79static inline unsigned long 90static inline unsigned long
80lcd_readl(struct pxafb_info *fbi, unsigned int off) 91lcd_readl(struct pxafb_info *fbi, unsigned int off)
@@ -156,6 +167,12 @@ pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
156 val |= ((blue >> 8) & 0x000000fc); 167 val |= ((blue >> 8) & 0x000000fc);
157 ((u32 *)(fbi->palette_cpu))[regno] = val; 168 ((u32 *)(fbi->palette_cpu))[regno] = val;
158 break; 169 break;
170 case LCCR4_PAL_FOR_3:
171 val = ((red << 8) & 0x00ff0000);
172 val |= ((green >> 0) & 0x0000ff00);
173 val |= ((blue >> 8) & 0x000000ff);
174 ((u32 *)(fbi->palette_cpu))[regno] = val;
175 break;
159 } 176 }
160 177
161 return 0; 178 return 0;
@@ -216,37 +233,110 @@ pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
216 return ret; 233 return ret;
217} 234}
218 235
219/* 236/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
220 * pxafb_bpp_to_lccr3(): 237static inline int var_to_depth(struct fb_var_screeninfo *var)
221 * Convert a bits per pixel value to the correct bit pattern for LCCR3
222 */
223static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
224{ 238{
225 int ret = 0; 239 return var->red.length + var->green.length +
240 var->blue.length + var->transp.length;
241}
242
243/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
244static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
245{
246 int bpp = -EINVAL;
247
226 switch (var->bits_per_pixel) { 248 switch (var->bits_per_pixel) {
227 case 1: ret = LCCR3_1BPP; break; 249 case 1: bpp = 0; break;
228 case 2: ret = LCCR3_2BPP; break; 250 case 2: bpp = 1; break;
229 case 4: ret = LCCR3_4BPP; break; 251 case 4: bpp = 2; break;
230 case 8: ret = LCCR3_8BPP; break; 252 case 8: bpp = 3; break;
231 case 16: ret = LCCR3_16BPP; break; 253 case 16: bpp = 4; break;
232 case 24: 254 case 24:
233 switch (var->red.length + var->green.length + 255 switch (var_to_depth(var)) {
234 var->blue.length + var->transp.length) { 256 case 18: bpp = 6; break; /* 18-bits/pixel packed */
235 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break; 257 case 19: bpp = 8; break; /* 19-bits/pixel packed */
236 case 19: ret = LCCR3_19BPP_P; break; 258 case 24: bpp = 9; break;
237 } 259 }
238 break; 260 break;
239 case 32: 261 case 32:
240 switch (var->red.length + var->green.length + 262 switch (var_to_depth(var)) {
241 var->blue.length + var->transp.length) { 263 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
242 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break; 264 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
243 case 19: ret = LCCR3_19BPP; break; 265 case 25: bpp = 10; break;
244 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
245 case 25: ret = LCCR3_25BPP; break;
246 } 266 }
247 break; 267 break;
248 } 268 }
249 return ret; 269 return bpp;
270}
271
272/*
273 * pxafb_var_to_lccr3():
274 * Convert a bits per pixel value to the correct bit pattern for LCCR3
275 *
276 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
277 * implication of the acutal use of transparency bit, which we handle it
278 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
279 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
280 *
281 * Transparency for palette pixel formats is not supported at the moment.
282 */
283static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
284{
285 int bpp = pxafb_var_to_bpp(var);
286 uint32_t lccr3;
287
288 if (bpp < 0)
289 return 0;
290
291 lccr3 = LCCR3_BPP(bpp);
292
293 switch (var_to_depth(var)) {
294 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
295 case 18: lccr3 |= LCCR3_PDFOR_3; break;
296 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
297 break;
298 case 19:
299 case 25: lccr3 |= LCCR3_PDFOR_0; break;
300 }
301 return lccr3;
302}
303
304#define SET_PIXFMT(v, r, g, b, t) \
305({ \
306 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
307 (v)->transp.length = (t) ? (t) : 0; \
308 (v)->blue.length = (b); (v)->blue.offset = 0; \
309 (v)->green.length = (g); (v)->green.offset = (b); \
310 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
311})
312
313/* set the RGBT bitfields of fb_var_screeninf according to
314 * var->bits_per_pixel and given depth
315 */
316static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
317{
318 if (depth == 0)
319 depth = var->bits_per_pixel;
320
321 if (var->bits_per_pixel < 16) {
322 /* indexed pixel formats */
323 var->red.offset = 0; var->red.length = 8;
324 var->green.offset = 0; var->green.length = 8;
325 var->blue.offset = 0; var->blue.length = 8;
326 var->transp.offset = 0; var->transp.length = 8;
327 }
328
329 switch (depth) {
330 case 16: var->transp.length ?
331 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
332 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
333 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
334 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
335 case 24: var->transp.length ?
336 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
337 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
338 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
339 }
250} 340}
251 341
252#ifdef CONFIG_CPU_FREQ 342#ifdef CONFIG_CPU_FREQ
@@ -308,8 +398,49 @@ static void pxafb_setmode(struct fb_var_screeninfo *var,
308 var->lower_margin = mode->lower_margin; 398 var->lower_margin = mode->lower_margin;
309 var->sync = mode->sync; 399 var->sync = mode->sync;
310 var->grayscale = mode->cmap_greyscale; 400 var->grayscale = mode->cmap_greyscale;
311 var->xres_virtual = var->xres; 401
312 var->yres_virtual = var->yres; 402 /* set the initial RGBA bitfields */
403 pxafb_set_pixfmt(var, mode->depth);
404}
405
406static int pxafb_adjust_timing(struct pxafb_info *fbi,
407 struct fb_var_screeninfo *var)
408{
409 int line_length;
410
411 var->xres = max_t(int, var->xres, MIN_XRES);
412 var->yres = max_t(int, var->yres, MIN_YRES);
413
414 if (!(fbi->lccr0 & LCCR0_LCDT)) {
415 clamp_val(var->hsync_len, 1, 64);
416 clamp_val(var->vsync_len, 1, 64);
417 clamp_val(var->left_margin, 1, 255);
418 clamp_val(var->right_margin, 1, 255);
419 clamp_val(var->upper_margin, 1, 255);
420 clamp_val(var->lower_margin, 1, 255);
421 }
422
423 /* make sure each line is aligned on word boundary */
424 line_length = var->xres * var->bits_per_pixel / 8;
425 line_length = ALIGN(line_length, 4);
426 var->xres = line_length * 8 / var->bits_per_pixel;
427
428 /* we don't support xpan, force xres_virtual to be equal to xres */
429 var->xres_virtual = var->xres;
430
431 if (var->accel_flags & FB_ACCELF_TEXT)
432 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
433 else
434 var->yres_virtual = max(var->yres_virtual, var->yres);
435
436 /* check for limits */
437 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
438 return -EINVAL;
439
440 if (var->yres > var->yres_virtual)
441 return -EINVAL;
442
443 return 0;
313} 444}
314 445
315/* 446/*
@@ -325,11 +456,7 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
325{ 456{
326 struct pxafb_info *fbi = (struct pxafb_info *)info; 457 struct pxafb_info *fbi = (struct pxafb_info *)info;
327 struct pxafb_mach_info *inf = fbi->dev->platform_data; 458 struct pxafb_mach_info *inf = fbi->dev->platform_data;
328 459 int err;
329 if (var->xres < MIN_XRES)
330 var->xres = MIN_XRES;
331 if (var->yres < MIN_YRES)
332 var->yres = MIN_YRES;
333 460
334 if (inf->fixed_modes) { 461 if (inf->fixed_modes) {
335 struct pxafb_mode_info *mode; 462 struct pxafb_mode_info *mode;
@@ -338,74 +465,18 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
338 if (!mode) 465 if (!mode)
339 return -EINVAL; 466 return -EINVAL;
340 pxafb_setmode(var, mode); 467 pxafb_setmode(var, mode);
341 } else {
342 if (var->xres > inf->modes->xres)
343 return -EINVAL;
344 if (var->yres > inf->modes->yres)
345 return -EINVAL;
346 if (var->bits_per_pixel > inf->modes->bpp)
347 return -EINVAL;
348 } 468 }
349 469
350 var->xres_virtual = 470 /* do a test conversion to BPP fields to check the color formats */
351 max(var->xres_virtual, var->xres); 471 err = pxafb_var_to_bpp(var);
352 var->yres_virtual = 472 if (err < 0)
353 max(var->yres_virtual, var->yres); 473 return err;
354 474
355 /* 475 pxafb_set_pixfmt(var, var_to_depth(var));
356 * Setup the RGB parameters for this display.
357 *
358 * The pixel packing format is described on page 7-11 of the
359 * PXA2XX Developer's Manual.
360 */
361 if (var->bits_per_pixel == 16) {
362 var->red.offset = 11; var->red.length = 5;
363 var->green.offset = 5; var->green.length = 6;
364 var->blue.offset = 0; var->blue.length = 5;
365 var->transp.offset = var->transp.length = 0;
366 } else if (var->bits_per_pixel > 16) {
367 struct pxafb_mode_info *mode;
368 476
369 mode = pxafb_getmode(inf, var); 477 err = pxafb_adjust_timing(fbi, var);
370 if (!mode) 478 if (err)
371 return -EINVAL; 479 return err;
372
373 switch (mode->depth) {
374 case 18: /* RGB666 */
375 var->transp.offset = var->transp.length = 0;
376 var->red.offset = 12; var->red.length = 6;
377 var->green.offset = 6; var->green.length = 6;
378 var->blue.offset = 0; var->blue.length = 6;
379 break;
380 case 19: /* RGBT666 */
381 var->transp.offset = 18; var->transp.length = 1;
382 var->red.offset = 12; var->red.length = 6;
383 var->green.offset = 6; var->green.length = 6;
384 var->blue.offset = 0; var->blue.length = 6;
385 break;
386 case 24: /* RGB888 */
387 var->transp.offset = var->transp.length = 0;
388 var->red.offset = 16; var->red.length = 8;
389 var->green.offset = 8; var->green.length = 8;
390 var->blue.offset = 0; var->blue.length = 8;
391 break;
392 case 25: /* RGBT888 */
393 var->transp.offset = 24; var->transp.length = 1;
394 var->red.offset = 16; var->red.length = 8;
395 var->green.offset = 8; var->green.length = 8;
396 var->blue.offset = 0; var->blue.length = 8;
397 break;
398 default:
399 return -EINVAL;
400 }
401 } else {
402 var->red.offset = var->green.offset = 0;
403 var->blue.offset = var->transp.offset = 0;
404 var->red.length = 8;
405 var->green.length = 8;
406 var->blue.length = 8;
407 var->transp.length = 0;
408 }
409 480
410#ifdef CONFIG_CPU_FREQ 481#ifdef CONFIG_CPU_FREQ
411 pr_debug("pxafb: dma period = %d ps\n", 482 pr_debug("pxafb: dma period = %d ps\n",
@@ -415,11 +486,6 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
415 return 0; 486 return 0;
416} 487}
417 488
418static inline void pxafb_set_truecolor(u_int is_true_color)
419{
420 /* do your machine-specific setup if needed */
421}
422
423/* 489/*
424 * pxafb_set_par(): 490 * pxafb_set_par():
425 * Set the user defined part of the display for the specified console 491 * Set the user defined part of the display for the specified console
@@ -452,11 +518,6 @@ static int pxafb_set_par(struct fb_info *info)
452 518
453 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; 519 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
454 520
455 /*
456 * Set (any) board control register to handle new color depth
457 */
458 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
459
460 if (fbi->fb.var.bits_per_pixel >= 16) 521 if (fbi->fb.var.bits_per_pixel >= 16)
461 fb_dealloc_cmap(&fbi->fb.cmap); 522 fb_dealloc_cmap(&fbi->fb.cmap);
462 else 523 else
@@ -467,6 +528,24 @@ static int pxafb_set_par(struct fb_info *info)
467 return 0; 528 return 0;
468} 529}
469 530
531static int pxafb_pan_display(struct fb_var_screeninfo *var,
532 struct fb_info *info)
533{
534 struct pxafb_info *fbi = (struct pxafb_info *)info;
535 int dma = DMA_MAX + DMA_BASE;
536
537 if (fbi->state != C_ENABLE)
538 return 0;
539
540 setup_base_frame(fbi, 1);
541
542 if (fbi->lccr0 & LCCR0_SDS)
543 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
544
545 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
546 return 0;
547}
548
470/* 549/*
471 * pxafb_blank(): 550 * pxafb_blank():
472 * Blank the display by setting all palette values to zero. Note, the 551 * Blank the display by setting all palette values to zero. Note, the
@@ -502,32 +581,342 @@ static int pxafb_blank(int blank, struct fb_info *info)
502 return 0; 581 return 0;
503} 582}
504 583
505static int pxafb_mmap(struct fb_info *info,
506 struct vm_area_struct *vma)
507{
508 struct pxafb_info *fbi = (struct pxafb_info *)info;
509 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
510
511 if (off < info->fix.smem_len) {
512 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
513 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
514 fbi->map_dma, fbi->map_size);
515 }
516 return -EINVAL;
517}
518
519static struct fb_ops pxafb_ops = { 584static struct fb_ops pxafb_ops = {
520 .owner = THIS_MODULE, 585 .owner = THIS_MODULE,
521 .fb_check_var = pxafb_check_var, 586 .fb_check_var = pxafb_check_var,
522 .fb_set_par = pxafb_set_par, 587 .fb_set_par = pxafb_set_par,
588 .fb_pan_display = pxafb_pan_display,
523 .fb_setcolreg = pxafb_setcolreg, 589 .fb_setcolreg = pxafb_setcolreg,
524 .fb_fillrect = cfb_fillrect, 590 .fb_fillrect = cfb_fillrect,
525 .fb_copyarea = cfb_copyarea, 591 .fb_copyarea = cfb_copyarea,
526 .fb_imageblit = cfb_imageblit, 592 .fb_imageblit = cfb_imageblit,
527 .fb_blank = pxafb_blank, 593 .fb_blank = pxafb_blank,
528 .fb_mmap = pxafb_mmap,
529}; 594};
530 595
596#ifdef CONFIG_FB_PXA_OVERLAY
597static void overlay1fb_setup(struct pxafb_layer *ofb)
598{
599 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
600 unsigned long start = ofb->video_mem_phys;
601 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
602}
603
604/* Depending on the enable status of overlay1/2, the DMA should be
605 * updated from FDADRx (when disabled) or FBRx (when enabled).
606 */
607static void overlay1fb_enable(struct pxafb_layer *ofb)
608{
609 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
610 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
611
612 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
613 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
614 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
615}
616
617static void overlay1fb_disable(struct pxafb_layer *ofb)
618{
619 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
620
621 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
622
623 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
624 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
625 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
626
627 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
628 pr_warning("%s: timeout disabling overlay1\n", __func__);
629
630 lcd_writel(ofb->fbi, LCCR5, lccr5);
631}
632
633static void overlay2fb_setup(struct pxafb_layer *ofb)
634{
635 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
636 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
637
638 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
639 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
640 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
641 } else {
642 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
643 switch (pfor) {
644 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
645 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
646 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
647 }
648 start[1] = start[0] + size;
649 start[2] = start[1] + size / div;
650 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
651 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
652 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
653 }
654}
655
656static void overlay2fb_enable(struct pxafb_layer *ofb)
657{
658 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
659 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
660 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
661 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
662 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
663
664 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
665 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
666 else {
667 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
668 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
669 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
670 }
671 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
672 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
673}
674
675static void overlay2fb_disable(struct pxafb_layer *ofb)
676{
677 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
678
679 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
680
681 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
682 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
683 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
684 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
685 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
686
687 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
688 pr_warning("%s: timeout disabling overlay2\n", __func__);
689}
690
691static struct pxafb_layer_ops ofb_ops[] = {
692 [0] = {
693 .enable = overlay1fb_enable,
694 .disable = overlay1fb_disable,
695 .setup = overlay1fb_setup,
696 },
697 [1] = {
698 .enable = overlay2fb_enable,
699 .disable = overlay2fb_disable,
700 .setup = overlay2fb_setup,
701 },
702};
703
704static int overlayfb_open(struct fb_info *info, int user)
705{
706 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
707
708 /* no support for framebuffer console on overlay */
709 if (user == 0)
710 return -ENODEV;
711
712 /* allow only one user at a time */
713 if (atomic_inc_and_test(&ofb->usage))
714 return -EBUSY;
715
716 /* unblank the base framebuffer */
717 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
718 return 0;
719}
720
721static int overlayfb_release(struct fb_info *info, int user)
722{
723 struct pxafb_layer *ofb = (struct pxafb_layer*) info;
724
725 atomic_dec(&ofb->usage);
726 ofb->ops->disable(ofb);
727
728 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
729 ofb->video_mem = NULL;
730 ofb->video_mem_size = 0;
731 return 0;
732}
733
734static int overlayfb_check_var(struct fb_var_screeninfo *var,
735 struct fb_info *info)
736{
737 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
738 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
739 int xpos, ypos, pfor, bpp;
740
741 xpos = NONSTD_TO_XPOS(var->nonstd);
742 ypos = NONSTD_TO_XPOS(var->nonstd);
743 pfor = NONSTD_TO_PFOR(var->nonstd);
744
745 bpp = pxafb_var_to_bpp(var);
746 if (bpp < 0)
747 return -EINVAL;
748
749 /* no support for YUV format on overlay1 */
750 if (ofb->id == OVERLAY1 && pfor != 0)
751 return -EINVAL;
752
753 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
754 switch (pfor) {
755 case OVERLAY_FORMAT_RGB:
756 bpp = pxafb_var_to_bpp(var);
757 if (bpp < 0)
758 return -EINVAL;
759
760 pxafb_set_pixfmt(var, var_to_depth(var));
761 break;
762 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
763 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
764 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
765 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
766 default:
767 return -EINVAL;
768 }
769
770 /* each line must start at a 32-bit word boundary */
771 if ((xpos * bpp) % 32)
772 return -EINVAL;
773
774 /* xres must align on 32-bit word boundary */
775 var->xres = roundup(var->xres * bpp, 32) / bpp;
776
777 if ((xpos + var->xres > base_var->xres) ||
778 (ypos + var->yres > base_var->yres))
779 return -EINVAL;
780
781 var->xres_virtual = var->xres;
782 var->yres_virtual = max(var->yres, var->yres_virtual);
783 return 0;
784}
785
786static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
787{
788 struct fb_var_screeninfo *var = &ofb->fb.var;
789 int pfor = NONSTD_TO_PFOR(var->nonstd);
790 int size, bpp = 0;
791
792 switch (pfor) {
793 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
794 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
795 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
796 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
797 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
798 }
799
800 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
801
802 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
803
804 /* don't re-allocate if the original video memory is enough */
805 if (ofb->video_mem) {
806 if (ofb->video_mem_size >= size)
807 return 0;
808
809 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
810 }
811
812 ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
813 if (ofb->video_mem == NULL)
814 return -ENOMEM;
815
816 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
817 ofb->video_mem_size = size;
818
819 ofb->fb.fix.smem_start = ofb->video_mem_phys;
820 ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual;
821 ofb->fb.screen_base = ofb->video_mem;
822 return 0;
823}
824
825static int overlayfb_set_par(struct fb_info *info)
826{
827 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
828 struct fb_var_screeninfo *var = &info->var;
829 int xpos, ypos, pfor, bpp, ret;
830
831 ret = overlayfb_map_video_memory(ofb);
832 if (ret)
833 return ret;
834
835 bpp = pxafb_var_to_bpp(var);
836 xpos = NONSTD_TO_XPOS(var->nonstd);
837 ypos = NONSTD_TO_XPOS(var->nonstd);
838 pfor = NONSTD_TO_PFOR(var->nonstd);
839
840 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
841 OVLxC1_BPP(bpp);
842 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
843
844 if (ofb->id == OVERLAY2)
845 ofb->control[1] |= OVL2C2_PFOR(pfor);
846
847 ofb->ops->setup(ofb);
848 ofb->ops->enable(ofb);
849 return 0;
850}
851
852static struct fb_ops overlay_fb_ops = {
853 .owner = THIS_MODULE,
854 .fb_open = overlayfb_open,
855 .fb_release = overlayfb_release,
856 .fb_check_var = overlayfb_check_var,
857 .fb_set_par = overlayfb_set_par,
858};
859
860static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
861 struct pxafb_layer *ofb, int id)
862{
863 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
864
865 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
866 ofb->fb.fix.xpanstep = 0;
867 ofb->fb.fix.ypanstep = 1;
868
869 ofb->fb.var.activate = FB_ACTIVATE_NOW;
870 ofb->fb.var.height = -1;
871 ofb->fb.var.width = -1;
872 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
873
874 ofb->fb.fbops = &overlay_fb_ops;
875 ofb->fb.flags = FBINFO_FLAG_DEFAULT;
876 ofb->fb.node = -1;
877 ofb->fb.pseudo_palette = NULL;
878
879 ofb->id = id;
880 ofb->ops = &ofb_ops[id];
881 atomic_set(&ofb->usage, 0);
882 ofb->fbi = fbi;
883 init_completion(&ofb->branch_done);
884}
885
886static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
887{
888 int i, ret;
889
890 for (i = 0; i < 2; i++) {
891 init_pxafb_overlay(fbi, &fbi->overlay[i], i);
892 ret = register_framebuffer(&fbi->overlay[i].fb);
893 if (ret) {
894 dev_err(fbi->dev, "failed to register overlay %d\n", i);
895 return ret;
896 }
897 }
898
899 /* mask all IU/BS/EOF/SOF interrupts */
900 lcd_writel(fbi, LCCR5, ~0);
901
902 /* place overlay(s) on top of base */
903 fbi->lccr0 |= LCCR0_OUC;
904 pr_info("PXA Overlay driver loaded successfully!\n");
905 return 0;
906}
907
908static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
909{
910 int i;
911
912 for (i = 0; i < 2; i++)
913 unregister_framebuffer(&fbi->overlay[i].fb);
914}
915#else
916static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
917static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
918#endif /* CONFIG_FB_PXA_OVERLAY */
919
531/* 920/*
532 * Calculate the PCD value from the clock rate (in picoseconds). 921 * Calculate the PCD value from the clock rate (in picoseconds).
533 * We take account of the PPCR clock setting. 922 * We take account of the PPCR clock setting.
@@ -607,22 +996,22 @@ unsigned long pxafb_get_hsync_time(struct device *dev)
607EXPORT_SYMBOL(pxafb_get_hsync_time); 996EXPORT_SYMBOL(pxafb_get_hsync_time);
608 997
609static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, 998static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
610 unsigned int offset, size_t size) 999 unsigned long start, size_t size)
611{ 1000{
612 struct pxafb_dma_descriptor *dma_desc, *pal_desc; 1001 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
613 unsigned int dma_desc_off, pal_desc_off; 1002 unsigned int dma_desc_off, pal_desc_off;
614 1003
615 if (dma < 0 || dma >= DMA_MAX) 1004 if (dma < 0 || dma >= DMA_MAX * 2)
616 return -EINVAL; 1005 return -EINVAL;
617 1006
618 dma_desc = &fbi->dma_buff->dma_desc[dma]; 1007 dma_desc = &fbi->dma_buff->dma_desc[dma];
619 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); 1008 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
620 1009
621 dma_desc->fsadr = fbi->screen_dma + offset; 1010 dma_desc->fsadr = start;
622 dma_desc->fidr = 0; 1011 dma_desc->fidr = 0;
623 dma_desc->ldcmd = size; 1012 dma_desc->ldcmd = size;
624 1013
625 if (pal < 0 || pal >= PAL_MAX) { 1014 if (pal < 0 || pal >= PAL_MAX * 2) {
626 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1015 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
627 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; 1016 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
628 } else { 1017 } else {
@@ -648,6 +1037,27 @@ static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
648 return 0; 1037 return 0;
649} 1038}
650 1039
1040static void setup_base_frame(struct pxafb_info *fbi, int branch)
1041{
1042 struct fb_var_screeninfo *var = &fbi->fb.var;
1043 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1044 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1045 unsigned long offset;
1046
1047 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1048 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1049
1050 nbytes = fix->line_length * var->yres;
1051 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1052
1053 if (fbi->lccr0 & LCCR0_SDS) {
1054 nbytes = nbytes / 2;
1055 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1056 }
1057
1058 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1059}
1060
651#ifdef CONFIG_FB_PXA_SMARTPANEL 1061#ifdef CONFIG_FB_PXA_SMARTPANEL
652static int setup_smart_dma(struct pxafb_info *fbi) 1062static int setup_smart_dma(struct pxafb_info *fbi)
653{ 1063{
@@ -701,6 +1111,7 @@ int pxafb_smart_flush(struct fb_info *info)
701 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1111 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
702 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1112 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
703 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1113 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1114 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
704 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 1115 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
705 lcd_writel(fbi, FDADR6, fbi->fdadr[6]); 1116 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
706 1117
@@ -727,12 +1138,19 @@ int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
727 int i; 1138 int i;
728 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 1139 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
729 1140
730 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ 1141 for (i = 0; i < n_cmds; i++, cmds++) {
731 for (i = 0; i < n_cmds; i++) { 1142 /* if it is a software delay, flush and delay */
1143 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1144 pxafb_smart_flush(info);
1145 mdelay(*cmds & 0xff);
1146 continue;
1147 }
1148
1149 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
732 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8) 1150 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
733 pxafb_smart_flush(info); 1151 pxafb_smart_flush(info);
734 1152
735 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++; 1153 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
736 } 1154 }
737 1155
738 return 0; 1156 return 0;
@@ -764,7 +1182,9 @@ static void setup_smart_timing(struct pxafb_info *fbi,
764 LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); 1182 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
765 1183
766 fbi->reg_lccr2 = LCCR2_DisHght(var->yres); 1184 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
767 fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk)); 1185 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1186 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1187 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
768 1188
769 /* FIXME: make this configurable */ 1189 /* FIXME: make this configurable */
770 fbi->reg_cmdcr = 1; 1190 fbi->reg_cmdcr = 1;
@@ -789,11 +1209,15 @@ static int pxafb_smart_thread(void *arg)
789 if (try_to_freeze()) 1209 if (try_to_freeze())
790 continue; 1210 continue;
791 1211
1212 mutex_lock(&fbi->ctrlr_lock);
1213
792 if (fbi->state == C_ENABLE) { 1214 if (fbi->state == C_ENABLE) {
793 inf->smart_update(&fbi->fb); 1215 inf->smart_update(&fbi->fb);
794 complete(&fbi->refresh_done); 1216 complete(&fbi->refresh_done);
795 } 1217 }
796 1218
1219 mutex_unlock(&fbi->ctrlr_lock);
1220
797 set_current_state(TASK_INTERRUPTIBLE); 1221 set_current_state(TASK_INTERRUPTIBLE);
798 schedule_timeout(30 * HZ / 1000); 1222 schedule_timeout(30 * HZ / 1000);
799 } 1223 }
@@ -804,16 +1228,22 @@ static int pxafb_smart_thread(void *arg)
804 1228
805static int pxafb_smart_init(struct pxafb_info *fbi) 1229static int pxafb_smart_init(struct pxafb_info *fbi)
806{ 1230{
807 if (!(fbi->lccr0 | LCCR0_LCDT)) 1231 if (!(fbi->lccr0 & LCCR0_LCDT))
808 return 0; 1232 return 0;
809 1233
1234 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1235 fbi->n_smart_cmds = 0;
1236
1237 init_completion(&fbi->command_done);
1238 init_completion(&fbi->refresh_done);
1239
810 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, 1240 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
811 "lcd_refresh"); 1241 "lcd_refresh");
812 if (IS_ERR(fbi->smart_thread)) { 1242 if (IS_ERR(fbi->smart_thread)) {
813 printk(KERN_ERR "%s: unable to create kernel thread\n", 1243 pr_err("%s: unable to create kernel thread\n", __func__);
814 __func__);
815 return PTR_ERR(fbi->smart_thread); 1244 return PTR_ERR(fbi->smart_thread);
816 } 1245 }
1246
817 return 0; 1247 return 0;
818} 1248}
819#else 1249#else
@@ -826,7 +1256,9 @@ int pxafb_smart_flush(struct fb_info *info)
826{ 1256{
827 return 0; 1257 return 0;
828} 1258}
829#endif /* CONFIG_FB_SMART_PANEL */ 1259
1260static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1261#endif /* CONFIG_FB_PXA_SMARTPANEL */
830 1262
831static void setup_parallel_timing(struct pxafb_info *fbi, 1263static void setup_parallel_timing(struct pxafb_info *fbi,
832 struct fb_var_screeninfo *var) 1264 struct fb_var_screeninfo *var)
@@ -874,51 +1306,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
874 struct pxafb_info *fbi) 1306 struct pxafb_info *fbi)
875{ 1307{
876 u_long flags; 1308 u_long flags;
877 size_t nbytes;
878
879#if DEBUG_VAR
880 if (!(fbi->lccr0 & LCCR0_LCDT)) {
881 if (var->xres < 16 || var->xres > 1024)
882 printk(KERN_ERR "%s: invalid xres %d\n",
883 fbi->fb.fix.id, var->xres);
884 switch (var->bits_per_pixel) {
885 case 1:
886 case 2:
887 case 4:
888 case 8:
889 case 16:
890 case 24:
891 case 32:
892 break;
893 default:
894 printk(KERN_ERR "%s: invalid bit depth %d\n",
895 fbi->fb.fix.id, var->bits_per_pixel);
896 break;
897 }
898 1309
899 if (var->hsync_len < 1 || var->hsync_len > 64)
900 printk(KERN_ERR "%s: invalid hsync_len %d\n",
901 fbi->fb.fix.id, var->hsync_len);
902 if (var->left_margin < 1 || var->left_margin > 255)
903 printk(KERN_ERR "%s: invalid left_margin %d\n",
904 fbi->fb.fix.id, var->left_margin);
905 if (var->right_margin < 1 || var->right_margin > 255)
906 printk(KERN_ERR "%s: invalid right_margin %d\n",
907 fbi->fb.fix.id, var->right_margin);
908 if (var->yres < 1 || var->yres > 1024)
909 printk(KERN_ERR "%s: invalid yres %d\n",
910 fbi->fb.fix.id, var->yres);
911 if (var->vsync_len < 1 || var->vsync_len > 64)
912 printk(KERN_ERR "%s: invalid vsync_len %d\n",
913 fbi->fb.fix.id, var->vsync_len);
914 if (var->upper_margin < 0 || var->upper_margin > 255)
915 printk(KERN_ERR "%s: invalid upper_margin %d\n",
916 fbi->fb.fix.id, var->upper_margin);
917 if (var->lower_margin < 0 || var->lower_margin > 255)
918 printk(KERN_ERR "%s: invalid lower_margin %d\n",
919 fbi->fb.fix.id, var->lower_margin);
920 }
921#endif
922 /* Update shadow copy atomically */ 1310 /* Update shadow copy atomically */
923 local_irq_save(flags); 1311 local_irq_save(flags);
924 1312
@@ -929,23 +1317,13 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
929#endif 1317#endif
930 setup_parallel_timing(fbi, var); 1318 setup_parallel_timing(fbi, var);
931 1319
1320 setup_base_frame(fbi, 0);
1321
932 fbi->reg_lccr0 = fbi->lccr0 | 1322 fbi->reg_lccr0 = fbi->lccr0 |
933 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | 1323 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
934 LCCR0_QDM | LCCR0_BM | LCCR0_OUM); 1324 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
935 1325
936 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var); 1326 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
937
938 nbytes = var->yres * fbi->fb.fix.line_length;
939
940 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
941 nbytes = nbytes / 2;
942 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
943 }
944
945 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
946 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
947 else
948 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
949 1327
950 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; 1328 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
951 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); 1329 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
@@ -959,6 +1337,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
959 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || 1337 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
960 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || 1338 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
961 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || 1339 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1340 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
962 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || 1341 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
963 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])) 1342 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
964 pxafb_schedule_work(fbi, C_REENABLE); 1343 pxafb_schedule_work(fbi, C_REENABLE);
@@ -976,67 +1355,16 @@ static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
976{ 1355{
977 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); 1356 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
978 1357
979 if (pxafb_backlight_power) 1358 if (fbi->backlight_power)
980 pxafb_backlight_power(on); 1359 fbi->backlight_power(on);
981} 1360}
982 1361
983static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) 1362static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
984{ 1363{
985 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); 1364 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
986 1365
987 if (pxafb_lcd_power) 1366 if (fbi->lcd_power)
988 pxafb_lcd_power(on, &fbi->fb.var); 1367 fbi->lcd_power(on, &fbi->fb.var);
989}
990
991static void pxafb_setup_gpio(struct pxafb_info *fbi)
992{
993 int gpio, ldd_bits;
994 unsigned int lccr0 = fbi->lccr0;
995
996 /*
997 * setup is based on type of panel supported
998 */
999
1000 /* 4 bit interface */
1001 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
1002 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
1003 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
1004 ldd_bits = 4;
1005
1006 /* 8 bit interface */
1007 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
1008 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1009 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
1010 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1011 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1012 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
1013 ldd_bits = 8;
1014
1015 /* 16 bit interface */
1016 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1017 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1018 (lccr0 & LCCR0_PAS) == LCCR0_Act))
1019 ldd_bits = 16;
1020
1021 else {
1022 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
1023 "bits per pixel\n");
1024 return;
1025 }
1026
1027 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
1028 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
1029 /* 18 bit interface */
1030 if (fbi->fb.var.bits_per_pixel > 16) {
1031 pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
1032 pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
1033 }
1034 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
1035 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
1036 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
1037
1038 if ((lccr0 & LCCR0_PAS) == 0)
1039 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
1040} 1368}
1041 1369
1042static void pxafb_enable_controller(struct pxafb_info *fbi) 1370static void pxafb_enable_controller(struct pxafb_info *fbi)
@@ -1056,6 +1384,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
1056 return; 1384 return;
1057 1385
1058 /* Sequence from 11.7.10 */ 1386 /* Sequence from 11.7.10 */
1387 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1059 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1388 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1060 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1389 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1061 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1390 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
@@ -1097,8 +1426,9 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
1097static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) 1426static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1098{ 1427{
1099 struct pxafb_info *fbi = dev_id; 1428 struct pxafb_info *fbi = dev_id;
1100 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR); 1429 unsigned int lccr0, lcsr, lcsr1;
1101 1430
1431 lcsr = lcd_readl(fbi, LCSR);
1102 if (lcsr & LCSR_LDD) { 1432 if (lcsr & LCSR_LDD) {
1103 lccr0 = lcd_readl(fbi, LCCR0); 1433 lccr0 = lcd_readl(fbi, LCCR0);
1104 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); 1434 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
@@ -1109,8 +1439,18 @@ static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1109 if (lcsr & LCSR_CMD_INT) 1439 if (lcsr & LCSR_CMD_INT)
1110 complete(&fbi->command_done); 1440 complete(&fbi->command_done);
1111#endif 1441#endif
1112
1113 lcd_writel(fbi, LCSR, lcsr); 1442 lcd_writel(fbi, LCSR, lcsr);
1443
1444#ifdef CONFIG_FB_PXA_OVERLAY
1445 lcsr1 = lcd_readl(fbi, LCSR1);
1446 if (lcsr1 & LCSR1_BS(1))
1447 complete(&fbi->overlay[0].branch_done);
1448
1449 if (lcsr1 & LCSR1_BS(2))
1450 complete(&fbi->overlay[1].branch_done);
1451
1452 lcd_writel(fbi, LCSR1, lcsr1);
1453#endif
1114 return IRQ_HANDLED; 1454 return IRQ_HANDLED;
1115} 1455}
1116 1456
@@ -1181,7 +1521,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1181 if (old_state == C_ENABLE) { 1521 if (old_state == C_ENABLE) {
1182 __pxafb_lcd_power(fbi, 0); 1522 __pxafb_lcd_power(fbi, 0);
1183 pxafb_disable_controller(fbi); 1523 pxafb_disable_controller(fbi);
1184 pxafb_setup_gpio(fbi);
1185 pxafb_enable_controller(fbi); 1524 pxafb_enable_controller(fbi);
1186 __pxafb_lcd_power(fbi, 1); 1525 __pxafb_lcd_power(fbi, 1);
1187 } 1526 }
@@ -1204,7 +1543,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1204 */ 1543 */
1205 if (old_state != C_ENABLE) { 1544 if (old_state != C_ENABLE) {
1206 fbi->state = C_ENABLE; 1545 fbi->state = C_ENABLE;
1207 pxafb_setup_gpio(fbi);
1208 pxafb_enable_controller(fbi); 1546 pxafb_enable_controller(fbi);
1209 __pxafb_lcd_power(fbi, 1); 1547 __pxafb_lcd_power(fbi, 1);
1210 __pxafb_backlight_power(fbi, 1); 1548 __pxafb_backlight_power(fbi, 1);
@@ -1303,77 +1641,34 @@ static int pxafb_resume(struct platform_device *dev)
1303#define pxafb_resume NULL 1641#define pxafb_resume NULL
1304#endif 1642#endif
1305 1643
1306/* 1644static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1307 * pxafb_map_video_memory():
1308 * Allocates the DRAM memory for the frame buffer. This buffer is
1309 * remapped into a non-cached, non-buffered, memory region to
1310 * allow palette and pixel writes to occur without flushing the
1311 * cache. Once this area is remapped, all virtual memory
1312 * access to the video memory should occur at the new region.
1313 */
1314static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1315{ 1645{
1316 /* 1646 int size = PAGE_ALIGN(fbi->video_mem_size);
1317 * We reserve one page for the palette, plus the size
1318 * of the framebuffer.
1319 */
1320 fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1321 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1322 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1323 &fbi->map_dma, GFP_KERNEL);
1324
1325 if (fbi->map_cpu) {
1326 /* prevent initial garbage on screen */
1327 memset(fbi->map_cpu, 0, fbi->map_size);
1328 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1329 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1330
1331 /*
1332 * FIXME: this is actually the wrong thing to place in
1333 * smem_start. But fbdev suffers from the problem that
1334 * it needs an API which doesn't exist (in this case,
1335 * dma_writecombine_mmap)
1336 */
1337 fbi->fb.fix.smem_start = fbi->screen_dma;
1338 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1339
1340 fbi->dma_buff = (void *) fbi->map_cpu;
1341 fbi->dma_buff_phys = fbi->map_dma;
1342 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1343 1647
1344 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16)); 1648 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1649 if (fbi->video_mem == NULL)
1650 return -ENOMEM;
1345 1651
1346#ifdef CONFIG_FB_PXA_SMARTPANEL 1652 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1347 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; 1653 fbi->video_mem_size = size;
1348 fbi->n_smart_cmds = 0;
1349#endif
1350 }
1351
1352 return fbi->map_cpu ? 0 : -ENOMEM;
1353}
1354 1654
1355static void pxafb_decode_mode_info(struct pxafb_info *fbi, 1655 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1356 struct pxafb_mode_info *modes, 1656 fbi->fb.fix.smem_len = fbi->video_mem_size;
1357 unsigned int num_modes) 1657 fbi->fb.screen_base = fbi->video_mem;
1358{
1359 unsigned int i, smemlen;
1360
1361 pxafb_setmode(&fbi->fb.var, &modes[0]);
1362 1658
1363 for (i = 0; i < num_modes; i++) { 1659 return fbi->video_mem ? 0 : -ENOMEM;
1364 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1365 if (smemlen > fbi->fb.fix.smem_len)
1366 fbi->fb.fix.smem_len = smemlen;
1367 }
1368} 1660}
1369 1661
1370static void pxafb_decode_mach_info(struct pxafb_info *fbi, 1662static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1371 struct pxafb_mach_info *inf) 1663 struct pxafb_mach_info *inf)
1372{ 1664{
1373 unsigned int lcd_conn = inf->lcd_conn; 1665 unsigned int lcd_conn = inf->lcd_conn;
1666 struct pxafb_mode_info *m;
1667 int i;
1374 1668
1375 fbi->cmap_inverse = inf->cmap_inverse; 1669 fbi->cmap_inverse = inf->cmap_inverse;
1376 fbi->cmap_static = inf->cmap_static; 1670 fbi->cmap_static = inf->cmap_static;
1671 fbi->lccr4 = inf->lccr4;
1377 1672
1378 switch (lcd_conn & LCD_TYPE_MASK) { 1673 switch (lcd_conn & LCD_TYPE_MASK) {
1379 case LCD_TYPE_MONO_STN: 1674 case LCD_TYPE_MONO_STN:
@@ -1398,7 +1693,6 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1398 /* fall back to backward compatibility way */ 1693 /* fall back to backward compatibility way */
1399 fbi->lccr0 = inf->lccr0; 1694 fbi->lccr0 = inf->lccr0;
1400 fbi->lccr3 = inf->lccr3; 1695 fbi->lccr3 = inf->lccr3;
1401 fbi->lccr4 = inf->lccr4;
1402 goto decode_mode; 1696 goto decode_mode;
1403 } 1697 }
1404 1698
@@ -1412,7 +1706,22 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1412 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; 1706 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1413 1707
1414decode_mode: 1708decode_mode:
1415 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes); 1709 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1710
1711 /* decide video memory size as follows:
1712 * 1. default to mode of maximum resolution
1713 * 2. allow platform to override
1714 * 3. allow module parameter to override
1715 */
1716 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1717 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1718 m->xres * m->yres * m->bpp / 8);
1719
1720 if (inf->video_mem_size > fbi->video_mem_size)
1721 fbi->video_mem_size = inf->video_mem_size;
1722
1723 if (video_mem_size > fbi->video_mem_size)
1724 fbi->video_mem_size = video_mem_size;
1416} 1725}
1417 1726
1418static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) 1727static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
@@ -1429,7 +1738,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1429 memset(fbi, 0, sizeof(struct pxafb_info)); 1738 memset(fbi, 0, sizeof(struct pxafb_info));
1430 fbi->dev = dev; 1739 fbi->dev = dev;
1431 1740
1432 fbi->clk = clk_get(dev, "LCDCLK"); 1741 fbi->clk = clk_get(dev, NULL);
1433 if (IS_ERR(fbi->clk)) { 1742 if (IS_ERR(fbi->clk)) {
1434 kfree(fbi); 1743 kfree(fbi);
1435 return NULL; 1744 return NULL;
@@ -1440,7 +1749,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1440 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1749 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1441 fbi->fb.fix.type_aux = 0; 1750 fbi->fb.fix.type_aux = 0;
1442 fbi->fb.fix.xpanstep = 0; 1751 fbi->fb.fix.xpanstep = 0;
1443 fbi->fb.fix.ypanstep = 0; 1752 fbi->fb.fix.ypanstep = 1;
1444 fbi->fb.fix.ywrapstep = 0; 1753 fbi->fb.fix.ywrapstep = 0;
1445 fbi->fb.fix.accel = FB_ACCEL_NONE; 1754 fbi->fb.fix.accel = FB_ACCEL_NONE;
1446 1755
@@ -1448,7 +1757,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1448 fbi->fb.var.activate = FB_ACTIVATE_NOW; 1757 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1449 fbi->fb.var.height = -1; 1758 fbi->fb.var.height = -1;
1450 fbi->fb.var.width = -1; 1759 fbi->fb.var.width = -1;
1451 fbi->fb.var.accel_flags = 0; 1760 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1452 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; 1761 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1453 1762
1454 fbi->fb.fbops = &pxafb_ops; 1763 fbi->fb.fbops = &pxafb_ops;
@@ -1468,10 +1777,6 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1468 INIT_WORK(&fbi->task, pxafb_task); 1777 INIT_WORK(&fbi->task, pxafb_task);
1469 mutex_init(&fbi->ctrlr_lock); 1778 mutex_init(&fbi->ctrlr_lock);
1470 init_completion(&fbi->disable_done); 1779 init_completion(&fbi->disable_done);
1471#ifdef CONFIG_FB_PXA_SMARTPANEL
1472 init_completion(&fbi->command_done);
1473 init_completion(&fbi->refresh_done);
1474#endif
1475 1780
1476 return fbi; 1781 return fbi;
1477} 1782}
@@ -1544,7 +1849,9 @@ static int __devinit parse_opt(struct device *dev, char *this_opt)
1544 1849
1545 s[0] = '\0'; 1850 s[0] = '\0';
1546 1851
1547 if (!strncmp(this_opt, "mode:", 5)) { 1852 if (!strncmp(this_opt, "vmem:", 5)) {
1853 video_mem_size = memparse(this_opt + 5, NULL);
1854 } else if (!strncmp(this_opt, "mode:", 5)) {
1548 return parse_opt_mode(dev, this_opt); 1855 return parse_opt_mode(dev, this_opt);
1549 } else if (!strncmp(this_opt, "pixclock:", 9)) { 1856 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1550 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); 1857 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
@@ -1748,8 +2055,7 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1748 ret = -EINVAL; 2055 ret = -EINVAL;
1749 goto failed; 2056 goto failed;
1750 } 2057 }
1751 pxafb_backlight_power = inf->pxafb_backlight_power; 2058
1752 pxafb_lcd_power = inf->pxafb_lcd_power;
1753 fbi = pxafb_init_fbinfo(&dev->dev); 2059 fbi = pxafb_init_fbinfo(&dev->dev);
1754 if (!fbi) { 2060 if (!fbi) {
1755 /* only reason for pxafb_init_fbinfo to fail is kmalloc */ 2061 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
@@ -1758,6 +2064,9 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1758 goto failed; 2064 goto failed;
1759 } 2065 }
1760 2066
2067 fbi->backlight_power = inf->pxafb_backlight_power;
2068 fbi->lcd_power = inf->pxafb_lcd_power;
2069
1761 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 2070 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1762 if (r == NULL) { 2071 if (r == NULL) {
1763 dev_err(&dev->dev, "no I/O memory resource defined\n"); 2072 dev_err(&dev->dev, "no I/O memory resource defined\n");
@@ -1779,12 +2088,20 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1779 goto failed_free_res; 2088 goto failed_free_res;
1780 } 2089 }
1781 2090
1782 /* Initialize video memory */ 2091 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1783 ret = pxafb_map_video_memory(fbi); 2092 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2093 &fbi->dma_buff_phys, GFP_KERNEL);
2094 if (fbi->dma_buff == NULL) {
2095 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2096 ret = -ENOMEM;
2097 goto failed_free_io;
2098 }
2099
2100 ret = pxafb_init_video_memory(fbi);
1784 if (ret) { 2101 if (ret) {
1785 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); 2102 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1786 ret = -ENOMEM; 2103 ret = -ENOMEM;
1787 goto failed_free_io; 2104 goto failed_free_dma;
1788 } 2105 }
1789 2106
1790 irq = platform_get_irq(dev, 0); 2107 irq = platform_get_irq(dev, 0);
@@ -1801,13 +2118,12 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1801 goto failed_free_mem; 2118 goto failed_free_mem;
1802 } 2119 }
1803 2120
1804#ifdef CONFIG_FB_PXA_SMARTPANEL
1805 ret = pxafb_smart_init(fbi); 2121 ret = pxafb_smart_init(fbi);
1806 if (ret) { 2122 if (ret) {
1807 dev_err(&dev->dev, "failed to initialize smartpanel\n"); 2123 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1808 goto failed_free_irq; 2124 goto failed_free_irq;
1809 } 2125 }
1810#endif 2126
1811 /* 2127 /*
1812 * This makes sure that our colour bitfield 2128 * This makes sure that our colour bitfield
1813 * descriptors are correctly initialised. 2129 * descriptors are correctly initialised.
@@ -1833,6 +2149,8 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1833 goto failed_free_cmap; 2149 goto failed_free_cmap;
1834 } 2150 }
1835 2151
2152 pxafb_overlay_init(fbi);
2153
1836#ifdef CONFIG_CPU_FREQ 2154#ifdef CONFIG_CPU_FREQ
1837 fbi->freq_transition.notifier_call = pxafb_freq_transition; 2155 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1838 fbi->freq_policy.notifier_call = pxafb_freq_policy; 2156 fbi->freq_policy.notifier_call = pxafb_freq_policy;
@@ -1855,8 +2173,10 @@ failed_free_cmap:
1855failed_free_irq: 2173failed_free_irq:
1856 free_irq(irq, fbi); 2174 free_irq(irq, fbi);
1857failed_free_mem: 2175failed_free_mem:
1858 dma_free_writecombine(&dev->dev, fbi->map_size, 2176 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1859 fbi->map_cpu, fbi->map_dma); 2177failed_free_dma:
2178 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2179 fbi->dma_buff, fbi->dma_buff_phys);
1860failed_free_io: 2180failed_free_io:
1861 iounmap(fbi->mmio_base); 2181 iounmap(fbi->mmio_base);
1862failed_free_res: 2182failed_free_res:
@@ -1881,6 +2201,7 @@ static int __devexit pxafb_remove(struct platform_device *dev)
1881 2201
1882 info = &fbi->fb; 2202 info = &fbi->fb;
1883 2203
2204 pxafb_overlay_exit(fbi);
1884 unregister_framebuffer(info); 2205 unregister_framebuffer(info);
1885 2206
1886 pxafb_disable_controller(fbi); 2207 pxafb_disable_controller(fbi);
@@ -1891,8 +2212,10 @@ static int __devexit pxafb_remove(struct platform_device *dev)
1891 irq = platform_get_irq(dev, 0); 2212 irq = platform_get_irq(dev, 0);
1892 free_irq(irq, fbi); 2213 free_irq(irq, fbi);
1893 2214
1894 dma_free_writecombine(&dev->dev, fbi->map_size, 2215 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1895 fbi->map_cpu, fbi->map_dma); 2216
2217 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2218 fbi->dma_buff, fbi->dma_buff_phys);
1896 2219
1897 iounmap(fbi->mmio_base); 2220 iounmap(fbi->mmio_base);
1898 2221
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
index 31541b86f13d..2353521c5c8c 100644
--- a/drivers/video/pxafb.h
+++ b/drivers/video/pxafb.h
@@ -54,11 +54,55 @@ enum {
54#define PALETTE_SIZE (256 * 4) 54#define PALETTE_SIZE (256 * 4)
55#define CMD_BUFF_SIZE (1024 * 50) 55#define CMD_BUFF_SIZE (1024 * 50)
56 56
57/* NOTE: the palette and frame dma descriptors are doubled to allow
58 * the 2nd set for branch settings (FBRx)
59 */
57struct pxafb_dma_buff { 60struct pxafb_dma_buff {
58 unsigned char palette[PAL_MAX * PALETTE_SIZE]; 61 unsigned char palette[PAL_MAX * PALETTE_SIZE];
59 uint16_t cmd_buff[CMD_BUFF_SIZE]; 62 uint16_t cmd_buff[CMD_BUFF_SIZE];
60 struct pxafb_dma_descriptor pal_desc[PAL_MAX]; 63 struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
61 struct pxafb_dma_descriptor dma_desc[DMA_MAX]; 64 struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
65};
66
67enum {
68 OVERLAY1,
69 OVERLAY2,
70};
71
72enum {
73 OVERLAY_FORMAT_RGB = 0,
74 OVERLAY_FORMAT_YUV444_PACKED,
75 OVERLAY_FORMAT_YUV444_PLANAR,
76 OVERLAY_FORMAT_YUV422_PLANAR,
77 OVERLAY_FORMAT_YUV420_PLANAR,
78};
79
80#define NONSTD_TO_XPOS(x) (((x) >> 0) & 0x3ff)
81#define NONSTD_TO_YPOS(x) (((x) >> 10) & 0x3ff)
82#define NONSTD_TO_PFOR(x) (((x) >> 20) & 0x7)
83
84struct pxafb_layer;
85
86struct pxafb_layer_ops {
87 void (*enable)(struct pxafb_layer *);
88 void (*disable)(struct pxafb_layer *);
89 void (*setup)(struct pxafb_layer *);
90};
91
92struct pxafb_layer {
93 struct fb_info fb;
94 int id;
95 atomic_t usage;
96 uint32_t control[2];
97
98 struct pxafb_layer_ops *ops;
99
100 void __iomem *video_mem;
101 unsigned long video_mem_phys;
102 size_t video_mem_size;
103 struct completion branch_done;
104
105 struct pxafb_info *fbi;
62}; 106};
63 107
64struct pxafb_info { 108struct pxafb_info {
@@ -69,24 +113,15 @@ struct pxafb_info {
69 void __iomem *mmio_base; 113 void __iomem *mmio_base;
70 114
71 struct pxafb_dma_buff *dma_buff; 115 struct pxafb_dma_buff *dma_buff;
116 size_t dma_buff_size;
72 dma_addr_t dma_buff_phys; 117 dma_addr_t dma_buff_phys;
73 dma_addr_t fdadr[DMA_MAX]; 118 dma_addr_t fdadr[DMA_MAX * 2];
74 119
75 /* 120 void __iomem *video_mem; /* virtual address of frame buffer */
76 * These are the addresses we mapped 121 unsigned long video_mem_phys; /* physical address of frame buffer */
77 * the framebuffer memory region to. 122 size_t video_mem_size; /* size of the frame buffer */
78 */
79 /* raw memory addresses */
80 dma_addr_t map_dma; /* physical */
81 u_char * map_cpu; /* virtual */
82 u_int map_size;
83
84 /* addresses of pieces placed in raw buffer */
85 u_char * screen_cpu; /* virtual address of frame buffer */
86 dma_addr_t screen_dma; /* physical address of frame buffer */
87 u16 * palette_cpu; /* virtual address of palette memory */ 123 u16 * palette_cpu; /* virtual address of palette memory */
88 u_int palette_size; 124 u_int palette_size;
89 ssize_t video_offset;
90 125
91 u_int lccr0; 126 u_int lccr0;
92 u_int lccr3; 127 u_int lccr3;
@@ -120,10 +155,17 @@ struct pxafb_info {
120 struct task_struct *smart_thread; 155 struct task_struct *smart_thread;
121#endif 156#endif
122 157
158#ifdef CONFIG_FB_PXA_OVERLAY
159 struct pxafb_layer overlay[2];
160#endif
161
123#ifdef CONFIG_CPU_FREQ 162#ifdef CONFIG_CPU_FREQ
124 struct notifier_block freq_transition; 163 struct notifier_block freq_transition;
125 struct notifier_block freq_policy; 164 struct notifier_block freq_policy;
126#endif 165#endif
166
167 void (*lcd_power)(int, struct fb_var_screeninfo *);
168 void (*backlight_power)(int);
127}; 169};
128 170
129#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member) 171#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
@@ -148,4 +190,10 @@ struct pxafb_info {
148#define MIN_XRES 64 190#define MIN_XRES 64
149#define MIN_YRES 64 191#define MIN_YRES 64
150 192
193/* maximum X and Y resolutions - note these are limits from the register
194 * bits length instead of the real ones
195 */
196#define MAX_XRES 1024
197#define MAX_YRES 1024
198
151#endif /* __PXAFB_H__ */ 199#endif /* __PXAFB_H__ */
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
index c052bd4c0b06..076f946fa0f5 100644
--- a/drivers/video/sa1100fb.c
+++ b/drivers/video/sa1100fb.c
@@ -114,7 +114,7 @@
114 * - convert dma address types to dma_addr_t 114 * - convert dma address types to dma_addr_t
115 * - remove unused 'montype' stuff 115 * - remove unused 'montype' stuff
116 * - remove redundant zero inits of init_var after the initial 116 * - remove redundant zero inits of init_var after the initial
117 * memzero. 117 * memset.
118 * - remove allow_modeset (acornfb idea does not belong here) 118 * - remove allow_modeset (acornfb idea does not belong here)
119 * 119 *
120 * 2001/05/28: <rmk@arm.linux.org.uk> 120 * 2001/05/28: <rmk@arm.linux.org.uk>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 11:01:13 -0500