viafb: improve pitch handling

Split the pitch handling up and replaces the calculation from virtual xres
and bpp with fix.line_length which already contains the pitch and does not
add any constrains for the virtual resolution.

Also add a bit to the second pitch which the documentation mentions but
which was ignored by the driver.

Although it is a bit unclear what the right pitch for some LCD modes is
this patch should have no negative runtime impact.

Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Scott Fang <ScottFang@viatech.com.cn>
Cc: Joseph Chan <JosephChan@via.com.tw>
Cc: Harald Welte <laforge@gnumonks.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 23 insertions, 50 deletions

diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 86050e79b892..4910561a9d34 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -36,13 +36,6 @@ static const struct pci_device_id_info pciidlist[] = {
         {0, 0, 0}
 };
 
-struct offset offset_reg = {
-        /* IGA1 Offset Register */
-        {IGA1_OFFSET_REG_NUM, {{CR13, 0, 7}, {CR35, 5, 7} } },
-        /* IGA2 Offset Register */
-        {IGA2_OFFSET_REG_NUM, {{CR66, 0, 7}, {CR67, 0, 1} } }
-};
-
 static struct pll_map pll_value[] = {
         {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M},
         {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M},
@@ -648,6 +641,26 @@ void viafb_set_secondary_address(u32 addr)
         viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
 }
 
+void viafb_set_primary_pitch(u32 pitch)
+{
+        DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
+        /* spec does not say that first adapter skips 3 bits but old
+         * code did it and seems to be reasonable in analogy to 2nd adapter
+         */
+        pitch = pitch >> 3;
+        viafb_write_reg(0x13, VIACR, pitch & 0xFF);
+        viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
+}
+
+void viafb_set_secondary_pitch(u32 pitch)
+{
+        DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
+        pitch = pitch >> 3;
+        viafb_write_reg(0x66, VIACR, pitch & 0xFF);
+        viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
+        viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
+}
+
 void viafb_set_output_path(int device, int set_iga, int output_interface)
 {
         switch (device) {
@@ -1076,30 +1089,6 @@ void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
         }
 }
 
-void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga)
-{
-        int reg_value;
-        int viafb_load_reg_num;
-        struct io_register *reg;
-
-        switch (set_iga) {
-        case IGA1_IGA2:
-        case IGA1:
-                reg_value = IGA1_OFFSET_FORMULA(h_addr, bpp_byte);
-                viafb_load_reg_num = offset_reg.iga1_offset_reg.reg_num;
-                reg = offset_reg.iga1_offset_reg.reg;
-                viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
-                if (set_iga == IGA1)
-                        break;
-        case IGA2:
-                reg_value = IGA2_OFFSET_FORMULA(h_addr, bpp_byte);
-                viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
-                reg = offset_reg.iga2_offset_reg.reg;
-                viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
-                break;
-        }
-}
-
 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
 {
         int reg_value;
@@ -1869,7 +1858,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
         load_fix_bit_crtc_reg();
         viafb_lock_crt();
         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
-        viafb_load_offset_reg(h_addr, bpp_byte, set_iga);
         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
 
         /* load FIFO */
@@ -2322,6 +2310,9 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
                 }
         }
 
+        viafb_set_primary_pitch(viafbinfo->fix.line_length);
+        viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
+                : viafbinfo->fix.line_length);
         /* Update Refresh Rate Setting */
 
         /* Clear On Screen */
@@ -2738,24 +2729,6 @@ void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
         }
 }
 
-void viafb_memory_pitch_patch(struct fb_info *info)
-{
-        if (info->var.xres != info->var.xres_virtual) {
-                viafb_load_offset_reg(info->var.xres_virtual,
-                                info->var.bits_per_pixel >> 3, IGA1);
-
-                if (viafb_SAMM_ON) {
-                        viafb_load_offset_reg(viafb_second_virtual_xres,
-                                viafb_bpp1 >> 3,
-                                        IGA2);
-                } else {
-                        viafb_load_offset_reg(info->var.xres_virtual,
-                                        info->var.bits_per_pixel >> 3, IGA2);
-                }
-
-        }
-}
-
 /*According var's xres, yres fill var's other timing information*/
 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
                           int mode_index)