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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/video/sstfb.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/video/sstfb.c')
-rw-r--r--drivers/video/sstfb.c1722
1 files changed, 1722 insertions, 0 deletions
diff --git a/drivers/video/sstfb.c b/drivers/video/sstfb.c
new file mode 100644
index 000000000000..663d53657fa4
--- /dev/null
+++ b/drivers/video/sstfb.c
@@ -0,0 +1,1722 @@
1/*
2 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
3 *
4 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
5 *
6 * Created 15 Jan 2000 by Ghozlane Toumi
7 *
8 * Contributions (and many thanks) :
9 *
10 * 03/2001 James Simmons <jsimmons@infradead.org>
11 * 04/2001 Paul Mundt <lethal@chaoticdreams.org>
12 * 05/2001 Urs Ganse <ursg@uni.de>
13 * (initial work on voodoo2 port, interlace)
14 * 09/2002 Helge Deller <deller@gmx.de>
15 * (enable driver on big-endian machines (hppa), ioctl fixes)
16 * 12/2002 Helge Deller <deller@gmx.de>
17 * (port driver to new frambuffer infrastructure)
18 * 01/2003 Helge Deller <deller@gmx.de>
19 * (initial work on fb hardware acceleration for voodoo2)
20 *
21 */
22
23/*
24 * The voodoo1 has the following memory mapped address space:
25 * 0x000000 - 0x3fffff : registers (4MB)
26 * 0x400000 - 0x7fffff : linear frame buffer (4MB)
27 * 0x800000 - 0xffffff : texture memory (8MB)
28 */
29
30/*
31 * misc notes, TODOs, toASKs, and deep thoughts
32
33-TODO: at one time or another test that the mode is acceptable by the monitor
34-ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
35 wich one should i use ? is there any preferred one ? It seems ARGB is
36 the one ...
37-TODO: in set_var check the validity of timings (hsync vsync)...
38-TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
39 a nop command. so it's ok as long as the commands we pass don't go
40 through the fifo. warning: issuing a nop command seems to need pci_fifo
41-FIXME: in case of failure in the init sequence, be sure we return to a safe
42 state.
43-FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
44 */
45
46/*
47 * debug info
48 * SST_DEBUG : enable debugging
49 * SST_DEBUG_REG : debug registers
50 * 0 : no debug
51 * 1 : dac calls, [un]set_bits, FbiInit
52 * 2 : insane debug level (log every register read/write)
53 * SST_DEBUG_FUNC : functions
54 * 0 : no debug
55 * 1 : function call / debug ioctl
56 * 2 : variables
57 * 3 : flood . you don't want to do that. trust me.
58 * SST_DEBUG_VAR : debug display/var structs
59 * 0 : no debug
60 * 1 : dumps display, fb_var
61 *
62 * sstfb specific ioctls:
63 * toggle vga (0x46db) : toggle vga_pass_through
64 * fill fb (0x46dc) : fills fb
65 * test disp (0x46de) : draws a test image
66 */
67
68#undef SST_DEBUG
69
70/* enable 24/32 bpp functions ? (completely untested!) */
71#undef EN_24_32_BPP
72
73/*
74 Default video mode .
75 0 800x600@60 took from glide
76 1 640x480@75 took from glide
77 2 1024x768@76 std fb.mode
78 3 640x480@60 glide default */
79#define DEFAULT_MODE 3
80
81/*
82 * Includes
83 */
84
85#include <linux/config.h>
86#include <linux/string.h>
87#include <linux/kernel.h>
88#include <linux/module.h>
89#include <linux/fb.h>
90#include <linux/pci.h>
91#include <linux/delay.h>
92#include <linux/init.h>
93#include <linux/slab.h>
94#include <asm/io.h>
95#include <asm/ioctl.h>
96#include <asm/uaccess.h>
97#include <video/sstfb.h>
98
99
100/* initialized by setup */
101
102static int vgapass; /* enable Vga passthrough cable */
103static int mem; /* mem size in MB, 0 = autodetect */
104static int clipping = 1; /* use clipping (slower, safer) */
105static int gfxclk; /* force FBI freq in Mhz . Dangerous */
106static int slowpci; /* slow PCI settings */
107
108static char *mode_option __devinitdata;
109
110enum {
111 ID_VOODOO1 = 0,
112 ID_VOODOO2 = 1,
113};
114
115#define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
116
117static struct sst_spec voodoo_spec[] __devinitdata = {
118 { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
119 { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 },
120};
121
122static struct fb_var_screeninfo sstfb_default =
123#if ( DEFAULT_MODE == 0 )
124 { /* 800x600@60, 16 bpp .borowed from glide/sst1/include/sst1init.h */
125 800, 600, 800, 600, 0, 0, 16, 0,
126 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
127 0, 0, -1, -1, 0,
128 25000, 86, 41, 23, 1, 127, 4,
129 0, FB_VMODE_NONINTERLACED };
130#elif ( DEFAULT_MODE == 1 )
131 {/* 640x480@75, 16 bpp .borowed from glide/sst1/include/sst1init.h */
132 640, 480, 640, 480, 0, 0, 16, 0,
133 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
134 0, 0, -1, -1, 0,
135 31746, 118, 17, 16, 1, 63, 3,
136 0, FB_VMODE_NONINTERLACED };
137#elif ( DEFAULT_MODE == 2 )
138 { /* 1024x768@76 took from my /etc/fb.modes */
139 1024, 768, 1024, 768,0, 0, 16,0,
140 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
141 0, 0, -1, -1, 0,
142 11764, 208, 8, 36, 16, 120, 3 ,
143 0, FB_VMODE_NONINTERLACED };
144#elif ( DEFAULT_MODE == 3 )
145 { /* 640x480@60 , 16bpp glide default ?*/
146 640, 480, 640, 480, 0, 0, 16, 0,
147 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
148 0, 0, -1, -1, 0,
149 39721 , 38, 26 , 25 ,18 , 96 ,2,
150 0, FB_VMODE_NONINTERLACED };
151#elif
152 #error "Invalid DEFAULT_MODE value !"
153#endif
154
155
156/*
157 * debug functions
158 */
159
160static void sstfb_drawdebugimage(struct fb_info *info);
161static int sstfb_dump_regs(struct fb_info *info);
162
163
164#if (SST_DEBUG_REG > 0)
165static void sst_dbg_print_read_reg(u32 reg, u32 val) {
166 const char *regname;
167 switch (reg) {
168 case FBIINIT0: regname = "FbiInit0"; break;
169 case FBIINIT1: regname = "FbiInit1"; break;
170 case FBIINIT2: regname = "FbiInit2"; break;
171 case FBIINIT3: regname = "FbiInit3"; break;
172 case FBIINIT4: regname = "FbiInit4"; break;
173 case FBIINIT5: regname = "FbiInit5"; break;
174 case FBIINIT6: regname = "FbiInit6"; break;
175 default: regname = NULL; break;
176 }
177 if (regname == NULL)
178 r_ddprintk("sst_read(%#x): %#x\n", reg, val);
179 else
180 r_dprintk(" sst_read(%s): %#x\n", regname, val);
181}
182
183static void sst_dbg_print_write_reg(u32 reg, u32 val) {
184 const char *regname;
185 switch (reg) {
186 case FBIINIT0: regname = "FbiInit0"; break;
187 case FBIINIT1: regname = "FbiInit1"; break;
188 case FBIINIT2: regname = "FbiInit2"; break;
189 case FBIINIT3: regname = "FbiInit3"; break;
190 case FBIINIT4: regname = "FbiInit4"; break;
191 case FBIINIT5: regname = "FbiInit5"; break;
192 case FBIINIT6: regname = "FbiInit6"; break;
193 default: regname = NULL; break;
194 }
195 if (regname == NULL)
196 r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
197 else
198 r_dprintk(" sst_write(%s, %#x)\n", regname, val);
199}
200#else /* (SST_DEBUG_REG > 0) */
201# define sst_dbg_print_read_reg(reg, val) do {} while(0)
202# define sst_dbg_print_write_reg(reg, val) do {} while(0)
203#endif /* (SST_DEBUG_REG > 0) */
204
205/*
206 * hardware access functions
207 */
208
209/* register access */
210#define sst_read(reg) __sst_read(par->mmio_vbase, reg)
211#define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val)
212#define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val)
213#define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val)
214#define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg)
215#define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val)
216#define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
217#define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
218
219static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
220{
221 u32 ret = readl(vbase + reg);
222 sst_dbg_print_read_reg(reg, ret);
223 return ret;
224}
225
226static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
227{
228 sst_dbg_print_write_reg(reg, val);
229 writel(val, vbase + reg);
230}
231
232static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
233{
234 r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
235 __sst_write(vbase, reg, __sst_read(vbase, reg) | val);
236}
237
238static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
239{
240 r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
241 __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
242}
243
244/*
245 * wait for the fbi chip. ASK: what happens if the fbi is stuck ?
246 *
247 * the FBI is supposed to be ready if we receive 5 time
248 * in a row a "idle" answer to our requests
249 */
250
251#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
252
253static int __sst_wait_idle(u8 __iomem *vbase)
254{
255 int count = 0;
256
257 /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
258
259 while(1) {
260 if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
261 f_dddprintk("status: busy\n");
262/* FIXME basicaly, this is a busy wait. maybe not that good. oh well;
263 * this is a small loop after all.
264 * Or maybe we should use mdelay() or udelay() here instead ? */
265 count = 0;
266 } else {
267 count++;
268 f_dddprintk("status: idle(%d)\n", count);
269 }
270 if (count >= 5) return 1;
271/* XXX do something to avoid hanging the machine if the voodoo is out */
272 }
273}
274
275
276/* dac access */
277/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
278static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
279{
280 u8 ret;
281
282 reg &= 0x07;
283 __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
284 __sst_wait_idle(vbase);
285 /* udelay(10); */
286 ret = __sst_read(vbase, DAC_READ) & 0xff;
287 r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
288
289 return ret;
290}
291
292static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
293{
294 r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
295 reg &= 0x07;
296 __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
297}
298
299/* indexed access to ti/att dacs */
300static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
301{
302 u32 ret;
303
304 __sst_dac_write(vbase, DACREG_ADDR_I, reg);
305 ret = __sst_dac_read(vbase, DACREG_DATA_I);
306 r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
307 return ret;
308}
309static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
310{
311 r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
312 __sst_dac_write(vbase, DACREG_ADDR_I, reg);
313 __sst_dac_write(vbase, DACREG_DATA_I, val);
314}
315
316/* compute the m,n,p , returns the real freq
317 * (ics datasheet : N <-> N1 , P <-> N2)
318 *
319 * Fout= Fref * (M+2)/( 2^P * (N+2))
320 * we try to get close to the asked freq
321 * with P as high, and M as low as possible
322 * range:
323 * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
324 * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
325 * we'll use the lowest limitation, should be precise enouth
326 */
327static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
328{
329 int m, m2, n, p, best_err, fout;
330 int best_n = -1;
331 int best_m = -1;
332
333 best_err = freq;
334 p = 3;
335 /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
336 while (((1 << p) * freq > VCO_MAX) && (p >= 0))
337 p--;
338 if (p == -1)
339 return -EINVAL;
340 for (n = 1; n < 32; n++) {
341 /* calc 2 * m so we can round it later*/
342 m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
343
344 m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
345 if (m >= 128)
346 break;
347 fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
348 if ((abs(fout - freq) < best_err) && (m > 0)) {
349 best_n = n;
350 best_m = m;
351 best_err = abs(fout - freq);
352 /* we get the lowest m , allowing 0.5% error in freq*/
353 if (200*best_err < freq) break;
354 }
355 }
356 if (best_n == -1) /* unlikely, but who knows ? */
357 return -EINVAL;
358 t->p = p;
359 t->n = best_n;
360 t->m = best_m;
361 *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
362 f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
363 t->m, t->n, t->p, *freq_out);
364 return 0;
365}
366
367/*
368 * clear lfb screen
369 */
370static void sstfb_clear_screen(struct fb_info *info)
371{
372 /* clear screen */
373 fb_memset(info->screen_base, 0, info->fix.smem_len);
374}
375
376
377/**
378 * sstfb_check_var - Optional function. Validates a var passed in.
379 * @var: frame buffer variable screen structure
380 * @info: frame buffer structure that represents a single frame buffer
381 */
382static int sstfb_check_var(struct fb_var_screeninfo *var,
383 struct fb_info *info)
384{
385 struct sstfb_par *par = (struct sstfb_par *) info->par;
386 int hSyncOff = var->xres + var->right_margin + var->left_margin;
387 int vSyncOff = var->yres + var->lower_margin + var->upper_margin;
388 int vBackPorch = var->left_margin, yDim = var->yres;
389 int vSyncOn = var->vsync_len;
390 int tiles_in_X, real_length;
391 unsigned int freq;
392
393 if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
394 eprintk("Pixclock at %ld KHZ out of range\n",
395 PICOS2KHZ(var->pixclock));
396 return -EINVAL;
397 }
398 var->pixclock = KHZ2PICOS(freq);
399
400 if (var->vmode & FB_VMODE_INTERLACED)
401 vBackPorch += (vBackPorch % 2);
402 if (var->vmode & FB_VMODE_DOUBLE) {
403 vBackPorch <<= 1;
404 yDim <<=1;
405 vSyncOn <<=1;
406 vSyncOff <<=1;
407 }
408
409 switch (var->bits_per_pixel) {
410 case 0 ... 16 :
411 var->bits_per_pixel = 16;
412 break;
413#ifdef EN_24_32_BPP
414 case 17 ... 24 :
415 var->bits_per_pixel = 24;
416 break;
417 case 25 ... 32 :
418 var->bits_per_pixel = 32;
419 break;
420#endif
421 default :
422 eprintk("Unsupported bpp %d\n", var->bits_per_pixel);
423 return -EINVAL;
424 }
425
426 /* validity tests */
427 if ((var->xres <= 1) || (yDim <= 0 )
428 || (var->hsync_len <= 1)
429 || (hSyncOff <= 1)
430 || (var->left_margin <= 2)
431 || (vSyncOn <= 0)
432 || (vSyncOff <= 0)
433 || (vBackPorch <= 0)) {
434 return -EINVAL;
435 }
436
437 if (IS_VOODOO2(par)) {
438 /* Voodoo 2 limits */
439 tiles_in_X = (var->xres + 63 ) / 64 * 2;
440
441 if (((var->xres - 1) >= POW2(11)) || (yDim >= POW2(11))) {
442 eprintk("Unsupported resolution %dx%d\n",
443 var->xres, var->yres);
444 return -EINVAL;
445 }
446
447 if (((var->hsync_len-1) >= POW2(9))
448 || ((hSyncOff-1) >= POW2(11))
449 || ((var->left_margin - 2) >= POW2(9))
450 || (vSyncOn >= POW2(13))
451 || (vSyncOff >= POW2(13))
452 || (vBackPorch >= POW2(9))
453 || (tiles_in_X >= POW2(6))
454 || (tiles_in_X <= 0)) {
455 eprintk("Unsupported Timings\n");
456 return -EINVAL;
457 }
458 } else {
459 /* Voodoo limits */
460 tiles_in_X = (var->xres + 63 ) / 64;
461
462 if (var->vmode) {
463 eprintk("Interlace/Doublescan not supported %#x\n",
464 var->vmode);
465 return -EINVAL;
466 }
467 if (((var->xres - 1) >= POW2(10)) || (var->yres >= POW2(10))) {
468 eprintk("Unsupported resolution %dx%d\n",
469 var->xres, var->yres);
470 return -EINVAL;
471 }
472 if (((var->hsync_len - 1) >= POW2(8))
473 || ((hSyncOff-1) >= POW2(10))
474 || ((var->left_margin - 2) >= POW2(8))
475 || (vSyncOn >= POW2(12))
476 || (vSyncOff >= POW2(12))
477 || (vBackPorch >= POW2(8))
478 || (tiles_in_X >= POW2(4))
479 || (tiles_in_X <= 0)) {
480 eprintk("Unsupported Timings\n");
481 return -EINVAL;
482 }
483 }
484
485 /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
486 /* FIXME: i don't like this... looks wrong */
487 real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 )
488 * ((var->bits_per_pixel == 16) ? 2 : 4);
489
490 if ((real_length * yDim) > info->fix.smem_len) {
491 eprintk("Not enough video memory\n");
492 return -ENOMEM;
493 }
494
495 var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
496 var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
497 var->xoffset = 0;
498 var->yoffset = 0;
499 var->height = -1;
500 var->width = -1;
501
502 /*
503 * correct the color bit fields
504 */
505 /* var->{red|green|blue}.msb_right = 0; */
506
507 switch (var->bits_per_pixel) {
508 case 16: /* RGB 565 LfbMode 0 */
509 var->red.length = 5;
510 var->green.length = 6;
511 var->blue.length = 5;
512 var->transp.length = 0;
513
514 var->red.offset = 11;
515 var->green.offset = 5;
516 var->blue.offset = 0;
517 var->transp.offset = 0;
518 break;
519#ifdef EN_24_32_BPP
520 case 24: /* RGB 888 LfbMode 4 */
521 case 32: /* ARGB 8888 LfbMode 5 */
522 var->red.length = 8;
523 var->green.length = 8;
524 var->blue.length = 8;
525 var->transp.length = 0;
526
527 var->red.offset = 16;
528 var->green.offset = 8;
529 var->blue.offset = 0;
530 var->transp.offset = 0; /* in 24bpp we fake a 32 bpp mode */
531 break;
532#endif
533 default:
534 return -EINVAL;
535 }
536 return 0;
537}
538
539/**
540 * sstfb_set_par - Optional function. Alters the hardware state.
541 * @info: frame buffer structure that represents a single frame buffer
542 */
543static int sstfb_set_par(struct fb_info *info)
544{
545 struct sstfb_par *par = (struct sstfb_par *) info->par;
546 u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
547 struct pci_dev *sst_dev = par->dev;
548 unsigned int freq;
549 int ntiles;
550
551 par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin;
552
553 par->yDim = info->var.yres;
554 par->vSyncOn = info->var.vsync_len;
555 par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin;
556 par->vBackPorch = info->var.upper_margin;
557
558 /* We need par->pll */
559 sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
560
561 if (info->var.vmode & FB_VMODE_INTERLACED)
562 par->vBackPorch += (par->vBackPorch % 2);
563 if (info->var.vmode & FB_VMODE_DOUBLE) {
564 par->vBackPorch <<= 1;
565 par->yDim <<=1;
566 par->vSyncOn <<=1;
567 par->vSyncOff <<=1;
568 }
569
570 if (IS_VOODOO2(par)) {
571 /* voodoo2 has 32 pixel wide tiles , BUT stange things
572 happen with odd number of tiles */
573 par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
574 } else {
575 /* voodoo1 has 64 pixels wide tiles. */
576 par->tiles_in_X = (info->var.xres + 63 ) / 64;
577 }
578
579 f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
580 f_ddprintk("%-7d %-8d %-7d %-8d\n",
581 info->var.hsync_len, par->hSyncOff,
582 par->vSyncOn, par->vSyncOff);
583 f_ddprintk("left_margin upper_margin xres yres Freq\n");
584 f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
585 info->var.left_margin, info->var.upper_margin,
586 info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
587
588 sst_write(NOPCMD, 0);
589 sst_wait_idle();
590 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
591 sst_set_bits(FBIINIT1, VIDEO_RESET);
592 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
593 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
594 sst_wait_idle();
595
596 /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
597
598 sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
599 sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
600 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
601 sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn);
602
603 fbiinit2 = sst_read(FBIINIT2);
604 fbiinit3 = sst_read(FBIINIT3);
605
606 /* everything is reset. we enable fbiinit2/3 remap : dac acces ok */
607 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
608 PCI_EN_INIT_WR | PCI_REMAP_DAC );
609
610 par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
611
612 /* set video clock */
613 par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
614
615 /* disable fbiinit2/3 remap */
616 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
617 PCI_EN_INIT_WR);
618
619 /* restore fbiinit2/3 */
620 sst_write(FBIINIT2,fbiinit2);
621 sst_write(FBIINIT3,fbiinit3);
622
623 fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
624 | EN_DATA_OE
625 | EN_BLANK_OE
626 | EN_HVSYNC_OE
627 | EN_DCLK_OE
628 /* | (15 << TILES_IN_X_SHIFT) */
629 | SEL_INPUT_VCLK_2X
630 /* | (2 << VCLK_2X_SEL_DEL_SHIFT)
631 | (2 << VCLK_DEL_SHIFT) */;
632/* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
633 in (near) future set them accordingly to revision + resolution (cf glide)
634 first understand what it stands for :)
635 FIXME: there are some artefacts... check for the vclk_in_delay
636 lets try with 6ns delay in both vclk_out & in...
637 doh... they're still there :\
638*/
639
640 ntiles = par->tiles_in_X;
641 if (IS_VOODOO2(par)) {
642 fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
643 | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
644/* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
645 and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
646 write our value. BTW due to the dac unable to read odd number of tiles, this
647 field is always null ... */
648 fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
649 }
650 else
651 fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
652
653 switch (info->var.bits_per_pixel) {
654 case 16:
655 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL;
656 break;
657#ifdef EN_24_32_BPP
658 case 24:
659 case 32:
660 /* sst_set_bits(FBIINIT1, SEL_SOURCE_VCLK_2X_DIV2 | EN_24BPP);*/
661 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL | EN_24BPP;
662 break;
663#endif
664 default:
665 return -EINVAL;
666 }
667 sst_write(FBIINIT1, fbiinit1);
668 if (IS_VOODOO2(par)) {
669 sst_write(FBIINIT6, fbiinit6);
670 fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
671 if (info->var.vmode & FB_VMODE_INTERLACED)
672 fbiinit5 |= INTERLACE;
673 if (info->var.vmode & FB_VMODE_DOUBLE)
674 fbiinit5 |= VDOUBLESCAN;
675 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
676 fbiinit5 |= HSYNC_HIGH;
677 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
678 fbiinit5 |= VSYNC_HIGH;
679 sst_write(FBIINIT5, fbiinit5);
680 }
681 sst_wait_idle();
682 sst_unset_bits(FBIINIT1, VIDEO_RESET);
683 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
684 sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
685 /* disables fbiinit writes */
686 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
687
688 /* set lfbmode : set mode + front buffer for reads/writes
689 + disable pipeline */
690 switch (info->var.bits_per_pixel) {
691 case 16:
692 lfbmode = LFB_565;
693 break;
694#ifdef EN_24_32_BPP
695 case 24:
696 lfbmode = LFB_888;
697 break;
698 case 32:
699 lfbmode = LFB_8888;
700 break;
701#endif
702 default:
703 return -EINVAL;
704 }
705
706#if defined(__BIG_ENDIAN)
707 /* Enable byte-swizzle functionality in hardware.
708 * With this enabled, all our read- and write-accesses to
709 * the voodoo framebuffer can be done in native format, and
710 * the hardware will automatically convert it to little-endian.
711 * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */
712 lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
713 LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
714#endif
715
716 if (clipping) {
717 sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
718 /*
719 * Set "clipping" dimensions. If clipping is disabled and
720 * writes to offscreen areas of the framebuffer are performed,
721 * the "behaviour is undefined" (_very_ undefined) - Urs
722 */
723 /* btw, it requires enabling pixel pipeline in LFBMODE .
724 off screen read/writes will just wrap and read/print pixels
725 on screen. Ugly but not that dangerous */
726 f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
727 info->var.xres - 1, par->yDim - 1);
728
729 sst_write(CLIP_LEFT_RIGHT, info->var.xres);
730 sst_write(CLIP_LOWY_HIGHY, par->yDim);
731 sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
732 } else {
733 /* no clipping : direct access, no pipeline */
734 sst_write(LFBMODE, lfbmode);
735 }
736 return 0;
737}
738
739/**
740 * sstfb_setcolreg - Optional function. Sets a color register.
741 * @regno: hardware colormap register
742 * @red: frame buffer colormap structure
743 * @green: The green value which can be up to 16 bits wide
744 * @blue: The blue value which can be up to 16 bits wide.
745 * @transp: If supported the alpha value which can be up to 16 bits wide.
746 * @info: frame buffer info structure
747 */
748static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
749 u_int transp, struct fb_info *info)
750{
751 u32 col;
752
753 f_dddprintk("sstfb_setcolreg\n");
754 f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
755 regno, red, green, blue, transp);
756 if (regno >= 16)
757 return -EINVAL;
758
759 red >>= (16 - info->var.red.length);
760 green >>= (16 - info->var.green.length);
761 blue >>= (16 - info->var.blue.length);
762 transp >>= (16 - info->var.transp.length);
763 col = (red << info->var.red.offset)
764 | (green << info->var.green.offset)
765 | (blue << info->var.blue.offset)
766 | (transp << info->var.transp.offset);
767
768 ((u32 *)info->pseudo_palette)[regno] = col;
769
770 return 0;
771}
772
773static int sstfb_ioctl(struct inode *inode, struct file *file,
774 u_int cmd, u_long arg, struct fb_info *info )
775{
776 struct sstfb_par *par = (struct sstfb_par *) info->par;
777 struct pci_dev *sst_dev = par->dev;
778 u32 fbiinit0, tmp, val;
779 u_long p;
780
781 switch (cmd) {
782
783 /* dump current FBIINIT values to system log */
784 case _IO('F', 0xdb): /* 0x46db */
785 return sstfb_dump_regs(info);
786
787 /* fills lfb with #arg pixels */
788 case _IOW('F', 0xdc, u32): /* 0x46dc */
789 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
790 return -EFAULT;
791 if (val > info->fix.smem_len)
792 val = info->fix.smem_len;
793 printk("filling %#x \n", val);
794 for (p=0 ; p<val; p+=2)
795 writew(p >> 6, info->screen_base + p);
796 return 0;
797
798 /* change VGA pass_through mode */
799 case _IOW('F', 0xdd, u32): /* 0x46dd */
800 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
801 return -EFAULT;
802 pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
803 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
804 tmp | PCI_EN_INIT_WR );
805 fbiinit0 = sst_read (FBIINIT0);
806 if (val) {
807 sst_write(FBIINIT0, fbiinit0 & ~EN_VGA_PASSTHROUGH);
808 iprintk("Disabling VGA pass-through\n");
809 } else {
810 sst_write(FBIINIT0, fbiinit0 | EN_VGA_PASSTHROUGH);
811 iprintk("Enabling VGA pass-through\n");
812 }
813 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
814 return 0;
815
816 /* draw test image */
817 case _IO('F', 0xde): /* 0x46de */
818 f_dprintk("test color display at %d bpp\n",
819 info->var.bits_per_pixel);
820 sstfb_drawdebugimage(info);
821 return 0;
822 }
823 return -EINVAL;
824}
825
826
827/*
828 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
829 */
830#if 0
831static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
832{
833 struct sstfb_par *par = (struct sstfb_par *) info->par;
834 u32 stride = info->fix.line_length;
835
836 if (!IS_VOODOO2(par))
837 return;
838
839 sst_write(BLTSRCBASEADDR, 0);
840 sst_write(BLTDSTBASEADDR, 0);
841 sst_write(BLTROP, BLTROP_COPY);
842 sst_write(BLTXYSTRIDES, stride | (stride << 16));
843 sst_write(BLTSRCXY, area->sx | (area->sy << 16));
844 sst_write(BLTDSTXY, area->dx | (area->dy << 16));
845 sst_write(BLTSIZE, area->width | (area->height << 16));
846 sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
847 (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
848 sst_wait_idle();
849}
850#endif
851
852
853/*
854 * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
855 */
856static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
857{
858 struct sstfb_par *par = (struct sstfb_par *) info->par;
859 u32 stride = info->fix.line_length;
860
861 if (!IS_VOODOO2(par))
862 return;
863
864 sst_write(BLTCLIPX, info->var.xres);
865 sst_write(BLTCLIPY, info->var.yres);
866
867 sst_write(BLTDSTBASEADDR, 0);
868 sst_write(BLTCOLOR, rect->color);
869 sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
870 sst_write(BLTXYSTRIDES, stride | (stride << 16));
871 sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
872 sst_write(BLTSIZE, rect->width | (rect->height << 16));
873 sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
874 | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
875 sst_wait_idle();
876}
877
878
879
880/*
881 * get lfb size
882 */
883static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize)
884{
885 u8 __iomem *fbbase_virt = info->screen_base;
886
887 /* force memsize */
888 if ((mem >= 1 ) && (mem <= 4)) {
889 *memsize = (mem * 0x100000);
890 iprintk("supplied memsize: %#x\n", *memsize);
891 return 1;
892 }
893
894 writel(0xdeadbeef, fbbase_virt);
895 writel(0xdeadbeef, fbbase_virt+0x100000);
896 writel(0xdeadbeef, fbbase_virt+0x200000);
897 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
898 readl(fbbase_virt), readl(fbbase_virt + 0x100000),
899 readl(fbbase_virt + 0x200000));
900
901 writel(0xabcdef01, fbbase_virt);
902
903 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
904 readl(fbbase_virt), readl(fbbase_virt + 0x100000),
905 readl(fbbase_virt + 0x200000));
906
907 /* checks for 4mb lfb, then 2, then defaults to 1 */
908 if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
909 *memsize = 0x400000;
910 else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
911 *memsize = 0x200000;
912 else
913 *memsize = 0x100000;
914 f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
915 return 1;
916}
917
918
919/*
920 * DAC detection routines
921 */
922
923/* fbi should be idle, and fifo emty and mem disabled */
924/* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
925
926static int __devinit sst_detect_att(struct fb_info *info)
927{
928 struct sstfb_par *par = (struct sstfb_par *) info->par;
929 int i, mir, dir;
930
931 for (i=0; i<3; i++) {
932 sst_dac_write(DACREG_WMA, 0); /* backdoor */
933 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
934 sst_dac_read(DACREG_RMR);
935 sst_dac_read(DACREG_RMR);
936 sst_dac_read(DACREG_RMR);
937 /* the fifth time, CR0 is read */
938 sst_dac_read(DACREG_RMR);
939 /* the 6th, manufacturer id register */
940 mir = sst_dac_read(DACREG_RMR);
941 /*the 7th, device ID register */
942 dir = sst_dac_read(DACREG_RMR);
943 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
944 if ((mir == DACREG_MIR_ATT ) && (dir == DACREG_DIR_ATT)) {
945 return 1;
946 }
947 }
948 return 0;
949}
950
951static int __devinit sst_detect_ti(struct fb_info *info)
952{
953 struct sstfb_par *par = (struct sstfb_par *) info->par;
954 int i, mir, dir;
955
956 for (i = 0; i<3; i++) {
957 sst_dac_write(DACREG_WMA, 0); /* backdoor */
958 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
959 sst_dac_read(DACREG_RMR);
960 sst_dac_read(DACREG_RMR);
961 sst_dac_read(DACREG_RMR);
962 /* the fifth time, CR0 is read */
963 sst_dac_read(DACREG_RMR);
964 /* the 6th, manufacturer id register */
965 mir = sst_dac_read(DACREG_RMR);
966 /*the 7th, device ID register */
967 dir = sst_dac_read(DACREG_RMR);
968 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
969 if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
970 return 1;
971 }
972 }
973 return 0;
974}
975
976/*
977 * try to detect ICS5342 ramdac
978 * we get the 1st byte (M value) of preset f1,f7 and fB
979 * why those 3 ? mmmh... for now, i'll do it the glide way...
980 * and ask questions later. anyway, it seems that all the freq registers are
981 * realy at their default state (cf specs) so i ask again, why those 3 regs ?
982 * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
983 * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
984 * touched...
985 * is it realy safe ? how can i reset this ramdac ? geee...
986 */
987static int __devinit sst_detect_ics(struct fb_info *info)
988{
989 struct sstfb_par *par = (struct sstfb_par *) info->par;
990 int m_clk0_1, m_clk0_7, m_clk1_b;
991 int n_clk0_1, n_clk0_7, n_clk1_b;
992 int i;
993
994 for (i = 0; i<5; i++ ) {
995 sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
996 m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
997 n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
998 sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
999 m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
1000 n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
1001 sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
1002 m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
1003 n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
1004 f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
1005 m_clk0_1, m_clk0_7, m_clk1_b);
1006 f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
1007 n_clk0_1, n_clk0_7, n_clk1_b);
1008 if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
1009 && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
1010 && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
1011 return 1;
1012 }
1013 }
1014 return 0;
1015}
1016
1017
1018/*
1019 * gfx, video, pci fifo should be reset, dram refresh disabled
1020 * see detect_dac
1021 */
1022
1023static int sst_set_pll_att_ti(struct fb_info *info,
1024 const struct pll_timing *t, const int clock)
1025{
1026 struct sstfb_par *par = (struct sstfb_par *) info->par;
1027 u8 cr0, cc;
1028
1029 /* enable indexed mode */
1030 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1031 sst_dac_read(DACREG_RMR); /* 1 time: RMR */
1032 sst_dac_read(DACREG_RMR); /* 2 RMR */
1033 sst_dac_read(DACREG_RMR); /* 3 // */
1034 sst_dac_read(DACREG_RMR); /* 4 // */
1035 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
1036
1037 sst_dac_write(DACREG_WMA, 0);
1038 sst_dac_read(DACREG_RMR);
1039 sst_dac_read(DACREG_RMR);
1040 sst_dac_read(DACREG_RMR);
1041 sst_dac_read(DACREG_RMR);
1042 sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
1043 | DACREG_CR0_EN_INDEXED
1044 | DACREG_CR0_8BIT
1045 | DACREG_CR0_PWDOWN );
1046 /* so, now we are in indexed mode . dunno if its common, but
1047 i find this way of doing things a little bit weird :p */
1048
1049 udelay(300);
1050 cc = dac_i_read(DACREG_CC_I);
1051 switch (clock) {
1052 case VID_CLOCK:
1053 dac_i_write(DACREG_AC0_I, t->m);
1054 dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
1055 dac_i_write(DACREG_CC_I,
1056 (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
1057 break;
1058 case GFX_CLOCK:
1059 dac_i_write(DACREG_BD0_I, t->m);
1060 dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
1061 dac_i_write(DACREG_CC_I,
1062 (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
1063 break;
1064 default:
1065 dprintk("%s: wrong clock code '%d'\n",
1066 __FUNCTION__, clock);
1067 return 0;
1068 }
1069 udelay(300);
1070
1071 /* power up the dac & return to "normal" non-indexed mode */
1072 dac_i_write(DACREG_CR0_I,
1073 cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
1074 return 1;
1075}
1076
1077static int sst_set_pll_ics(struct fb_info *info,
1078 const struct pll_timing *t, const int clock)
1079{
1080 struct sstfb_par *par = (struct sstfb_par *) info->par;
1081 u8 pll_ctrl;
1082
1083 sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
1084 pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
1085 switch(clock) {
1086 case VID_CLOCK:
1087 sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
1088 sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1089 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1090 /* selects freq f0 for clock 0 */
1091 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1092 sst_dac_write(DACREG_ICS_PLLDATA,
1093 (pll_ctrl & 0xd8)
1094 | DACREG_ICS_CLK0
1095 | DACREG_ICS_CLK0_0);
1096 break;
1097 case GFX_CLOCK :
1098 sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
1099 sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1100 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1101 /* selects freq fA for clock 1 */
1102 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1103 sst_dac_write(DACREG_ICS_PLLDATA,
1104 (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
1105 break;
1106 default:
1107 dprintk("%s: wrong clock code '%d'\n",
1108 __FUNCTION__, clock);
1109 return 0;
1110 }
1111 udelay(300);
1112 return 1;
1113}
1114
1115static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
1116{
1117 struct sstfb_par *par = (struct sstfb_par *) info->par;
1118 u8 cr0;
1119
1120 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1121 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1122 sst_dac_read(DACREG_RMR);
1123 sst_dac_read(DACREG_RMR);
1124 sst_dac_read(DACREG_RMR);
1125 /* the fifth time, CR0 is read */
1126 cr0 = sst_dac_read(DACREG_RMR);
1127
1128 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1129 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1130 sst_dac_read(DACREG_RMR);
1131 sst_dac_read(DACREG_RMR);
1132 sst_dac_read(DACREG_RMR);
1133 /* cr0 */
1134 switch(bpp) {
1135 case 16:
1136 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
1137 break;
1138#ifdef EN_24_32_BPP
1139 case 24:
1140 case 32:
1141 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_24BPP);
1142 break;
1143#endif
1144 default:
1145 dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
1146 break;
1147 }
1148}
1149
1150static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
1151{
1152 struct sstfb_par *par = (struct sstfb_par *) info->par;
1153
1154 switch(bpp) {
1155 case 16:
1156 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
1157 break;
1158#ifdef EN_24_32_BPP
1159 case 24:
1160 case 32:
1161 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_24BPP);
1162 break;
1163#endif
1164 default:
1165 dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
1166 break;
1167 }
1168}
1169
1170/*
1171 * detect dac type
1172 * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
1173 * dram refresh disabled, FbiInit remaped.
1174 * TODO: mmh.. maybe i shoud put the "prerequisite" in the func ...
1175 */
1176
1177
1178static struct dac_switch dacs[] __devinitdata = {
1179 { .name = "TI TVP3409",
1180 .detect = sst_detect_ti,
1181 .set_pll = sst_set_pll_att_ti,
1182 .set_vidmod = sst_set_vidmod_att_ti },
1183
1184 { .name = "AT&T ATT20C409",
1185 .detect = sst_detect_att,
1186 .set_pll = sst_set_pll_att_ti,
1187 .set_vidmod = sst_set_vidmod_att_ti },
1188 { .name = "ICS ICS5342",
1189 .detect = sst_detect_ics,
1190 .set_pll = sst_set_pll_ics,
1191 .set_vidmod = sst_set_vidmod_ics },
1192};
1193
1194static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
1195{
1196 int i, ret = 0;
1197
1198 for (i=0; i<sizeof(dacs)/sizeof(dacs[0]); i++) {
1199 ret = dacs[i].detect(info);
1200 if (ret) break;
1201 }
1202 if (!ret)
1203 return 0;
1204 f_dprintk("%s found %s\n", __FUNCTION__, dacs[i].name);
1205 par->dac_sw = dacs[i];
1206 return 1;
1207}
1208
1209/*
1210 * Internal Routines
1211 */
1212static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par)
1213{
1214 u32 fbiinit0, fbiinit1, fbiinit4;
1215 struct pci_dev *dev = par->dev;
1216 struct pll_timing gfx_timings;
1217 struct sst_spec *spec;
1218 int Fout;
1219
1220 spec = &voodoo_spec[par->type];
1221 f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 "
1222 " fbiinit6\n");
1223 f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
1224 sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
1225 sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
1226 /* disable video clock */
1227 pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
1228
1229 /* enable writing to init registers, disable pci fifo */
1230 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1231 /* reset video */
1232 sst_set_bits(FBIINIT1, VIDEO_RESET);
1233 sst_wait_idle();
1234 /* reset gfx + pci fifo */
1235 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1236 sst_wait_idle();
1237
1238 /* unreset fifo */
1239 /*sst_unset_bits(FBIINIT0, FIFO_RESET);
1240 sst_wait_idle();*/
1241 /* unreset FBI */
1242 /*sst_unset_bits(FBIINIT0, FBI_RESET);
1243 sst_wait_idle();*/
1244
1245 /* disable dram refresh */
1246 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1247 sst_wait_idle();
1248 /* remap fbinit2/3 to dac */
1249 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1250 PCI_EN_INIT_WR | PCI_REMAP_DAC );
1251 /* detect dac type */
1252 if (!sst_detect_dactype(info, par)) {
1253 eprintk("Unknown dac type\n");
1254 //FIXME watch it: we are not in a safe state, bad bad bad.
1255 return 0;
1256 }
1257
1258 /* set graphic clock */
1259 par->gfx_clock = spec->default_gfx_clock;
1260 if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
1261 iprintk("Using supplied graphic freq : %dMHz\n", gfxclk);
1262 par->gfx_clock = gfxclk *1000;
1263 } else if (gfxclk) {
1264 wprintk ("%dMhz is way out of spec! Using default\n", gfxclk);
1265 }
1266
1267 sst_calc_pll(par->gfx_clock, &Fout, &gfx_timings);
1268 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1269
1270 /* disable fbiinit remap */
1271 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1272 PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
1273 /* defaults init registers */
1274 /* FbiInit0: unreset gfx, unreset fifo */
1275 fbiinit0 = FBIINIT0_DEFAULT;
1276 fbiinit1 = FBIINIT1_DEFAULT;
1277 fbiinit4 = FBIINIT4_DEFAULT;
1278 if (vgapass)
1279 fbiinit0 &= ~EN_VGA_PASSTHROUGH;
1280 else
1281 fbiinit0 |= EN_VGA_PASSTHROUGH;
1282 if (slowpci) {
1283 fbiinit1 |= SLOW_PCI_WRITES;
1284 fbiinit4 |= SLOW_PCI_READS;
1285 } else {
1286 fbiinit1 &= ~SLOW_PCI_WRITES;
1287 fbiinit4 &= ~SLOW_PCI_READS;
1288 }
1289 sst_write(FBIINIT0, fbiinit0);
1290 sst_wait_idle();
1291 sst_write(FBIINIT1, fbiinit1);
1292 sst_wait_idle();
1293 sst_write(FBIINIT2, FBIINIT2_DEFAULT);
1294 sst_wait_idle();
1295 sst_write(FBIINIT3, FBIINIT3_DEFAULT);
1296 sst_wait_idle();
1297 sst_write(FBIINIT4, fbiinit4);
1298 sst_wait_idle();
1299 if (IS_VOODOO2(par)) {
1300 sst_write(FBIINIT6, FBIINIT6_DEFAULT);
1301 sst_wait_idle();
1302 }
1303
1304 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
1305 pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
1306 return 1;
1307}
1308
1309static void __devexit sst_shutdown(struct fb_info *info)
1310{
1311 struct sstfb_par *par = (struct sstfb_par *) info->par;
1312 struct pci_dev *dev = par->dev;
1313 struct pll_timing gfx_timings;
1314 int Fout;
1315
1316 /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
1317 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1318 sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
1319 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1320 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1321 sst_wait_idle();
1322 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1323 PCI_EN_INIT_WR | PCI_REMAP_DAC);
1324 /* set 20Mhz gfx clock */
1325 sst_calc_pll(20000, &Fout, &gfx_timings);
1326 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1327 /* TODO maybe shutdown the dac, vrefresh and so on... */
1328 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1329 PCI_EN_INIT_WR);
1330 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | EN_VGA_PASSTHROUGH);
1331 pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
1332 /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
1333 * from start ? */
1334 pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
1335
1336}
1337
1338/*
1339 * Interface to the world
1340 */
1341#ifndef MODULE
1342static int __init sstfb_setup(char *options)
1343{
1344 char *this_opt;
1345
1346 if (!options || !*options)
1347 return 0;
1348
1349 while ((this_opt = strsep(&options, ",")) != NULL) {
1350 if (!*this_opt) continue;
1351
1352 f_ddprintk("option %s\n", this_opt);
1353
1354 if (!strcmp(this_opt, "vganopass"))
1355 vgapass = 0;
1356 else if (!strcmp(this_opt, "vgapass"))
1357 vgapass = 1;
1358 else if (!strcmp(this_opt, "clipping"))
1359 clipping = 1;
1360 else if (!strcmp(this_opt, "noclipping"))
1361 clipping = 0;
1362 else if (!strcmp(this_opt, "fastpci"))
1363 slowpci = 0;
1364 else if (!strcmp(this_opt, "slowpci"))
1365 slowpci = 1;
1366 else if (!strncmp(this_opt, "mem:",4))
1367 mem = simple_strtoul (this_opt+4, NULL, 0);
1368 else if (!strncmp(this_opt, "gfxclk:",7))
1369 gfxclk = simple_strtoul (this_opt+7, NULL, 0);
1370 else
1371 mode_option = this_opt;
1372 }
1373 return 0;
1374}
1375#endif
1376
1377static struct fb_ops sstfb_ops = {
1378 .owner = THIS_MODULE,
1379 .fb_check_var = sstfb_check_var,
1380 .fb_set_par = sstfb_set_par,
1381 .fb_setcolreg = sstfb_setcolreg,
1382 .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */
1383 .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */
1384 .fb_imageblit = cfb_imageblit,
1385 .fb_cursor = soft_cursor,
1386 .fb_ioctl = sstfb_ioctl,
1387};
1388
1389static int __devinit sstfb_probe(struct pci_dev *pdev,
1390 const struct pci_device_id *id)
1391{
1392 struct fb_info *info;
1393 struct fb_fix_screeninfo *fix;
1394 struct sstfb_par *par;
1395 struct sst_spec *spec;
1396 int err;
1397
1398 struct all_info {
1399 struct fb_info info;
1400 struct sstfb_par par;
1401 u32 pseudo_palette[16];
1402 } *all;
1403
1404 /* Enable device in PCI config. */
1405 if ((err=pci_enable_device(pdev))) {
1406 eprintk("cannot enable device\n");
1407 return err;
1408 }
1409
1410 /* Allocate the fb and par structures. */
1411 all = kmalloc(sizeof(*all), GFP_KERNEL);
1412 if (!all)
1413 return -ENOMEM;
1414 memset(all, 0, sizeof(*all));
1415 pci_set_drvdata(pdev, all);
1416
1417 info = &all->info;
1418 par = info->par = &all->par;
1419 fix = &info->fix;
1420
1421 par->type = id->driver_data;
1422 spec = &voodoo_spec[par->type];
1423 f_ddprintk("found device : %s\n", spec->name);
1424
1425 par->dev = pdev;
1426 pci_read_config_byte(pdev, PCI_REVISION_ID, &par->revision);
1427
1428 fix->mmio_start = pci_resource_start(pdev,0);
1429 fix->mmio_len = 0x400000;
1430 fix->smem_start = fix->mmio_start + 0x400000;
1431
1432 if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
1433 eprintk("cannot reserve mmio memory\n");
1434 goto fail_mmio_mem;
1435 }
1436
1437 if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
1438 eprintk("cannot reserve fb memory\n");
1439 goto fail_fb_mem;
1440 }
1441
1442 par->mmio_vbase = ioremap_nocache(fix->mmio_start,
1443 fix->mmio_len);
1444 if (!par->mmio_vbase) {
1445 eprintk("cannot remap register area %#lx\n",
1446 fix->mmio_start);
1447 goto fail_mmio_remap;
1448 }
1449 info->screen_base = ioremap_nocache(fix->smem_start, 0x400000);
1450 if (!info->screen_base) {
1451 eprintk("cannot remap framebuffer %#lx\n",
1452 fix->smem_start);
1453 goto fail_fb_remap;
1454 }
1455
1456 if (!sst_init(info, par)) {
1457 eprintk("Init failed\n");
1458 goto fail;
1459 }
1460 sst_get_memsize(info, &fix->smem_len);
1461 strlcpy(fix->id, spec->name, sizeof(fix->id));
1462
1463 iprintk("%s (revision %d) with %s dac\n",
1464 fix->id, par->revision, par->dac_sw.name);
1465 iprintk("framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
1466 fix->smem_start, info->screen_base,
1467 fix->smem_len >> 20);
1468
1469 f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase);
1470 f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
1471 f_ddprintk("fbbase_virt: %p\n", info->screen_base);
1472
1473 info->flags = FBINFO_DEFAULT;
1474 info->fbops = &sstfb_ops;
1475 info->pseudo_palette = &all->pseudo_palette;
1476
1477 fix->type = FB_TYPE_PACKED_PIXELS;
1478 fix->visual = FB_VISUAL_TRUECOLOR;
1479 fix->accel = FB_ACCEL_NONE; /* FIXME */
1480 /*
1481 * According to the specs, the linelength must be of 1024 *pixels*
1482 * and the 24bpp mode is in fact a 32 bpp mode.
1483 */
1484 fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
1485
1486 if ( mode_option &&
1487 fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16)) {
1488 eprintk("can't set supplied video mode. Using default\n");
1489 info->var = sstfb_default;
1490 } else
1491 info->var = sstfb_default;
1492
1493 if (sstfb_check_var(&info->var, info)) {
1494 eprintk("invalid default video mode.\n");
1495 goto fail;
1496 }
1497
1498 if (sstfb_set_par(info)) {
1499 eprintk("can't set default video mode.\n");
1500 goto fail;
1501 }
1502
1503 fb_alloc_cmap(&info->cmap, 256, 0);
1504
1505 /* register fb */
1506 info->device = &pdev->dev;
1507 if (register_framebuffer(info) < 0) {
1508 eprintk("can't register framebuffer.\n");
1509 goto fail;
1510 }
1511
1512 if (1) /* set to 0 to see an initial bitmap instead */
1513 sstfb_clear_screen(info);
1514 else
1515 sstfb_drawdebugimage(info);
1516
1517 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n",
1518 info->node, fix->id, info->screen_base);
1519
1520 return 0;
1521
1522fail:
1523 iounmap(info->screen_base);
1524fail_fb_remap:
1525 iounmap(par->mmio_vbase);
1526fail_mmio_remap:
1527 release_mem_region(fix->smem_start, 0x400000);
1528fail_fb_mem:
1529 release_mem_region(fix->mmio_start, info->fix.mmio_len);
1530fail_mmio_mem:
1531 kfree(info);
1532 return -ENXIO; /* no voodoo detected */
1533}
1534
1535static void __devexit sstfb_remove(struct pci_dev *pdev)
1536{
1537 struct sstfb_par *par;
1538 struct fb_info *info;
1539
1540 info = pci_get_drvdata(pdev);
1541 par = (struct sstfb_par *) info->par;
1542
1543 sst_shutdown(info);
1544 unregister_framebuffer(info);
1545 iounmap(info->screen_base);
1546 iounmap(par->mmio_vbase);
1547 release_mem_region(info->fix.smem_start, 0x400000);
1548 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1549 kfree(info);
1550}
1551
1552
1553static struct pci_device_id sstfb_id_tbl[] = {
1554 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO,
1555 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO1 },
1556 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2,
1557 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO2 },
1558 { 0 },
1559};
1560
1561static struct pci_driver sstfb_driver = {
1562 .name = "sstfb",
1563 .id_table = sstfb_id_tbl,
1564 .probe = sstfb_probe,
1565 .remove = __devexit_p(sstfb_remove),
1566};
1567
1568
1569static int __devinit sstfb_init(void)
1570{
1571#ifndef MODULE
1572 char *option = NULL;
1573
1574 if (fb_get_options("sstfb", &option))
1575 return -ENODEV;
1576 sstfb_setup(option);
1577#endif
1578 return pci_register_driver(&sstfb_driver);
1579}
1580
1581#ifdef MODULE
1582static void __devexit sstfb_exit(void)
1583{
1584 pci_unregister_driver(&sstfb_driver);
1585}
1586#endif
1587
1588
1589/*
1590 * testing and debugging functions
1591 */
1592
1593static int sstfb_dump_regs(struct fb_info *info)
1594{
1595#ifdef SST_DEBUG
1596 static struct { u32 reg ; const char *reg_name;} pci_regs[] = {
1597 { PCI_INIT_ENABLE, "initenable"},
1598 { PCI_VCLK_ENABLE, "enable vclk"},
1599 { PCI_VCLK_DISABLE, "disable vclk"},
1600 };
1601
1602 static struct { u32 reg ; const char *reg_name;} sst_regs[] = {
1603 {FBIINIT0,"fbiinit0"},
1604 {FBIINIT1,"fbiinit1"},
1605 {FBIINIT2,"fbiinit2"},
1606 {FBIINIT3,"fbiinit3"},
1607 {FBIINIT4,"fbiinit4"},
1608 {FBIINIT5,"fbiinit5"},
1609 {FBIINIT6,"fbiinit6"},
1610 {FBIINIT7,"fbiinit7"},
1611 {LFBMODE,"lfbmode"},
1612 {FBZMODE,"fbzmode"},
1613 };
1614
1615 const int pci_s = sizeof(pci_regs)/sizeof(pci_regs[0]);
1616 const int sst_s = sizeof(sst_regs)/sizeof(sst_regs[0]);
1617 struct sstfb_par *par = (struct sstfb_par *) info->par;
1618 struct pci_dev *dev = par->dev;
1619 u32 pci_res[pci_s];
1620 u32 sst_res[sst_s];
1621 int i;
1622
1623 for (i=0; i<pci_s; i++) {
1624 pci_read_config_dword(dev, pci_regs[i].reg, &pci_res[i]);
1625 }
1626 for (i=0; i<sst_s; i++) {
1627 sst_res[i] = sst_read(sst_regs[i].reg);
1628 }
1629
1630 dprintk("hardware register dump:\n");
1631 for (i=0; i<pci_s; i++) {
1632 dprintk("%s %0#10x\n", pci_regs[i].reg_name, pci_res[i]);
1633 }
1634 for (i=0; i<sst_s; i++) {
1635 dprintk("%s %0#10x\n", sst_regs[i].reg_name, sst_res[i]);
1636 }
1637 return 0;
1638#else
1639 return -EINVAL;
1640#endif
1641}
1642
1643static void sstfb_fillrect_softw( struct fb_info *info, const struct fb_fillrect *rect)
1644{
1645 u8 __iomem *fbbase_virt = info->screen_base;
1646 int x, y, w = info->var.bits_per_pixel == 16 ? 2 : 4;
1647 u32 color = rect->color, height = rect->height;
1648 u8 __iomem *p;
1649
1650 if (w==2) color |= color<<16;
1651 for (y=rect->dy; height; y++, height--) {
1652 p = fbbase_virt + y*info->fix.line_length + rect->dx*w;
1653 x = rect->width;
1654 if (w==2) x>>=1;
1655 while (x) {
1656 writel(color, p);
1657 p += 4;
1658 x--;
1659 }
1660 }
1661}
1662
1663static void sstfb_drawrect_XY( struct fb_info *info, int x, int y,
1664 int w, int h, int color, int hwfunc)
1665{
1666 struct fb_fillrect rect;
1667 rect.dx = x;
1668 rect.dy = y;
1669 rect.height = h;
1670 rect.width = w;
1671 rect.color = color;
1672 rect.rop = ROP_COPY;
1673 if (hwfunc)
1674 sstfb_fillrect(info, &rect);
1675 else
1676 sstfb_fillrect_softw(info, &rect);
1677}
1678
1679/* print some squares on the fb */
1680static void sstfb_drawdebugimage(struct fb_info *info)
1681{
1682 static int idx;
1683
1684 /* clear screen */
1685 sstfb_clear_screen(info);
1686
1687 idx = (idx+1) & 1;
1688
1689 /* white rect */
1690 sstfb_drawrect_XY(info, 0, 0, 50, 50, 0xffff, idx);
1691
1692 /* blue rect */
1693 sstfb_drawrect_XY(info, 50, 50, 50, 50, 0x001f, idx);
1694
1695 /* green rect */
1696 sstfb_drawrect_XY(info, 100, 100, 80, 80, 0x07e0, idx);
1697
1698 /* red rect */
1699 sstfb_drawrect_XY(info, 250, 250, 120, 100, 0xf800, idx);
1700}
1701
1702module_init(sstfb_init);
1703
1704#ifdef MODULE
1705module_exit(sstfb_exit);
1706#endif
1707
1708MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>");
1709MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
1710MODULE_LICENSE("GPL");
1711
1712module_param(mem, int, 0);
1713MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
1714module_param(vgapass, bool, 0);
1715MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
1716module_param(clipping, bool, 0);
1717MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
1718module_param(gfxclk, int, 0);
1719MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
1720module_param(slowpci, bool, 0);
1721MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");
1722
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 06:27:20 -0500