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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-02-13 08:31:38 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-04-17 01:10:19 -0400
commitf7018c21350204c4cf628462f229d44d03545254 (patch)
tree408787177164cf51cc06f7aabdb04fcff8d2b6aa /drivers/video/riva
parentc26ef3eb3c11274bad1b64498d0a134f85755250 (diff)
video: move fbdev to drivers/video/fbdev
The drivers/video directory is a mess. It contains generic video related files, directories for backlight, console, linux logo, lots of fbdev device drivers, fbdev framework files. Make some order into the chaos by creating drivers/video/fbdev directory, and move all fbdev related files there. No functionality is changed, although I guess it is possible that some subtle Makefile build order related issue could be created by this patch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Clark <robdclark@gmail.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/video/riva')
-rw-r--r--drivers/video/riva/Makefile11
-rw-r--r--drivers/video/riva/fbdev.c2230
-rw-r--r--drivers/video/riva/nv_driver.c422
-rw-r--r--drivers/video/riva/nv_type.h58
-rw-r--r--drivers/video/riva/nvreg.h188
-rw-r--r--drivers/video/riva/riva_hw.c2268
-rw-r--r--drivers/video/riva/riva_hw.h563
-rw-r--r--drivers/video/riva/riva_tbl.h1008
-rw-r--r--drivers/video/riva/rivafb-i2c.c166
-rw-r--r--drivers/video/riva/rivafb.h77
10 files changed, 0 insertions, 6991 deletions
diff --git a/drivers/video/riva/Makefile b/drivers/video/riva/Makefile
deleted file mode 100644
index 8898c9915b02..000000000000
--- a/drivers/video/riva/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the Riva framebuffer driver
3#
4
5obj-$(CONFIG_FB_RIVA) += rivafb.o
6
7rivafb-objs := fbdev.o riva_hw.o nv_driver.o
8
9ifdef CONFIG_FB_RIVA_I2C
10 rivafb-objs += rivafb-i2c.o
11endif
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c
deleted file mode 100644
index 8a8d7f060784..000000000000
--- a/drivers/video/riva/fbdev.c
+++ /dev/null
@@ -1,2230 +0,0 @@
1/*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/string.h>
36#include <linux/mm.h>
37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/fb.h>
40#include <linux/init.h>
41#include <linux/pci.h>
42#include <linux/backlight.h>
43#include <linux/bitrev.h>
44#ifdef CONFIG_MTRR
45#include <asm/mtrr.h>
46#endif
47#ifdef CONFIG_PPC_OF
48#include <asm/prom.h>
49#include <asm/pci-bridge.h>
50#endif
51#ifdef CONFIG_PMAC_BACKLIGHT
52#include <asm/machdep.h>
53#include <asm/backlight.h>
54#endif
55
56#include "rivafb.h"
57#include "nvreg.h"
58
59/* version number of this driver */
60#define RIVAFB_VERSION "0.9.5b"
61
62/* ------------------------------------------------------------------------- *
63 *
64 * various helpful macros and constants
65 *
66 * ------------------------------------------------------------------------- */
67#ifdef CONFIG_FB_RIVA_DEBUG
68#define NVTRACE printk
69#else
70#define NVTRACE if(0) printk
71#endif
72
73#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
74#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
75
76#ifdef CONFIG_FB_RIVA_DEBUG
77#define assert(expr) \
78 if(!(expr)) { \
79 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
80 #expr,__FILE__,__func__,__LINE__); \
81 BUG(); \
82 }
83#else
84#define assert(expr)
85#endif
86
87#define PFX "rivafb: "
88
89/* macro that allows you to set overflow bits */
90#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
91#define SetBit(n) (1<<(n))
92#define Set8Bits(value) ((value)&0xff)
93
94/* HW cursor parameters */
95#define MAX_CURS 32
96
97/* ------------------------------------------------------------------------- *
98 *
99 * prototypes
100 *
101 * ------------------------------------------------------------------------- */
102
103static int rivafb_blank(int blank, struct fb_info *info);
104
105/* ------------------------------------------------------------------------- *
106 *
107 * card identification
108 *
109 * ------------------------------------------------------------------------- */
110
111static struct pci_device_id rivafb_pci_tbl[] = {
112 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152 // NF2/IGP version, GeForce 4 MX, NV18
153 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
197 { 0, } /* terminate list */
198};
199MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
200
201/* ------------------------------------------------------------------------- *
202 *
203 * global variables
204 *
205 * ------------------------------------------------------------------------- */
206
207/* command line data, set in rivafb_setup() */
208static int flatpanel = -1; /* Autodetect later */
209static int forceCRTC = -1;
210static bool noaccel = 0;
211#ifdef CONFIG_MTRR
212static bool nomtrr = 0;
213#endif
214#ifdef CONFIG_PMAC_BACKLIGHT
215static int backlight = 1;
216#else
217static int backlight = 0;
218#endif
219
220static char *mode_option = NULL;
221static bool strictmode = 0;
222
223static struct fb_fix_screeninfo rivafb_fix = {
224 .type = FB_TYPE_PACKED_PIXELS,
225 .xpanstep = 1,
226 .ypanstep = 1,
227};
228
229static struct fb_var_screeninfo rivafb_default_var = {
230 .xres = 640,
231 .yres = 480,
232 .xres_virtual = 640,
233 .yres_virtual = 480,
234 .bits_per_pixel = 8,
235 .red = {0, 8, 0},
236 .green = {0, 8, 0},
237 .blue = {0, 8, 0},
238 .transp = {0, 0, 0},
239 .activate = FB_ACTIVATE_NOW,
240 .height = -1,
241 .width = -1,
242 .pixclock = 39721,
243 .left_margin = 40,
244 .right_margin = 24,
245 .upper_margin = 32,
246 .lower_margin = 11,
247 .hsync_len = 96,
248 .vsync_len = 2,
249 .vmode = FB_VMODE_NONINTERLACED
250};
251
252/* from GGI */
253static const struct riva_regs reg_template = {
254 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
255 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
256 0x41, 0x01, 0x0F, 0x00, 0x00},
257 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
258 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
260 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
262 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
265 0x00, /* 0x40 */
266 },
267 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
268 0xFF},
269 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
270 0xEB /* MISC */
271};
272
273/*
274 * Backlight control
275 */
276#ifdef CONFIG_FB_RIVA_BACKLIGHT
277/* We do not have any information about which values are allowed, thus
278 * we used safe values.
279 */
280#define MIN_LEVEL 0x158
281#define MAX_LEVEL 0x534
282#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
283
284static int riva_bl_get_level_brightness(struct riva_par *par,
285 int level)
286{
287 struct fb_info *info = pci_get_drvdata(par->pdev);
288 int nlevel;
289
290 /* Get and convert the value */
291 /* No locking on bl_curve since accessing a single value */
292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
293
294 if (nlevel < 0)
295 nlevel = 0;
296 else if (nlevel < MIN_LEVEL)
297 nlevel = MIN_LEVEL;
298 else if (nlevel > MAX_LEVEL)
299 nlevel = MAX_LEVEL;
300
301 return nlevel;
302}
303
304static int riva_bl_update_status(struct backlight_device *bd)
305{
306 struct riva_par *par = bl_get_data(bd);
307 U032 tmp_pcrt, tmp_pmc;
308 int level;
309
310 if (bd->props.power != FB_BLANK_UNBLANK ||
311 bd->props.fb_blank != FB_BLANK_UNBLANK)
312 level = 0;
313 else
314 level = bd->props.brightness;
315
316 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
317 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
318 if(level > 0) {
319 tmp_pcrt |= 0x1;
320 tmp_pmc |= (1 << 31); /* backlight bit */
321 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
322 }
323 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
324 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
325
326 return 0;
327}
328
329static int riva_bl_get_brightness(struct backlight_device *bd)
330{
331 return bd->props.brightness;
332}
333
334static const struct backlight_ops riva_bl_ops = {
335 .get_brightness = riva_bl_get_brightness,
336 .update_status = riva_bl_update_status,
337};
338
339static void riva_bl_init(struct riva_par *par)
340{
341 struct backlight_properties props;
342 struct fb_info *info = pci_get_drvdata(par->pdev);
343 struct backlight_device *bd;
344 char name[12];
345
346 if (!par->FlatPanel)
347 return;
348
349#ifdef CONFIG_PMAC_BACKLIGHT
350 if (!machine_is(powermac) ||
351 !pmac_has_backlight_type("mnca"))
352 return;
353#endif
354
355 snprintf(name, sizeof(name), "rivabl%d", info->node);
356
357 memset(&props, 0, sizeof(struct backlight_properties));
358 props.type = BACKLIGHT_RAW;
359 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
360 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops,
361 &props);
362 if (IS_ERR(bd)) {
363 info->bl_dev = NULL;
364 printk(KERN_WARNING "riva: Backlight registration failed\n");
365 goto error;
366 }
367
368 info->bl_dev = bd;
369 fb_bl_default_curve(info, 0,
370 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
371 FB_BACKLIGHT_MAX);
372
373 bd->props.brightness = bd->props.max_brightness;
374 bd->props.power = FB_BLANK_UNBLANK;
375 backlight_update_status(bd);
376
377 printk("riva: Backlight initialized (%s)\n", name);
378
379 return;
380
381error:
382 return;
383}
384
385static void riva_bl_exit(struct fb_info *info)
386{
387 struct backlight_device *bd = info->bl_dev;
388
389 backlight_device_unregister(bd);
390 printk("riva: Backlight unloaded\n");
391}
392#else
393static inline void riva_bl_init(struct riva_par *par) {}
394static inline void riva_bl_exit(struct fb_info *info) {}
395#endif /* CONFIG_FB_RIVA_BACKLIGHT */
396
397/* ------------------------------------------------------------------------- *
398 *
399 * MMIO access macros
400 *
401 * ------------------------------------------------------------------------- */
402
403static inline void CRTCout(struct riva_par *par, unsigned char index,
404 unsigned char val)
405{
406 VGA_WR08(par->riva.PCIO, 0x3d4, index);
407 VGA_WR08(par->riva.PCIO, 0x3d5, val);
408}
409
410static inline unsigned char CRTCin(struct riva_par *par,
411 unsigned char index)
412{
413 VGA_WR08(par->riva.PCIO, 0x3d4, index);
414 return (VGA_RD08(par->riva.PCIO, 0x3d5));
415}
416
417static inline void GRAout(struct riva_par *par, unsigned char index,
418 unsigned char val)
419{
420 VGA_WR08(par->riva.PVIO, 0x3ce, index);
421 VGA_WR08(par->riva.PVIO, 0x3cf, val);
422}
423
424static inline unsigned char GRAin(struct riva_par *par,
425 unsigned char index)
426{
427 VGA_WR08(par->riva.PVIO, 0x3ce, index);
428 return (VGA_RD08(par->riva.PVIO, 0x3cf));
429}
430
431static inline void SEQout(struct riva_par *par, unsigned char index,
432 unsigned char val)
433{
434 VGA_WR08(par->riva.PVIO, 0x3c4, index);
435 VGA_WR08(par->riva.PVIO, 0x3c5, val);
436}
437
438static inline unsigned char SEQin(struct riva_par *par,
439 unsigned char index)
440{
441 VGA_WR08(par->riva.PVIO, 0x3c4, index);
442 return (VGA_RD08(par->riva.PVIO, 0x3c5));
443}
444
445static inline void ATTRout(struct riva_par *par, unsigned char index,
446 unsigned char val)
447{
448 VGA_WR08(par->riva.PCIO, 0x3c0, index);
449 VGA_WR08(par->riva.PCIO, 0x3c0, val);
450}
451
452static inline unsigned char ATTRin(struct riva_par *par,
453 unsigned char index)
454{
455 VGA_WR08(par->riva.PCIO, 0x3c0, index);
456 return (VGA_RD08(par->riva.PCIO, 0x3c1));
457}
458
459static inline void MISCout(struct riva_par *par, unsigned char val)
460{
461 VGA_WR08(par->riva.PVIO, 0x3c2, val);
462}
463
464static inline unsigned char MISCin(struct riva_par *par)
465{
466 return (VGA_RD08(par->riva.PVIO, 0x3cc));
467}
468
469static inline void reverse_order(u32 *l)
470{
471 u8 *a = (u8 *)l;
472 a[0] = bitrev8(a[0]);
473 a[1] = bitrev8(a[1]);
474 a[2] = bitrev8(a[2]);
475 a[3] = bitrev8(a[3]);
476}
477
478/* ------------------------------------------------------------------------- *
479 *
480 * cursor stuff
481 *
482 * ------------------------------------------------------------------------- */
483
484/**
485 * rivafb_load_cursor_image - load cursor image to hardware
486 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
487 * @par: pointer to private data
488 * @w: width of cursor image in pixels
489 * @h: height of cursor image in scanlines
490 * @bg: background color (ARGB1555) - alpha bit determines opacity
491 * @fg: foreground color (ARGB1555)
492 *
493 * DESCRIPTiON:
494 * Loads cursor image based on a monochrome source and mask bitmap. The
495 * image bits determines the color of the pixel, 0 for background, 1 for
496 * foreground. Only the affected region (as determined by @w and @h
497 * parameters) will be updated.
498 *
499 * CALLED FROM:
500 * rivafb_cursor()
501 */
502static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
503 u16 bg, u16 fg, u32 w, u32 h)
504{
505 int i, j, k = 0;
506 u32 b, tmp;
507 u32 *data = (u32 *)data8;
508 bg = le16_to_cpu(bg);
509 fg = le16_to_cpu(fg);
510
511 w = (w + 1) & ~1;
512
513 for (i = 0; i < h; i++) {
514 b = *data++;
515 reverse_order(&b);
516
517 for (j = 0; j < w/2; j++) {
518 tmp = 0;
519#if defined (__BIG_ENDIAN)
520 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
521 b <<= 1;
522 tmp |= (b & (1 << 31)) ? fg : bg;
523 b <<= 1;
524#else
525 tmp = (b & 1) ? fg : bg;
526 b >>= 1;
527 tmp |= (b & 1) ? fg << 16 : bg << 16;
528 b >>= 1;
529#endif
530 writel(tmp, &par->riva.CURSOR[k++]);
531 }
532 k += (MAX_CURS - w)/2;
533 }
534}
535
536/* ------------------------------------------------------------------------- *
537 *
538 * general utility functions
539 *
540 * ------------------------------------------------------------------------- */
541
542/**
543 * riva_wclut - set CLUT entry
544 * @chip: pointer to RIVA_HW_INST object
545 * @regnum: register number
546 * @red: red component
547 * @green: green component
548 * @blue: blue component
549 *
550 * DESCRIPTION:
551 * Sets color register @regnum.
552 *
553 * CALLED FROM:
554 * rivafb_setcolreg()
555 */
556static void riva_wclut(RIVA_HW_INST *chip,
557 unsigned char regnum, unsigned char red,
558 unsigned char green, unsigned char blue)
559{
560 VGA_WR08(chip->PDIO, 0x3c8, regnum);
561 VGA_WR08(chip->PDIO, 0x3c9, red);
562 VGA_WR08(chip->PDIO, 0x3c9, green);
563 VGA_WR08(chip->PDIO, 0x3c9, blue);
564}
565
566/**
567 * riva_rclut - read fromCLUT register
568 * @chip: pointer to RIVA_HW_INST object
569 * @regnum: register number
570 * @red: red component
571 * @green: green component
572 * @blue: blue component
573 *
574 * DESCRIPTION:
575 * Reads red, green, and blue from color register @regnum.
576 *
577 * CALLED FROM:
578 * rivafb_setcolreg()
579 */
580static void riva_rclut(RIVA_HW_INST *chip,
581 unsigned char regnum, unsigned char *red,
582 unsigned char *green, unsigned char *blue)
583{
584
585 VGA_WR08(chip->PDIO, 0x3c7, regnum);
586 *red = VGA_RD08(chip->PDIO, 0x3c9);
587 *green = VGA_RD08(chip->PDIO, 0x3c9);
588 *blue = VGA_RD08(chip->PDIO, 0x3c9);
589}
590
591/**
592 * riva_save_state - saves current chip state
593 * @par: pointer to riva_par object containing info for current riva board
594 * @regs: pointer to riva_regs object
595 *
596 * DESCRIPTION:
597 * Saves current chip state to @regs.
598 *
599 * CALLED FROM:
600 * rivafb_probe()
601 */
602/* from GGI */
603static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
604{
605 int i;
606
607 NVTRACE_ENTER();
608 par->riva.LockUnlock(&par->riva, 0);
609
610 par->riva.UnloadStateExt(&par->riva, &regs->ext);
611
612 regs->misc_output = MISCin(par);
613
614 for (i = 0; i < NUM_CRT_REGS; i++)
615 regs->crtc[i] = CRTCin(par, i);
616
617 for (i = 0; i < NUM_ATC_REGS; i++)
618 regs->attr[i] = ATTRin(par, i);
619
620 for (i = 0; i < NUM_GRC_REGS; i++)
621 regs->gra[i] = GRAin(par, i);
622
623 for (i = 0; i < NUM_SEQ_REGS; i++)
624 regs->seq[i] = SEQin(par, i);
625 NVTRACE_LEAVE();
626}
627
628/**
629 * riva_load_state - loads current chip state
630 * @par: pointer to riva_par object containing info for current riva board
631 * @regs: pointer to riva_regs object
632 *
633 * DESCRIPTION:
634 * Loads chip state from @regs.
635 *
636 * CALLED FROM:
637 * riva_load_video_mode()
638 * rivafb_probe()
639 * rivafb_remove()
640 */
641/* from GGI */
642static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
643{
644 RIVA_HW_STATE *state = &regs->ext;
645 int i;
646
647 NVTRACE_ENTER();
648 CRTCout(par, 0x11, 0x00);
649
650 par->riva.LockUnlock(&par->riva, 0);
651
652 par->riva.LoadStateExt(&par->riva, state);
653
654 MISCout(par, regs->misc_output);
655
656 for (i = 0; i < NUM_CRT_REGS; i++) {
657 switch (i) {
658 case 0x19:
659 case 0x20 ... 0x40:
660 break;
661 default:
662 CRTCout(par, i, regs->crtc[i]);
663 }
664 }
665
666 for (i = 0; i < NUM_ATC_REGS; i++)
667 ATTRout(par, i, regs->attr[i]);
668
669 for (i = 0; i < NUM_GRC_REGS; i++)
670 GRAout(par, i, regs->gra[i]);
671
672 for (i = 0; i < NUM_SEQ_REGS; i++)
673 SEQout(par, i, regs->seq[i]);
674 NVTRACE_LEAVE();
675}
676
677/**
678 * riva_load_video_mode - calculate timings
679 * @info: pointer to fb_info object containing info for current riva board
680 *
681 * DESCRIPTION:
682 * Calculate some timings and then send em off to riva_load_state().
683 *
684 * CALLED FROM:
685 * rivafb_set_par()
686 */
687static int riva_load_video_mode(struct fb_info *info)
688{
689 int bpp, width, hDisplaySize, hDisplay, hStart,
690 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
691 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
692 int rc;
693 struct riva_par *par = info->par;
694 struct riva_regs newmode;
695
696 NVTRACE_ENTER();
697 /* time to calculate */
698 rivafb_blank(FB_BLANK_NORMAL, info);
699
700 bpp = info->var.bits_per_pixel;
701 if (bpp == 16 && info->var.green.length == 5)
702 bpp = 15;
703 width = info->var.xres_virtual;
704 hDisplaySize = info->var.xres;
705 hDisplay = (hDisplaySize / 8) - 1;
706 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
707 hEnd = (hDisplaySize + info->var.right_margin +
708 info->var.hsync_len) / 8 - 1;
709 hTotal = (hDisplaySize + info->var.right_margin +
710 info->var.hsync_len + info->var.left_margin) / 8 - 5;
711 hBlankStart = hDisplay;
712 hBlankEnd = hTotal + 4;
713
714 height = info->var.yres_virtual;
715 vDisplay = info->var.yres - 1;
716 vStart = info->var.yres + info->var.lower_margin - 1;
717 vEnd = info->var.yres + info->var.lower_margin +
718 info->var.vsync_len - 1;
719 vTotal = info->var.yres + info->var.lower_margin +
720 info->var.vsync_len + info->var.upper_margin + 2;
721 vBlankStart = vDisplay;
722 vBlankEnd = vTotal + 1;
723 dotClock = 1000000000 / info->var.pixclock;
724
725 memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
726
727 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
728 vTotal |= 1;
729
730 if (par->FlatPanel) {
731 vStart = vTotal - 3;
732 vEnd = vTotal - 2;
733 vBlankStart = vStart;
734 hStart = hTotal - 3;
735 hEnd = hTotal - 2;
736 hBlankEnd = hTotal + 4;
737 }
738
739 newmode.crtc[0x0] = Set8Bits (hTotal);
740 newmode.crtc[0x1] = Set8Bits (hDisplay);
741 newmode.crtc[0x2] = Set8Bits (hBlankStart);
742 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
743 newmode.crtc[0x4] = Set8Bits (hStart);
744 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
745 | SetBitField (hEnd, 4: 0, 4:0);
746 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
747 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
748 | SetBitField (vDisplay, 8: 8, 1:1)
749 | SetBitField (vStart, 8: 8, 2:2)
750 | SetBitField (vBlankStart, 8: 8, 3:3)
751 | SetBit (4)
752 | SetBitField (vTotal, 9: 9, 5:5)
753 | SetBitField (vDisplay, 9: 9, 6:6)
754 | SetBitField (vStart, 9: 9, 7:7);
755 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
756 | SetBit (6);
757 newmode.crtc[0x10] = Set8Bits (vStart);
758 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
759 | SetBit (5);
760 newmode.crtc[0x12] = Set8Bits (vDisplay);
761 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
762 newmode.crtc[0x15] = Set8Bits (vBlankStart);
763 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
764
765 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
766 | SetBitField(vBlankStart,10:10,3:3)
767 | SetBitField(vStart,10:10,2:2)
768 | SetBitField(vDisplay,10:10,1:1)
769 | SetBitField(vTotal,10:10,0:0);
770 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
771 | SetBitField(hDisplay,8:8,1:1)
772 | SetBitField(hBlankStart,8:8,2:2)
773 | SetBitField(hStart,8:8,3:3);
774 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
775 | SetBitField(vDisplay,11:11,2:2)
776 | SetBitField(vStart,11:11,4:4)
777 | SetBitField(vBlankStart,11:11,6:6);
778
779 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
780 int tmp = (hTotal >> 1) & ~1;
781 newmode.ext.interlace = Set8Bits(tmp);
782 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
783 } else
784 newmode.ext.interlace = 0xff; /* interlace off */
785
786 if (par->riva.Architecture >= NV_ARCH_10)
787 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
788
789 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
790 newmode.misc_output &= ~0x40;
791 else
792 newmode.misc_output |= 0x40;
793 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
794 newmode.misc_output &= ~0x80;
795 else
796 newmode.misc_output |= 0x80;
797
798 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
799 hDisplaySize, height, dotClock);
800 if (rc)
801 goto out;
802
803 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
804 0xfff000ff;
805 if (par->FlatPanel == 1) {
806 newmode.ext.pixel |= (1 << 7);
807 newmode.ext.scale |= (1 << 8);
808 }
809 if (par->SecondCRTC) {
810 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
811 ~0x00001000;
812 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
813 0x00001000;
814 newmode.ext.crtcOwner = 3;
815 newmode.ext.pllsel |= 0x20000800;
816 newmode.ext.vpll2 = newmode.ext.vpll;
817 } else if (par->riva.twoHeads) {
818 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
819 0x00001000;
820 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
821 ~0x00001000;
822 newmode.ext.crtcOwner = 0;
823 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
824 }
825 if (par->FlatPanel == 1) {
826 newmode.ext.pixel |= (1 << 7);
827 newmode.ext.scale |= (1 << 8);
828 }
829 newmode.ext.cursorConfig = 0x02000100;
830 par->current_state = newmode;
831 riva_load_state(par, &par->current_state);
832 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
833
834out:
835 rivafb_blank(FB_BLANK_UNBLANK, info);
836 NVTRACE_LEAVE();
837
838 return rc;
839}
840
841static void riva_update_var(struct fb_var_screeninfo *var,
842 const struct fb_videomode *modedb)
843{
844 NVTRACE_ENTER();
845 var->xres = var->xres_virtual = modedb->xres;
846 var->yres = modedb->yres;
847 if (var->yres_virtual < var->yres)
848 var->yres_virtual = var->yres;
849 var->xoffset = var->yoffset = 0;
850 var->pixclock = modedb->pixclock;
851 var->left_margin = modedb->left_margin;
852 var->right_margin = modedb->right_margin;
853 var->upper_margin = modedb->upper_margin;
854 var->lower_margin = modedb->lower_margin;
855 var->hsync_len = modedb->hsync_len;
856 var->vsync_len = modedb->vsync_len;
857 var->sync = modedb->sync;
858 var->vmode = modedb->vmode;
859 NVTRACE_LEAVE();
860}
861
862/**
863 * rivafb_do_maximize -
864 * @info: pointer to fb_info object containing info for current riva board
865 * @var:
866 * @nom:
867 * @den:
868 *
869 * DESCRIPTION:
870 * .
871 *
872 * RETURNS:
873 * -EINVAL on failure, 0 on success
874 *
875 *
876 * CALLED FROM:
877 * rivafb_check_var()
878 */
879static int rivafb_do_maximize(struct fb_info *info,
880 struct fb_var_screeninfo *var,
881 int nom, int den)
882{
883 static struct {
884 int xres, yres;
885 } modes[] = {
886 {1600, 1280},
887 {1280, 1024},
888 {1024, 768},
889 {800, 600},
890 {640, 480},
891 {-1, -1}
892 };
893 int i;
894
895 NVTRACE_ENTER();
896 /* use highest possible virtual resolution */
897 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
898 printk(KERN_WARNING PFX
899 "using maximum available virtual resolution\n");
900 for (i = 0; modes[i].xres != -1; i++) {
901 if (modes[i].xres * nom / den * modes[i].yres <
902 info->fix.smem_len)
903 break;
904 }
905 if (modes[i].xres == -1) {
906 printk(KERN_ERR PFX
907 "could not find a virtual resolution that fits into video memory!!\n");
908 NVTRACE("EXIT - EINVAL error\n");
909 return -EINVAL;
910 }
911 var->xres_virtual = modes[i].xres;
912 var->yres_virtual = modes[i].yres;
913
914 printk(KERN_INFO PFX
915 "virtual resolution set to maximum of %dx%d\n",
916 var->xres_virtual, var->yres_virtual);
917 } else if (var->xres_virtual == -1) {
918 var->xres_virtual = (info->fix.smem_len * den /
919 (nom * var->yres_virtual)) & ~15;
920 printk(KERN_WARNING PFX
921 "setting virtual X resolution to %d\n", var->xres_virtual);
922 } else if (var->yres_virtual == -1) {
923 var->xres_virtual = (var->xres_virtual + 15) & ~15;
924 var->yres_virtual = info->fix.smem_len * den /
925 (nom * var->xres_virtual);
926 printk(KERN_WARNING PFX
927 "setting virtual Y resolution to %d\n", var->yres_virtual);
928 } else {
929 var->xres_virtual = (var->xres_virtual + 15) & ~15;
930 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
931 printk(KERN_ERR PFX
932 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
933 var->xres, var->yres, var->bits_per_pixel);
934 NVTRACE("EXIT - EINVAL error\n");
935 return -EINVAL;
936 }
937 }
938
939 if (var->xres_virtual * nom / den >= 8192) {
940 printk(KERN_WARNING PFX
941 "virtual X resolution (%d) is too high, lowering to %d\n",
942 var->xres_virtual, 8192 * den / nom - 16);
943 var->xres_virtual = 8192 * den / nom - 16;
944 }
945
946 if (var->xres_virtual < var->xres) {
947 printk(KERN_ERR PFX
948 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
949 return -EINVAL;
950 }
951
952 if (var->yres_virtual < var->yres) {
953 printk(KERN_ERR PFX
954 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
955 return -EINVAL;
956 }
957 if (var->yres_virtual > 0x7fff/nom)
958 var->yres_virtual = 0x7fff/nom;
959 if (var->xres_virtual > 0x7fff/nom)
960 var->xres_virtual = 0x7fff/nom;
961 NVTRACE_LEAVE();
962 return 0;
963}
964
965static void
966riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
967{
968 RIVA_FIFO_FREE(par->riva, Patt, 4);
969 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
970 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
971 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
972 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
973}
974
975/* acceleration routines */
976static inline void wait_for_idle(struct riva_par *par)
977{
978 while (par->riva.Busy(&par->riva));
979}
980
981/*
982 * Set ROP. Translate X rop into ROP3. Internal routine.
983 */
984static void
985riva_set_rop_solid(struct riva_par *par, int rop)
986{
987 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
988 RIVA_FIFO_FREE(par->riva, Rop, 1);
989 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
990
991}
992
993static void riva_setup_accel(struct fb_info *info)
994{
995 struct riva_par *par = info->par;
996
997 RIVA_FIFO_FREE(par->riva, Clip, 2);
998 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
999 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1000 (info->var.xres_virtual & 0xffff) |
1001 (info->var.yres_virtual << 16));
1002 riva_set_rop_solid(par, 0xcc);
1003 wait_for_idle(par);
1004}
1005
1006/**
1007 * riva_get_cmap_len - query current color map length
1008 * @var: standard kernel fb changeable data
1009 *
1010 * DESCRIPTION:
1011 * Get current color map length.
1012 *
1013 * RETURNS:
1014 * Length of color map
1015 *
1016 * CALLED FROM:
1017 * rivafb_setcolreg()
1018 */
1019static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1020{
1021 int rc = 256; /* reasonable default */
1022
1023 switch (var->green.length) {
1024 case 8:
1025 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1026 break;
1027 case 5:
1028 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1029 break;
1030 case 6:
1031 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1032 break;
1033 default:
1034 /* should not occur */
1035 break;
1036 }
1037 return rc;
1038}
1039
1040/* ------------------------------------------------------------------------- *
1041 *
1042 * framebuffer operations
1043 *
1044 * ------------------------------------------------------------------------- */
1045
1046static int rivafb_open(struct fb_info *info, int user)
1047{
1048 struct riva_par *par = info->par;
1049
1050 NVTRACE_ENTER();
1051 mutex_lock(&par->open_lock);
1052 if (!par->ref_count) {
1053#ifdef CONFIG_X86
1054 memset(&par->state, 0, sizeof(struct vgastate));
1055 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1056 /* save the DAC for Riva128 */
1057 if (par->riva.Architecture == NV_ARCH_03)
1058 par->state.flags |= VGA_SAVE_CMAP;
1059 save_vga(&par->state);
1060#endif
1061 /* vgaHWunlock() + riva unlock (0x7F) */
1062 CRTCout(par, 0x11, 0xFF);
1063 par->riva.LockUnlock(&par->riva, 0);
1064
1065 riva_save_state(par, &par->initial_state);
1066 }
1067 par->ref_count++;
1068 mutex_unlock(&par->open_lock);
1069 NVTRACE_LEAVE();
1070 return 0;
1071}
1072
1073static int rivafb_release(struct fb_info *info, int user)
1074{
1075 struct riva_par *par = info->par;
1076
1077 NVTRACE_ENTER();
1078 mutex_lock(&par->open_lock);
1079 if (!par->ref_count) {
1080 mutex_unlock(&par->open_lock);
1081 return -EINVAL;
1082 }
1083 if (par->ref_count == 1) {
1084 par->riva.LockUnlock(&par->riva, 0);
1085 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1086 riva_load_state(par, &par->initial_state);
1087#ifdef CONFIG_X86
1088 restore_vga(&par->state);
1089#endif
1090 par->riva.LockUnlock(&par->riva, 1);
1091 }
1092 par->ref_count--;
1093 mutex_unlock(&par->open_lock);
1094 NVTRACE_LEAVE();
1095 return 0;
1096}
1097
1098static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1099{
1100 const struct fb_videomode *mode;
1101 struct riva_par *par = info->par;
1102 int nom, den; /* translating from pixels->bytes */
1103 int mode_valid = 0;
1104
1105 NVTRACE_ENTER();
1106 switch (var->bits_per_pixel) {
1107 case 1 ... 8:
1108 var->red.offset = var->green.offset = var->blue.offset = 0;
1109 var->red.length = var->green.length = var->blue.length = 8;
1110 var->bits_per_pixel = 8;
1111 nom = den = 1;
1112 break;
1113 case 9 ... 15:
1114 var->green.length = 5;
1115 /* fall through */
1116 case 16:
1117 var->bits_per_pixel = 16;
1118 /* The Riva128 supports RGB555 only */
1119 if (par->riva.Architecture == NV_ARCH_03)
1120 var->green.length = 5;
1121 if (var->green.length == 5) {
1122 /* 0rrrrrgg gggbbbbb */
1123 var->red.offset = 10;
1124 var->green.offset = 5;
1125 var->blue.offset = 0;
1126 var->red.length = 5;
1127 var->green.length = 5;
1128 var->blue.length = 5;
1129 } else {
1130 /* rrrrrggg gggbbbbb */
1131 var->red.offset = 11;
1132 var->green.offset = 5;
1133 var->blue.offset = 0;
1134 var->red.length = 5;
1135 var->green.length = 6;
1136 var->blue.length = 5;
1137 }
1138 nom = 2;
1139 den = 1;
1140 break;
1141 case 17 ... 32:
1142 var->red.length = var->green.length = var->blue.length = 8;
1143 var->bits_per_pixel = 32;
1144 var->red.offset = 16;
1145 var->green.offset = 8;
1146 var->blue.offset = 0;
1147 nom = 4;
1148 den = 1;
1149 break;
1150 default:
1151 printk(KERN_ERR PFX
1152 "mode %dx%dx%d rejected...color depth not supported.\n",
1153 var->xres, var->yres, var->bits_per_pixel);
1154 NVTRACE("EXIT, returning -EINVAL\n");
1155 return -EINVAL;
1156 }
1157
1158 if (!strictmode) {
1159 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1160 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1161 mode_valid = 1;
1162 }
1163
1164 /* calculate modeline if supported by monitor */
1165 if (!mode_valid && info->monspecs.gtf) {
1166 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1167 mode_valid = 1;
1168 }
1169
1170 if (!mode_valid) {
1171 mode = fb_find_best_mode(var, &info->modelist);
1172 if (mode) {
1173 riva_update_var(var, mode);
1174 mode_valid = 1;
1175 }
1176 }
1177
1178 if (!mode_valid && info->monspecs.modedb_len)
1179 return -EINVAL;
1180
1181 if (var->xres_virtual < var->xres)
1182 var->xres_virtual = var->xres;
1183 if (var->yres_virtual <= var->yres)
1184 var->yres_virtual = -1;
1185 if (rivafb_do_maximize(info, var, nom, den) < 0)
1186 return -EINVAL;
1187
1188 /* truncate xoffset and yoffset to maximum if too high */
1189 if (var->xoffset > var->xres_virtual - var->xres)
1190 var->xoffset = var->xres_virtual - var->xres - 1;
1191
1192 if (var->yoffset > var->yres_virtual - var->yres)
1193 var->yoffset = var->yres_virtual - var->yres - 1;
1194
1195 var->red.msb_right =
1196 var->green.msb_right =
1197 var->blue.msb_right =
1198 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1199 NVTRACE_LEAVE();
1200 return 0;
1201}
1202
1203static int rivafb_set_par(struct fb_info *info)
1204{
1205 struct riva_par *par = info->par;
1206 int rc = 0;
1207
1208 NVTRACE_ENTER();
1209 /* vgaHWunlock() + riva unlock (0x7F) */
1210 CRTCout(par, 0x11, 0xFF);
1211 par->riva.LockUnlock(&par->riva, 0);
1212 rc = riva_load_video_mode(info);
1213 if (rc)
1214 goto out;
1215 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1216 riva_setup_accel(info);
1217
1218 par->cursor_reset = 1;
1219 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1220 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1221 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1222
1223 if (info->flags & FBINFO_HWACCEL_DISABLED)
1224 info->pixmap.scan_align = 1;
1225 else
1226 info->pixmap.scan_align = 4;
1227
1228out:
1229 NVTRACE_LEAVE();
1230 return rc;
1231}
1232
1233/**
1234 * rivafb_pan_display
1235 * @var: standard kernel fb changeable data
1236 * @con: TODO
1237 * @info: pointer to fb_info object containing info for current riva board
1238 *
1239 * DESCRIPTION:
1240 * Pan (or wrap, depending on the `vmode' field) the display using the
1241 * `xoffset' and `yoffset' fields of the `var' structure.
1242 * If the values don't fit, return -EINVAL.
1243 *
1244 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1245 */
1246static int rivafb_pan_display(struct fb_var_screeninfo *var,
1247 struct fb_info *info)
1248{
1249 struct riva_par *par = info->par;
1250 unsigned int base;
1251
1252 NVTRACE_ENTER();
1253 base = var->yoffset * info->fix.line_length + var->xoffset;
1254 par->riva.SetStartAddress(&par->riva, base);
1255 NVTRACE_LEAVE();
1256 return 0;
1257}
1258
1259static int rivafb_blank(int blank, struct fb_info *info)
1260{
1261 struct riva_par *par= info->par;
1262 unsigned char tmp, vesa;
1263
1264 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1265 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1266
1267 NVTRACE_ENTER();
1268
1269 if (blank)
1270 tmp |= 0x20;
1271
1272 switch (blank) {
1273 case FB_BLANK_UNBLANK:
1274 case FB_BLANK_NORMAL:
1275 break;
1276 case FB_BLANK_VSYNC_SUSPEND:
1277 vesa |= 0x80;
1278 break;
1279 case FB_BLANK_HSYNC_SUSPEND:
1280 vesa |= 0x40;
1281 break;
1282 case FB_BLANK_POWERDOWN:
1283 vesa |= 0xc0;
1284 break;
1285 }
1286
1287 SEQout(par, 0x01, tmp);
1288 CRTCout(par, 0x1a, vesa);
1289
1290 NVTRACE_LEAVE();
1291
1292 return 0;
1293}
1294
1295/**
1296 * rivafb_setcolreg
1297 * @regno: register index
1298 * @red: red component
1299 * @green: green component
1300 * @blue: blue component
1301 * @transp: transparency
1302 * @info: pointer to fb_info object containing info for current riva board
1303 *
1304 * DESCRIPTION:
1305 * Set a single color register. The values supplied have a 16 bit
1306 * magnitude.
1307 *
1308 * RETURNS:
1309 * Return != 0 for invalid regno.
1310 *
1311 * CALLED FROM:
1312 * fbcmap.c:fb_set_cmap()
1313 */
1314static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1315 unsigned blue, unsigned transp,
1316 struct fb_info *info)
1317{
1318 struct riva_par *par = info->par;
1319 RIVA_HW_INST *chip = &par->riva;
1320 int i;
1321
1322 if (regno >= riva_get_cmap_len(&info->var))
1323 return -EINVAL;
1324
1325 if (info->var.grayscale) {
1326 /* gray = 0.30*R + 0.59*G + 0.11*B */
1327 red = green = blue =
1328 (red * 77 + green * 151 + blue * 28) >> 8;
1329 }
1330
1331 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1332 ((u32 *) info->pseudo_palette)[regno] =
1333 (regno << info->var.red.offset) |
1334 (regno << info->var.green.offset) |
1335 (regno << info->var.blue.offset);
1336 /*
1337 * The Riva128 2D engine requires color information in
1338 * TrueColor format even if framebuffer is in DirectColor
1339 */
1340 if (par->riva.Architecture == NV_ARCH_03) {
1341 switch (info->var.bits_per_pixel) {
1342 case 16:
1343 par->palette[regno] = ((red & 0xf800) >> 1) |
1344 ((green & 0xf800) >> 6) |
1345 ((blue & 0xf800) >> 11);
1346 break;
1347 case 32:
1348 par->palette[regno] = ((red & 0xff00) << 8) |
1349 ((green & 0xff00)) |
1350 ((blue & 0xff00) >> 8);
1351 break;
1352 }
1353 }
1354 }
1355
1356 switch (info->var.bits_per_pixel) {
1357 case 8:
1358 /* "transparent" stuff is completely ignored. */
1359 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1360 break;
1361 case 16:
1362 if (info->var.green.length == 5) {
1363 for (i = 0; i < 8; i++) {
1364 riva_wclut(chip, regno*8+i, red >> 8,
1365 green >> 8, blue >> 8);
1366 }
1367 } else {
1368 u8 r, g, b;
1369
1370 if (regno < 32) {
1371 for (i = 0; i < 8; i++) {
1372 riva_wclut(chip, regno*8+i,
1373 red >> 8, green >> 8,
1374 blue >> 8);
1375 }
1376 }
1377 riva_rclut(chip, regno*4, &r, &g, &b);
1378 for (i = 0; i < 4; i++)
1379 riva_wclut(chip, regno*4+i, r,
1380 green >> 8, b);
1381 }
1382 break;
1383 case 32:
1384 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1385 break;
1386 default:
1387 /* do nothing */
1388 break;
1389 }
1390 return 0;
1391}
1392
1393/**
1394 * rivafb_fillrect - hardware accelerated color fill function
1395 * @info: pointer to fb_info structure
1396 * @rect: pointer to fb_fillrect structure
1397 *
1398 * DESCRIPTION:
1399 * This function fills up a region of framebuffer memory with a solid
1400 * color with a choice of two different ROP's, copy or invert.
1401 *
1402 * CALLED FROM:
1403 * framebuffer hook
1404 */
1405static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1406{
1407 struct riva_par *par = info->par;
1408 u_int color, rop = 0;
1409
1410 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1411 cfb_fillrect(info, rect);
1412 return;
1413 }
1414
1415 if (info->var.bits_per_pixel == 8)
1416 color = rect->color;
1417 else {
1418 if (par->riva.Architecture != NV_ARCH_03)
1419 color = ((u32 *)info->pseudo_palette)[rect->color];
1420 else
1421 color = par->palette[rect->color];
1422 }
1423
1424 switch (rect->rop) {
1425 case ROP_XOR:
1426 rop = 0x66;
1427 break;
1428 case ROP_COPY:
1429 default:
1430 rop = 0xCC;
1431 break;
1432 }
1433
1434 riva_set_rop_solid(par, rop);
1435
1436 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1437 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1438
1439 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1440 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1441 (rect->dx << 16) | rect->dy);
1442 mb();
1443 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1444 (rect->width << 16) | rect->height);
1445 mb();
1446 riva_set_rop_solid(par, 0xcc);
1447
1448}
1449
1450/**
1451 * rivafb_copyarea - hardware accelerated blit function
1452 * @info: pointer to fb_info structure
1453 * @region: pointer to fb_copyarea structure
1454 *
1455 * DESCRIPTION:
1456 * This copies an area of pixels from one location to another
1457 *
1458 * CALLED FROM:
1459 * framebuffer hook
1460 */
1461static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1462{
1463 struct riva_par *par = info->par;
1464
1465 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1466 cfb_copyarea(info, region);
1467 return;
1468 }
1469
1470 RIVA_FIFO_FREE(par->riva, Blt, 3);
1471 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1472 (region->sy << 16) | region->sx);
1473 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1474 (region->dy << 16) | region->dx);
1475 mb();
1476 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1477 (region->height << 16) | region->width);
1478 mb();
1479}
1480
1481static inline void convert_bgcolor_16(u32 *col)
1482{
1483 *col = ((*col & 0x0000F800) << 8)
1484 | ((*col & 0x00007E0) << 5)
1485 | ((*col & 0x0000001F) << 3)
1486 | 0xFF000000;
1487 mb();
1488}
1489
1490/**
1491 * rivafb_imageblit: hardware accelerated color expand function
1492 * @info: pointer to fb_info structure
1493 * @image: pointer to fb_image structure
1494 *
1495 * DESCRIPTION:
1496 * If the source is a monochrome bitmap, the function fills up a a region
1497 * of framebuffer memory with pixels whose color is determined by the bit
1498 * setting of the bitmap, 1 - foreground, 0 - background.
1499 *
1500 * If the source is not a monochrome bitmap, color expansion is not done.
1501 * In this case, it is channeled to a software function.
1502 *
1503 * CALLED FROM:
1504 * framebuffer hook
1505 */
1506static void rivafb_imageblit(struct fb_info *info,
1507 const struct fb_image *image)
1508{
1509 struct riva_par *par = info->par;
1510 u32 fgx = 0, bgx = 0, width, tmp;
1511 u8 *cdat = (u8 *) image->data;
1512 volatile u32 __iomem *d;
1513 int i, size;
1514
1515 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1516 cfb_imageblit(info, image);
1517 return;
1518 }
1519
1520 switch (info->var.bits_per_pixel) {
1521 case 8:
1522 fgx = image->fg_color;
1523 bgx = image->bg_color;
1524 break;
1525 case 16:
1526 case 32:
1527 if (par->riva.Architecture != NV_ARCH_03) {
1528 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1529 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1530 } else {
1531 fgx = par->palette[image->fg_color];
1532 bgx = par->palette[image->bg_color];
1533 }
1534 if (info->var.green.length == 6)
1535 convert_bgcolor_16(&bgx);
1536 break;
1537 }
1538
1539 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1540 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1541 (image->dy << 16) | (image->dx & 0xFFFF));
1542 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1543 (((image->dy + image->height) << 16) |
1544 ((image->dx + image->width) & 0xffff)));
1545 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1546 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1547 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1548 (image->height << 16) | ((image->width + 31) & ~31));
1549 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1550 (image->height << 16) | ((image->width + 31) & ~31));
1551 NV_WR32(&par->riva.Bitmap->PointE, 0,
1552 (image->dy << 16) | (image->dx & 0xFFFF));
1553
1554 d = &par->riva.Bitmap->MonochromeData01E;
1555
1556 width = (image->width + 31)/32;
1557 size = width * image->height;
1558 while (size >= 16) {
1559 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1560 for (i = 0; i < 16; i++) {
1561 tmp = *((u32 *)cdat);
1562 cdat = (u8 *)((u32 *)cdat + 1);
1563 reverse_order(&tmp);
1564 NV_WR32(d, i*4, tmp);
1565 }
1566 size -= 16;
1567 }
1568 if (size) {
1569 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1570 for (i = 0; i < size; i++) {
1571 tmp = *((u32 *) cdat);
1572 cdat = (u8 *)((u32 *)cdat + 1);
1573 reverse_order(&tmp);
1574 NV_WR32(d, i*4, tmp);
1575 }
1576 }
1577}
1578
1579/**
1580 * rivafb_cursor - hardware cursor function
1581 * @info: pointer to info structure
1582 * @cursor: pointer to fbcursor structure
1583 *
1584 * DESCRIPTION:
1585 * A cursor function that supports displaying a cursor image via hardware.
1586 * Within the kernel, copy and invert rops are supported. If exported
1587 * to user space, only the copy rop will be supported.
1588 *
1589 * CALLED FROM
1590 * framebuffer hook
1591 */
1592static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1593{
1594 struct riva_par *par = info->par;
1595 u8 data[MAX_CURS * MAX_CURS/8];
1596 int i, set = cursor->set;
1597 u16 fg, bg;
1598
1599 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1600 return -ENXIO;
1601
1602 par->riva.ShowHideCursor(&par->riva, 0);
1603
1604 if (par->cursor_reset) {
1605 set = FB_CUR_SETALL;
1606 par->cursor_reset = 0;
1607 }
1608
1609 if (set & FB_CUR_SETSIZE)
1610 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1611
1612 if (set & FB_CUR_SETPOS) {
1613 u32 xx, yy, temp;
1614
1615 yy = cursor->image.dy - info->var.yoffset;
1616 xx = cursor->image.dx - info->var.xoffset;
1617 temp = xx & 0xFFFF;
1618 temp |= yy << 16;
1619
1620 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1621 }
1622
1623
1624 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1625 u32 bg_idx = cursor->image.bg_color;
1626 u32 fg_idx = cursor->image.fg_color;
1627 u32 s_pitch = (cursor->image.width+7) >> 3;
1628 u32 d_pitch = MAX_CURS/8;
1629 u8 *dat = (u8 *) cursor->image.data;
1630 u8 *msk = (u8 *) cursor->mask;
1631 u8 *src;
1632
1633 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1634
1635 if (src) {
1636 switch (cursor->rop) {
1637 case ROP_XOR:
1638 for (i = 0; i < s_pitch * cursor->image.height; i++)
1639 src[i] = dat[i] ^ msk[i];
1640 break;
1641 case ROP_COPY:
1642 default:
1643 for (i = 0; i < s_pitch * cursor->image.height; i++)
1644 src[i] = dat[i] & msk[i];
1645 break;
1646 }
1647
1648 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1649 cursor->image.height);
1650
1651 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1652 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1653 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1654 1 << 15;
1655
1656 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1657 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1658 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1659 1 << 15;
1660
1661 par->riva.LockUnlock(&par->riva, 0);
1662
1663 rivafb_load_cursor_image(par, data, bg, fg,
1664 cursor->image.width,
1665 cursor->image.height);
1666 kfree(src);
1667 }
1668 }
1669
1670 if (cursor->enable)
1671 par->riva.ShowHideCursor(&par->riva, 1);
1672
1673 return 0;
1674}
1675
1676static int rivafb_sync(struct fb_info *info)
1677{
1678 struct riva_par *par = info->par;
1679
1680 wait_for_idle(par);
1681 return 0;
1682}
1683
1684/* ------------------------------------------------------------------------- *
1685 *
1686 * initialization helper functions
1687 *
1688 * ------------------------------------------------------------------------- */
1689
1690/* kernel interface */
1691static struct fb_ops riva_fb_ops = {
1692 .owner = THIS_MODULE,
1693 .fb_open = rivafb_open,
1694 .fb_release = rivafb_release,
1695 .fb_check_var = rivafb_check_var,
1696 .fb_set_par = rivafb_set_par,
1697 .fb_setcolreg = rivafb_setcolreg,
1698 .fb_pan_display = rivafb_pan_display,
1699 .fb_blank = rivafb_blank,
1700 .fb_fillrect = rivafb_fillrect,
1701 .fb_copyarea = rivafb_copyarea,
1702 .fb_imageblit = rivafb_imageblit,
1703 .fb_cursor = rivafb_cursor,
1704 .fb_sync = rivafb_sync,
1705};
1706
1707static int riva_set_fbinfo(struct fb_info *info)
1708{
1709 unsigned int cmap_len;
1710 struct riva_par *par = info->par;
1711
1712 NVTRACE_ENTER();
1713 info->flags = FBINFO_DEFAULT
1714 | FBINFO_HWACCEL_XPAN
1715 | FBINFO_HWACCEL_YPAN
1716 | FBINFO_HWACCEL_COPYAREA
1717 | FBINFO_HWACCEL_FILLRECT
1718 | FBINFO_HWACCEL_IMAGEBLIT;
1719
1720 /* Accel seems to not work properly on NV30 yet...*/
1721 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1722 printk(KERN_DEBUG PFX "disabling acceleration\n");
1723 info->flags |= FBINFO_HWACCEL_DISABLED;
1724 }
1725
1726 info->var = rivafb_default_var;
1727 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1728 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1729
1730 info->pseudo_palette = par->pseudo_palette;
1731
1732 cmap_len = riva_get_cmap_len(&info->var);
1733 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1734
1735 info->pixmap.size = 8 * 1024;
1736 info->pixmap.buf_align = 4;
1737 info->pixmap.access_align = 32;
1738 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1739 info->var.yres_virtual = -1;
1740 NVTRACE_LEAVE();
1741 return (rivafb_check_var(&info->var, info));
1742}
1743
1744#ifdef CONFIG_PPC_OF
1745static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1746{
1747 struct riva_par *par = info->par;
1748 struct device_node *dp;
1749 const unsigned char *pedid = NULL;
1750 const unsigned char *disptype = NULL;
1751 static char *propnames[] = {
1752 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1753 int i;
1754
1755 NVTRACE_ENTER();
1756 dp = pci_device_to_OF_node(pd);
1757 for (; dp != NULL; dp = dp->child) {
1758 disptype = of_get_property(dp, "display-type", NULL);
1759 if (disptype == NULL)
1760 continue;
1761 if (strncmp(disptype, "LCD", 3) != 0)
1762 continue;
1763 for (i = 0; propnames[i] != NULL; ++i) {
1764 pedid = of_get_property(dp, propnames[i], NULL);
1765 if (pedid != NULL) {
1766 par->EDID = (unsigned char *)pedid;
1767 NVTRACE("LCD found.\n");
1768 return 1;
1769 }
1770 }
1771 }
1772 NVTRACE_LEAVE();
1773 return 0;
1774}
1775#endif /* CONFIG_PPC_OF */
1776
1777#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1778static int riva_get_EDID_i2c(struct fb_info *info)
1779{
1780 struct riva_par *par = info->par;
1781 struct fb_var_screeninfo var;
1782 int i;
1783
1784 NVTRACE_ENTER();
1785 riva_create_i2c_busses(par);
1786 for (i = 0; i < 3; i++) {
1787 if (!par->chan[i].par)
1788 continue;
1789 riva_probe_i2c_connector(par, i, &par->EDID);
1790 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1791 printk(PFX "Found EDID Block from BUS %i\n", i);
1792 break;
1793 }
1794 }
1795
1796 NVTRACE_LEAVE();
1797 return (par->EDID) ? 1 : 0;
1798}
1799#endif /* CONFIG_FB_RIVA_I2C */
1800
1801static void riva_update_default_var(struct fb_var_screeninfo *var,
1802 struct fb_info *info)
1803{
1804 struct fb_monspecs *specs = &info->monspecs;
1805 struct fb_videomode modedb;
1806
1807 NVTRACE_ENTER();
1808 /* respect mode options */
1809 if (mode_option) {
1810 fb_find_mode(var, info, mode_option,
1811 specs->modedb, specs->modedb_len,
1812 NULL, 8);
1813 } else if (specs->modedb != NULL) {
1814 /* get first mode in database as fallback */
1815 modedb = specs->modedb[0];
1816 /* get preferred timing */
1817 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1818 int i;
1819
1820 for (i = 0; i < specs->modedb_len; i++) {
1821 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1822 modedb = specs->modedb[i];
1823 break;
1824 }
1825 }
1826 }
1827 var->bits_per_pixel = 8;
1828 riva_update_var(var, &modedb);
1829 }
1830 NVTRACE_LEAVE();
1831}
1832
1833
1834static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1835{
1836 NVTRACE_ENTER();
1837#ifdef CONFIG_PPC_OF
1838 if (!riva_get_EDID_OF(info, pdev))
1839 printk(PFX "could not retrieve EDID from OF\n");
1840#elif defined(CONFIG_FB_RIVA_I2C)
1841 if (!riva_get_EDID_i2c(info))
1842 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1843#endif
1844 NVTRACE_LEAVE();
1845}
1846
1847
1848static void riva_get_edidinfo(struct fb_info *info)
1849{
1850 struct fb_var_screeninfo *var = &rivafb_default_var;
1851 struct riva_par *par = info->par;
1852
1853 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1854 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1855 &info->modelist);
1856 riva_update_default_var(var, info);
1857
1858 /* if user specified flatpanel, we respect that */
1859 if (info->monspecs.input & FB_DISP_DDI)
1860 par->FlatPanel = 1;
1861}
1862
1863/* ------------------------------------------------------------------------- *
1864 *
1865 * PCI bus
1866 *
1867 * ------------------------------------------------------------------------- */
1868
1869static u32 riva_get_arch(struct pci_dev *pd)
1870{
1871 u32 arch = 0;
1872
1873 switch (pd->device & 0x0ff0) {
1874 case 0x0100: /* GeForce 256 */
1875 case 0x0110: /* GeForce2 MX */
1876 case 0x0150: /* GeForce2 */
1877 case 0x0170: /* GeForce4 MX */
1878 case 0x0180: /* GeForce4 MX (8x AGP) */
1879 case 0x01A0: /* nForce */
1880 case 0x01F0: /* nForce2 */
1881 arch = NV_ARCH_10;
1882 break;
1883 case 0x0200: /* GeForce3 */
1884 case 0x0250: /* GeForce4 Ti */
1885 case 0x0280: /* GeForce4 Ti (8x AGP) */
1886 arch = NV_ARCH_20;
1887 break;
1888 case 0x0300: /* GeForceFX 5800 */
1889 case 0x0310: /* GeForceFX 5600 */
1890 case 0x0320: /* GeForceFX 5200 */
1891 case 0x0330: /* GeForceFX 5900 */
1892 case 0x0340: /* GeForceFX 5700 */
1893 arch = NV_ARCH_30;
1894 break;
1895 case 0x0020: /* TNT, TNT2 */
1896 arch = NV_ARCH_04;
1897 break;
1898 case 0x0010: /* Riva128 */
1899 arch = NV_ARCH_03;
1900 break;
1901 default: /* unknown architecture */
1902 break;
1903 }
1904 return arch;
1905}
1906
1907static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1908{
1909 struct riva_par *default_par;
1910 struct fb_info *info;
1911 int ret;
1912
1913 NVTRACE_ENTER();
1914 assert(pd != NULL);
1915
1916 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1917 if (!info) {
1918 printk (KERN_ERR PFX "could not allocate memory\n");
1919 ret = -ENOMEM;
1920 goto err_ret;
1921 }
1922 default_par = info->par;
1923 default_par->pdev = pd;
1924
1925 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1926 if (info->pixmap.addr == NULL) {
1927 ret = -ENOMEM;
1928 goto err_framebuffer_release;
1929 }
1930
1931 ret = pci_enable_device(pd);
1932 if (ret < 0) {
1933 printk(KERN_ERR PFX "cannot enable PCI device\n");
1934 goto err_free_pixmap;
1935 }
1936
1937 ret = pci_request_regions(pd, "rivafb");
1938 if (ret < 0) {
1939 printk(KERN_ERR PFX "cannot request PCI regions\n");
1940 goto err_disable_device;
1941 }
1942
1943 mutex_init(&default_par->open_lock);
1944 default_par->riva.Architecture = riva_get_arch(pd);
1945
1946 default_par->Chipset = (pd->vendor << 16) | pd->device;
1947 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1948
1949 if(default_par->riva.Architecture == 0) {
1950 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1951 ret=-ENODEV;
1952 goto err_release_region;
1953 }
1954 if(default_par->riva.Architecture == NV_ARCH_10 ||
1955 default_par->riva.Architecture == NV_ARCH_20 ||
1956 default_par->riva.Architecture == NV_ARCH_30) {
1957 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1958 } else {
1959 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1960 }
1961
1962 default_par->FlatPanel = flatpanel;
1963 if (flatpanel == 1)
1964 printk(KERN_INFO PFX "flatpanel support enabled\n");
1965 default_par->forceCRTC = forceCRTC;
1966
1967 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1968 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1969
1970 {
1971 /* enable IO and mem if not already done */
1972 unsigned short cmd;
1973
1974 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1975 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1976 pci_write_config_word(pd, PCI_COMMAND, cmd);
1977 }
1978
1979 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1980 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1981
1982 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1983 rivafb_fix.mmio_len);
1984 if (!default_par->ctrl_base) {
1985 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1986 ret = -EIO;
1987 goto err_release_region;
1988 }
1989
1990 switch (default_par->riva.Architecture) {
1991 case NV_ARCH_03:
1992 /* Riva128's PRAMIN is in the "framebuffer" space
1993 * Since these cards were never made with more than 8 megabytes
1994 * we can safely allocate this separately.
1995 */
1996 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1997 if (!default_par->riva.PRAMIN) {
1998 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1999 ret = -EIO;
2000 goto err_iounmap_ctrl_base;
2001 }
2002 break;
2003 case NV_ARCH_04:
2004 case NV_ARCH_10:
2005 case NV_ARCH_20:
2006 case NV_ARCH_30:
2007 default_par->riva.PCRTC0 =
2008 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2009 default_par->riva.PRAMIN =
2010 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2011 break;
2012 }
2013 riva_common_setup(default_par);
2014
2015 if (default_par->riva.Architecture == NV_ARCH_03) {
2016 default_par->riva.PCRTC = default_par->riva.PCRTC0
2017 = default_par->riva.PGRAPH;
2018 }
2019
2020 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2021 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2022 info->screen_base = ioremap(rivafb_fix.smem_start,
2023 rivafb_fix.smem_len);
2024 if (!info->screen_base) {
2025 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2026 ret = -EIO;
2027 goto err_iounmap_pramin;
2028 }
2029
2030#ifdef CONFIG_MTRR
2031 if (!nomtrr) {
2032 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2033 rivafb_fix.smem_len,
2034 MTRR_TYPE_WRCOMB, 1);
2035 if (default_par->mtrr.vram < 0) {
2036 printk(KERN_ERR PFX "unable to setup MTRR\n");
2037 } else {
2038 default_par->mtrr.vram_valid = 1;
2039 /* let there be speed */
2040 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2041 }
2042 }
2043#endif /* CONFIG_MTRR */
2044
2045 info->fbops = &riva_fb_ops;
2046 info->fix = rivafb_fix;
2047 riva_get_EDID(info, pd);
2048 riva_get_edidinfo(info);
2049
2050 ret=riva_set_fbinfo(info);
2051 if (ret < 0) {
2052 printk(KERN_ERR PFX "error setting initial video mode\n");
2053 goto err_iounmap_screen_base;
2054 }
2055
2056 fb_destroy_modedb(info->monspecs.modedb);
2057 info->monspecs.modedb = NULL;
2058
2059 pci_set_drvdata(pd, info);
2060
2061 if (backlight)
2062 riva_bl_init(info->par);
2063
2064 ret = register_framebuffer(info);
2065 if (ret < 0) {
2066 printk(KERN_ERR PFX
2067 "error registering riva framebuffer\n");
2068 goto err_iounmap_screen_base;
2069 }
2070
2071 printk(KERN_INFO PFX
2072 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2073 info->fix.id,
2074 RIVAFB_VERSION,
2075 info->fix.smem_len / (1024 * 1024),
2076 info->fix.smem_start);
2077
2078 NVTRACE_LEAVE();
2079 return 0;
2080
2081err_iounmap_screen_base:
2082#ifdef CONFIG_FB_RIVA_I2C
2083 riva_delete_i2c_busses(info->par);
2084#endif
2085 iounmap(info->screen_base);
2086err_iounmap_pramin:
2087 if (default_par->riva.Architecture == NV_ARCH_03)
2088 iounmap(default_par->riva.PRAMIN);
2089err_iounmap_ctrl_base:
2090 iounmap(default_par->ctrl_base);
2091err_release_region:
2092 pci_release_regions(pd);
2093err_disable_device:
2094err_free_pixmap:
2095 kfree(info->pixmap.addr);
2096err_framebuffer_release:
2097 framebuffer_release(info);
2098err_ret:
2099 return ret;
2100}
2101
2102static void rivafb_remove(struct pci_dev *pd)
2103{
2104 struct fb_info *info = pci_get_drvdata(pd);
2105 struct riva_par *par = info->par;
2106
2107 NVTRACE_ENTER();
2108
2109#ifdef CONFIG_FB_RIVA_I2C
2110 riva_delete_i2c_busses(par);
2111 kfree(par->EDID);
2112#endif
2113
2114 unregister_framebuffer(info);
2115
2116 riva_bl_exit(info);
2117
2118#ifdef CONFIG_MTRR
2119 if (par->mtrr.vram_valid)
2120 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2121 info->fix.smem_len);
2122#endif /* CONFIG_MTRR */
2123
2124 iounmap(par->ctrl_base);
2125 iounmap(info->screen_base);
2126 if (par->riva.Architecture == NV_ARCH_03)
2127 iounmap(par->riva.PRAMIN);
2128 pci_release_regions(pd);
2129 kfree(info->pixmap.addr);
2130 framebuffer_release(info);
2131 NVTRACE_LEAVE();
2132}
2133
2134/* ------------------------------------------------------------------------- *
2135 *
2136 * initialization
2137 *
2138 * ------------------------------------------------------------------------- */
2139
2140#ifndef MODULE
2141static int rivafb_setup(char *options)
2142{
2143 char *this_opt;
2144
2145 NVTRACE_ENTER();
2146 if (!options || !*options)
2147 return 0;
2148
2149 while ((this_opt = strsep(&options, ",")) != NULL) {
2150 if (!strncmp(this_opt, "forceCRTC", 9)) {
2151 char *p;
2152
2153 p = this_opt + 9;
2154 if (!*p || !*(++p)) continue;
2155 forceCRTC = *p - '0';
2156 if (forceCRTC < 0 || forceCRTC > 1)
2157 forceCRTC = -1;
2158 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2159 flatpanel = 1;
2160 } else if (!strncmp(this_opt, "backlight:", 10)) {
2161 backlight = simple_strtoul(this_opt+10, NULL, 0);
2162#ifdef CONFIG_MTRR
2163 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2164 nomtrr = 1;
2165#endif
2166 } else if (!strncmp(this_opt, "strictmode", 10)) {
2167 strictmode = 1;
2168 } else if (!strncmp(this_opt, "noaccel", 7)) {
2169 noaccel = 1;
2170 } else
2171 mode_option = this_opt;
2172 }
2173 NVTRACE_LEAVE();
2174 return 0;
2175}
2176#endif /* !MODULE */
2177
2178static struct pci_driver rivafb_driver = {
2179 .name = "rivafb",
2180 .id_table = rivafb_pci_tbl,
2181 .probe = rivafb_probe,
2182 .remove = rivafb_remove,
2183};
2184
2185
2186
2187/* ------------------------------------------------------------------------- *
2188 *
2189 * modularization
2190 *
2191 * ------------------------------------------------------------------------- */
2192
2193static int rivafb_init(void)
2194{
2195#ifndef MODULE
2196 char *option = NULL;
2197
2198 if (fb_get_options("rivafb", &option))
2199 return -ENODEV;
2200 rivafb_setup(option);
2201#endif
2202 return pci_register_driver(&rivafb_driver);
2203}
2204
2205
2206module_init(rivafb_init);
2207
2208static void __exit rivafb_exit(void)
2209{
2210 pci_unregister_driver(&rivafb_driver);
2211}
2212
2213module_exit(rivafb_exit);
2214
2215module_param(noaccel, bool, 0);
2216MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2217module_param(flatpanel, int, 0);
2218MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2219module_param(forceCRTC, int, 0);
2220MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2221#ifdef CONFIG_MTRR
2222module_param(nomtrr, bool, 0);
2223MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2224#endif
2225module_param(strictmode, bool, 0);
2226MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2227
2228MODULE_AUTHOR("Ani Joshi, maintainer");
2229MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2230MODULE_LICENSE("GPL");
diff --git a/drivers/video/riva/nv_driver.c b/drivers/video/riva/nv_driver.c
deleted file mode 100644
index f3694cf17e58..000000000000
--- a/drivers/video/riva/nv_driver.c
+++ /dev/null
@@ -1,422 +0,0 @@
1/* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */
2/*
3 * Copyright 1996-1997 David J. McKay
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24/*
25 * GPL licensing note -- nVidia is allowing a liberal interpretation of
26 * the documentation restriction above, to merely say that this nVidia's
27 * copyright and disclaimer should be included with all code derived
28 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
29 */
30
31/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
32 <jpaana@s2.org> */
33
34/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0
355 20:47:06 mvojkovi Exp $ */
36
37#include <linux/delay.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include "nv_type.h"
41#include "rivafb.h"
42#include "nvreg.h"
43
44#define PFX "rivafb: "
45
46static inline unsigned char MISCin(struct riva_par *par)
47{
48 return (VGA_RD08(par->riva.PVIO, 0x3cc));
49}
50
51static Bool
52riva_is_connected(struct riva_par *par, Bool second)
53{
54 volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0;
55 U032 reg52C, reg608;
56 Bool present;
57
58 if(second) PRAMDAC += 0x800;
59
60 reg52C = NV_RD32(PRAMDAC, 0x052C);
61 reg608 = NV_RD32(PRAMDAC, 0x0608);
62
63 NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
64
65 NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
66 mdelay(1);
67 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
68
69 NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140);
70 NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000);
71
72 mdelay(1);
73
74 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE;
75
76 NV_WR32(par->riva.PRAMDAC0, 0x0608,
77 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF);
78
79 NV_WR32(PRAMDAC, 0x052C, reg52C);
80 NV_WR32(PRAMDAC, 0x0608, reg608);
81
82 return present;
83}
84
85static void
86riva_override_CRTC(struct riva_par *par)
87{
88 printk(KERN_INFO PFX
89 "Detected CRTC controller %i being used\n",
90 par->SecondCRTC ? 1 : 0);
91
92 if(par->forceCRTC != -1) {
93 printk(KERN_INFO PFX
94 "Forcing usage of CRTC %i\n", par->forceCRTC);
95 par->SecondCRTC = par->forceCRTC;
96 }
97}
98
99static void
100riva_is_second(struct riva_par *par)
101{
102 if (par->FlatPanel == 1) {
103 switch(par->Chipset & 0xffff) {
104 case 0x0174:
105 case 0x0175:
106 case 0x0176:
107 case 0x0177:
108 case 0x0179:
109 case 0x017C:
110 case 0x017D:
111 case 0x0186:
112 case 0x0187:
113 /* this might not be a good default for the chips below */
114 case 0x0286:
115 case 0x028C:
116 case 0x0316:
117 case 0x0317:
118 case 0x031A:
119 case 0x031B:
120 case 0x031C:
121 case 0x031D:
122 case 0x031E:
123 case 0x031F:
124 case 0x0324:
125 case 0x0325:
126 case 0x0328:
127 case 0x0329:
128 case 0x032C:
129 case 0x032D:
130 par->SecondCRTC = TRUE;
131 break;
132 default:
133 par->SecondCRTC = FALSE;
134 break;
135 }
136 } else {
137 if(riva_is_connected(par, 0)) {
138
139 if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100)
140 par->SecondCRTC = TRUE;
141 else
142 par->SecondCRTC = FALSE;
143 } else
144 if (riva_is_connected(par, 1)) {
145 if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100)
146 par->SecondCRTC = TRUE;
147 else
148 par->SecondCRTC = FALSE;
149 } else /* default */
150 par->SecondCRTC = FALSE;
151 }
152 riva_override_CRTC(par);
153}
154
155unsigned long riva_get_memlen(struct riva_par *par)
156{
157 RIVA_HW_INST *chip = &par->riva;
158 unsigned long memlen = 0;
159 unsigned int chipset = par->Chipset;
160 struct pci_dev* dev;
161 u32 amt;
162
163 switch (chip->Architecture) {
164 case NV_ARCH_03:
165 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
166 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
167 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) {
168 /*
169 * SDRAM 128 ZX.
170 */
171 switch (NV_RD32(chip->PFB,0x00000000) & 0x03) {
172 case 2:
173 memlen = 1024 * 4;
174 break;
175 case 1:
176 memlen = 1024 * 2;
177 break;
178 default:
179 memlen = 1024 * 8;
180 break;
181 }
182 } else {
183 memlen = 1024 * 8;
184 }
185 } else {
186 /*
187 * SGRAM 128.
188 */
189 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
190 case 0:
191 memlen = 1024 * 8;
192 break;
193 case 2:
194 memlen = 1024 * 4;
195 break;
196 default:
197 memlen = 1024 * 2;
198 break;
199 }
200 }
201 break;
202 case NV_ARCH_04:
203 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) {
204 memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) *
205 1024 * 2 + 1024 * 2;
206 } else {
207 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
208 case 0:
209 memlen = 1024 * 32;
210 break;
211 case 1:
212 memlen = 1024 * 4;
213 break;
214 case 2:
215 memlen = 1024 * 8;
216 break;
217 case 3:
218 default:
219 memlen = 1024 * 16;
220 break;
221 }
222 }
223 break;
224 case NV_ARCH_10:
225 case NV_ARCH_20:
226 case NV_ARCH_30:
227 if(chipset == NV_CHIP_IGEFORCE2) {
228
229 dev = pci_get_bus_and_slot(0, 1);
230 pci_read_config_dword(dev, 0x7C, &amt);
231 pci_dev_put(dev);
232 memlen = (((amt >> 6) & 31) + 1) * 1024;
233 } else if (chipset == NV_CHIP_0x01F0) {
234 dev = pci_get_bus_and_slot(0, 1);
235 pci_read_config_dword(dev, 0x84, &amt);
236 pci_dev_put(dev);
237 memlen = (((amt >> 4) & 127) + 1) * 1024;
238 } else {
239 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) &
240 0x000000FF){
241 case 0x02:
242 memlen = 1024 * 2;
243 break;
244 case 0x04:
245 memlen = 1024 * 4;
246 break;
247 case 0x08:
248 memlen = 1024 * 8;
249 break;
250 case 0x10:
251 memlen = 1024 * 16;
252 break;
253 case 0x20:
254 memlen = 1024 * 32;
255 break;
256 case 0x40:
257 memlen = 1024 * 64;
258 break;
259 case 0x80:
260 memlen = 1024 * 128;
261 break;
262 default:
263 memlen = 1024 * 16;
264 break;
265 }
266 }
267 break;
268 }
269 return memlen;
270}
271
272unsigned long riva_get_maxdclk(struct riva_par *par)
273{
274 RIVA_HW_INST *chip = &par->riva;
275 unsigned long dclk = 0;
276
277 switch (chip->Architecture) {
278 case NV_ARCH_03:
279 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
280 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
281 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) {
282 /*
283 * SDRAM 128 ZX.
284 */
285 dclk = 800000;
286 } else {
287 dclk = 1000000;
288 }
289 } else {
290 /*
291 * SGRAM 128.
292 */
293 dclk = 1000000;
294 }
295 break;
296 case NV_ARCH_04:
297 case NV_ARCH_10:
298 case NV_ARCH_20:
299 case NV_ARCH_30:
300 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) {
301 case 3:
302 dclk = 800000;
303 break;
304 default:
305 dclk = 1000000;
306 break;
307 }
308 break;
309 }
310 return dclk;
311}
312
313void
314riva_common_setup(struct riva_par *par)
315{
316 par->riva.EnableIRQ = 0;
317 par->riva.PRAMDAC0 =
318 (volatile U032 __iomem *)(par->ctrl_base + 0x00680000);
319 par->riva.PFB =
320 (volatile U032 __iomem *)(par->ctrl_base + 0x00100000);
321 par->riva.PFIFO =
322 (volatile U032 __iomem *)(par->ctrl_base + 0x00002000);
323 par->riva.PGRAPH =
324 (volatile U032 __iomem *)(par->ctrl_base + 0x00400000);
325 par->riva.PEXTDEV =
326 (volatile U032 __iomem *)(par->ctrl_base + 0x00101000);
327 par->riva.PTIMER =
328 (volatile U032 __iomem *)(par->ctrl_base + 0x00009000);
329 par->riva.PMC =
330 (volatile U032 __iomem *)(par->ctrl_base + 0x00000000);
331 par->riva.FIFO =
332 (volatile U032 __iomem *)(par->ctrl_base + 0x00800000);
333 par->riva.PCIO0 = par->ctrl_base + 0x00601000;
334 par->riva.PDIO0 = par->ctrl_base + 0x00681000;
335 par->riva.PVIO = par->ctrl_base + 0x000C0000;
336
337 par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0;
338
339 if (par->FlatPanel == -1) {
340 switch (par->Chipset & 0xffff) {
341 case 0x0112: /* known laptop chips */
342 case 0x0174:
343 case 0x0175:
344 case 0x0176:
345 case 0x0177:
346 case 0x0179:
347 case 0x017C:
348 case 0x017D:
349 case 0x0186:
350 case 0x0187:
351 case 0x0286:
352 case 0x028C:
353 case 0x0316:
354 case 0x0317:
355 case 0x031A:
356 case 0x031B:
357 case 0x031C:
358 case 0x031D:
359 case 0x031E:
360 case 0x031F:
361 case 0x0324:
362 case 0x0325:
363 case 0x0328:
364 case 0x0329:
365 case 0x032C:
366 case 0x032D:
367 printk(KERN_INFO PFX
368 "On a laptop. Assuming Digital Flat Panel\n");
369 par->FlatPanel = 1;
370 break;
371 default:
372 break;
373 }
374 }
375
376 switch (par->Chipset & 0x0ff0) {
377 case 0x0110:
378 if (par->Chipset == NV_CHIP_GEFORCE2_GO)
379 par->SecondCRTC = TRUE;
380#if defined(__powerpc__)
381 if (par->FlatPanel == 1)
382 par->SecondCRTC = TRUE;
383#endif
384 riva_override_CRTC(par);
385 break;
386 case 0x0170:
387 case 0x0180:
388 case 0x01F0:
389 case 0x0250:
390 case 0x0280:
391 case 0x0300:
392 case 0x0310:
393 case 0x0320:
394 case 0x0330:
395 case 0x0340:
396 riva_is_second(par);
397 break;
398 default:
399 break;
400 }
401
402 if (par->SecondCRTC) {
403 par->riva.PCIO = par->riva.PCIO0 + 0x2000;
404 par->riva.PCRTC = par->riva.PCRTC0 + 0x800;
405 par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800;
406 par->riva.PDIO = par->riva.PDIO0 + 0x2000;
407 } else {
408 par->riva.PCIO = par->riva.PCIO0;
409 par->riva.PCRTC = par->riva.PCRTC0;
410 par->riva.PRAMDAC = par->riva.PRAMDAC0;
411 par->riva.PDIO = par->riva.PDIO0;
412 }
413
414 if (par->FlatPanel == -1) {
415 /* Fix me, need x86 DDC code */
416 par->FlatPanel = 0;
417 }
418 par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
419
420 RivaGetConfig(&par->riva, par->Chipset);
421}
422
diff --git a/drivers/video/riva/nv_type.h b/drivers/video/riva/nv_type.h
deleted file mode 100644
index a69480c9a67c..000000000000
--- a/drivers/video/riva/nv_type.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.35 2002/08/05 20:47:06 mvojkovi Exp $ */
2
3#ifndef __NV_STRUCT_H__
4#define __NV_STRUCT_H__
5
6#define NV_CHIP_RIVA_128 ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128)
7#define NV_CHIP_TNT ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT)
8#define NV_CHIP_TNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2)
9#define NV_CHIP_UTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2)
10#define NV_CHIP_VTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2)
11#define NV_CHIP_UVTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2)
12#define NV_CHIP_ITNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2)
13#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256)
14#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR)
15#define NV_CHIP_QUADRO ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_QUADRO)
16#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX)
17#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX_100)
18#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR)
19#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO)
20#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS)
21#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_TI)
22#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA)
23#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO)
24#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460)
25#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440)
26#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420)
27#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO)
28#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO)
29#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32)
30#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL)
31#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64)
32#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_200)
33#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL)
34#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL)
35#define NV_CHIP_0x0180 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0180)
36#define NV_CHIP_0x0181 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0181)
37#define NV_CHIP_0x0182 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0182)
38#define NV_CHIP_0x0188 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0188)
39#define NV_CHIP_0x018A ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018A)
40#define NV_CHIP_0x018B ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018B)
41#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_IGEFORCE2)
42#define NV_CHIP_0x01F0 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x01F0)
43#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3)
44#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_200)
45#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_500)
46#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO_DCC)
47#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600)
48#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400)
49#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200)
50#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL)
51#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL)
52#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL)
53#define NV_CHIP_0x0280 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0280)
54#define NV_CHIP_0x0281 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0281)
55#define NV_CHIP_0x0288 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0288)
56#define NV_CHIP_0x0289 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0289)
57
58#endif /* __NV_STRUCT_H__ */
diff --git a/drivers/video/riva/nvreg.h b/drivers/video/riva/nvreg.h
deleted file mode 100644
index abfc167ae8d8..000000000000
--- a/drivers/video/riva/nvreg.h
+++ /dev/null
@@ -1,188 +0,0 @@
1/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
2/*
3 * Copyright 1996-1997 David J. McKay
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */
25
26#ifndef __NVREG_H_
27#define __NVREG_H_
28
29/* Little macro to construct bitmask for contiguous ranges of bits */
30#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
31#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
32
33/* Macro to set specific bitfields (mask has to be a macro x:y) ! */
34#define SetBF(mask,value) ((value) << (0?mask))
35#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
36
37#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
38 | SetBF(mask,value)))
39
40#define DEVICE_BASE(device) (0?NV##_##device)
41#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
42
43/* This is where we will have to have conditional compilation */
44#define DEVICE_ACCESS(device,reg) \
45 nvCONTROL[(NV_##device##_##reg)/4]
46
47#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
48#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg)
49#define DEVICE_PRINT(device,reg) \
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
51#define DEVICE_DEF(device,mask,value) \
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
54#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
55
56#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value)
57#define PDAC_Read(reg) DEVICE_READ(PDAC,reg)
58#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg)
59#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value)
60#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value)
61#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask)
62
63#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)
64#define PFB_Read(reg) DEVICE_READ(PFB,reg)
65#define PFB_Print(reg) DEVICE_PRINT(PFB,reg)
66#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)
67#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)
68#define PFB_Mask(mask) DEVICE_MASK(PFB,mask)
69
70#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value)
71#define PRM_Read(reg) DEVICE_READ(PRM,reg)
72#define PRM_Print(reg) DEVICE_PRINT(PRM,reg)
73#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value)
74#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value)
75#define PRM_Mask(mask) DEVICE_MASK(PRM,mask)
76
77#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value)
78#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg)
79#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg)
80#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value)
81#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value)
82#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask)
83
84#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
85#define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
86#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
87#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
88#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
89#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
90
91#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value)
92#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg)
93#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg)
94#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value)
95#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value)
96#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask)
97
98#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value)
99#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)
100#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg)
101#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value)
102#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value)
103#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)
104
105#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
106#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
107#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
108#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
109#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
110#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
111
112#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value)
113#define PRAM_Read(reg) DEVICE_READ(PRAM,reg)
114#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg)
115#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value)
116#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value)
117#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask)
118
119#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value)
120#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg)
121#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg)
122#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value)
123#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value)
124#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask)
125
126#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127#define PMC_Read(reg) DEVICE_READ(PMC,reg)
128#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
132
133#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134#define PMC_Read(reg) DEVICE_READ(PMC,reg)
135#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
137#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
138#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
139
140
141#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value)
142#define PBUS_Read(reg) DEVICE_READ(PBUS,reg)
143#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg)
144#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value)
145#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value)
146#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask)
147
148
149#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value)
150#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg)
151#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg)
152#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value)
153#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value)
154#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask)
155
156
157#define PDAC_ReadExt(reg) \
158 ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
159 (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
160 (PDAC_Read(INDEX_DATA)))
161
162#define PDAC_WriteExt(reg,value)\
163 ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
164 (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
165 (PDAC_Write(INDEX_DATA,(value))))
166
167#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5)
168#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5))
169
170#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)
171#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)
172
173#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
174#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
175#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
176
177#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)
178#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))
179
180extern volatile unsigned *nvCONTROL;
181
182typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType;
183
184NVChipType GetChipType(void);
185
186#endif
187
188
diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c
deleted file mode 100644
index 78fdbf5178d7..000000000000
--- a/drivers/video/riva/riva_hw.c
+++ /dev/null
@@ -1,2268 +0,0 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45 */
46
47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */
48
49#include <linux/kernel.h>
50#include <linux/pci.h>
51#include <linux/pci_ids.h>
52#include "riva_hw.h"
53#include "riva_tbl.h"
54#include "nv_type.h"
55
56/*
57 * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
58 * operate identically (except TNT has more memory and better 3D quality.
59 */
60static int nv3Busy
61(
62 RIVA_HW_INST *chip
63)
64{
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);
67}
68static int nv4Busy
69(
70 RIVA_HW_INST *chip
71)
72{
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
75}
76static int nv10Busy
77(
78 RIVA_HW_INST *chip
79)
80{
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
83}
84
85static void vgaLockUnlock
86(
87 RIVA_HW_INST *chip,
88 int Lock
89)
90{
91 U008 cr11;
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11);
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5);
94 if(Lock) cr11 |= 0x80;
95 else cr11 &= ~0x80;
96 VGA_WR08(chip->PCIO, 0x3D5, cr11);
97}
98static void nv3LockUnlock
99(
100 RIVA_HW_INST *chip,
101 int Lock
102)
103{
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06);
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
106 vgaLockUnlock(chip, Lock);
107}
108static void nv4LockUnlock
109(
110 RIVA_HW_INST *chip,
111 int Lock
112)
113{
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
116 vgaLockUnlock(chip, Lock);
117}
118
119static int ShowHideCursor
120(
121 RIVA_HW_INST *chip,
122 int ShowHide
123)
124{
125 int cursor;
126 cursor = chip->CurrentState->cursor1;
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
128 (ShowHide & 0x01);
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31);
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
131 return (cursor & 0x01);
132}
133
134/****************************************************************************\
135* *
136* The video arbitration routines calculate some "magic" numbers. Fixes *
137* the snow seen when accessing the framebuffer without it. *
138* It just works (I hope). *
139* *
140\****************************************************************************/
141
142#define DEFAULT_GR_LWM 100
143#define DEFAULT_VID_LWM 100
144#define DEFAULT_GR_BURST_SIZE 256
145#define DEFAULT_VID_BURST_SIZE 128
146#define VIDEO 0
147#define GRAPHICS 1
148#define MPORT 2
149#define ENGINE 3
150#define GFIFO_SIZE 320
151#define GFIFO_SIZE_128 256
152#define MFIFO_SIZE 120
153#define VFIFO_SIZE 256
154
155typedef struct {
156 int gdrain_rate;
157 int vdrain_rate;
158 int mdrain_rate;
159 int gburst_size;
160 int vburst_size;
161 char vid_en;
162 char gr_en;
163 int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
164 int by_gfacc;
165 char vid_only_once;
166 char gr_only_once;
167 char first_vacc;
168 char first_gacc;
169 char first_macc;
170 int vocc;
171 int gocc;
172 int mocc;
173 char cur;
174 char engine_en;
175 char converged;
176 int priority;
177} nv3_arb_info;
178typedef struct {
179 int graphics_lwm;
180 int video_lwm;
181 int graphics_burst_size;
182 int video_burst_size;
183 int graphics_hi_priority;
184 int media_hi_priority;
185 int rtl_values;
186 int valid;
187} nv3_fifo_info;
188typedef struct {
189 char pix_bpp;
190 char enable_video;
191 char gr_during_vid;
192 char enable_mp;
193 int memory_width;
194 int video_scale;
195 int pclk_khz;
196 int mclk_khz;
197 int mem_page_miss;
198 int mem_latency;
199 char mem_aligned;
200} nv3_sim_state;
201typedef struct {
202 int graphics_lwm;
203 int video_lwm;
204 int graphics_burst_size;
205 int video_burst_size;
206 int valid;
207} nv4_fifo_info;
208typedef struct {
209 int pclk_khz;
210 int mclk_khz;
211 int nvclk_khz;
212 char mem_page_miss;
213 char mem_latency;
214 int memory_width;
215 char enable_video;
216 char gr_during_vid;
217 char pix_bpp;
218 char mem_aligned;
219 char enable_mp;
220} nv4_sim_state;
221typedef struct {
222 int graphics_lwm;
223 int video_lwm;
224 int graphics_burst_size;
225 int video_burst_size;
226 int valid;
227} nv10_fifo_info;
228typedef struct {
229 int pclk_khz;
230 int mclk_khz;
231 int nvclk_khz;
232 char mem_page_miss;
233 char mem_latency;
234 u32 memory_type;
235 int memory_width;
236 char enable_video;
237 char gr_during_vid;
238 char pix_bpp;
239 char mem_aligned;
240 char enable_mp;
241} nv10_sim_state;
242static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
243{
244 int iter = 0;
245 int tmp;
246 int vfsize, mfsize, gfsize;
247 int mburst_size = 32;
248 int mmisses, gmisses, vmisses;
249 int misses;
250 int vlwm, glwm, mlwm;
251 int last, next, cur;
252 int max_gfsize ;
253 long ns;
254
255 vlwm = 0;
256 glwm = 0;
257 mlwm = 0;
258 vfsize = 0;
259 gfsize = 0;
260 cur = ainfo->cur;
261 mmisses = 2;
262 gmisses = 2;
263 vmisses = 2;
264 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
265 else max_gfsize = GFIFO_SIZE;
266 max_gfsize = GFIFO_SIZE;
267 while (1)
268 {
269 if (ainfo->vid_en)
270 {
271 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
272 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
273 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
274 vfsize = ns * ainfo->vdrain_rate / 1000000;
275 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize;
276 }
277 if (state->enable_mp)
278 {
279 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
280 }
281 if (ainfo->gr_en)
282 {
283 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
284 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
285 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
286 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;
287 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
288 }
289 mfsize = 0;
290 if (!state->gr_during_vid && ainfo->vid_en)
291 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
292 next = VIDEO;
293 else if (ainfo->mocc < 0)
294 next = MPORT;
295 else if (ainfo->gocc< ainfo->by_gfacc)
296 next = GRAPHICS;
297 else return (0);
298 else switch (ainfo->priority)
299 {
300 case VIDEO:
301 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
302 next = VIDEO;
303 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
304 next = GRAPHICS;
305 else if (ainfo->mocc<0)
306 next = MPORT;
307 else return (0);
308 break;
309 case GRAPHICS:
310 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
311 next = GRAPHICS;
312 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
313 next = VIDEO;
314 else if (ainfo->mocc<0)
315 next = MPORT;
316 else return (0);
317 break;
318 default:
319 if (ainfo->mocc<0)
320 next = MPORT;
321 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
322 next = GRAPHICS;
323 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
324 next = VIDEO;
325 else return (0);
326 break;
327 }
328 last = cur;
329 cur = next;
330 iter++;
331 switch (cur)
332 {
333 case VIDEO:
334 if (last==cur) misses = 0;
335 else if (ainfo->first_vacc) misses = vmisses;
336 else misses = 1;
337 ainfo->first_vacc = 0;
338 if (last!=cur)
339 {
340 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
341 vlwm = ns * ainfo->vdrain_rate/ 1000000;
342 vlwm = ainfo->vocc - vlwm;
343 }
344 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
345 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
346 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
347 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
348 break;
349 case GRAPHICS:
350 if (last==cur) misses = 0;
351 else if (ainfo->first_gacc) misses = gmisses;
352 else misses = 1;
353 ainfo->first_gacc = 0;
354 if (last!=cur)
355 {
356 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
357 glwm = ns * ainfo->gdrain_rate/1000000;
358 glwm = ainfo->gocc - glwm;
359 }
360 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
361 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
362 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
363 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
364 break;
365 default:
366 if (last==cur) misses = 0;
367 else if (ainfo->first_macc) misses = mmisses;
368 else misses = 1;
369 ainfo->first_macc = 0;
370 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
371 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
372 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
373 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
374 break;
375 }
376 if (iter>100)
377 {
378 ainfo->converged = 0;
379 return (1);
380 }
381 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
382 tmp = ns * ainfo->gdrain_rate/1000000;
383 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)
384 {
385 ainfo->converged = 0;
386 return (1);
387 }
388 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
389 tmp = ns * ainfo->vdrain_rate/1000000;
390 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE)
391 {
392 ainfo->converged = 0;
393 return (1);
394 }
395 if (abs(ainfo->gocc) > max_gfsize)
396 {
397 ainfo->converged = 0;
398 return (1);
399 }
400 if (abs(ainfo->vocc) > VFIFO_SIZE)
401 {
402 ainfo->converged = 0;
403 return (1);
404 }
405 if (abs(ainfo->mocc) > MFIFO_SIZE)
406 {
407 ainfo->converged = 0;
408 return (1);
409 }
410 if (abs(vfsize) > VFIFO_SIZE)
411 {
412 ainfo->converged = 0;
413 return (1);
414 }
415 if (abs(gfsize) > max_gfsize)
416 {
417 ainfo->converged = 0;
418 return (1);
419 }
420 if (abs(mfsize) > MFIFO_SIZE)
421 {
422 ainfo->converged = 0;
423 return (1);
424 }
425 }
426}
427static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
428{
429 long ens, vns, mns, gns;
430 int mmisses, gmisses, vmisses, eburst_size, mburst_size;
431 int refresh_cycle;
432
433 refresh_cycle = 0;
434 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
435 mmisses = 2;
436 if (state->mem_aligned) gmisses = 2;
437 else gmisses = 3;
438 vmisses = 2;
439 eburst_size = state->memory_width * 1;
440 mburst_size = 32;
441 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
442 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
443 ainfo->wcmocc = 0;
444 ainfo->wcgocc = 0;
445 ainfo->wcvocc = 0;
446 ainfo->wcvlwm = 0;
447 ainfo->wcglwm = 0;
448 ainfo->engine_en = 1;
449 ainfo->converged = 1;
450 if (ainfo->engine_en)
451 {
452 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
453 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
454 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
455 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
456 ainfo->cur = ENGINE;
457 ainfo->first_vacc = 1;
458 ainfo->first_gacc = 1;
459 ainfo->first_macc = 1;
460 nv3_iterate(res_info, state,ainfo);
461 }
462 if (state->enable_mp)
463 {
464 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
465 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
466 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
467 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
468 ainfo->cur = MPORT;
469 ainfo->first_vacc = 1;
470 ainfo->first_gacc = 1;
471 ainfo->first_macc = 0;
472 nv3_iterate(res_info, state,ainfo);
473 }
474 if (ainfo->gr_en)
475 {
476 ainfo->first_vacc = 1;
477 ainfo->first_gacc = 0;
478 ainfo->first_macc = 1;
479 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
480 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
481 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
482 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;
483 ainfo->cur = GRAPHICS;
484 nv3_iterate(res_info, state,ainfo);
485 }
486 if (ainfo->vid_en)
487 {
488 ainfo->first_vacc = 0;
489 ainfo->first_gacc = 1;
490 ainfo->first_macc = 1;
491 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
492 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
493 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
494 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
495 ainfo->cur = VIDEO;
496 nv3_iterate(res_info, state, ainfo);
497 }
498 if (ainfo->converged)
499 {
500 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16;
501 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32;
502 res_info->graphics_burst_size = ainfo->gburst_size;
503 res_info->video_burst_size = ainfo->vburst_size;
504 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
505 res_info->media_hi_priority = (ainfo->priority == MPORT);
506 if (res_info->video_lwm > 160)
507 {
508 res_info->graphics_lwm = 256;
509 res_info->video_lwm = 128;
510 res_info->graphics_burst_size = 64;
511 res_info->video_burst_size = 64;
512 res_info->graphics_hi_priority = 0;
513 res_info->media_hi_priority = 0;
514 ainfo->converged = 0;
515 return (0);
516 }
517 if (res_info->video_lwm > 128)
518 {
519 res_info->video_lwm = 128;
520 }
521 return (1);
522 }
523 else
524 {
525 res_info->graphics_lwm = 256;
526 res_info->video_lwm = 128;
527 res_info->graphics_burst_size = 64;
528 res_info->video_burst_size = 64;
529 res_info->graphics_hi_priority = 0;
530 res_info->media_hi_priority = 0;
531 return (0);
532 }
533}
534static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
535{
536 int done, g,v, p;
537
538 done = 0;
539 for (p=0; p < 2; p++)
540 {
541 for (g=128 ; g > 32; g= g>> 1)
542 {
543 for (v=128; v >=32; v = v>> 1)
544 {
545 ainfo->priority = p;
546 ainfo->gburst_size = g;
547 ainfo->vburst_size = v;
548 done = nv3_arb(res_info, state,ainfo);
549 if (done && (g==128))
550 if ((res_info->graphics_lwm + g) > 256)
551 done = 0;
552 if (done)
553 goto Done;
554 }
555 }
556 }
557
558 Done:
559 return done;
560}
561static void nv3CalcArbitration
562(
563 nv3_fifo_info * res_info,
564 nv3_sim_state * state
565)
566{
567 nv3_fifo_info save_info;
568 nv3_arb_info ainfo;
569 char res_gr, res_vid;
570
571 ainfo.gr_en = 1;
572 ainfo.vid_en = state->enable_video;
573 ainfo.vid_only_once = 0;
574 ainfo.gr_only_once = 0;
575 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
576 ainfo.vdrain_rate = (int) state->pclk_khz * 2;
577 if (state->video_scale != 0)
578 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
579 ainfo.mdrain_rate = 33000;
580 res_info->rtl_values = 0;
581 if (!state->gr_during_vid && state->enable_video)
582 {
583 ainfo.gr_only_once = 1;
584 ainfo.gr_en = 1;
585 ainfo.gdrain_rate = 0;
586 res_vid = nv3_get_param(res_info, state, &ainfo);
587 res_vid = ainfo.converged;
588 save_info.video_lwm = res_info->video_lwm;
589 save_info.video_burst_size = res_info->video_burst_size;
590 ainfo.vid_en = 1;
591 ainfo.vid_only_once = 1;
592 ainfo.gr_en = 1;
593 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
594 ainfo.vdrain_rate = 0;
595 res_gr = nv3_get_param(res_info, state, &ainfo);
596 res_gr = ainfo.converged;
597 res_info->video_lwm = save_info.video_lwm;
598 res_info->video_burst_size = save_info.video_burst_size;
599 res_info->valid = res_gr & res_vid;
600 }
601 else
602 {
603 if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
604 if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
605 res_gr = nv3_get_param(res_info, state, &ainfo);
606 res_info->valid = ainfo.converged;
607 }
608}
609static void nv3UpdateArbitrationSettings
610(
611 unsigned VClk,
612 unsigned pixelDepth,
613 unsigned *burst,
614 unsigned *lwm,
615 RIVA_HW_INST *chip
616)
617{
618 nv3_fifo_info fifo_data;
619 nv3_sim_state sim_data;
620 unsigned int M, N, P, pll, MClk;
621
622 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
623 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
624 MClk = (N * chip->CrystalFreqKHz / M) >> P;
625 sim_data.pix_bpp = (char)pixelDepth;
626 sim_data.enable_video = 0;
627 sim_data.enable_mp = 0;
628 sim_data.video_scale = 1;
629 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
630 128 : 64;
631 sim_data.memory_width = 128;
632
633 sim_data.mem_latency = 9;
634 sim_data.mem_aligned = 1;
635 sim_data.mem_page_miss = 11;
636 sim_data.gr_during_vid = 0;
637 sim_data.pclk_khz = VClk;
638 sim_data.mclk_khz = MClk;
639 nv3CalcArbitration(&fifo_data, &sim_data);
640 if (fifo_data.valid)
641 {
642 int b = fifo_data.graphics_burst_size >> 4;
643 *burst = 0;
644 while (b >>= 1)
645 (*burst)++;
646 *lwm = fifo_data.graphics_lwm >> 3;
647 }
648 else
649 {
650 *lwm = 0x24;
651 *burst = 0x2;
652 }
653}
654static void nv4CalcArbitration
655(
656 nv4_fifo_info *fifo,
657 nv4_sim_state *arb
658)
659{
660 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
661 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
662 int found, mclk_extra, mclk_loop, cbs, m1, p1;
663 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
664 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
665 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
666 int craw, vraw;
667
668 fifo->valid = 1;
669 pclk_freq = arb->pclk_khz;
670 mclk_freq = arb->mclk_khz;
671 nvclk_freq = arb->nvclk_khz;
672 pagemiss = arb->mem_page_miss;
673 cas = arb->mem_latency;
674 width = arb->memory_width >> 6;
675 video_enable = arb->enable_video;
676 color_key_enable = arb->gr_during_vid;
677 bpp = arb->pix_bpp;
678 align = arb->mem_aligned;
679 mp_enable = arb->enable_mp;
680 clwm = 0;
681 vlwm = 0;
682 cbs = 128;
683 pclks = 2;
684 nvclks = 2;
685 nvclks += 2;
686 nvclks += 1;
687 mclks = 5;
688 mclks += 3;
689 mclks += 1;
690 mclks += cas;
691 mclks += 1;
692 mclks += 1;
693 mclks += 1;
694 mclks += 1;
695 mclk_extra = 3;
696 nvclks += 2;
697 nvclks += 1;
698 nvclks += 1;
699 nvclks += 1;
700 if (mp_enable)
701 mclks+=4;
702 nvclks += 0;
703 pclks += 0;
704 found = 0;
705 vbs = 0;
706 while (found != 1)
707 {
708 fifo->valid = 1;
709 found = 1;
710 mclk_loop = mclks+mclk_extra;
711 us_m = mclk_loop *1000*1000 / mclk_freq;
712 us_n = nvclks*1000*1000 / nvclk_freq;
713 us_p = nvclks*1000*1000 / pclk_freq;
714 if (video_enable)
715 {
716 video_drain_rate = pclk_freq * 2;
717 crtc_drain_rate = pclk_freq * bpp/8;
718 vpagemiss = 2;
719 vpagemiss += 1;
720 crtpagemiss = 2;
721 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
722 if (nvclk_freq * 2 > mclk_freq * width)
723 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
724 else
725 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
726 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
727 vlwm = us_video * video_drain_rate/(1000*1000);
728 vlwm++;
729 vbs = 128;
730 if (vlwm > 128) vbs = 64;
731 if (vlwm > (256-64)) vbs = 32;
732 if (nvclk_freq * 2 > mclk_freq * width)
733 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
734 else
735 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
736 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
737 us_crt =
738 us_video
739 +video_fill_us
740 +cpm_us
741 +us_m + us_n +us_p
742 ;
743 clwm = us_crt * crtc_drain_rate/(1000*1000);
744 clwm++;
745 }
746 else
747 {
748 crtc_drain_rate = pclk_freq * bpp/8;
749 crtpagemiss = 2;
750 crtpagemiss += 1;
751 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
752 us_crt = cpm_us + us_m + us_n + us_p ;
753 clwm = us_crt * crtc_drain_rate/(1000*1000);
754 clwm++;
755 }
756 m1 = clwm + cbs - 512;
757 p1 = m1 * pclk_freq / mclk_freq;
758 p1 = p1 * bpp / 8;
759 if ((p1 < m1) && (m1 > 0))
760 {
761 fifo->valid = 0;
762 found = 0;
763 if (mclk_extra ==0) found = 1;
764 mclk_extra--;
765 }
766 else if (video_enable)
767 {
768 if ((clwm > 511) || (vlwm > 255))
769 {
770 fifo->valid = 0;
771 found = 0;
772 if (mclk_extra ==0) found = 1;
773 mclk_extra--;
774 }
775 }
776 else
777 {
778 if (clwm > 519)
779 {
780 fifo->valid = 0;
781 found = 0;
782 if (mclk_extra ==0) found = 1;
783 mclk_extra--;
784 }
785 }
786 craw = clwm;
787 vraw = vlwm;
788 if (clwm < 384) clwm = 384;
789 if (vlwm < 128) vlwm = 128;
790 data = (int)(clwm);
791 fifo->graphics_lwm = data;
792 fifo->graphics_burst_size = 128;
793 data = (int)((vlwm+15));
794 fifo->video_lwm = data;
795 fifo->video_burst_size = vbs;
796 }
797}
798static void nv4UpdateArbitrationSettings
799(
800 unsigned VClk,
801 unsigned pixelDepth,
802 unsigned *burst,
803 unsigned *lwm,
804 RIVA_HW_INST *chip
805)
806{
807 nv4_fifo_info fifo_data;
808 nv4_sim_state sim_data;
809 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
810
811 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
812 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
813 MClk = (N * chip->CrystalFreqKHz / M) >> P;
814 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
815 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
816 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
817 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
818 sim_data.pix_bpp = (char)pixelDepth;
819 sim_data.enable_video = 0;
820 sim_data.enable_mp = 0;
821 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
822 128 : 64;
823 sim_data.mem_latency = (char)cfg1 & 0x0F;
824 sim_data.mem_aligned = 1;
825 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
826 sim_data.gr_during_vid = 0;
827 sim_data.pclk_khz = VClk;
828 sim_data.mclk_khz = MClk;
829 sim_data.nvclk_khz = NVClk;
830 nv4CalcArbitration(&fifo_data, &sim_data);
831 if (fifo_data.valid)
832 {
833 int b = fifo_data.graphics_burst_size >> 4;
834 *burst = 0;
835 while (b >>= 1)
836 (*burst)++;
837 *lwm = fifo_data.graphics_lwm >> 3;
838 }
839}
840static void nv10CalcArbitration
841(
842 nv10_fifo_info *fifo,
843 nv10_sim_state *arb
844)
845{
846 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
847 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
848 int nvclk_fill, us_extra;
849 int found, mclk_extra, mclk_loop, cbs, m1;
850 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
851 int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate;
852 int vus_m, vus_n, vus_p;
853 int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm;
854 int clwm_rnd_down;
855 int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2;
856 int pclks_2_top_fifo, min_mclk_extra;
857 int us_min_mclk_extra;
858
859 fifo->valid = 1;
860 pclk_freq = arb->pclk_khz; /* freq in KHz */
861 mclk_freq = arb->mclk_khz;
862 nvclk_freq = arb->nvclk_khz;
863 pagemiss = arb->mem_page_miss;
864 cas = arb->mem_latency;
865 width = arb->memory_width/64;
866 video_enable = arb->enable_video;
867 color_key_enable = arb->gr_during_vid;
868 bpp = arb->pix_bpp;
869 align = arb->mem_aligned;
870 mp_enable = arb->enable_mp;
871 clwm = 0;
872 vlwm = 1024;
873
874 cbs = 512;
875 vbs = 512;
876
877 pclks = 4; /* lwm detect. */
878
879 nvclks = 3; /* lwm -> sync. */
880 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
881
882 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
883
884 mclks += 1; /* arb_hp_req */
885 mclks += 5; /* ap_hp_req tiling pipeline */
886
887 mclks += 2; /* tc_req latency fifo */
888 mclks += 2; /* fb_cas_n_ memory request to fbio block */
889 mclks += 7; /* sm_d_rdv data returned from fbio block */
890
891 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
892 if (arb->memory_type == 0)
893 if (arb->memory_width == 64) /* 64 bit bus */
894 mclks += 4;
895 else
896 mclks += 2;
897 else
898 if (arb->memory_width == 64) /* 64 bit bus */
899 mclks += 2;
900 else
901 mclks += 1;
902
903 if ((!video_enable) && (arb->memory_width == 128))
904 {
905 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
906 min_mclk_extra = 17;
907 }
908 else
909 {
910 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
911 /* mclk_extra = 4; */ /* Margin of error */
912 min_mclk_extra = 18;
913 }
914
915 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
916 nvclks += 1; /* fbi_d_rdv_n */
917 nvclks += 1; /* Fbi_d_rdata */
918 nvclks += 1; /* crtfifo load */
919
920 if(mp_enable)
921 mclks+=4; /* Mp can get in with a burst of 8. */
922 /* Extra clocks determined by heuristics */
923
924 nvclks += 0;
925 pclks += 0;
926 found = 0;
927 while(found != 1) {
928 fifo->valid = 1;
929 found = 1;
930 mclk_loop = mclks+mclk_extra;
931 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
932 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
933 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
934 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
935 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
936 us_pipe = us_m + us_n + us_p;
937 us_pipe_min = us_m_min + us_n + us_p;
938 us_extra = 0;
939
940 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
941 vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */
942 vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */
943 vus_pipe = vus_m + vus_n + vus_p;
944
945 if(video_enable) {
946 video_drain_rate = pclk_freq * 4; /* MB/s */
947 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
948
949 vpagemiss = 1; /* self generating page miss */
950 vpagemiss += 1; /* One higher priority before */
951
952 crtpagemiss = 2; /* self generating page miss */
953 if(mp_enable)
954 crtpagemiss += 1; /* if MA0 conflict */
955
956 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
957
958 us_video = vpm_us + vus_m; /* Video has separate read return path */
959
960 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
961 us_crt =
962 us_video /* Wait for video */
963 +cpm_us /* CRT Page miss */
964 +us_m + us_n +us_p /* other latency */
965 ;
966
967 clwm = us_crt * crtc_drain_rate/(1000*1000);
968 clwm++; /* fixed point <= float_point - 1. Fixes that */
969 } else {
970 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
971
972 crtpagemiss = 1; /* self generating page miss */
973 crtpagemiss += 1; /* MA0 page miss */
974 if(mp_enable)
975 crtpagemiss += 1; /* if MA0 conflict */
976 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
977 us_crt = cpm_us + us_m + us_n + us_p ;
978 clwm = us_crt * crtc_drain_rate/(1000*1000);
979 clwm++; /* fixed point <= float_point - 1. Fixes that */
980
981 /*
982 //
983 // Another concern, only for high pclks so don't do this
984 // with video:
985 // What happens if the latency to fetch the cbs is so large that
986 // fifo empties. In that case we need to have an alternate clwm value
987 // based off the total burst fetch
988 //
989 us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
990 us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq;
991 clwm_mt = us_crt * crtc_drain_rate/(1000*1000);
992 clwm_mt ++;
993 if(clwm_mt > clwm)
994 clwm = clwm_mt;
995 */
996 /* Finally, a heuristic check when width == 64 bits */
997 if(width == 1){
998 nvclk_fill = nvclk_freq * 8;
999 if(crtc_drain_rate * 100 >= nvclk_fill * 102)
1000 clwm = 0xfff; /*Large number to fail */
1001
1002 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
1003 clwm = 1024;
1004 cbs = 512;
1005 us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
1006 }
1007 }
1008 }
1009
1010
1011 /*
1012 Overfill check:
1013
1014 */
1015
1016 clwm_rnd_down = ((int)clwm/8)*8;
1017 if (clwm_rnd_down < clwm)
1018 clwm += 8;
1019
1020 m1 = clwm + cbs - 1024; /* Amount of overfill */
1021 m2us = us_pipe_min + us_min_mclk_extra;
1022 pclks_2_top_fifo = (1024-clwm)/(8*width);
1023
1024 /* pclk cycles to drain */
1025 p1clk = m2us * pclk_freq/(1000*1000);
1026 p2 = p1clk * bpp / 8; /* bytes drained. */
1027
1028 if((p2 < m1) && (m1 > 0)) {
1029 fifo->valid = 0;
1030 found = 0;
1031 if(min_mclk_extra == 0) {
1032 if(cbs <= 32) {
1033 found = 1; /* Can't adjust anymore! */
1034 } else {
1035 cbs = cbs/2; /* reduce the burst size */
1036 }
1037 } else {
1038 min_mclk_extra--;
1039 }
1040 } else {
1041 if (clwm > 1023){ /* Have some margin */
1042 fifo->valid = 0;
1043 found = 0;
1044 if(min_mclk_extra == 0)
1045 found = 1; /* Can't adjust anymore! */
1046 else
1047 min_mclk_extra--;
1048 }
1049 }
1050 craw = clwm;
1051
1052 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
1053 data = (int)(clwm);
1054 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
1055 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
1056
1057 /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */
1058 fifo->video_lwm = 1024; fifo->video_burst_size = 512;
1059 }
1060}
1061static void nv10UpdateArbitrationSettings
1062(
1063 unsigned VClk,
1064 unsigned pixelDepth,
1065 unsigned *burst,
1066 unsigned *lwm,
1067 RIVA_HW_INST *chip
1068)
1069{
1070 nv10_fifo_info fifo_data;
1071 nv10_sim_state sim_data;
1072 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
1073
1074 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
1075 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1076 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1077 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1078 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1079 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1080 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
1081 sim_data.pix_bpp = (char)pixelDepth;
1082 sim_data.enable_video = 0;
1083 sim_data.enable_mp = 0;
1084 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ?
1085 1 : 0;
1086 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1087 128 : 64;
1088 sim_data.mem_latency = (char)cfg1 & 0x0F;
1089 sim_data.mem_aligned = 1;
1090 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
1091 sim_data.gr_during_vid = 0;
1092 sim_data.pclk_khz = VClk;
1093 sim_data.mclk_khz = MClk;
1094 sim_data.nvclk_khz = NVClk;
1095 nv10CalcArbitration(&fifo_data, &sim_data);
1096 if (fifo_data.valid)
1097 {
1098 int b = fifo_data.graphics_burst_size >> 4;
1099 *burst = 0;
1100 while (b >>= 1)
1101 (*burst)++;
1102 *lwm = fifo_data.graphics_lwm >> 3;
1103 }
1104}
1105
1106static void nForceUpdateArbitrationSettings
1107(
1108 unsigned VClk,
1109 unsigned pixelDepth,
1110 unsigned *burst,
1111 unsigned *lwm,
1112 RIVA_HW_INST *chip
1113)
1114{
1115 nv10_fifo_info fifo_data;
1116 nv10_sim_state sim_data;
1117 unsigned int M, N, P, pll, MClk, NVClk;
1118 unsigned int uMClkPostDiv;
1119 struct pci_dev *dev;
1120
1121 dev = pci_get_bus_and_slot(0, 3);
1122 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
1123 pci_dev_put(dev);
1124 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
1125
1126 if(!uMClkPostDiv) uMClkPostDiv = 4;
1127 MClk = 400000 / uMClkPostDiv;
1128
1129 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1130 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1131 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1132 sim_data.pix_bpp = (char)pixelDepth;
1133 sim_data.enable_video = 0;
1134 sim_data.enable_mp = 0;
1135
1136 dev = pci_get_bus_and_slot(0, 1);
1137 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
1138 pci_dev_put(dev);
1139 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
1140
1141 sim_data.memory_width = 64;
1142 sim_data.mem_latency = 3;
1143 sim_data.mem_aligned = 1;
1144 sim_data.mem_page_miss = 10;
1145 sim_data.gr_during_vid = 0;
1146 sim_data.pclk_khz = VClk;
1147 sim_data.mclk_khz = MClk;
1148 sim_data.nvclk_khz = NVClk;
1149 nv10CalcArbitration(&fifo_data, &sim_data);
1150 if (fifo_data.valid)
1151 {
1152 int b = fifo_data.graphics_burst_size >> 4;
1153 *burst = 0;
1154 while (b >>= 1)
1155 (*burst)++;
1156 *lwm = fifo_data.graphics_lwm >> 3;
1157 }
1158}
1159
1160/****************************************************************************\
1161* *
1162* RIVA Mode State Routines *
1163* *
1164\****************************************************************************/
1165
1166/*
1167 * Calculate the Video Clock parameters for the PLL.
1168 */
1169static int CalcVClock
1170(
1171 int clockIn,
1172 int *clockOut,
1173 int *mOut,
1174 int *nOut,
1175 int *pOut,
1176 RIVA_HW_INST *chip
1177)
1178{
1179 unsigned lowM, highM, highP;
1180 unsigned DeltaNew, DeltaOld;
1181 unsigned VClk, Freq;
1182 unsigned M, N, P;
1183
1184 DeltaOld = 0xFFFFFFFF;
1185
1186 VClk = (unsigned)clockIn;
1187
1188 if (chip->CrystalFreqKHz == 13500)
1189 {
1190 lowM = 7;
1191 highM = 13 - (chip->Architecture == NV_ARCH_03);
1192 }
1193 else
1194 {
1195 lowM = 8;
1196 highM = 14 - (chip->Architecture == NV_ARCH_03);
1197 }
1198
1199 highP = 4 - (chip->Architecture == NV_ARCH_03);
1200 for (P = 0; P <= highP; P ++)
1201 {
1202 Freq = VClk << P;
1203 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
1204 {
1205 for (M = lowM; M <= highM; M++)
1206 {
1207 N = (VClk << P) * M / chip->CrystalFreqKHz;
1208 if(N <= 255) {
1209 Freq = (chip->CrystalFreqKHz * N / M) >> P;
1210 if (Freq > VClk)
1211 DeltaNew = Freq - VClk;
1212 else
1213 DeltaNew = VClk - Freq;
1214 if (DeltaNew < DeltaOld)
1215 {
1216 *mOut = M;
1217 *nOut = N;
1218 *pOut = P;
1219 *clockOut = Freq;
1220 DeltaOld = DeltaNew;
1221 }
1222 }
1223 }
1224 }
1225 }
1226
1227 /* non-zero: M/N/P/clock values assigned. zero: error (not set) */
1228 return (DeltaOld != 0xFFFFFFFF);
1229}
1230/*
1231 * Calculate extended mode parameters (SVGA) and save in a
1232 * mode state structure.
1233 */
1234int CalcStateExt
1235(
1236 RIVA_HW_INST *chip,
1237 RIVA_HW_STATE *state,
1238 int bpp,
1239 int width,
1240 int hDisplaySize,
1241 int height,
1242 int dotClock
1243)
1244{
1245 int pixelDepth;
1246 int uninitialized_var(VClk),uninitialized_var(m),
1247 uninitialized_var(n), uninitialized_var(p);
1248
1249 /*
1250 * Save mode parameters.
1251 */
1252 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
1253 state->width = width;
1254 state->height = height;
1255 /*
1256 * Extended RIVA registers.
1257 */
1258 pixelDepth = (bpp + 1)/8;
1259 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip))
1260 return -EINVAL;
1261
1262 switch (chip->Architecture)
1263 {
1264 case NV_ARCH_03:
1265 nv3UpdateArbitrationSettings(VClk,
1266 pixelDepth * 8,
1267 &(state->arbitration0),
1268 &(state->arbitration1),
1269 chip);
1270 state->cursor0 = 0x00;
1271 state->cursor1 = 0x78;
1272 state->cursor2 = 0x00000000;
1273 state->pllsel = 0x10010100;
1274 state->config = ((width + 31)/32)
1275 | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
1276 | 0x1000;
1277 state->general = 0x00100100;
1278 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
1279 break;
1280 case NV_ARCH_04:
1281 nv4UpdateArbitrationSettings(VClk,
1282 pixelDepth * 8,
1283 &(state->arbitration0),
1284 &(state->arbitration1),
1285 chip);
1286 state->cursor0 = 0x00;
1287 state->cursor1 = 0xFC;
1288 state->cursor2 = 0x00000000;
1289 state->pllsel = 0x10000700;
1290 state->config = 0x00001114;
1291 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1292 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1293 break;
1294 case NV_ARCH_10:
1295 case NV_ARCH_20:
1296 case NV_ARCH_30:
1297 if((chip->Chipset == NV_CHIP_IGEFORCE2) ||
1298 (chip->Chipset == NV_CHIP_0x01F0))
1299 {
1300 nForceUpdateArbitrationSettings(VClk,
1301 pixelDepth * 8,
1302 &(state->arbitration0),
1303 &(state->arbitration1),
1304 chip);
1305 } else {
1306 nv10UpdateArbitrationSettings(VClk,
1307 pixelDepth * 8,
1308 &(state->arbitration0),
1309 &(state->arbitration1),
1310 chip);
1311 }
1312 state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1313 state->cursor1 = (chip->CursorStart >> 11) << 2;
1314 state->cursor2 = chip->CursorStart >> 24;
1315 state->pllsel = 0x10000700;
1316 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0);
1317 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1318 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1319 break;
1320 }
1321
1322 /* Paul Richards: below if block borks things in kernel for some reason */
1323 /* Tony: Below is needed to set hardware in DirectColor */
1324 if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
1325 state->general |= 0x00000030;
1326
1327 state->vpll = (p << 16) | (n << 8) | m;
1328 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
1329 state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
1330 state->offset0 =
1331 state->offset1 =
1332 state->offset2 =
1333 state->offset3 = 0;
1334 state->pitch0 =
1335 state->pitch1 =
1336 state->pitch2 =
1337 state->pitch3 = pixelDepth * width;
1338
1339 return 0;
1340}
1341/*
1342 * Load fixed function state and pre-calculated/stored state.
1343 */
1344#if 0
1345#define LOAD_FIXED_STATE(tbl,dev) \
1346 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1347 chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
1348#define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1349 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1350 chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
1351#define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1352 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1353 chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
1354#define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1355 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1356 chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
1357#define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1358 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1359 chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
1360#endif
1361
1362#define LOAD_FIXED_STATE(tbl,dev) \
1363 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1364 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1365#define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1366 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1367 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1368#define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1369 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1370 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1371#define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1372 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1373 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1374#define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1375 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1376 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1377
1378static void UpdateFifoState
1379(
1380 RIVA_HW_INST *chip
1381)
1382{
1383 int i;
1384
1385 switch (chip->Architecture)
1386 {
1387 case NV_ARCH_04:
1388 LOAD_FIXED_STATE(nv4,FIFO);
1389 chip->Tri03 = NULL;
1390 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1391 break;
1392 case NV_ARCH_10:
1393 case NV_ARCH_20:
1394 case NV_ARCH_30:
1395 /*
1396 * Initialize state for the RivaTriangle3D05 routines.
1397 */
1398 LOAD_FIXED_STATE(nv10tri05,PGRAPH);
1399 LOAD_FIXED_STATE(nv10,FIFO);
1400 chip->Tri03 = NULL;
1401 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1402 break;
1403 }
1404}
1405static void LoadStateExt
1406(
1407 RIVA_HW_INST *chip,
1408 RIVA_HW_STATE *state
1409)
1410{
1411 int i;
1412
1413 /*
1414 * Load HW fixed function state.
1415 */
1416 LOAD_FIXED_STATE(Riva,PMC);
1417 LOAD_FIXED_STATE(Riva,PTIMER);
1418 switch (chip->Architecture)
1419 {
1420 case NV_ARCH_03:
1421 /*
1422 * Make sure frame buffer config gets set before loading PRAMIN.
1423 */
1424 NV_WR32(chip->PFB, 0x00000200, state->config);
1425 LOAD_FIXED_STATE(nv3,PFIFO);
1426 LOAD_FIXED_STATE(nv3,PRAMIN);
1427 LOAD_FIXED_STATE(nv3,PGRAPH);
1428 switch (state->bpp)
1429 {
1430 case 15:
1431 case 16:
1432 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
1433 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
1434 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1435 break;
1436 case 24:
1437 case 32:
1438 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
1439 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
1440 chip->Tri03 = NULL;
1441 break;
1442 case 8:
1443 default:
1444 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
1445 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
1446 chip->Tri03 = NULL;
1447 break;
1448 }
1449 for (i = 0x00000; i < 0x00800; i++)
1450 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03);
1451 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);
1452 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);
1453 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);
1454 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);
1455 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);
1456 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);
1457 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);
1458 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);
1459 break;
1460 case NV_ARCH_04:
1461 /*
1462 * Make sure frame buffer config gets set before loading PRAMIN.
1463 */
1464 NV_WR32(chip->PFB, 0x00000200, state->config);
1465 LOAD_FIXED_STATE(nv4,PFIFO);
1466 LOAD_FIXED_STATE(nv4,PRAMIN);
1467 LOAD_FIXED_STATE(nv4,PGRAPH);
1468 switch (state->bpp)
1469 {
1470 case 15:
1471 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
1472 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
1473 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1474 break;
1475 case 16:
1476 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
1477 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
1478 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1479 break;
1480 case 24:
1481 case 32:
1482 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
1483 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
1484 chip->Tri03 = NULL;
1485 break;
1486 case 8:
1487 default:
1488 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
1489 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
1490 chip->Tri03 = NULL;
1491 break;
1492 }
1493 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1494 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1495 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1496 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1497 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1498 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1499 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1500 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1501 break;
1502 case NV_ARCH_10:
1503 case NV_ARCH_20:
1504 case NV_ARCH_30:
1505 if(chip->twoHeads) {
1506 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1507 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1508 chip->LockUnlock(chip, 0);
1509 }
1510
1511 LOAD_FIXED_STATE(nv10,PFIFO);
1512 LOAD_FIXED_STATE(nv10,PRAMIN);
1513 LOAD_FIXED_STATE(nv10,PGRAPH);
1514 switch (state->bpp)
1515 {
1516 case 15:
1517 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
1518 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
1519 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1520 break;
1521 case 16:
1522 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
1523 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
1524 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1525 break;
1526 case 24:
1527 case 32:
1528 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
1529 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
1530 chip->Tri03 = NULL;
1531 break;
1532 case 8:
1533 default:
1534 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
1535 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
1536 chip->Tri03 = NULL;
1537 break;
1538 }
1539
1540 if(chip->Architecture == NV_ARCH_10) {
1541 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1542 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1543 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1544 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1545 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1546 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1547 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1548 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1549 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);
1550 } else {
1551 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);
1552 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);
1553 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);
1554 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);
1555 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);
1556 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);
1557 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);
1558 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);
1559 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);
1560 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);
1561 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200));
1562 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204));
1563 }
1564 if(chip->twoHeads) {
1565 NV_WR32(chip->PCRTC0, 0x00000860, state->head);
1566 NV_WR32(chip->PCRTC0, 0x00002860, state->head2);
1567 }
1568 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25));
1569
1570 NV_WR32(chip->PMC, 0x00008704, 1);
1571 NV_WR32(chip->PMC, 0x00008140, 0);
1572 NV_WR32(chip->PMC, 0x00008920, 0);
1573 NV_WR32(chip->PMC, 0x00008924, 0);
1574 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);
1575 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);
1576 NV_WR32(chip->PMC, 0x00001588, 0);
1577
1578 NV_WR32(chip->PFB, 0x00000240, 0);
1579 NV_WR32(chip->PFB, 0x00000250, 0);
1580 NV_WR32(chip->PFB, 0x00000260, 0);
1581 NV_WR32(chip->PFB, 0x00000270, 0);
1582 NV_WR32(chip->PFB, 0x00000280, 0);
1583 NV_WR32(chip->PFB, 0x00000290, 0);
1584 NV_WR32(chip->PFB, 0x000002A0, 0);
1585 NV_WR32(chip->PFB, 0x000002B0, 0);
1586
1587 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240));
1588 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244));
1589 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248));
1590 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C));
1591 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250));
1592 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254));
1593 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258));
1594 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C));
1595 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260));
1596 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264));
1597 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268));
1598 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C));
1599 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270));
1600 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274));
1601 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278));
1602 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C));
1603 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280));
1604 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284));
1605 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288));
1606 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C));
1607 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290));
1608 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294));
1609 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298));
1610 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C));
1611 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0));
1612 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4));
1613 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8));
1614 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC));
1615 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0));
1616 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4));
1617 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8));
1618 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC));
1619 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000);
1620 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000);
1621 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1622 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008);
1623 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200);
1624 for (i = 0; i < (3*16); i++)
1625 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1626 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1627 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1628 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800);
1629 for (i = 0; i < (16*16); i++)
1630 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1631 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000);
1632 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004);
1633 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400);
1634 for (i = 0; i < (59*4); i++)
1635 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1636 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800);
1637 for (i = 0; i < (47*4); i++)
1638 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1639 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00);
1640 for (i = 0; i < (3*4); i++)
1641 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1642 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000);
1643 for (i = 0; i < (19*4); i++)
1644 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1645 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400);
1646 for (i = 0; i < (12*4); i++)
1647 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1648 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800);
1649 for (i = 0; i < (12*4); i++)
1650 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1651 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400);
1652 for (i = 0; i < (8*4); i++)
1653 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1654 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000);
1655 for (i = 0; i < 16; i++)
1656 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1657 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1658 for (i = 0; i < 4; i++)
1659 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1660
1661 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);
1662
1663 if(chip->flatPanel) {
1664 if((chip->Chipset & 0x0ff0) == 0x0110) {
1665 NV_WR32(chip->PRAMDAC, 0x0528, state->dither);
1666 } else
1667 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1668 NV_WR32(chip->PRAMDAC, 0x083C, state->dither);
1669 }
1670
1671 VGA_WR08(chip->PCIO, 0x03D4, 0x53);
1672 VGA_WR08(chip->PCIO, 0x03D5, 0);
1673 VGA_WR08(chip->PCIO, 0x03D4, 0x54);
1674 VGA_WR08(chip->PCIO, 0x03D5, 0);
1675 VGA_WR08(chip->PCIO, 0x03D4, 0x21);
1676 VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
1677 }
1678
1679 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1680 VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1681 }
1682 LOAD_FIXED_STATE(Riva,FIFO);
1683 UpdateFifoState(chip);
1684 /*
1685 * Load HW mode state.
1686 */
1687 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1688 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1689 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1690 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
1691 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1692 VGA_WR08(chip->PCIO, 0x03D5, state->screen);
1693 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1694 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
1695 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1696 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
1697 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1698 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
1699 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1700 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
1701 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1702 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1703 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1704 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1705 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1706 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1707 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1708 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1709
1710 if(!chip->flatPanel) {
1711 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
1712 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);
1713 if(chip->twoHeads)
1714 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);
1715 } else {
1716 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);
1717 }
1718 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);
1719
1720 /*
1721 * Turn off VBlank enable and reset.
1722 */
1723 NV_WR32(chip->PCRTC, 0x00000140, 0);
1724 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit);
1725 /*
1726 * Set interrupt enable.
1727 */
1728 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);
1729 /*
1730 * Set current state pointer.
1731 */
1732 chip->CurrentState = state;
1733 /*
1734 * Reset FIFO free and empty counts.
1735 */
1736 chip->FifoFreeCount = 0;
1737 /* Free count from first subchannel */
1738 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0);
1739}
1740static void UnloadStateExt
1741(
1742 RIVA_HW_INST *chip,
1743 RIVA_HW_STATE *state
1744)
1745{
1746 /*
1747 * Save current HW state.
1748 */
1749 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1750 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
1751 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1752 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
1753 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1754 state->screen = VGA_RD08(chip->PCIO, 0x03D5);
1755 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1756 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
1757 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1758 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
1759 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1760 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
1761 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1762 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
1763 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1764 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1765 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1766 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1767 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1768 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1769 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1770 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1771 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);
1772 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520);
1773 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C);
1774 state->general = NV_RD32(chip->PRAMDAC, 0x00000600);
1775 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848);
1776 state->config = NV_RD32(chip->PFB, 0x00000200);
1777 switch (chip->Architecture)
1778 {
1779 case NV_ARCH_03:
1780 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630);
1781 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634);
1782 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638);
1783 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C);
1784 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650);
1785 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654);
1786 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658);
1787 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C);
1788 break;
1789 case NV_ARCH_04:
1790 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1791 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1792 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1793 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1794 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1795 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1796 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1797 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1798 break;
1799 case NV_ARCH_10:
1800 case NV_ARCH_20:
1801 case NV_ARCH_30:
1802 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1803 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1804 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1805 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1806 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1807 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1808 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1809 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1810 if(chip->twoHeads) {
1811 state->head = NV_RD32(chip->PCRTC0, 0x00000860);
1812 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860);
1813 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1814 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1815 }
1816 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1817 state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1818 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810);
1819
1820 if((chip->Chipset & 0x0ff0) == 0x0110) {
1821 state->dither = NV_RD32(chip->PRAMDAC, 0x0528);
1822 } else
1823 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1824 state->dither = NV_RD32(chip->PRAMDAC, 0x083C);
1825 }
1826 break;
1827 }
1828}
1829static void SetStartAddress
1830(
1831 RIVA_HW_INST *chip,
1832 unsigned start
1833)
1834{
1835 NV_WR32(chip->PCRTC, 0x800, start);
1836}
1837
1838static void SetStartAddress3
1839(
1840 RIVA_HW_INST *chip,
1841 unsigned start
1842)
1843{
1844 int offset = start >> 2;
1845 int pan = (start & 3) << 1;
1846 unsigned char tmp;
1847
1848 /*
1849 * Unlock extended registers.
1850 */
1851 chip->LockUnlock(chip, 0);
1852 /*
1853 * Set start address.
1854 */
1855 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
1856 offset >>= 8;
1857 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
1858 offset >>= 8;
1859 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1860 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
1861 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1862 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
1863 /*
1864 * 4 pixel pan register.
1865 */
1866 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
1867 VGA_WR08(chip->PCIO, 0x3C0, 0x13);
1868 VGA_WR08(chip->PCIO, 0x3C0, pan);
1869}
1870static void nv3SetSurfaces2D
1871(
1872 RIVA_HW_INST *chip,
1873 unsigned surf0,
1874 unsigned surf1
1875)
1876{
1877 RivaSurface __iomem *Surface =
1878 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1879
1880 RIVA_FIFO_FREE(*chip,Tri03,5);
1881 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1882 NV_WR32(&Surface->Offset, 0, surf0);
1883 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1884 NV_WR32(&Surface->Offset, 0, surf1);
1885 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1886}
1887static void nv4SetSurfaces2D
1888(
1889 RIVA_HW_INST *chip,
1890 unsigned surf0,
1891 unsigned surf1
1892)
1893{
1894 RivaSurface __iomem *Surface =
1895 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1896
1897 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1898 NV_WR32(&Surface->Offset, 0, surf0);
1899 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1900 NV_WR32(&Surface->Offset, 0, surf1);
1901 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1902}
1903static void nv10SetSurfaces2D
1904(
1905 RIVA_HW_INST *chip,
1906 unsigned surf0,
1907 unsigned surf1
1908)
1909{
1910 RivaSurface __iomem *Surface =
1911 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1912
1913 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1914 NV_WR32(&Surface->Offset, 0, surf0);
1915 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1916 NV_WR32(&Surface->Offset, 0, surf1);
1917 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1918}
1919static void nv3SetSurfaces3D
1920(
1921 RIVA_HW_INST *chip,
1922 unsigned surf0,
1923 unsigned surf1
1924)
1925{
1926 RivaSurface __iomem *Surface =
1927 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1928
1929 RIVA_FIFO_FREE(*chip,Tri03,5);
1930 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1931 NV_WR32(&Surface->Offset, 0, surf0);
1932 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1933 NV_WR32(&Surface->Offset, 0, surf1);
1934 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1935}
1936static void nv4SetSurfaces3D
1937(
1938 RIVA_HW_INST *chip,
1939 unsigned surf0,
1940 unsigned surf1
1941)
1942{
1943 RivaSurface __iomem *Surface =
1944 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1945
1946 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1947 NV_WR32(&Surface->Offset, 0, surf0);
1948 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1949 NV_WR32(&Surface->Offset, 0, surf1);
1950 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1951}
1952static void nv10SetSurfaces3D
1953(
1954 RIVA_HW_INST *chip,
1955 unsigned surf0,
1956 unsigned surf1
1957)
1958{
1959 RivaSurface3D __iomem *Surfaces3D =
1960 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]);
1961
1962 RIVA_FIFO_FREE(*chip,Tri03,4);
1963 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007);
1964 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0);
1965 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1);
1966 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1967}
1968
1969/****************************************************************************\
1970* *
1971* Probe RIVA Chip Configuration *
1972* *
1973\****************************************************************************/
1974
1975static void nv3GetConfig
1976(
1977 RIVA_HW_INST *chip
1978)
1979{
1980 /*
1981 * Fill in chip configuration.
1982 */
1983 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020)
1984 {
1985 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
1986 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02))
1987 {
1988 /*
1989 * SDRAM 128 ZX.
1990 */
1991 chip->RamBandwidthKBytesPerSec = 800000;
1992 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03)
1993 {
1994 case 2:
1995 chip->RamAmountKBytes = 1024 * 4;
1996 break;
1997 case 1:
1998 chip->RamAmountKBytes = 1024 * 2;
1999 break;
2000 default:
2001 chip->RamAmountKBytes = 1024 * 8;
2002 break;
2003 }
2004 }
2005 else
2006 {
2007 chip->RamBandwidthKBytesPerSec = 1000000;
2008 chip->RamAmountKBytes = 1024 * 8;
2009 }
2010 }
2011 else
2012 {
2013 /*
2014 * SGRAM 128.
2015 */
2016 chip->RamBandwidthKBytesPerSec = 1000000;
2017 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2018 {
2019 case 0:
2020 chip->RamAmountKBytes = 1024 * 8;
2021 break;
2022 case 2:
2023 chip->RamAmountKBytes = 1024 * 4;
2024 break;
2025 default:
2026 chip->RamAmountKBytes = 1024 * 2;
2027 break;
2028 }
2029 }
2030 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2031 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
2032 chip->VBlankBit = 0x00000100;
2033 chip->MaxVClockFreqKHz = 256000;
2034 /*
2035 * Set chip functions.
2036 */
2037 chip->Busy = nv3Busy;
2038 chip->ShowHideCursor = ShowHideCursor;
2039 chip->LoadStateExt = LoadStateExt;
2040 chip->UnloadStateExt = UnloadStateExt;
2041 chip->SetStartAddress = SetStartAddress3;
2042 chip->SetSurfaces2D = nv3SetSurfaces2D;
2043 chip->SetSurfaces3D = nv3SetSurfaces3D;
2044 chip->LockUnlock = nv3LockUnlock;
2045}
2046static void nv4GetConfig
2047(
2048 RIVA_HW_INST *chip
2049)
2050{
2051 /*
2052 * Fill in chip configuration.
2053 */
2054 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100)
2055 {
2056 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2
2057 + 1024 * 2;
2058 }
2059 else
2060 {
2061 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2062 {
2063 case 0:
2064 chip->RamAmountKBytes = 1024 * 32;
2065 break;
2066 case 1:
2067 chip->RamAmountKBytes = 1024 * 4;
2068 break;
2069 case 2:
2070 chip->RamAmountKBytes = 1024 * 8;
2071 break;
2072 case 3:
2073 default:
2074 chip->RamAmountKBytes = 1024 * 16;
2075 break;
2076 }
2077 }
2078 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2079 {
2080 case 3:
2081 chip->RamBandwidthKBytesPerSec = 800000;
2082 break;
2083 default:
2084 chip->RamBandwidthKBytesPerSec = 1000000;
2085 break;
2086 }
2087 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2088 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
2089 chip->VBlankBit = 0x00000001;
2090 chip->MaxVClockFreqKHz = 350000;
2091 /*
2092 * Set chip functions.
2093 */
2094 chip->Busy = nv4Busy;
2095 chip->ShowHideCursor = ShowHideCursor;
2096 chip->LoadStateExt = LoadStateExt;
2097 chip->UnloadStateExt = UnloadStateExt;
2098 chip->SetStartAddress = SetStartAddress;
2099 chip->SetSurfaces2D = nv4SetSurfaces2D;
2100 chip->SetSurfaces3D = nv4SetSurfaces3D;
2101 chip->LockUnlock = nv4LockUnlock;
2102}
2103static void nv10GetConfig
2104(
2105 RIVA_HW_INST *chip,
2106 unsigned int chipset
2107)
2108{
2109 struct pci_dev* dev;
2110 u32 amt;
2111
2112#ifdef __BIG_ENDIAN
2113 /* turn on big endian register access */
2114 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001))
2115 NV_WR32(chip->PMC, 0x00000004, 0x01000001);
2116#endif
2117
2118 /*
2119 * Fill in chip configuration.
2120 */
2121 if(chipset == NV_CHIP_IGEFORCE2) {
2122 dev = pci_get_bus_and_slot(0, 1);
2123 pci_read_config_dword(dev, 0x7C, &amt);
2124 pci_dev_put(dev);
2125 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
2126 } else if(chipset == NV_CHIP_0x01F0) {
2127 dev = pci_get_bus_and_slot(0, 1);
2128 pci_read_config_dword(dev, 0x84, &amt);
2129 pci_dev_put(dev);
2130 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
2131 } else {
2132 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)
2133 {
2134 case 0x02:
2135 chip->RamAmountKBytes = 1024 * 2;
2136 break;
2137 case 0x04:
2138 chip->RamAmountKBytes = 1024 * 4;
2139 break;
2140 case 0x08:
2141 chip->RamAmountKBytes = 1024 * 8;
2142 break;
2143 case 0x10:
2144 chip->RamAmountKBytes = 1024 * 16;
2145 break;
2146 case 0x20:
2147 chip->RamAmountKBytes = 1024 * 32;
2148 break;
2149 case 0x40:
2150 chip->RamAmountKBytes = 1024 * 64;
2151 break;
2152 case 0x80:
2153 chip->RamAmountKBytes = 1024 * 128;
2154 break;
2155 default:
2156 chip->RamAmountKBytes = 1024 * 16;
2157 break;
2158 }
2159 }
2160 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2161 {
2162 case 3:
2163 chip->RamBandwidthKBytesPerSec = 800000;
2164 break;
2165 default:
2166 chip->RamBandwidthKBytesPerSec = 1000000;
2167 break;
2168 }
2169 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ?
2170 14318 : 13500;
2171
2172 switch (chipset & 0x0ff0) {
2173 case 0x0170:
2174 case 0x0180:
2175 case 0x01F0:
2176 case 0x0250:
2177 case 0x0280:
2178 case 0x0300:
2179 case 0x0310:
2180 case 0x0320:
2181 case 0x0330:
2182 case 0x0340:
2183 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22))
2184 chip->CrystalFreqKHz = 27000;
2185 break;
2186 default:
2187 break;
2188 }
2189
2190 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
2191 chip->CURSOR = NULL; /* can't set this here */
2192 chip->VBlankBit = 0x00000001;
2193 chip->MaxVClockFreqKHz = 350000;
2194 /*
2195 * Set chip functions.
2196 */
2197 chip->Busy = nv10Busy;
2198 chip->ShowHideCursor = ShowHideCursor;
2199 chip->LoadStateExt = LoadStateExt;
2200 chip->UnloadStateExt = UnloadStateExt;
2201 chip->SetStartAddress = SetStartAddress;
2202 chip->SetSurfaces2D = nv10SetSurfaces2D;
2203 chip->SetSurfaces3D = nv10SetSurfaces3D;
2204 chip->LockUnlock = nv4LockUnlock;
2205
2206 switch(chipset & 0x0ff0) {
2207 case 0x0110:
2208 case 0x0170:
2209 case 0x0180:
2210 case 0x01F0:
2211 case 0x0250:
2212 case 0x0280:
2213 case 0x0300:
2214 case 0x0310:
2215 case 0x0320:
2216 case 0x0330:
2217 case 0x0340:
2218 chip->twoHeads = TRUE;
2219 break;
2220 default:
2221 chip->twoHeads = FALSE;
2222 break;
2223 }
2224}
2225int RivaGetConfig
2226(
2227 RIVA_HW_INST *chip,
2228 unsigned int chipset
2229)
2230{
2231 /*
2232 * Save this so future SW know whats it's dealing with.
2233 */
2234 chip->Version = RIVA_SW_VERSION;
2235 /*
2236 * Chip specific configuration.
2237 */
2238 switch (chip->Architecture)
2239 {
2240 case NV_ARCH_03:
2241 nv3GetConfig(chip);
2242 break;
2243 case NV_ARCH_04:
2244 nv4GetConfig(chip);
2245 break;
2246 case NV_ARCH_10:
2247 case NV_ARCH_20:
2248 case NV_ARCH_30:
2249 nv10GetConfig(chip, chipset);
2250 break;
2251 default:
2252 return (-1);
2253 }
2254 chip->Chipset = chipset;
2255 /*
2256 * Fill in FIFO pointers.
2257 */
2258 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]);
2259 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]);
2260 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]);
2261 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]);
2262 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]);
2263 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]);
2264 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]);
2265 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
2266 return (0);
2267}
2268
diff --git a/drivers/video/riva/riva_hw.h b/drivers/video/riva/riva_hw.h
deleted file mode 100644
index c2769f73e0b2..000000000000
--- a/drivers/video/riva/riva_hw.h
+++ /dev/null
@@ -1,563 +0,0 @@
1/***************************************************************************\
2|* *|
3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38\***************************************************************************/
39
40/*
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45 */
46
47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
48#ifndef __RIVA_HW_H__
49#define __RIVA_HW_H__
50#define RIVA_SW_VERSION 0x00010003
51
52#ifndef Bool
53typedef int Bool;
54#endif
55
56#ifndef TRUE
57#define TRUE 1
58#endif
59#ifndef FALSE
60#define FALSE 0
61#endif
62#ifndef NULL
63#define NULL 0
64#endif
65
66/*
67 * Typedefs to force certain sized values.
68 */
69typedef unsigned char U008;
70typedef unsigned short U016;
71typedef unsigned int U032;
72
73/*
74 * HW access macros.
75 */
76#include <asm/io.h>
77
78#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
79#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
80#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
81#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
82#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
83#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
84
85#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
86#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
87
88/*
89 * Define different architectures.
90 */
91#define NV_ARCH_03 0x03
92#define NV_ARCH_04 0x04
93#define NV_ARCH_10 0x10
94#define NV_ARCH_20 0x20
95#define NV_ARCH_30 0x30
96#define NV_ARCH_40 0x40
97
98/***************************************************************************\
99* *
100* FIFO registers. *
101* *
102\***************************************************************************/
103
104/*
105 * Raster OPeration. Windows style ROP3.
106 */
107typedef volatile struct
108{
109 U032 reserved00[4];
110#ifdef __BIG_ENDIAN
111 U032 FifoFree;
112#else
113 U016 FifoFree;
114 U016 Nop;
115#endif
116 U032 reserved01[0x0BB];
117 U032 Rop3;
118} RivaRop;
119/*
120 * 8X8 Monochrome pattern.
121 */
122typedef volatile struct
123{
124 U032 reserved00[4];
125#ifdef __BIG_ENDIAN
126 U032 FifoFree;
127#else
128 U016 FifoFree;
129 U016 Nop;
130#endif
131 U032 reserved01[0x0BD];
132 U032 Shape;
133 U032 reserved03[0x001];
134 U032 Color0;
135 U032 Color1;
136 U032 Monochrome[2];
137} RivaPattern;
138/*
139 * Scissor clip rectangle.
140 */
141typedef volatile struct
142{
143 U032 reserved00[4];
144#ifdef __BIG_ENDIAN
145 U032 FifoFree;
146#else
147 U016 FifoFree;
148 U016 Nop;
149#endif
150 U032 reserved01[0x0BB];
151 U032 TopLeft;
152 U032 WidthHeight;
153} RivaClip;
154/*
155 * 2D filled rectangle.
156 */
157typedef volatile struct
158{
159 U032 reserved00[4];
160#ifdef __BIG_ENDIAN
161 U032 FifoFree;
162#else
163 U016 FifoFree;
164 U016 Nop[1];
165#endif
166 U032 reserved01[0x0BC];
167 U032 Color;
168 U032 reserved03[0x03E];
169 U032 TopLeft;
170 U032 WidthHeight;
171} RivaRectangle;
172/*
173 * 2D screen-screen BLT.
174 */
175typedef volatile struct
176{
177 U032 reserved00[4];
178#ifdef __BIG_ENDIAN
179 U032 FifoFree;
180#else
181 U016 FifoFree;
182 U016 Nop;
183#endif
184 U032 reserved01[0x0BB];
185 U032 TopLeftSrc;
186 U032 TopLeftDst;
187 U032 WidthHeight;
188} RivaScreenBlt;
189/*
190 * 2D pixel BLT.
191 */
192typedef volatile struct
193{
194 U032 reserved00[4];
195#ifdef __BIG_ENDIAN
196 U032 FifoFree;
197#else
198 U016 FifoFree;
199 U016 Nop[1];
200#endif
201 U032 reserved01[0x0BC];
202 U032 TopLeft;
203 U032 WidthHeight;
204 U032 WidthHeightIn;
205 U032 reserved02[0x03C];
206 U032 Pixels;
207} RivaPixmap;
208/*
209 * Filled rectangle combined with monochrome expand. Useful for glyphs.
210 */
211typedef volatile struct
212{
213 U032 reserved00[4];
214#ifdef __BIG_ENDIAN
215 U032 FifoFree;
216#else
217 U016 FifoFree;
218 U016 Nop;
219#endif
220 U032 reserved01[0x0BB];
221 U032 reserved03[(0x040)-1];
222 U032 Color1A;
223 struct
224 {
225 U032 TopLeft;
226 U032 WidthHeight;
227 } UnclippedRectangle[64];
228 U032 reserved04[(0x080)-3];
229 struct
230 {
231 U032 TopLeft;
232 U032 BottomRight;
233 } ClipB;
234 U032 Color1B;
235 struct
236 {
237 U032 TopLeft;
238 U032 BottomRight;
239 } ClippedRectangle[64];
240 U032 reserved05[(0x080)-5];
241 struct
242 {
243 U032 TopLeft;
244 U032 BottomRight;
245 } ClipC;
246 U032 Color1C;
247 U032 WidthHeightC;
248 U032 PointC;
249 U032 MonochromeData1C;
250 U032 reserved06[(0x080)+121];
251 struct
252 {
253 U032 TopLeft;
254 U032 BottomRight;
255 } ClipD;
256 U032 Color1D;
257 U032 WidthHeightInD;
258 U032 WidthHeightOutD;
259 U032 PointD;
260 U032 MonochromeData1D;
261 U032 reserved07[(0x080)+120];
262 struct
263 {
264 U032 TopLeft;
265 U032 BottomRight;
266 } ClipE;
267 U032 Color0E;
268 U032 Color1E;
269 U032 WidthHeightInE;
270 U032 WidthHeightOutE;
271 U032 PointE;
272 U032 MonochromeData01E;
273} RivaBitmap;
274/*
275 * 3D textured, Z buffered triangle.
276 */
277typedef volatile struct
278{
279 U032 reserved00[4];
280#ifdef __BIG_ENDIAN
281 U032 FifoFree;
282#else
283 U016 FifoFree;
284 U016 Nop;
285#endif
286 U032 reserved01[0x0BC];
287 U032 TextureOffset;
288 U032 TextureFormat;
289 U032 TextureFilter;
290 U032 FogColor;
291/* This is a problem on LynxOS */
292#ifdef Control
293#undef Control
294#endif
295 U032 Control;
296 U032 AlphaTest;
297 U032 reserved02[0x339];
298 U032 FogAndIndex;
299 U032 Color;
300 float ScreenX;
301 float ScreenY;
302 float ScreenZ;
303 float EyeM;
304 float TextureS;
305 float TextureT;
306} RivaTexturedTriangle03;
307typedef volatile struct
308{
309 U032 reserved00[4];
310#ifdef __BIG_ENDIAN
311 U032 FifoFree;
312#else
313 U016 FifoFree;
314 U016 Nop;
315#endif
316 U032 reserved01[0x0BB];
317 U032 ColorKey;
318 U032 TextureOffset;
319 U032 TextureFormat;
320 U032 TextureFilter;
321 U032 Blend;
322/* This is a problem on LynxOS */
323#ifdef Control
324#undef Control
325#endif
326 U032 Control;
327 U032 FogColor;
328 U032 reserved02[0x39];
329 struct
330 {
331 float ScreenX;
332 float ScreenY;
333 float ScreenZ;
334 float EyeM;
335 U032 Color;
336 U032 Specular;
337 float TextureS;
338 float TextureT;
339 } Vertex[16];
340 U032 DrawTriangle3D;
341} RivaTexturedTriangle05;
342/*
343 * 2D line.
344 */
345typedef volatile struct
346{
347 U032 reserved00[4];
348#ifdef __BIG_ENDIAN
349 U032 FifoFree;
350#else
351 U016 FifoFree;
352 U016 Nop[1];
353#endif
354 U032 reserved01[0x0BC];
355 U032 Color; /* source color 0304-0307*/
356 U032 Reserved02[0x03e];
357 struct { /* start aliased methods in array 0400- */
358 U032 point0; /* y_x S16_S16 in pixels 0- 3*/
359 U032 point1; /* y_x S16_S16 in pixels 4- 7*/
360 } Lin[16]; /* end of aliased methods in array -047f*/
361 struct { /* start aliased methods in array 0480- */
362 U032 point0X; /* in pixels, 0 at left 0- 3*/
363 U032 point0Y; /* in pixels, 0 at top 4- 7*/
364 U032 point1X; /* in pixels, 0 at left 8- b*/
365 U032 point1Y; /* in pixels, 0 at top c- f*/
366 } Lin32[8]; /* end of aliased methods in array -04ff*/
367 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
368 struct { /* start aliased methods in array 0580- */
369 U032 x; /* in pixels, 0 at left 0- 3*/
370 U032 y; /* in pixels, 0 at top 4- 7*/
371 } PolyLin32[16]; /* end of aliased methods in array -05ff*/
372 struct { /* start aliased methods in array 0600- */
373 U032 color; /* source color 0- 3*/
374 U032 point; /* y_x S16_S16 in pixels 4- 7*/
375 } ColorPolyLin[16]; /* end of aliased methods in array -067f*/
376} RivaLine;
377/*
378 * 2D/3D surfaces
379 */
380typedef volatile struct
381{
382 U032 reserved00[4];
383#ifdef __BIG_ENDIAN
384 U032 FifoFree;
385#else
386 U016 FifoFree;
387 U016 Nop;
388#endif
389 U032 reserved01[0x0BE];
390 U032 Offset;
391} RivaSurface;
392typedef volatile struct
393{
394 U032 reserved00[4];
395#ifdef __BIG_ENDIAN
396 U032 FifoFree;
397#else
398 U016 FifoFree;
399 U016 Nop;
400#endif
401 U032 reserved01[0x0BD];
402 U032 Pitch;
403 U032 RenderBufferOffset;
404 U032 ZBufferOffset;
405} RivaSurface3D;
406
407/***************************************************************************\
408* *
409* Virtualized RIVA H/W interface. *
410* *
411\***************************************************************************/
412
413#define FP_ENABLE 1
414#define FP_DITHER 2
415
416struct _riva_hw_inst;
417struct _riva_hw_state;
418/*
419 * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
420 */
421typedef struct _riva_hw_inst
422{
423 /*
424 * Chip specific settings.
425 */
426 U032 Architecture;
427 U032 Version;
428 U032 Chipset;
429 U032 CrystalFreqKHz;
430 U032 RamAmountKBytes;
431 U032 MaxVClockFreqKHz;
432 U032 RamBandwidthKBytesPerSec;
433 U032 EnableIRQ;
434 U032 IO;
435 U032 VBlankBit;
436 U032 FifoFreeCount;
437 U032 FifoEmptyCount;
438 U032 CursorStart;
439 U032 flatPanel;
440 Bool twoHeads;
441 /*
442 * Non-FIFO registers.
443 */
444 volatile U032 __iomem *PCRTC0;
445 volatile U032 __iomem *PCRTC;
446 volatile U032 __iomem *PRAMDAC0;
447 volatile U032 __iomem *PFB;
448 volatile U032 __iomem *PFIFO;
449 volatile U032 __iomem *PGRAPH;
450 volatile U032 __iomem *PEXTDEV;
451 volatile U032 __iomem *PTIMER;
452 volatile U032 __iomem *PMC;
453 volatile U032 __iomem *PRAMIN;
454 volatile U032 __iomem *FIFO;
455 volatile U032 __iomem *CURSOR;
456 volatile U008 __iomem *PCIO0;
457 volatile U008 __iomem *PCIO;
458 volatile U008 __iomem *PVIO;
459 volatile U008 __iomem *PDIO0;
460 volatile U008 __iomem *PDIO;
461 volatile U032 __iomem *PRAMDAC;
462 /*
463 * Common chip functions.
464 */
465 int (*Busy)(struct _riva_hw_inst *);
466 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
467 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
468 void (*SetStartAddress)(struct _riva_hw_inst *,U032);
469 void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
470 void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
471 int (*ShowHideCursor)(struct _riva_hw_inst *,int);
472 void (*LockUnlock)(struct _riva_hw_inst *, int);
473 /*
474 * Current extended mode settings.
475 */
476 struct _riva_hw_state *CurrentState;
477 /*
478 * FIFO registers.
479 */
480 RivaRop __iomem *Rop;
481 RivaPattern __iomem *Patt;
482 RivaClip __iomem *Clip;
483 RivaPixmap __iomem *Pixmap;
484 RivaScreenBlt __iomem *Blt;
485 RivaBitmap __iomem *Bitmap;
486 RivaLine __iomem *Line;
487 RivaTexturedTriangle03 __iomem *Tri03;
488 RivaTexturedTriangle05 __iomem *Tri05;
489} RIVA_HW_INST;
490/*
491 * Extended mode state information.
492 */
493typedef struct _riva_hw_state
494{
495 U032 bpp;
496 U032 width;
497 U032 height;
498 U032 interlace;
499 U032 repaint0;
500 U032 repaint1;
501 U032 screen;
502 U032 scale;
503 U032 dither;
504 U032 extra;
505 U032 pixel;
506 U032 horiz;
507 U032 arbitration0;
508 U032 arbitration1;
509 U032 vpll;
510 U032 vpll2;
511 U032 pllsel;
512 U032 general;
513 U032 crtcOwner;
514 U032 head;
515 U032 head2;
516 U032 config;
517 U032 cursorConfig;
518 U032 cursor0;
519 U032 cursor1;
520 U032 cursor2;
521 U032 offset0;
522 U032 offset1;
523 U032 offset2;
524 U032 offset3;
525 U032 pitch0;
526 U032 pitch1;
527 U032 pitch2;
528 U032 pitch3;
529} RIVA_HW_STATE;
530
531/*
532 * function prototypes
533 */
534
535extern int CalcStateExt
536(
537 RIVA_HW_INST *chip,
538 RIVA_HW_STATE *state,
539 int bpp,
540 int width,
541 int hDisplaySize,
542 int height,
543 int dotClock
544);
545
546/*
547 * External routines.
548 */
549int RivaGetConfig(RIVA_HW_INST *, unsigned int);
550/*
551 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
552 */
553
554#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \
555{ \
556 while ((hwinst).FifoFreeCount < (cnt)) { \
557 mb();mb(); \
558 (hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \
559 } \
560 (hwinst).FifoFreeCount -= (cnt); \
561}
562#endif /* __RIVA_HW_H__ */
563
diff --git a/drivers/video/riva/riva_tbl.h b/drivers/video/riva/riva_tbl.h
deleted file mode 100644
index 7ee7d72932d4..000000000000
--- a/drivers/video/riva/riva_tbl.h
+++ /dev/null
@@ -1,1008 +0,0 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45 */
46
47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.9 2002/01/30 01:35:03 mvojkovi Exp $ */
48
49
50/*
51 * RIVA Fixed Functionality Init Tables.
52 */
53static unsigned RivaTablePMC[][2] =
54{
55 {0x00000050, 0x00000000},
56 {0x00000080, 0xFFFF00FF},
57 {0x00000080, 0xFFFFFFFF}
58};
59static unsigned RivaTablePTIMER[][2] =
60{
61 {0x00000080, 0x00000008},
62 {0x00000084, 0x00000003},
63 {0x00000050, 0x00000000},
64 {0x00000040, 0xFFFFFFFF}
65};
66static unsigned RivaTableFIFO[][2] =
67{
68 {0x00000000, 0x80000000},
69 {0x00000800, 0x80000001},
70 {0x00001000, 0x80000002},
71 {0x00001800, 0x80000010},
72 {0x00002000, 0x80000011},
73 {0x00002800, 0x80000012},
74 {0x00003000, 0x80000016},
75 {0x00003800, 0x80000013}
76};
77static unsigned nv3TablePFIFO[][2] =
78{
79 {0x00000140, 0x00000000},
80 {0x00000480, 0x00000000},
81 {0x00000490, 0x00000000},
82 {0x00000494, 0x00000000},
83 {0x00000481, 0x00000000},
84 {0x00000084, 0x00000000},
85 {0x00000086, 0x00002000},
86 {0x00000085, 0x00002200},
87 {0x00000484, 0x00000000},
88 {0x0000049C, 0x00000000},
89 {0x00000104, 0x00000000},
90 {0x00000108, 0x00000000},
91 {0x00000100, 0x00000000},
92 {0x000004A0, 0x00000000},
93 {0x000004A4, 0x00000000},
94 {0x000004A8, 0x00000000},
95 {0x000004AC, 0x00000000},
96 {0x000004B0, 0x00000000},
97 {0x000004B4, 0x00000000},
98 {0x000004B8, 0x00000000},
99 {0x000004BC, 0x00000000},
100 {0x00000050, 0x00000000},
101 {0x00000040, 0xFFFFFFFF},
102 {0x00000480, 0x00000001},
103 {0x00000490, 0x00000001},
104 {0x00000140, 0x00000001}
105};
106static unsigned nv3TablePGRAPH[][2] =
107{
108 {0x00000020, 0x1230001F},
109 {0x00000021, 0x10113000},
110 {0x00000022, 0x1131F101},
111 {0x00000023, 0x0100F531},
112 {0x00000060, 0x00000000},
113 {0x00000065, 0x00000000},
114 {0x00000068, 0x00000000},
115 {0x00000069, 0x00000000},
116 {0x0000006A, 0x00000000},
117 {0x0000006B, 0x00000000},
118 {0x0000006C, 0x00000000},
119 {0x0000006D, 0x00000000},
120 {0x0000006E, 0x00000000},
121 {0x0000006F, 0x00000000},
122 {0x000001A8, 0x00000000},
123 {0x00000440, 0xFFFFFFFF},
124 {0x00000480, 0x00000001},
125 {0x000001A0, 0x00000000},
126 {0x000001A2, 0x00000000},
127 {0x0000018A, 0xFFFFFFFF},
128 {0x00000190, 0x00000000},
129 {0x00000142, 0x00000000},
130 {0x00000154, 0x00000000},
131 {0x00000155, 0xFFFFFFFF},
132 {0x00000156, 0x00000000},
133 {0x00000157, 0xFFFFFFFF},
134 {0x00000064, 0x10010002},
135 {0x00000050, 0x00000000},
136 {0x00000051, 0x00000000},
137 {0x00000040, 0xFFFFFFFF},
138 {0x00000041, 0xFFFFFFFF},
139 {0x00000440, 0xFFFFFFFF},
140 {0x000001A9, 0x00000001}
141};
142static unsigned nv3TablePGRAPH_8BPP[][2] =
143{
144 {0x000001AA, 0x00001111}
145};
146static unsigned nv3TablePGRAPH_15BPP[][2] =
147{
148 {0x000001AA, 0x00002222}
149};
150static unsigned nv3TablePGRAPH_32BPP[][2] =
151{
152 {0x000001AA, 0x00003333}
153};
154static unsigned nv3TablePRAMIN[][2] =
155{
156 {0x00000500, 0x00010000},
157 {0x00000501, 0x007FFFFF},
158 {0x00000200, 0x80000000},
159 {0x00000201, 0x00C20341},
160 {0x00000204, 0x80000001},
161 {0x00000205, 0x00C50342},
162 {0x00000208, 0x80000002},
163 {0x00000209, 0x00C60343},
164 {0x0000020C, 0x80000003},
165 {0x0000020D, 0x00DC0348},
166 {0x00000210, 0x80000004},
167 {0x00000211, 0x00DC0349},
168 {0x00000214, 0x80000005},
169 {0x00000215, 0x00DC034A},
170 {0x00000218, 0x80000006},
171 {0x00000219, 0x00DC034B},
172 {0x00000240, 0x80000010},
173 {0x00000241, 0x00D10344},
174 {0x00000244, 0x80000011},
175 {0x00000245, 0x00D00345},
176 {0x00000248, 0x80000012},
177 {0x00000249, 0x00CC0346},
178 {0x0000024C, 0x80000013},
179 {0x0000024D, 0x00D70347},
180 {0x00000258, 0x80000016},
181 {0x00000259, 0x00CA034C},
182 {0x00000D05, 0x00000000},
183 {0x00000D06, 0x00000000},
184 {0x00000D07, 0x00000000},
185 {0x00000D09, 0x00000000},
186 {0x00000D0A, 0x00000000},
187 {0x00000D0B, 0x00000000},
188 {0x00000D0D, 0x00000000},
189 {0x00000D0E, 0x00000000},
190 {0x00000D0F, 0x00000000},
191 {0x00000D11, 0x00000000},
192 {0x00000D12, 0x00000000},
193 {0x00000D13, 0x00000000},
194 {0x00000D15, 0x00000000},
195 {0x00000D16, 0x00000000},
196 {0x00000D17, 0x00000000},
197 {0x00000D19, 0x00000000},
198 {0x00000D1A, 0x00000000},
199 {0x00000D1B, 0x00000000},
200 {0x00000D1D, 0x00000140},
201 {0x00000D1E, 0x00000000},
202 {0x00000D1F, 0x00000000},
203 {0x00000D20, 0x10100200},
204 {0x00000D21, 0x00000000},
205 {0x00000D22, 0x00000000},
206 {0x00000D23, 0x00000000},
207 {0x00000D24, 0x10210200},
208 {0x00000D25, 0x00000000},
209 {0x00000D26, 0x00000000},
210 {0x00000D27, 0x00000000},
211 {0x00000D28, 0x10420200},
212 {0x00000D29, 0x00000000},
213 {0x00000D2A, 0x00000000},
214 {0x00000D2B, 0x00000000},
215 {0x00000D2C, 0x10830200},
216 {0x00000D2D, 0x00000000},
217 {0x00000D2E, 0x00000000},
218 {0x00000D2F, 0x00000000},
219 {0x00000D31, 0x00000000},
220 {0x00000D32, 0x00000000},
221 {0x00000D33, 0x00000000}
222};
223static unsigned nv3TablePRAMIN_8BPP[][2] =
224{
225 /* 0xXXXXX3XX For MSB mono format */
226 /* 0xXXXXX2XX For LSB mono format */
227 {0x00000D04, 0x10110203},
228 {0x00000D08, 0x10110203},
229 {0x00000D0C, 0x1011020B},
230 {0x00000D10, 0x10118203},
231 {0x00000D14, 0x10110203},
232 {0x00000D18, 0x10110203},
233 {0x00000D1C, 0x10419208},
234 {0x00000D30, 0x10118203}
235};
236static unsigned nv3TablePRAMIN_15BPP[][2] =
237{
238 /* 0xXXXXX2XX For MSB mono format */
239 /* 0xXXXXX3XX For LSB mono format */
240 {0x00000D04, 0x10110200},
241 {0x00000D08, 0x10110200},
242 {0x00000D0C, 0x10110208},
243 {0x00000D10, 0x10118200},
244 {0x00000D14, 0x10110200},
245 {0x00000D18, 0x10110200},
246 {0x00000D1C, 0x10419208},
247 {0x00000D30, 0x10118200}
248};
249static unsigned nv3TablePRAMIN_32BPP[][2] =
250{
251 /* 0xXXXXX3XX For MSB mono format */
252 /* 0xXXXXX2XX For LSB mono format */
253 {0x00000D04, 0x10110201},
254 {0x00000D08, 0x10110201},
255 {0x00000D0C, 0x10110209},
256 {0x00000D10, 0x10118201},
257 {0x00000D14, 0x10110201},
258 {0x00000D18, 0x10110201},
259 {0x00000D1C, 0x10419208},
260 {0x00000D30, 0x10118201}
261};
262static unsigned nv4TableFIFO[][2] =
263{
264 {0x00003800, 0x80000014}
265};
266static unsigned nv4TablePFIFO[][2] =
267{
268 {0x00000140, 0x00000000},
269 {0x00000480, 0x00000000},
270 {0x00000494, 0x00000000},
271 {0x00000481, 0x00000000},
272 {0x0000048B, 0x00000000},
273 {0x00000400, 0x00000000},
274 {0x00000414, 0x00000000},
275 {0x00000084, 0x03000100},
276 {0x00000085, 0x00000110},
277 {0x00000086, 0x00000112},
278 {0x00000143, 0x0000FFFF},
279 {0x00000496, 0x0000FFFF},
280 {0x00000050, 0x00000000},
281 {0x00000040, 0xFFFFFFFF},
282 {0x00000415, 0x00000001},
283 {0x00000480, 0x00000001},
284 {0x00000494, 0x00000001},
285 {0x00000495, 0x00000001},
286 {0x00000140, 0x00000001}
287};
288static unsigned nv4TablePGRAPH[][2] =
289{
290 {0x00000020, 0x1231C001},
291 {0x00000021, 0x72111101},
292 {0x00000022, 0x11D5F071},
293 {0x00000023, 0x10D4FF31},
294 {0x00000060, 0x00000000},
295 {0x00000068, 0x00000000},
296 {0x00000070, 0x00000000},
297 {0x00000078, 0x00000000},
298 {0x00000061, 0x00000000},
299 {0x00000069, 0x00000000},
300 {0x00000071, 0x00000000},
301 {0x00000079, 0x00000000},
302 {0x00000062, 0x00000000},
303 {0x0000006A, 0x00000000},
304 {0x00000072, 0x00000000},
305 {0x0000007A, 0x00000000},
306 {0x00000063, 0x00000000},
307 {0x0000006B, 0x00000000},
308 {0x00000073, 0x00000000},
309 {0x0000007B, 0x00000000},
310 {0x00000064, 0x00000000},
311 {0x0000006C, 0x00000000},
312 {0x00000074, 0x00000000},
313 {0x0000007C, 0x00000000},
314 {0x00000065, 0x00000000},
315 {0x0000006D, 0x00000000},
316 {0x00000075, 0x00000000},
317 {0x0000007D, 0x00000000},
318 {0x00000066, 0x00000000},
319 {0x0000006E, 0x00000000},
320 {0x00000076, 0x00000000},
321 {0x0000007E, 0x00000000},
322 {0x00000067, 0x00000000},
323 {0x0000006F, 0x00000000},
324 {0x00000077, 0x00000000},
325 {0x0000007F, 0x00000000},
326 {0x00000058, 0x00000000},
327 {0x00000059, 0x00000000},
328 {0x0000005A, 0x00000000},
329 {0x0000005B, 0x00000000},
330 {0x00000196, 0x00000000},
331 {0x000001A1, 0x01FFFFFF},
332 {0x00000197, 0x00000000},
333 {0x000001A2, 0x01FFFFFF},
334 {0x00000198, 0x00000000},
335 {0x000001A3, 0x01FFFFFF},
336 {0x00000199, 0x00000000},
337 {0x000001A4, 0x01FFFFFF},
338 {0x00000050, 0x00000000},
339 {0x00000040, 0xFFFFFFFF},
340 {0x0000005C, 0x10010100},
341 {0x000001C4, 0xFFFFFFFF},
342 {0x000001C8, 0x00000001},
343 {0x00000204, 0x00000000},
344 {0x000001C3, 0x00000001}
345};
346static unsigned nv4TablePGRAPH_8BPP[][2] =
347{
348 {0x000001C9, 0x00111111},
349 {0x00000186, 0x00001010},
350 {0x0000020C, 0x03020202}
351};
352static unsigned nv4TablePGRAPH_15BPP[][2] =
353{
354 {0x000001C9, 0x00226222},
355 {0x00000186, 0x00002071},
356 {0x0000020C, 0x09080808}
357};
358static unsigned nv4TablePGRAPH_16BPP[][2] =
359{
360 {0x000001C9, 0x00556555},
361 {0x00000186, 0x000050C2},
362 {0x0000020C, 0x0C0B0B0B}
363};
364static unsigned nv4TablePGRAPH_32BPP[][2] =
365{
366 {0x000001C9, 0x0077D777},
367 {0x00000186, 0x000070E5},
368 {0x0000020C, 0x0E0D0D0D}
369};
370static unsigned nv4TablePRAMIN[][2] =
371{
372 {0x00000000, 0x80000010},
373 {0x00000001, 0x80011145},
374 {0x00000002, 0x80000011},
375 {0x00000003, 0x80011146},
376 {0x00000004, 0x80000012},
377 {0x00000005, 0x80011147},
378 {0x00000006, 0x80000013},
379 {0x00000007, 0x80011148},
380 {0x00000008, 0x80000014},
381 {0x00000009, 0x80011149},
382 {0x0000000A, 0x80000015},
383 {0x0000000B, 0x8001114A},
384 {0x0000000C, 0x80000016},
385 {0x0000000D, 0x8001114F},
386 {0x00000020, 0x80000000},
387 {0x00000021, 0x80011142},
388 {0x00000022, 0x80000001},
389 {0x00000023, 0x80011143},
390 {0x00000024, 0x80000002},
391 {0x00000025, 0x80011144},
392 {0x00000026, 0x80000003},
393 {0x00000027, 0x8001114B},
394 {0x00000028, 0x80000004},
395 {0x00000029, 0x8001114C},
396 {0x0000002A, 0x80000005},
397 {0x0000002B, 0x8001114D},
398 {0x0000002C, 0x80000006},
399 {0x0000002D, 0x8001114E},
400 {0x00000500, 0x00003000},
401 {0x00000501, 0x01FFFFFF},
402 {0x00000502, 0x00000002},
403 {0x00000503, 0x00000002},
404 {0x00000508, 0x01008043},
405 {0x0000050A, 0x00000000},
406 {0x0000050B, 0x00000000},
407 {0x0000050C, 0x01008019},
408 {0x0000050E, 0x00000000},
409 {0x0000050F, 0x00000000},
410#if 1
411 {0x00000510, 0x01008018},
412#else
413 {0x00000510, 0x01008044},
414#endif
415 {0x00000512, 0x00000000},
416 {0x00000513, 0x00000000},
417 {0x00000514, 0x01008021},
418 {0x00000516, 0x00000000},
419 {0x00000517, 0x00000000},
420 {0x00000518, 0x0100805F},
421 {0x0000051A, 0x00000000},
422 {0x0000051B, 0x00000000},
423#if 1
424 {0x0000051C, 0x0100804B},
425#else
426 {0x0000051C, 0x0100804A},
427#endif
428 {0x0000051E, 0x00000000},
429 {0x0000051F, 0x00000000},
430 {0x00000520, 0x0100A048},
431 {0x00000521, 0x00000D01},
432 {0x00000522, 0x11401140},
433 {0x00000523, 0x00000000},
434 {0x00000524, 0x0300A054},
435 {0x00000525, 0x00000D01},
436 {0x00000526, 0x11401140},
437 {0x00000527, 0x00000000},
438 {0x00000528, 0x0300A055},
439 {0x00000529, 0x00000D01},
440 {0x0000052A, 0x11401140},
441 {0x0000052B, 0x00000000},
442 {0x0000052C, 0x00000058},
443 {0x0000052E, 0x11401140},
444 {0x0000052F, 0x00000000},
445 {0x00000530, 0x00000059},
446 {0x00000532, 0x11401140},
447 {0x00000533, 0x00000000},
448 {0x00000534, 0x0000005A},
449 {0x00000536, 0x11401140},
450 {0x00000537, 0x00000000},
451 {0x00000538, 0x0000005B},
452 {0x0000053A, 0x11401140},
453 {0x0000053B, 0x00000000},
454 {0x0000053C, 0x0300A01C},
455 {0x0000053E, 0x11401140},
456 {0x0000053F, 0x00000000}
457};
458static unsigned nv4TablePRAMIN_8BPP[][2] =
459{
460 /* 0xXXXXXX01 For MSB mono format */
461 /* 0xXXXXXX02 For LSB mono format */
462 {0x00000509, 0x00000302},
463 {0x0000050D, 0x00000302},
464 {0x00000511, 0x00000202},
465 {0x00000515, 0x00000302},
466 {0x00000519, 0x00000302},
467 {0x0000051D, 0x00000302},
468 {0x0000052D, 0x00000302},
469 {0x0000052E, 0x00000302},
470 {0x00000535, 0x00000000},
471 {0x00000539, 0x00000000},
472 {0x0000053D, 0x00000302}
473};
474static unsigned nv4TablePRAMIN_15BPP[][2] =
475{
476 /* 0xXXXXXX01 For MSB mono format */
477 /* 0xXXXXXX02 For LSB mono format */
478 {0x00000509, 0x00000902},
479 {0x0000050D, 0x00000902},
480 {0x00000511, 0x00000802},
481 {0x00000515, 0x00000902},
482 {0x00000519, 0x00000902},
483 {0x0000051D, 0x00000902},
484 {0x0000052D, 0x00000902},
485 {0x0000052E, 0x00000902},
486 {0x00000535, 0x00000702},
487 {0x00000539, 0x00000702},
488 {0x0000053D, 0x00000902}
489};
490static unsigned nv4TablePRAMIN_16BPP[][2] =
491{
492 /* 0xXXXXXX01 For MSB mono format */
493 /* 0xXXXXXX02 For LSB mono format */
494 {0x00000509, 0x00000C02},
495 {0x0000050D, 0x00000C02},
496 {0x00000511, 0x00000B02},
497 {0x00000515, 0x00000C02},
498 {0x00000519, 0x00000C02},
499 {0x0000051D, 0x00000C02},
500 {0x0000052D, 0x00000C02},
501 {0x0000052E, 0x00000C02},
502 {0x00000535, 0x00000702},
503 {0x00000539, 0x00000702},
504 {0x0000053D, 0x00000C02}
505};
506static unsigned nv4TablePRAMIN_32BPP[][2] =
507{
508 /* 0xXXXXXX01 For MSB mono format */
509 /* 0xXXXXXX02 For LSB mono format */
510 {0x00000509, 0x00000E02},
511 {0x0000050D, 0x00000E02},
512 {0x00000511, 0x00000D02},
513 {0x00000515, 0x00000E02},
514 {0x00000519, 0x00000E02},
515 {0x0000051D, 0x00000E02},
516 {0x0000052D, 0x00000E02},
517 {0x0000052E, 0x00000E02},
518 {0x00000535, 0x00000E02},
519 {0x00000539, 0x00000E02},
520 {0x0000053D, 0x00000E02}
521};
522static unsigned nv10TableFIFO[][2] =
523{
524 {0x00003800, 0x80000014}
525};
526static unsigned nv10TablePFIFO[][2] =
527{
528 {0x00000140, 0x00000000},
529 {0x00000480, 0x00000000},
530 {0x00000494, 0x00000000},
531 {0x00000481, 0x00000000},
532 {0x0000048B, 0x00000000},
533 {0x00000400, 0x00000000},
534 {0x00000414, 0x00000000},
535 {0x00000084, 0x03000100},
536 {0x00000085, 0x00000110},
537 {0x00000086, 0x00000112},
538 {0x00000143, 0x0000FFFF},
539 {0x00000496, 0x0000FFFF},
540 {0x00000050, 0x00000000},
541 {0x00000040, 0xFFFFFFFF},
542 {0x00000415, 0x00000001},
543 {0x00000480, 0x00000001},
544 {0x00000494, 0x00000001},
545 {0x00000495, 0x00000001},
546 {0x00000140, 0x00000001}
547};
548static unsigned nv10TablePGRAPH[][2] =
549{
550 {0x00000020, 0x0003FFFF},
551 {0x00000021, 0x00118701},
552 {0x00000022, 0x24F82AD9},
553 {0x00000023, 0x55DE0030},
554 {0x00000020, 0x00000000},
555 {0x00000024, 0x00000000},
556 {0x00000058, 0x00000000},
557 {0x00000060, 0x00000000},
558 {0x00000068, 0x00000000},
559 {0x00000070, 0x00000000},
560 {0x00000078, 0x00000000},
561 {0x00000059, 0x00000000},
562 {0x00000061, 0x00000000},
563 {0x00000069, 0x00000000},
564 {0x00000071, 0x00000000},
565 {0x00000079, 0x00000000},
566 {0x0000005A, 0x00000000},
567 {0x00000062, 0x00000000},
568 {0x0000006A, 0x00000000},
569 {0x00000072, 0x00000000},
570 {0x0000007A, 0x00000000},
571 {0x0000005B, 0x00000000},
572 {0x00000063, 0x00000000},
573 {0x0000006B, 0x00000000},
574 {0x00000073, 0x00000000},
575 {0x0000007B, 0x00000000},
576 {0x0000005C, 0x00000000},
577 {0x00000064, 0x00000000},
578 {0x0000006C, 0x00000000},
579 {0x00000074, 0x00000000},
580 {0x0000007C, 0x00000000},
581 {0x0000005D, 0x00000000},
582 {0x00000065, 0x00000000},
583 {0x0000006D, 0x00000000},
584 {0x00000075, 0x00000000},
585 {0x0000007D, 0x00000000},
586 {0x0000005E, 0x00000000},
587 {0x00000066, 0x00000000},
588 {0x0000006E, 0x00000000},
589 {0x00000076, 0x00000000},
590 {0x0000007E, 0x00000000},
591 {0x0000005F, 0x00000000},
592 {0x00000067, 0x00000000},
593 {0x0000006F, 0x00000000},
594 {0x00000077, 0x00000000},
595 {0x0000007F, 0x00000000},
596 {0x00000053, 0x00000000},
597 {0x00000054, 0x00000000},
598 {0x00000055, 0x00000000},
599 {0x00000056, 0x00000000},
600 {0x00000057, 0x00000000},
601 {0x00000196, 0x00000000},
602 {0x000001A1, 0x01FFFFFF},
603 {0x00000197, 0x00000000},
604 {0x000001A2, 0x01FFFFFF},
605 {0x00000198, 0x00000000},
606 {0x000001A3, 0x01FFFFFF},
607 {0x00000199, 0x00000000},
608 {0x000001A4, 0x01FFFFFF},
609 {0x0000019A, 0x00000000},
610 {0x000001A5, 0x01FFFFFF},
611 {0x0000019B, 0x00000000},
612 {0x000001A6, 0x01FFFFFF},
613 {0x00000050, 0x01111111},
614 {0x00000040, 0xFFFFFFFF},
615 {0x00000051, 0x10010100},
616 {0x000001C5, 0xFFFFFFFF},
617 {0x000001C8, 0x00000001},
618 {0x00000204, 0x00000000},
619 {0x000001C4, 0x00000001}
620};
621static unsigned nv10TablePGRAPH_8BPP[][2] =
622{
623 {0x000001C9, 0x00111111},
624 {0x00000186, 0x00001010},
625 {0x0000020C, 0x03020202}
626};
627static unsigned nv10TablePGRAPH_15BPP[][2] =
628{
629 {0x000001C9, 0x00226222},
630 {0x00000186, 0x00002071},
631 {0x0000020C, 0x09080808}
632};
633static unsigned nv10TablePGRAPH_16BPP[][2] =
634{
635 {0x000001C9, 0x00556555},
636 {0x00000186, 0x000050C2},
637 {0x0000020C, 0x000B0B0C}
638};
639static unsigned nv10TablePGRAPH_32BPP[][2] =
640{
641 {0x000001C9, 0x0077D777},
642 {0x00000186, 0x000070E5},
643 {0x0000020C, 0x0E0D0D0D}
644};
645static unsigned nv10tri05TablePGRAPH[][2] =
646{
647 {(0x00000E00/4), 0x00000000},
648 {(0x00000E04/4), 0x00000000},
649 {(0x00000E08/4), 0x00000000},
650 {(0x00000E0C/4), 0x00000000},
651 {(0x00000E10/4), 0x00001000},
652 {(0x00000E14/4), 0x00001000},
653 {(0x00000E18/4), 0x4003ff80},
654 {(0x00000E1C/4), 0x00000000},
655 {(0x00000E20/4), 0x00000000},
656 {(0x00000E24/4), 0x00000000},
657 {(0x00000E28/4), 0x00000000},
658 {(0x00000E2C/4), 0x00000000},
659 {(0x00000E30/4), 0x00080008},
660 {(0x00000E34/4), 0x00080008},
661 {(0x00000E38/4), 0x00000000},
662 {(0x00000E3C/4), 0x00000000},
663 {(0x00000E40/4), 0x00000000},
664 {(0x00000E44/4), 0x00000000},
665 {(0x00000E48/4), 0x00000000},
666 {(0x00000E4C/4), 0x00000000},
667 {(0x00000E50/4), 0x00000000},
668 {(0x00000E54/4), 0x00000000},
669 {(0x00000E58/4), 0x00000000},
670 {(0x00000E5C/4), 0x00000000},
671 {(0x00000E60/4), 0x00000000},
672 {(0x00000E64/4), 0x10000000},
673 {(0x00000E68/4), 0x00000000},
674 {(0x00000E6C/4), 0x00000000},
675 {(0x00000E70/4), 0x00000000},
676 {(0x00000E74/4), 0x00000000},
677 {(0x00000E78/4), 0x00000000},
678 {(0x00000E7C/4), 0x00000000},
679 {(0x00000E80/4), 0x00000000},
680 {(0x00000E84/4), 0x00000000},
681 {(0x00000E88/4), 0x08000000},
682 {(0x00000E8C/4), 0x00000000},
683 {(0x00000E90/4), 0x00000000},
684 {(0x00000E94/4), 0x00000000},
685 {(0x00000E98/4), 0x00000000},
686 {(0x00000E9C/4), 0x4B7FFFFF},
687 {(0x00000EA0/4), 0x00000000},
688 {(0x00000EA4/4), 0x00000000},
689 {(0x00000EA8/4), 0x00000000},
690 {(0x00000F00/4), 0x07FF0800},
691 {(0x00000F04/4), 0x07FF0800},
692 {(0x00000F08/4), 0x07FF0800},
693 {(0x00000F0C/4), 0x07FF0800},
694 {(0x00000F10/4), 0x07FF0800},
695 {(0x00000F14/4), 0x07FF0800},
696 {(0x00000F18/4), 0x07FF0800},
697 {(0x00000F1C/4), 0x07FF0800},
698 {(0x00000F20/4), 0x07FF0800},
699 {(0x00000F24/4), 0x07FF0800},
700 {(0x00000F28/4), 0x07FF0800},
701 {(0x00000F2C/4), 0x07FF0800},
702 {(0x00000F30/4), 0x07FF0800},
703 {(0x00000F34/4), 0x07FF0800},
704 {(0x00000F38/4), 0x07FF0800},
705 {(0x00000F3C/4), 0x07FF0800},
706 {(0x00000F40/4), 0x10000000},
707 {(0x00000F44/4), 0x00000000},
708 {(0x00000F50/4), 0x00006740},
709 {(0x00000F54/4), 0x00000000},
710 {(0x00000F54/4), 0x00000000},
711 {(0x00000F54/4), 0x00000000},
712 {(0x00000F54/4), 0x3F800000},
713 {(0x00000F50/4), 0x00006750},
714 {(0x00000F54/4), 0x40000000},
715 {(0x00000F54/4), 0x40000000},
716 {(0x00000F54/4), 0x40000000},
717 {(0x00000F54/4), 0x40000000},
718 {(0x00000F50/4), 0x00006760},
719 {(0x00000F54/4), 0x00000000},
720 {(0x00000F54/4), 0x00000000},
721 {(0x00000F54/4), 0x3F800000},
722 {(0x00000F54/4), 0x00000000},
723 {(0x00000F50/4), 0x00006770},
724 {(0x00000F54/4), 0xC5000000},
725 {(0x00000F54/4), 0xC5000000},
726 {(0x00000F54/4), 0x00000000},
727 {(0x00000F54/4), 0x00000000},
728 {(0x00000F50/4), 0x00006780},
729 {(0x00000F54/4), 0x00000000},
730 {(0x00000F54/4), 0x00000000},
731 {(0x00000F54/4), 0x3F800000},
732 {(0x00000F54/4), 0x00000000},
733 {(0x00000F50/4), 0x000067A0},
734 {(0x00000F54/4), 0x3F800000},
735 {(0x00000F54/4), 0x3F800000},
736 {(0x00000F54/4), 0x3F800000},
737 {(0x00000F54/4), 0x3F800000},
738 {(0x00000F50/4), 0x00006AB0},
739 {(0x00000F54/4), 0x3F800000},
740 {(0x00000F54/4), 0x3F800000},
741 {(0x00000F54/4), 0x3F800000},
742 {(0x00000F50/4), 0x00006AC0},
743 {(0x00000F54/4), 0x00000000},
744 {(0x00000F54/4), 0x00000000},
745 {(0x00000F54/4), 0x00000000},
746 {(0x00000F50/4), 0x00006C10},
747 {(0x00000F54/4), 0xBF800000},
748 {(0x00000F50/4), 0x00007030},
749 {(0x00000F54/4), 0x7149F2CA},
750 {(0x00000F50/4), 0x00007040},
751 {(0x00000F54/4), 0x7149F2CA},
752 {(0x00000F50/4), 0x00007050},
753 {(0x00000F54/4), 0x7149F2CA},
754 {(0x00000F50/4), 0x00007060},
755 {(0x00000F54/4), 0x7149F2CA},
756 {(0x00000F50/4), 0x00007070},
757 {(0x00000F54/4), 0x7149F2CA},
758 {(0x00000F50/4), 0x00007080},
759 {(0x00000F54/4), 0x7149F2CA},
760 {(0x00000F50/4), 0x00007090},
761 {(0x00000F54/4), 0x7149F2CA},
762 {(0x00000F50/4), 0x000070A0},
763 {(0x00000F54/4), 0x7149F2CA},
764 {(0x00000F50/4), 0x00006A80},
765 {(0x00000F54/4), 0x00000000},
766 {(0x00000F54/4), 0x00000000},
767 {(0x00000F54/4), 0x3F800000},
768 {(0x00000F50/4), 0x00006AA0},
769 {(0x00000F54/4), 0x00000000},
770 {(0x00000F54/4), 0x00000000},
771 {(0x00000F54/4), 0x00000000},
772 {(0x00000F50/4), 0x00000040},
773 {(0x00000F54/4), 0x00000005},
774 {(0x00000F50/4), 0x00006400},
775 {(0x00000F54/4), 0x3F800000},
776 {(0x00000F54/4), 0x3F800000},
777 {(0x00000F54/4), 0x4B7FFFFF},
778 {(0x00000F54/4), 0x00000000},
779 {(0x00000F50/4), 0x00006410},
780 {(0x00000F54/4), 0xC5000000},
781 {(0x00000F54/4), 0xC5000000},
782 {(0x00000F54/4), 0x00000000},
783 {(0x00000F54/4), 0x00000000},
784 {(0x00000F50/4), 0x00006420},
785 {(0x00000F54/4), 0x00000000},
786 {(0x00000F54/4), 0x00000000},
787 {(0x00000F54/4), 0x00000000},
788 {(0x00000F54/4), 0x00000000},
789 {(0x00000F50/4), 0x00006430},
790 {(0x00000F54/4), 0x00000000},
791 {(0x00000F54/4), 0x00000000},
792 {(0x00000F54/4), 0x00000000},
793 {(0x00000F54/4), 0x00000000},
794 {(0x00000F50/4), 0x000064C0},
795 {(0x00000F54/4), 0x3F800000},
796 {(0x00000F54/4), 0x3F800000},
797 {(0x00000F54/4), 0x477FFFFF},
798 {(0x00000F54/4), 0x3F800000},
799 {(0x00000F50/4), 0x000064D0},
800 {(0x00000F54/4), 0xC5000000},
801 {(0x00000F54/4), 0xC5000000},
802 {(0x00000F54/4), 0x00000000},
803 {(0x00000F54/4), 0x00000000},
804 {(0x00000F50/4), 0x000064E0},
805 {(0x00000F54/4), 0xC4FFF000},
806 {(0x00000F54/4), 0xC4FFF000},
807 {(0x00000F54/4), 0x00000000},
808 {(0x00000F54/4), 0x00000000},
809 {(0x00000F50/4), 0x000064F0},
810 {(0x00000F54/4), 0x00000000},
811 {(0x00000F54/4), 0x00000000},
812 {(0x00000F54/4), 0x00000000},
813 {(0x00000F54/4), 0x00000000},
814 {(0x00000F40/4), 0x30000000},
815 {(0x00000F44/4), 0x00000004},
816 {(0x00000F48/4), 0x10000000},
817 {(0x00000F4C/4), 0x00000000}
818};
819static unsigned nv10TablePRAMIN[][2] =
820{
821 {0x00000000, 0x80000010},
822 {0x00000001, 0x80011145},
823 {0x00000002, 0x80000011},
824 {0x00000003, 0x80011146},
825 {0x00000004, 0x80000012},
826 {0x00000005, 0x80011147},
827 {0x00000006, 0x80000013},
828 {0x00000007, 0x80011148},
829 {0x00000008, 0x80000014},
830 {0x00000009, 0x80011149},
831 {0x0000000A, 0x80000015},
832 {0x0000000B, 0x8001114A},
833 {0x0000000C, 0x80000016},
834 {0x0000000D, 0x80011150},
835 {0x00000020, 0x80000000},
836 {0x00000021, 0x80011142},
837 {0x00000022, 0x80000001},
838 {0x00000023, 0x80011143},
839 {0x00000024, 0x80000002},
840 {0x00000025, 0x80011144},
841 {0x00000026, 0x80000003},
842 {0x00000027, 0x8001114B},
843 {0x00000028, 0x80000004},
844 {0x00000029, 0x8001114C},
845 {0x0000002A, 0x80000005},
846 {0x0000002B, 0x8001114D},
847 {0x0000002C, 0x80000006},
848 {0x0000002D, 0x8001114E},
849 {0x0000002E, 0x80000007},
850 {0x0000002F, 0x8001114F},
851 {0x00000500, 0x00003000},
852 {0x00000501, 0x01FFFFFF},
853 {0x00000502, 0x00000002},
854 {0x00000503, 0x00000002},
855#ifdef __BIG_ENDIAN
856 {0x00000508, 0x01088043},
857#else
858 {0x00000508, 0x01008043},
859#endif
860 {0x0000050A, 0x00000000},
861 {0x0000050B, 0x00000000},
862#ifdef __BIG_ENDIAN
863 {0x0000050C, 0x01088019},
864#else
865 {0x0000050C, 0x01008019},
866#endif
867 {0x0000050E, 0x00000000},
868 {0x0000050F, 0x00000000},
869#ifdef __BIG_ENDIAN
870 {0x00000510, 0x01088018},
871#else
872 {0x00000510, 0x01008018},
873#endif
874 {0x00000512, 0x00000000},
875 {0x00000513, 0x00000000},
876#ifdef __BIG_ENDIAN
877 {0x00000514, 0x01088021},
878#else
879 {0x00000514, 0x01008021},
880#endif
881 {0x00000516, 0x00000000},
882 {0x00000517, 0x00000000},
883#ifdef __BIG_ENDIAN
884 {0x00000518, 0x0108805F},
885#else
886 {0x00000518, 0x0100805F},
887#endif
888 {0x0000051A, 0x00000000},
889 {0x0000051B, 0x00000000},
890#ifdef __BIG_ENDIAN
891 {0x0000051C, 0x0108804B},
892#else
893 {0x0000051C, 0x0100804B},
894#endif
895 {0x0000051E, 0x00000000},
896 {0x0000051F, 0x00000000},
897 {0x00000520, 0x0100A048},
898 {0x00000521, 0x00000D01},
899 {0x00000522, 0x11401140},
900 {0x00000523, 0x00000000},
901 {0x00000524, 0x0300A094},
902 {0x00000525, 0x00000D01},
903 {0x00000526, 0x11401140},
904 {0x00000527, 0x00000000},
905 {0x00000528, 0x0300A095},
906 {0x00000529, 0x00000D01},
907 {0x0000052A, 0x11401140},
908 {0x0000052B, 0x00000000},
909#ifdef __BIG_ENDIAN
910 {0x0000052C, 0x00080058},
911#else
912 {0x0000052C, 0x00000058},
913#endif
914 {0x0000052E, 0x11401140},
915 {0x0000052F, 0x00000000},
916#ifdef __BIG_ENDIAN
917 {0x00000530, 0x00080059},
918#else
919 {0x00000530, 0x00000059},
920#endif
921 {0x00000532, 0x11401140},
922 {0x00000533, 0x00000000},
923 {0x00000534, 0x0000005A},
924 {0x00000536, 0x11401140},
925 {0x00000537, 0x00000000},
926 {0x00000538, 0x0000005B},
927 {0x0000053A, 0x11401140},
928 {0x0000053B, 0x00000000},
929 {0x0000053C, 0x00000093},
930 {0x0000053E, 0x11401140},
931 {0x0000053F, 0x00000000},
932#ifdef __BIG_ENDIAN
933 {0x00000540, 0x0308A01C},
934#else
935 {0x00000540, 0x0300A01C},
936#endif
937 {0x00000542, 0x11401140},
938 {0x00000543, 0x00000000}
939};
940static unsigned nv10TablePRAMIN_8BPP[][2] =
941{
942 /* 0xXXXXXX01 For MSB mono format */
943 /* 0xXXXXXX02 For LSB mono format */
944 {0x00000509, 0x00000302},
945 {0x0000050D, 0x00000302},
946 {0x00000511, 0x00000202},
947 {0x00000515, 0x00000302},
948 {0x00000519, 0x00000302},
949 {0x0000051D, 0x00000302},
950 {0x0000052D, 0x00000302},
951 {0x0000052E, 0x00000302},
952 {0x00000535, 0x00000000},
953 {0x00000539, 0x00000000},
954 {0x0000053D, 0x00000000},
955 {0x00000541, 0x00000302}
956};
957static unsigned nv10TablePRAMIN_15BPP[][2] =
958{
959 /* 0xXXXXXX01 For MSB mono format */
960 /* 0xXXXXXX02 For LSB mono format */
961 {0x00000509, 0x00000902},
962 {0x0000050D, 0x00000902},
963 {0x00000511, 0x00000802},
964 {0x00000515, 0x00000902},
965 {0x00000519, 0x00000902},
966 {0x0000051D, 0x00000902},
967 {0x0000052D, 0x00000902},
968 {0x0000052E, 0x00000902},
969 {0x00000535, 0x00000902},
970 {0x00000539, 0x00000902},
971 {0x0000053D, 0x00000902},
972 {0x00000541, 0x00000902}
973};
974static unsigned nv10TablePRAMIN_16BPP[][2] =
975{
976 /* 0xXXXXXX01 For MSB mono format */
977 /* 0xXXXXXX02 For LSB mono format */
978 {0x00000509, 0x00000C02},
979 {0x0000050D, 0x00000C02},
980 {0x00000511, 0x00000B02},
981 {0x00000515, 0x00000C02},
982 {0x00000519, 0x00000C02},
983 {0x0000051D, 0x00000C02},
984 {0x0000052D, 0x00000C02},
985 {0x0000052E, 0x00000C02},
986 {0x00000535, 0x00000C02},
987 {0x00000539, 0x00000C02},
988 {0x0000053D, 0x00000C02},
989 {0x00000541, 0x00000C02}
990};
991static unsigned nv10TablePRAMIN_32BPP[][2] =
992{
993 /* 0xXXXXXX01 For MSB mono format */
994 /* 0xXXXXXX02 For LSB mono format */
995 {0x00000509, 0x00000E02},
996 {0x0000050D, 0x00000E02},
997 {0x00000511, 0x00000D02},
998 {0x00000515, 0x00000E02},
999 {0x00000519, 0x00000E02},
1000 {0x0000051D, 0x00000E02},
1001 {0x0000052D, 0x00000E02},
1002 {0x0000052E, 0x00000E02},
1003 {0x00000535, 0x00000E02},
1004 {0x00000539, 0x00000E02},
1005 {0x0000053D, 0x00000E02},
1006 {0x00000541, 0x00000E02}
1007};
1008
diff --git a/drivers/video/riva/rivafb-i2c.c b/drivers/video/riva/rivafb-i2c.c
deleted file mode 100644
index 6a183375ced1..000000000000
--- a/drivers/video/riva/rivafb-i2c.c
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
7 *
8 * Based on radeonfb-i2c.c
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19#include <linux/fb.h>
20#include <linux/jiffies.h>
21
22#include <asm/io.h>
23
24#include "rivafb.h"
25#include "../edid.h"
26
27static void riva_gpio_setscl(void* data, int state)
28{
29 struct riva_i2c_chan *chan = data;
30 struct riva_par *par = chan->par;
31 u32 val;
32
33 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
34 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
35
36 if (state)
37 val |= 0x20;
38 else
39 val &= ~0x20;
40
41 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
42 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
43}
44
45static void riva_gpio_setsda(void* data, int state)
46{
47 struct riva_i2c_chan *chan = data;
48 struct riva_par *par = chan->par;
49 u32 val;
50
51 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
52 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
53
54 if (state)
55 val |= 0x10;
56 else
57 val &= ~0x10;
58
59 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
60 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
61}
62
63static int riva_gpio_getscl(void* data)
64{
65 struct riva_i2c_chan *chan = data;
66 struct riva_par *par = chan->par;
67 u32 val = 0;
68
69 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
70 if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04)
71 val = 1;
72
73 return val;
74}
75
76static int riva_gpio_getsda(void* data)
77{
78 struct riva_i2c_chan *chan = data;
79 struct riva_par *par = chan->par;
80 u32 val = 0;
81
82 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
83 if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08)
84 val = 1;
85
86 return val;
87}
88
89static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name,
90 unsigned int i2c_class)
91{
92 int rc;
93
94 strcpy(chan->adapter.name, name);
95 chan->adapter.owner = THIS_MODULE;
96 chan->adapter.class = i2c_class;
97 chan->adapter.algo_data = &chan->algo;
98 chan->adapter.dev.parent = &chan->par->pdev->dev;
99 chan->algo.setsda = riva_gpio_setsda;
100 chan->algo.setscl = riva_gpio_setscl;
101 chan->algo.getsda = riva_gpio_getsda;
102 chan->algo.getscl = riva_gpio_getscl;
103 chan->algo.udelay = 40;
104 chan->algo.timeout = msecs_to_jiffies(2);
105 chan->algo.data = chan;
106
107 i2c_set_adapdata(&chan->adapter, chan);
108
109 /* Raise SCL and SDA */
110 riva_gpio_setsda(chan, 1);
111 riva_gpio_setscl(chan, 1);
112 udelay(20);
113
114 rc = i2c_bit_add_bus(&chan->adapter);
115 if (rc == 0)
116 dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name);
117 else {
118 dev_warn(&chan->par->pdev->dev,
119 "Failed to register I2C bus %s.\n", name);
120 chan->par = NULL;
121 }
122
123 return rc;
124}
125
126void riva_create_i2c_busses(struct riva_par *par)
127{
128 par->chan[0].par = par;
129 par->chan[1].par = par;
130 par->chan[2].par = par;
131
132 par->chan[0].ddc_base = 0x36;
133 par->chan[1].ddc_base = 0x3e;
134 par->chan[2].ddc_base = 0x50;
135 riva_setup_i2c_bus(&par->chan[0], "BUS1", I2C_CLASS_HWMON);
136 riva_setup_i2c_bus(&par->chan[1], "BUS2", 0);
137 riva_setup_i2c_bus(&par->chan[2], "BUS3", 0);
138}
139
140void riva_delete_i2c_busses(struct riva_par *par)
141{
142 int i;
143
144 for (i = 0; i < 3; i++) {
145 if (!par->chan[i].par)
146 continue;
147 i2c_del_adapter(&par->chan[i].adapter);
148 par->chan[i].par = NULL;
149 }
150}
151
152int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid)
153{
154 u8 *edid = NULL;
155
156 if (par->chan[conn].par)
157 edid = fb_ddc_read(&par->chan[conn].adapter);
158
159 if (out_edid)
160 *out_edid = edid;
161 if (!edid)
162 return 1;
163
164 return 0;
165}
166
diff --git a/drivers/video/riva/rivafb.h b/drivers/video/riva/rivafb.h
deleted file mode 100644
index d9f107b704c6..000000000000
--- a/drivers/video/riva/rivafb.h
+++ /dev/null
@@ -1,77 +0,0 @@
1#ifndef __RIVAFB_H
2#define __RIVAFB_H
3
4#include <linux/fb.h>
5#include <video/vga.h>
6#include <linux/i2c.h>
7#include <linux/i2c-algo-bit.h>
8
9#include "riva_hw.h"
10
11/* GGI compatibility macros */
12#define NUM_SEQ_REGS 0x05
13#define NUM_CRT_REGS 0x41
14#define NUM_GRC_REGS 0x09
15#define NUM_ATC_REGS 0x15
16
17/* I2C */
18#define DDC_SCL_READ_MASK (1 << 2)
19#define DDC_SCL_WRITE_MASK (1 << 5)
20#define DDC_SDA_READ_MASK (1 << 3)
21#define DDC_SDA_WRITE_MASK (1 << 4)
22
23/* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
24 * From KGI originally. */
25struct riva_regs {
26 u8 attr[NUM_ATC_REGS];
27 u8 crtc[NUM_CRT_REGS];
28 u8 gra[NUM_GRC_REGS];
29 u8 seq[NUM_SEQ_REGS];
30 u8 misc_output;
31 RIVA_HW_STATE ext;
32};
33
34struct riva_par;
35
36struct riva_i2c_chan {
37 struct riva_par *par;
38 unsigned long ddc_base;
39 struct i2c_adapter adapter;
40 struct i2c_algo_bit_data algo;
41};
42
43struct riva_par {
44 RIVA_HW_INST riva; /* interface to riva_hw.c */
45 u32 pseudo_palette[16]; /* default palette */
46 u32 palette[16]; /* for Riva128 */
47 u8 __iomem *ctrl_base; /* virtual control register base addr */
48 unsigned dclk_max; /* max DCLK */
49
50 struct riva_regs initial_state; /* initial startup video mode */
51 struct riva_regs current_state;
52#ifdef CONFIG_X86
53 struct vgastate state;
54#endif
55 struct mutex open_lock;
56 unsigned int ref_count;
57 unsigned char *EDID;
58 unsigned int Chipset;
59 int forceCRTC;
60 Bool SecondCRTC;
61 int FlatPanel;
62 struct pci_dev *pdev;
63 int cursor_reset;
64#ifdef CONFIG_MTRR
65 struct { int vram; int vram_valid; } mtrr;
66#endif
67 struct riva_i2c_chan chan[3];
68};
69
70void riva_common_setup(struct riva_par *);
71unsigned long riva_get_memlen(struct riva_par *);
72unsigned long riva_get_maxdclk(struct riva_par *);
73void riva_delete_i2c_busses(struct riva_par *par);
74void riva_create_i2c_busses(struct riva_par *par);
75int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid);
76
77#endif /* __RIVAFB_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 19:11:36 -0400