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authorArchit Taneja <archit@ti.com>2011-05-06 02:15:49 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-05-11 07:20:52 -0400
commit9b372c2d9da43be00e8a267730a2428e0eae12e8 (patch)
treec95ccff308f5410fefc3d9d307e3a458ae3acf76 /drivers/video/omap2/dss
parent5bdd3c9a7da3ddf820d9d479530ceecde9d4a316 (diff)
OMAP: DSS2: Clean up DISPC overlay register definitions
Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss')
-rw-r--r--drivers/video/omap2/dss/dispc.c884
-rw-r--r--drivers/video/omap2/dss/dispc.h386
2 files changed, 771 insertions, 499 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index cbaaa3568455..46f456adcb61 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -41,95 +41,11 @@
41 41
42#include "dss.h" 42#include "dss.h"
43#include "dss_features.h" 43#include "dss_features.h"
44#include "dispc.h"
44 45
45/* DISPC */ 46/* DISPC */
46#define DISPC_SZ_REGS SZ_4K 47#define DISPC_SZ_REGS SZ_4K
47 48
48struct dispc_reg { u16 idx; };
49
50#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
51
52/*
53 * DISPC common registers and
54 * DISPC channel registers , ch = 0 for LCD, ch = 1 for
55 * DIGIT, and ch = 2 for LCD2
56 */
57#define DISPC_REVISION DISPC_REG(0x0000)
58#define DISPC_SYSCONFIG DISPC_REG(0x0010)
59#define DISPC_SYSSTATUS DISPC_REG(0x0014)
60#define DISPC_IRQSTATUS DISPC_REG(0x0018)
61#define DISPC_IRQENABLE DISPC_REG(0x001C)
62#define DISPC_CONTROL DISPC_REG(0x0040)
63#define DISPC_CONTROL2 DISPC_REG(0x0238)
64#define DISPC_CONFIG DISPC_REG(0x0044)
65#define DISPC_CONFIG2 DISPC_REG(0x0620)
66#define DISPC_CAPABLE DISPC_REG(0x0048)
67#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
68 (ch == 1 ? 0x0050 : 0x03AC))
69#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
70 (ch == 1 ? 0x0058 : 0x03B0))
71#define DISPC_LINE_STATUS DISPC_REG(0x005C)
72#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
73#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
74#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
75#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
76#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
77#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
78#define DISPC_SIZE_DIG DISPC_REG(0x0078)
79#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
80
81/* DISPC GFX plane */
82#define DISPC_GFX_BA0 DISPC_REG(0x0080)
83#define DISPC_GFX_BA1 DISPC_REG(0x0084)
84#define DISPC_GFX_POSITION DISPC_REG(0x0088)
85#define DISPC_GFX_SIZE DISPC_REG(0x008C)
86#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
87#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
88#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
89#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
90#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
91#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
92#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
93
94#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
95#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
96#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
97#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
98#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
99#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
100
101#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
102
103/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
104#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
105
106#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
107#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
108#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
109#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
110#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
111#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
112#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
113#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
114#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
115#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
116#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
117#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
118#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
119
120/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
121#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
122/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
123#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
124/* coef index i = {0, 1, 2, 3, 4} */
125#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
126/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
127#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
128
129#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
130
131#define DISPC_DIVISOR DISPC_REG(0x0804)
132
133#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ 49#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
134 DISPC_IRQ_OCP_ERR | \ 50 DISPC_IRQ_OCP_ERR | \
135 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ 51 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
@@ -167,10 +83,6 @@ struct dispc_v_coef {
167#define REG_FLD_MOD(idx, val, start, end) \ 83#define REG_FLD_MOD(idx, val, start, end) \
168 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) 84 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
169 85
170static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
171 DISPC_VID_ATTRIBUTES(0),
172 DISPC_VID_ATTRIBUTES(1) };
173
174struct dispc_irq_stats { 86struct dispc_irq_stats {
175 unsigned long last_reset; 87 unsigned long last_reset;
176 unsigned irq_count; 88 unsigned irq_count;
@@ -248,16 +160,16 @@ void dispc_save_context(void)
248 SR(CONFIG2); 160 SR(CONFIG2);
249 } 161 }
250 162
251 SR(GFX_BA0); 163 SR(OVL_BA0(OMAP_DSS_GFX));
252 SR(GFX_BA1); 164 SR(OVL_BA1(OMAP_DSS_GFX));
253 SR(GFX_POSITION); 165 SR(OVL_POSITION(OMAP_DSS_GFX));
254 SR(GFX_SIZE); 166 SR(OVL_SIZE(OMAP_DSS_GFX));
255 SR(GFX_ATTRIBUTES); 167 SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
256 SR(GFX_FIFO_THRESHOLD); 168 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
257 SR(GFX_ROW_INC); 169 SR(OVL_ROW_INC(OMAP_DSS_GFX));
258 SR(GFX_PIXEL_INC); 170 SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
259 SR(GFX_WINDOW_SKIP); 171 SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
260 SR(GFX_TABLE_BA); 172 SR(OVL_TABLE_BA(OMAP_DSS_GFX));
261 173
262 SR(DATA_CYCLE1(0)); 174 SR(DATA_CYCLE1(0));
263 SR(DATA_CYCLE2(0)); 175 SR(DATA_CYCLE2(0));
@@ -276,105 +188,105 @@ void dispc_save_context(void)
276 SR(DATA_CYCLE3(2)); 188 SR(DATA_CYCLE3(2));
277 } 189 }
278 190
279 SR(GFX_PRELOAD); 191 SR(OVL_PRELOAD(OMAP_DSS_GFX));
280 192
281 /* VID1 */ 193 /* VID1 */
282 SR(VID_BA0(0)); 194 SR(OVL_BA0(OMAP_DSS_VIDEO1));
283 SR(VID_BA1(0)); 195 SR(OVL_BA1(OMAP_DSS_VIDEO1));
284 SR(VID_POSITION(0)); 196 SR(OVL_POSITION(OMAP_DSS_VIDEO1));
285 SR(VID_SIZE(0)); 197 SR(OVL_SIZE(OMAP_DSS_VIDEO1));
286 SR(VID_ATTRIBUTES(0)); 198 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
287 SR(VID_FIFO_THRESHOLD(0)); 199 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
288 SR(VID_ROW_INC(0)); 200 SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
289 SR(VID_PIXEL_INC(0)); 201 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
290 SR(VID_FIR(0)); 202 SR(OVL_FIR(OMAP_DSS_VIDEO1));
291 SR(VID_PICTURE_SIZE(0)); 203 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
292 SR(VID_ACCU0(0)); 204 SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
293 SR(VID_ACCU1(0)); 205 SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
294 206
295 SR(VID_FIR_COEF_H(0, 0)); 207 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
296 SR(VID_FIR_COEF_H(0, 1)); 208 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
297 SR(VID_FIR_COEF_H(0, 2)); 209 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
298 SR(VID_FIR_COEF_H(0, 3)); 210 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
299 SR(VID_FIR_COEF_H(0, 4)); 211 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
300 SR(VID_FIR_COEF_H(0, 5)); 212 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
301 SR(VID_FIR_COEF_H(0, 6)); 213 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
302 SR(VID_FIR_COEF_H(0, 7)); 214 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
303 215
304 SR(VID_FIR_COEF_HV(0, 0)); 216 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
305 SR(VID_FIR_COEF_HV(0, 1)); 217 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
306 SR(VID_FIR_COEF_HV(0, 2)); 218 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
307 SR(VID_FIR_COEF_HV(0, 3)); 219 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
308 SR(VID_FIR_COEF_HV(0, 4)); 220 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
309 SR(VID_FIR_COEF_HV(0, 5)); 221 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
310 SR(VID_FIR_COEF_HV(0, 6)); 222 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
311 SR(VID_FIR_COEF_HV(0, 7)); 223 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
312 224
313 SR(VID_CONV_COEF(0, 0)); 225 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
314 SR(VID_CONV_COEF(0, 1)); 226 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
315 SR(VID_CONV_COEF(0, 2)); 227 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
316 SR(VID_CONV_COEF(0, 3)); 228 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
317 SR(VID_CONV_COEF(0, 4)); 229 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
318 230
319 SR(VID_FIR_COEF_V(0, 0)); 231 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
320 SR(VID_FIR_COEF_V(0, 1)); 232 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
321 SR(VID_FIR_COEF_V(0, 2)); 233 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
322 SR(VID_FIR_COEF_V(0, 3)); 234 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
323 SR(VID_FIR_COEF_V(0, 4)); 235 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
324 SR(VID_FIR_COEF_V(0, 5)); 236 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
325 SR(VID_FIR_COEF_V(0, 6)); 237 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
326 SR(VID_FIR_COEF_V(0, 7)); 238 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
327 239
328 SR(VID_PRELOAD(0)); 240 SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
329 241
330 /* VID2 */ 242 /* VID2 */
331 SR(VID_BA0(1)); 243 SR(OVL_BA0(OMAP_DSS_VIDEO2));
332 SR(VID_BA1(1)); 244 SR(OVL_BA1(OMAP_DSS_VIDEO2));
333 SR(VID_POSITION(1)); 245 SR(OVL_POSITION(OMAP_DSS_VIDEO2));
334 SR(VID_SIZE(1)); 246 SR(OVL_SIZE(OMAP_DSS_VIDEO2));
335 SR(VID_ATTRIBUTES(1)); 247 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
336 SR(VID_FIFO_THRESHOLD(1)); 248 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
337 SR(VID_ROW_INC(1)); 249 SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
338 SR(VID_PIXEL_INC(1)); 250 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
339 SR(VID_FIR(1)); 251 SR(OVL_FIR(OMAP_DSS_VIDEO2));
340 SR(VID_PICTURE_SIZE(1)); 252 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
341 SR(VID_ACCU0(1)); 253 SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
342 SR(VID_ACCU1(1)); 254 SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
343 255
344 SR(VID_FIR_COEF_H(1, 0)); 256 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
345 SR(VID_FIR_COEF_H(1, 1)); 257 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
346 SR(VID_FIR_COEF_H(1, 2)); 258 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
347 SR(VID_FIR_COEF_H(1, 3)); 259 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
348 SR(VID_FIR_COEF_H(1, 4)); 260 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
349 SR(VID_FIR_COEF_H(1, 5)); 261 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
350 SR(VID_FIR_COEF_H(1, 6)); 262 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
351 SR(VID_FIR_COEF_H(1, 7)); 263 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
352 264
353 SR(VID_FIR_COEF_HV(1, 0)); 265 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
354 SR(VID_FIR_COEF_HV(1, 1)); 266 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
355 SR(VID_FIR_COEF_HV(1, 2)); 267 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
356 SR(VID_FIR_COEF_HV(1, 3)); 268 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
357 SR(VID_FIR_COEF_HV(1, 4)); 269 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
358 SR(VID_FIR_COEF_HV(1, 5)); 270 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
359 SR(VID_FIR_COEF_HV(1, 6)); 271 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
360 SR(VID_FIR_COEF_HV(1, 7)); 272 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
361 273
362 SR(VID_CONV_COEF(1, 0)); 274 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
363 SR(VID_CONV_COEF(1, 1)); 275 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
364 SR(VID_CONV_COEF(1, 2)); 276 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
365 SR(VID_CONV_COEF(1, 3)); 277 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
366 SR(VID_CONV_COEF(1, 4)); 278 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
367 279
368 SR(VID_FIR_COEF_V(1, 0)); 280 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
369 SR(VID_FIR_COEF_V(1, 1)); 281 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
370 SR(VID_FIR_COEF_V(1, 2)); 282 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
371 SR(VID_FIR_COEF_V(1, 3)); 283 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
372 SR(VID_FIR_COEF_V(1, 4)); 284 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
373 SR(VID_FIR_COEF_V(1, 5)); 285 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
374 SR(VID_FIR_COEF_V(1, 6)); 286 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
375 SR(VID_FIR_COEF_V(1, 7)); 287 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
376 288
377 SR(VID_PRELOAD(1)); 289 SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
378 290
379 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 291 if (dss_has_feature(FEAT_CORE_CLK_DIV))
380 SR(DIVISOR); 292 SR(DIVISOR);
@@ -409,16 +321,17 @@ void dispc_restore_context(void)
409 RR(CONFIG2); 321 RR(CONFIG2);
410 } 322 }
411 323
412 RR(GFX_BA0); 324 RR(OVL_BA0(OMAP_DSS_GFX));
413 RR(GFX_BA1); 325 RR(OVL_BA1(OMAP_DSS_GFX));
414 RR(GFX_POSITION); 326 RR(OVL_POSITION(OMAP_DSS_GFX));
415 RR(GFX_SIZE); 327 RR(OVL_SIZE(OMAP_DSS_GFX));
416 RR(GFX_ATTRIBUTES); 328 RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
417 RR(GFX_FIFO_THRESHOLD); 329 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
418 RR(GFX_ROW_INC); 330 RR(OVL_ROW_INC(OMAP_DSS_GFX));
419 RR(GFX_PIXEL_INC); 331 RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
420 RR(GFX_WINDOW_SKIP); 332 RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
421 RR(GFX_TABLE_BA); 333 RR(OVL_TABLE_BA(OMAP_DSS_GFX));
334
422 335
423 RR(DATA_CYCLE1(0)); 336 RR(DATA_CYCLE1(0));
424 RR(DATA_CYCLE2(0)); 337 RR(DATA_CYCLE2(0));
@@ -437,105 +350,105 @@ void dispc_restore_context(void)
437 RR(CPR_COEF_R(2)); 350 RR(CPR_COEF_R(2));
438 } 351 }
439 352
440 RR(GFX_PRELOAD); 353 RR(OVL_PRELOAD(OMAP_DSS_GFX));
441 354
442 /* VID1 */ 355 /* VID1 */
443 RR(VID_BA0(0)); 356 RR(OVL_BA0(OMAP_DSS_VIDEO1));
444 RR(VID_BA1(0)); 357 RR(OVL_BA1(OMAP_DSS_VIDEO1));
445 RR(VID_POSITION(0)); 358 RR(OVL_POSITION(OMAP_DSS_VIDEO1));
446 RR(VID_SIZE(0)); 359 RR(OVL_SIZE(OMAP_DSS_VIDEO1));
447 RR(VID_ATTRIBUTES(0)); 360 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
448 RR(VID_FIFO_THRESHOLD(0)); 361 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
449 RR(VID_ROW_INC(0)); 362 RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
450 RR(VID_PIXEL_INC(0)); 363 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
451 RR(VID_FIR(0)); 364 RR(OVL_FIR(OMAP_DSS_VIDEO1));
452 RR(VID_PICTURE_SIZE(0)); 365 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
453 RR(VID_ACCU0(0)); 366 RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
454 RR(VID_ACCU1(0)); 367 RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
455 368
456 RR(VID_FIR_COEF_H(0, 0)); 369 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
457 RR(VID_FIR_COEF_H(0, 1)); 370 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
458 RR(VID_FIR_COEF_H(0, 2)); 371 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
459 RR(VID_FIR_COEF_H(0, 3)); 372 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
460 RR(VID_FIR_COEF_H(0, 4)); 373 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
461 RR(VID_FIR_COEF_H(0, 5)); 374 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
462 RR(VID_FIR_COEF_H(0, 6)); 375 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
463 RR(VID_FIR_COEF_H(0, 7)); 376 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
464 377
465 RR(VID_FIR_COEF_HV(0, 0)); 378 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
466 RR(VID_FIR_COEF_HV(0, 1)); 379 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
467 RR(VID_FIR_COEF_HV(0, 2)); 380 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
468 RR(VID_FIR_COEF_HV(0, 3)); 381 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
469 RR(VID_FIR_COEF_HV(0, 4)); 382 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
470 RR(VID_FIR_COEF_HV(0, 5)); 383 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
471 RR(VID_FIR_COEF_HV(0, 6)); 384 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
472 RR(VID_FIR_COEF_HV(0, 7)); 385 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
473 386
474 RR(VID_CONV_COEF(0, 0)); 387 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
475 RR(VID_CONV_COEF(0, 1)); 388 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
476 RR(VID_CONV_COEF(0, 2)); 389 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
477 RR(VID_CONV_COEF(0, 3)); 390 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
478 RR(VID_CONV_COEF(0, 4)); 391 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
479 392
480 RR(VID_FIR_COEF_V(0, 0)); 393 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
481 RR(VID_FIR_COEF_V(0, 1)); 394 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
482 RR(VID_FIR_COEF_V(0, 2)); 395 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
483 RR(VID_FIR_COEF_V(0, 3)); 396 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
484 RR(VID_FIR_COEF_V(0, 4)); 397 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
485 RR(VID_FIR_COEF_V(0, 5)); 398 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
486 RR(VID_FIR_COEF_V(0, 6)); 399 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
487 RR(VID_FIR_COEF_V(0, 7)); 400 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
488 401
489 RR(VID_PRELOAD(0)); 402 RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
490 403
491 /* VID2 */ 404 /* VID2 */
492 RR(VID_BA0(1)); 405 RR(OVL_BA0(OMAP_DSS_VIDEO2));
493 RR(VID_BA1(1)); 406 RR(OVL_BA1(OMAP_DSS_VIDEO2));
494 RR(VID_POSITION(1)); 407 RR(OVL_POSITION(OMAP_DSS_VIDEO2));
495 RR(VID_SIZE(1)); 408 RR(OVL_SIZE(OMAP_DSS_VIDEO2));
496 RR(VID_ATTRIBUTES(1)); 409 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
497 RR(VID_FIFO_THRESHOLD(1)); 410 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
498 RR(VID_ROW_INC(1)); 411 RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
499 RR(VID_PIXEL_INC(1)); 412 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
500 RR(VID_FIR(1)); 413 RR(OVL_FIR(OMAP_DSS_VIDEO2));
501 RR(VID_PICTURE_SIZE(1)); 414 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
502 RR(VID_ACCU0(1)); 415 RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
503 RR(VID_ACCU1(1)); 416 RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
504 417
505 RR(VID_FIR_COEF_H(1, 0)); 418 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
506 RR(VID_FIR_COEF_H(1, 1)); 419 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
507 RR(VID_FIR_COEF_H(1, 2)); 420 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
508 RR(VID_FIR_COEF_H(1, 3)); 421 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
509 RR(VID_FIR_COEF_H(1, 4)); 422 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
510 RR(VID_FIR_COEF_H(1, 5)); 423 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
511 RR(VID_FIR_COEF_H(1, 6)); 424 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
512 RR(VID_FIR_COEF_H(1, 7)); 425 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
513 426
514 RR(VID_FIR_COEF_HV(1, 0)); 427 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
515 RR(VID_FIR_COEF_HV(1, 1)); 428 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
516 RR(VID_FIR_COEF_HV(1, 2)); 429 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
517 RR(VID_FIR_COEF_HV(1, 3)); 430 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
518 RR(VID_FIR_COEF_HV(1, 4)); 431 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
519 RR(VID_FIR_COEF_HV(1, 5)); 432 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
520 RR(VID_FIR_COEF_HV(1, 6)); 433 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
521 RR(VID_FIR_COEF_HV(1, 7)); 434 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
522 435
523 RR(VID_CONV_COEF(1, 0)); 436 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
524 RR(VID_CONV_COEF(1, 1)); 437 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
525 RR(VID_CONV_COEF(1, 2)); 438 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
526 RR(VID_CONV_COEF(1, 3)); 439 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
527 RR(VID_CONV_COEF(1, 4)); 440 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
528 441
529 RR(VID_FIR_COEF_V(1, 0)); 442 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
530 RR(VID_FIR_COEF_V(1, 1)); 443 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
531 RR(VID_FIR_COEF_V(1, 2)); 444 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
532 RR(VID_FIR_COEF_V(1, 3)); 445 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
533 RR(VID_FIR_COEF_V(1, 4)); 446 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
534 RR(VID_FIR_COEF_V(1, 5)); 447 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
535 RR(VID_FIR_COEF_V(1, 6)); 448 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
536 RR(VID_FIR_COEF_V(1, 7)); 449 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
537 450
538 RR(VID_PRELOAD(1)); 451 RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
539 452
540 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 453 if (dss_has_feature(FEAT_CORE_CLK_DIV))
541 RR(DIVISOR); 454 RR(DIVISOR);
@@ -632,23 +545,17 @@ end:
632 545
633static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value) 546static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
634{ 547{
635 BUG_ON(plane == OMAP_DSS_GFX); 548 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
636
637 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
638} 549}
639 550
640static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value) 551static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
641{ 552{
642 BUG_ON(plane == OMAP_DSS_GFX); 553 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
643
644 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
645} 554}
646 555
647static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value) 556static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
648{ 557{
649 BUG_ON(plane == OMAP_DSS_GFX); 558 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
650
651 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
652} 559}
653 560
654static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup, 561static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
@@ -779,72 +686,73 @@ static void _dispc_setup_color_conv_coef(void)
779 686
780 ct = &ctbl_bt601_5; 687 ct = &ctbl_bt601_5;
781 688
782 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry)); 689 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
783 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb)); 690 CVAL(ct->rcr, ct->ry));
784 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr)); 691 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
785 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by)); 692 CVAL(ct->gy, ct->rcb));
786 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb)); 693 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
787 694 CVAL(ct->gcb, ct->gcr));
788 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry)); 695 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
789 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb)); 696 CVAL(ct->bcr, ct->by));
790 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr)); 697 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
791 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by)); 698 CVAL(0, ct->bcb));
792 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb)); 699
700 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
701 CVAL(ct->rcr, ct->ry));
702 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
703 CVAL(ct->gy, ct->rcb));
704 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
705 CVAL(ct->gcb, ct->gcr));
706 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
707 CVAL(ct->bcr, ct->by));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
709 CVAL(0, ct->bcb));
793 710
794#undef CVAL 711#undef CVAL
795 712
796 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11); 713 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
797 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11); 714 ct->full_range, 11, 11);
715 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
716 ct->full_range, 11, 11);
798} 717}
799 718
800 719
801static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr) 720static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
802{ 721{
803 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0, 722 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
804 DISPC_VID_BA0(0),
805 DISPC_VID_BA0(1) };
806
807 dispc_write_reg(ba0_reg[plane], paddr);
808} 723}
809 724
810static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr) 725static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
811{ 726{
812 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1, 727 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
813 DISPC_VID_BA1(0),
814 DISPC_VID_BA1(1) };
815
816 dispc_write_reg(ba1_reg[plane], paddr);
817} 728}
818 729
819static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y) 730static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
820{ 731{
821 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
822 DISPC_VID_POSITION(0),
823 DISPC_VID_POSITION(1) };
824
825 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); 732 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
826 dispc_write_reg(pos_reg[plane], val); 733
734 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
827} 735}
828 736
829static void _dispc_set_pic_size(enum omap_plane plane, int width, int height) 737static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
830{ 738{
831 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
832 DISPC_VID_PICTURE_SIZE(0),
833 DISPC_VID_PICTURE_SIZE(1) };
834 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 739 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
835 dispc_write_reg(siz_reg[plane], val); 740
741 if (plane == OMAP_DSS_GFX)
742 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
743 else
744 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
836} 745}
837 746
838static void _dispc_set_vid_size(enum omap_plane plane, int width, int height) 747static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
839{ 748{
840 u32 val; 749 u32 val;
841 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
842 DISPC_VID_SIZE(1) };
843 750
844 BUG_ON(plane == OMAP_DSS_GFX); 751 BUG_ON(plane == OMAP_DSS_GFX);
845 752
846 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 753 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
847 dispc_write_reg(vsi_reg[plane-1], val); 754
755 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
848} 756}
849 757
850static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable) 758static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
@@ -856,7 +764,7 @@ static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
856 plane == OMAP_DSS_VIDEO1) 764 plane == OMAP_DSS_VIDEO1)
857 return; 765 return;
858 766
859 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28); 767 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
860} 768}
861 769
862static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha) 770static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
@@ -876,20 +784,12 @@ static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
876 784
877static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc) 785static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
878{ 786{
879 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC, 787 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
880 DISPC_VID_PIXEL_INC(0),
881 DISPC_VID_PIXEL_INC(1) };
882
883 dispc_write_reg(ri_reg[plane], inc);
884} 788}
885 789
886static void _dispc_set_row_inc(enum omap_plane plane, s32 inc) 790static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
887{ 791{
888 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC, 792 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
889 DISPC_VID_ROW_INC(0),
890 DISPC_VID_ROW_INC(1) };
891
892 dispc_write_reg(ri_reg[plane], inc);
893} 793}
894 794
895static void _dispc_set_color_mode(enum omap_plane plane, 795static void _dispc_set_color_mode(enum omap_plane plane,
@@ -930,7 +830,7 @@ static void _dispc_set_color_mode(enum omap_plane plane,
930 BUG(); break; 830 BUG(); break;
931 } 831 }
932 832
933 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1); 833 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
934} 834}
935 835
936static void _dispc_set_channel_out(enum omap_plane plane, 836static void _dispc_set_channel_out(enum omap_plane plane,
@@ -953,7 +853,7 @@ static void _dispc_set_channel_out(enum omap_plane plane,
953 return; 853 return;
954 } 854 }
955 855
956 val = dispc_read_reg(dispc_reg_att[plane]); 856 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
957 if (dss_has_feature(FEAT_MGR_LCD2)) { 857 if (dss_has_feature(FEAT_MGR_LCD2)) {
958 switch (channel) { 858 switch (channel) {
959 case OMAP_DSS_CHANNEL_LCD: 859 case OMAP_DSS_CHANNEL_LCD:
@@ -977,7 +877,7 @@ static void _dispc_set_channel_out(enum omap_plane plane,
977 } else { 877 } else {
978 val = FLD_MOD(val, channel, shift, shift); 878 val = FLD_MOD(val, channel, shift, shift);
979 } 879 }
980 dispc_write_reg(dispc_reg_att[plane], val); 880 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
981} 881}
982 882
983void dispc_set_burst_size(enum omap_plane plane, 883void dispc_set_burst_size(enum omap_plane plane,
@@ -1001,9 +901,9 @@ void dispc_set_burst_size(enum omap_plane plane,
1001 return; 901 return;
1002 } 902 }
1003 903
1004 val = dispc_read_reg(dispc_reg_att[plane]); 904 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1005 val = FLD_MOD(val, burst_size, shift+1, shift); 905 val = FLD_MOD(val, burst_size, shift+1, shift);
1006 dispc_write_reg(dispc_reg_att[plane], val); 906 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1007 907
1008 enable_clocks(0); 908 enable_clocks(0);
1009} 909}
@@ -1028,9 +928,9 @@ static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1028 928
1029 BUG_ON(plane == OMAP_DSS_GFX); 929 BUG_ON(plane == OMAP_DSS_GFX);
1030 930
1031 val = dispc_read_reg(dispc_reg_att[plane]); 931 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1032 val = FLD_MOD(val, enable, 9, 9); 932 val = FLD_MOD(val, enable, 9, 9);
1033 dispc_write_reg(dispc_reg_att[plane], val); 933 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1034} 934}
1035 935
1036void dispc_enable_replication(enum omap_plane plane, bool enable) 936void dispc_enable_replication(enum omap_plane plane, bool enable)
@@ -1043,7 +943,7 @@ void dispc_enable_replication(enum omap_plane plane, bool enable)
1043 bit = 10; 943 bit = 10;
1044 944
1045 enable_clocks(1); 945 enable_clocks(1);
1046 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit); 946 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1047 enable_clocks(0); 947 enable_clocks(0);
1048} 948}
1049 949
@@ -1069,9 +969,6 @@ void dispc_set_digit_size(u16 width, u16 height)
1069 969
1070static void dispc_read_plane_fifo_sizes(void) 970static void dispc_read_plane_fifo_sizes(void)
1071{ 971{
1072 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1073 DISPC_VID_FIFO_SIZE_STATUS(0),
1074 DISPC_VID_FIFO_SIZE_STATUS(1) };
1075 u32 size; 972 u32 size;
1076 int plane; 973 int plane;
1077 u8 start, end; 974 u8 start, end;
@@ -1081,7 +978,8 @@ static void dispc_read_plane_fifo_sizes(void)
1081 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); 978 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1082 979
1083 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) { 980 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1084 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end); 981 size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
982 start, end);
1085 dispc.fifo_size[plane] = size; 983 dispc.fifo_size[plane] = size;
1086 } 984 }
1087 985
@@ -1095,23 +993,22 @@ u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1095 993
1096void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) 994void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1097{ 995{
1098 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1099 DISPC_VID_FIFO_THRESHOLD(0),
1100 DISPC_VID_FIFO_THRESHOLD(1) };
1101 u8 hi_start, hi_end, lo_start, lo_end; 996 u8 hi_start, hi_end, lo_start, lo_end;
1102 997
998 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
999 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1000
1103 enable_clocks(1); 1001 enable_clocks(1);
1104 1002
1105 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n", 1003 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1106 plane, 1004 plane,
1107 REG_GET(ftrs_reg[plane], 11, 0), 1005 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1108 REG_GET(ftrs_reg[plane], 27, 16), 1006 lo_start, lo_end),
1007 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1008 hi_start, hi_end),
1109 low, high); 1009 low, high);
1110 1010
1111 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); 1011 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1112 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1113
1114 dispc_write_reg(ftrs_reg[plane],
1115 FLD_VAL(high, hi_start, hi_end) | 1012 FLD_VAL(high, hi_start, hi_end) |
1116 FLD_VAL(low, lo_start, lo_end)); 1013 FLD_VAL(low, lo_start, lo_end));
1117 1014
@@ -1131,55 +1028,43 @@ void dispc_enable_fifomerge(bool enable)
1131static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc) 1028static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1132{ 1029{
1133 u32 val; 1030 u32 val;
1134 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1135 DISPC_VID_FIR(1) };
1136 u8 hinc_start, hinc_end, vinc_start, vinc_end; 1031 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1137 1032
1138 BUG_ON(plane == OMAP_DSS_GFX);
1139
1140 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end); 1033 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1141 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end); 1034 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1142 1035
1143 val = FLD_VAL(vinc, vinc_start, vinc_end) | 1036 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1144 FLD_VAL(hinc, hinc_start, hinc_end); 1037 FLD_VAL(hinc, hinc_start, hinc_end);
1145 1038
1146 dispc_write_reg(fir_reg[plane-1], val); 1039 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1147} 1040}
1148 1041
1149static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) 1042static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1150{ 1043{
1151 u32 val; 1044 u32 val;
1152 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1153 DISPC_VID_ACCU0(1) };
1154 u8 hor_start, hor_end, vert_start, vert_end; 1045 u8 hor_start, hor_end, vert_start, vert_end;
1155 1046
1156 BUG_ON(plane == OMAP_DSS_GFX);
1157
1158 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1047 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1159 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1048 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1160 1049
1161 val = FLD_VAL(vaccu, vert_start, vert_end) | 1050 val = FLD_VAL(vaccu, vert_start, vert_end) |
1162 FLD_VAL(haccu, hor_start, hor_end); 1051 FLD_VAL(haccu, hor_start, hor_end);
1163 1052
1164 dispc_write_reg(ac0_reg[plane-1], val); 1053 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1165} 1054}
1166 1055
1167static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) 1056static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1168{ 1057{
1169 u32 val; 1058 u32 val;
1170 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1171 DISPC_VID_ACCU1(1) };
1172 u8 hor_start, hor_end, vert_start, vert_end; 1059 u8 hor_start, hor_end, vert_start, vert_end;
1173 1060
1174 BUG_ON(plane == OMAP_DSS_GFX);
1175
1176 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1061 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1177 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1062 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1178 1063
1179 val = FLD_VAL(vaccu, vert_start, vert_end) | 1064 val = FLD_VAL(vaccu, vert_start, vert_end) |
1180 FLD_VAL(haccu, hor_start, hor_end); 1065 FLD_VAL(haccu, hor_start, hor_end);
1181 1066
1182 dispc_write_reg(ac1_reg[plane-1], val); 1067 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1183} 1068}
1184 1069
1185 1070
@@ -1215,7 +1100,7 @@ static void _dispc_set_scaling(enum omap_plane plane,
1215 1100
1216 _dispc_set_fir(plane, fir_hinc, fir_vinc); 1101 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1217 1102
1218 l = dispc_read_reg(dispc_reg_att[plane]); 1103 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1219 1104
1220 /* RESIZEENABLE and VERTICALTAPS */ 1105 /* RESIZEENABLE and VERTICALTAPS */
1221 l &= ~((0x3 << 5) | (0x1 << 21)); 1106 l &= ~((0x3 << 5) | (0x1 << 21));
@@ -1236,7 +1121,7 @@ static void _dispc_set_scaling(enum omap_plane plane,
1236 l |= five_taps ? (1 << 22) : 0; 1121 l |= five_taps ? (1 << 22) : 0;
1237 } 1122 }
1238 1123
1239 dispc_write_reg(dispc_reg_att[plane], l); 1124 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1240 1125
1241 /* 1126 /*
1242 * field 0 = even field = bottom field 1127 * field 0 = even field = bottom field
@@ -1302,9 +1187,10 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1302 row_repeat = false; 1187 row_repeat = false;
1303 } 1188 }
1304 1189
1305 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); 1190 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1306 if (dss_has_feature(FEAT_ROWREPEATENABLE)) 1191 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1307 REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18); 1192 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1193 row_repeat ? 1 : 0, 18, 18);
1308} 1194}
1309 1195
1310static int color_mode_to_bpp(enum omap_color_mode color_mode) 1196static int color_mode_to_bpp(enum omap_color_mode color_mode)
@@ -1806,7 +1692,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
1806 1692
1807static void _dispc_enable_plane(enum omap_plane plane, bool enable) 1693static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1808{ 1694{
1809 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0); 1695 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1810} 1696}
1811 1697
1812static void dispc_disable_isr(void *data, u32 mask) 1698static void dispc_disable_isr(void *data, u32 mask)
@@ -2516,7 +2402,7 @@ void dispc_dump_irqs(struct seq_file *s)
2516 2402
2517void dispc_dump_regs(struct seq_file *s) 2403void dispc_dump_regs(struct seq_file *s)
2518{ 2404{
2519#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r)) 2405#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2520 2406
2521 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); 2407 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
2522 2408
@@ -2553,17 +2439,17 @@ void dispc_dump_regs(struct seq_file *s)
2553 DUMPREG(DISPC_SIZE_LCD(2)); 2439 DUMPREG(DISPC_SIZE_LCD(2));
2554 } 2440 }
2555 2441
2556 DUMPREG(DISPC_GFX_BA0); 2442 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
2557 DUMPREG(DISPC_GFX_BA1); 2443 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
2558 DUMPREG(DISPC_GFX_POSITION); 2444 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
2559 DUMPREG(DISPC_GFX_SIZE); 2445 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
2560 DUMPREG(DISPC_GFX_ATTRIBUTES); 2446 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
2561 DUMPREG(DISPC_GFX_FIFO_THRESHOLD); 2447 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
2562 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS); 2448 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
2563 DUMPREG(DISPC_GFX_ROW_INC); 2449 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
2564 DUMPREG(DISPC_GFX_PIXEL_INC); 2450 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
2565 DUMPREG(DISPC_GFX_WINDOW_SKIP); 2451 DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
2566 DUMPREG(DISPC_GFX_TABLE_BA); 2452 DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
2567 2453
2568 DUMPREG(DISPC_DATA_CYCLE1(0)); 2454 DUMPREG(DISPC_DATA_CYCLE1(0));
2569 DUMPREG(DISPC_DATA_CYCLE2(0)); 2455 DUMPREG(DISPC_DATA_CYCLE2(0));
@@ -2582,98 +2468,98 @@ void dispc_dump_regs(struct seq_file *s)
2582 DUMPREG(DISPC_CPR_COEF_B(2)); 2468 DUMPREG(DISPC_CPR_COEF_B(2));
2583 } 2469 }
2584 2470
2585 DUMPREG(DISPC_GFX_PRELOAD); 2471 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
2586 2472
2587 DUMPREG(DISPC_VID_BA0(0)); 2473 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
2588 DUMPREG(DISPC_VID_BA1(0)); 2474 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
2589 DUMPREG(DISPC_VID_POSITION(0)); 2475 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
2590 DUMPREG(DISPC_VID_SIZE(0)); 2476 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
2591 DUMPREG(DISPC_VID_ATTRIBUTES(0)); 2477 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
2592 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0)); 2478 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
2593 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0)); 2479 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
2594 DUMPREG(DISPC_VID_ROW_INC(0)); 2480 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
2595 DUMPREG(DISPC_VID_PIXEL_INC(0)); 2481 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
2596 DUMPREG(DISPC_VID_FIR(0)); 2482 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
2597 DUMPREG(DISPC_VID_PICTURE_SIZE(0)); 2483 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
2598 DUMPREG(DISPC_VID_ACCU0(0)); 2484 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
2599 DUMPREG(DISPC_VID_ACCU1(0)); 2485 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
2600 2486
2601 DUMPREG(DISPC_VID_BA0(1)); 2487 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
2602 DUMPREG(DISPC_VID_BA1(1)); 2488 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
2603 DUMPREG(DISPC_VID_POSITION(1)); 2489 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
2604 DUMPREG(DISPC_VID_SIZE(1)); 2490 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
2605 DUMPREG(DISPC_VID_ATTRIBUTES(1)); 2491 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
2606 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1)); 2492 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
2607 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1)); 2493 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
2608 DUMPREG(DISPC_VID_ROW_INC(1)); 2494 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
2609 DUMPREG(DISPC_VID_PIXEL_INC(1)); 2495 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
2610 DUMPREG(DISPC_VID_FIR(1)); 2496 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
2611 DUMPREG(DISPC_VID_PICTURE_SIZE(1)); 2497 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
2612 DUMPREG(DISPC_VID_ACCU0(1)); 2498 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
2613 DUMPREG(DISPC_VID_ACCU1(1)); 2499 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
2614 2500
2615 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0)); 2501 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
2616 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1)); 2502 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
2617 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2)); 2503 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
2618 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3)); 2504 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
2619 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4)); 2505 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
2620 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5)); 2506 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
2621 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6)); 2507 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
2622 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7)); 2508 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
2623 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0)); 2509 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
2624 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1)); 2510 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
2625 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2)); 2511 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
2626 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3)); 2512 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
2627 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4)); 2513 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
2628 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5)); 2514 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
2629 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6)); 2515 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
2630 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7)); 2516 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
2631 DUMPREG(DISPC_VID_CONV_COEF(0, 0)); 2517 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
2632 DUMPREG(DISPC_VID_CONV_COEF(0, 1)); 2518 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
2633 DUMPREG(DISPC_VID_CONV_COEF(0, 2)); 2519 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
2634 DUMPREG(DISPC_VID_CONV_COEF(0, 3)); 2520 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
2635 DUMPREG(DISPC_VID_CONV_COEF(0, 4)); 2521 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
2636 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0)); 2522 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
2637 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1)); 2523 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
2638 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2)); 2524 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
2639 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3)); 2525 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
2640 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4)); 2526 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
2641 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5)); 2527 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
2642 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6)); 2528 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
2643 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7)); 2529 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
2644 2530
2645 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0)); 2531 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
2646 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1)); 2532 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
2647 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2)); 2533 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
2648 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3)); 2534 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
2649 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4)); 2535 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
2650 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5)); 2536 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
2651 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6)); 2537 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
2652 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7)); 2538 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
2653 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0)); 2539 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
2654 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1)); 2540 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
2655 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2)); 2541 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
2656 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3)); 2542 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
2657 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4)); 2543 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
2658 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5)); 2544 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
2659 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6)); 2545 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
2660 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7)); 2546 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
2661 DUMPREG(DISPC_VID_CONV_COEF(1, 0)); 2547 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
2662 DUMPREG(DISPC_VID_CONV_COEF(1, 1)); 2548 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
2663 DUMPREG(DISPC_VID_CONV_COEF(1, 2)); 2549 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
2664 DUMPREG(DISPC_VID_CONV_COEF(1, 3)); 2550 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
2665 DUMPREG(DISPC_VID_CONV_COEF(1, 4)); 2551 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
2666 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0)); 2552 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
2667 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1)); 2553 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
2668 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2)); 2554 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
2669 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3)); 2555 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
2670 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4)); 2556 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
2671 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5)); 2557 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
2672 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6)); 2558 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
2673 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7)); 2559 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
2674 2560
2675 DUMPREG(DISPC_VID_PRELOAD(0)); 2561 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
2676 DUMPREG(DISPC_VID_PRELOAD(1)); 2562 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
2677 2563
2678 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); 2564 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
2679#undef DUMPREG 2565#undef DUMPREG
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h
new file mode 100644
index 000000000000..f22346b59c58
--- /dev/null
+++ b/drivers/video/omap2/dss/dispc.h
@@ -0,0 +1,386 @@
1/*
2 * linux/drivers/video/omap2/dss/dispc.h
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __OMAP2_DISPC_REG_H
22#define __OMAP2_DISPC_REG_H
23
24struct dispc_reg { u16 idx; };
25
26#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
27
28/*
29 * DISPC common registers and
30 * DISPC channel registers , ch = 0 for LCD, ch = 1 for
31 * DIGIT, and ch = 2 for LCD2
32 */
33#define DISPC_REVISION DISPC_REG(0x0000)
34#define DISPC_SYSCONFIG DISPC_REG(0x0010)
35#define DISPC_SYSSTATUS DISPC_REG(0x0014)
36#define DISPC_IRQSTATUS DISPC_REG(0x0018)
37#define DISPC_IRQENABLE DISPC_REG(0x001C)
38#define DISPC_CONTROL DISPC_REG(0x0040)
39#define DISPC_CONTROL2 DISPC_REG(0x0238)
40#define DISPC_CONFIG DISPC_REG(0x0044)
41#define DISPC_CONFIG2 DISPC_REG(0x0620)
42#define DISPC_CAPABLE DISPC_REG(0x0048)
43#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
44 (ch == 1 ? 0x0050 : 0x03AC))
45#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
46 (ch == 1 ? 0x0058 : 0x03B0))
47#define DISPC_LINE_STATUS DISPC_REG(0x005C)
48#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
49#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
50#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
51#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
52#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
53#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
54#define DISPC_SIZE_DIG DISPC_REG(0x0078)
55#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
56
57#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
58#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
59#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
60#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
61#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
62#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
63
64#define DISPC_DIVISOR DISPC_REG(0x0804)
65
66/* DISPC overlay registers */
67#define DISPC_OVL_BA0(n) DISPC_REG(DISPC_OVL_BASE(n) + \
68 DISPC_BA0_OFFSET(n))
69#define DISPC_OVL_BA1(n) DISPC_REG(DISPC_OVL_BASE(n) + \
70 DISPC_BA1_OFFSET(n))
71#define DISPC_OVL_POSITION(n) DISPC_REG(DISPC_OVL_BASE(n) + \
72 DISPC_POS_OFFSET(n))
73#define DISPC_OVL_SIZE(n) DISPC_REG(DISPC_OVL_BASE(n) + \
74 DISPC_SIZE_OFFSET(n))
75#define DISPC_OVL_ATTRIBUTES(n) DISPC_REG(DISPC_OVL_BASE(n) + \
76 DISPC_ATTR_OFFSET(n))
77#define DISPC_OVL_FIFO_THRESHOLD(n) DISPC_REG(DISPC_OVL_BASE(n) + \
78 DISPC_FIFO_THRESH_OFFSET(n))
79#define DISPC_OVL_FIFO_SIZE_STATUS(n) DISPC_REG(DISPC_OVL_BASE(n) + \
80 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
81#define DISPC_OVL_ROW_INC(n) DISPC_REG(DISPC_OVL_BASE(n) + \
82 DISPC_ROW_INC_OFFSET(n))
83#define DISPC_OVL_PIXEL_INC(n) DISPC_REG(DISPC_OVL_BASE(n) + \
84 DISPC_PIX_INC_OFFSET(n))
85#define DISPC_OVL_WINDOW_SKIP(n) DISPC_REG(DISPC_OVL_BASE(n) + \
86 DISPC_WINDOW_SKIP_OFFSET(n))
87#define DISPC_OVL_TABLE_BA(n) DISPC_REG(DISPC_OVL_BASE(n) + \
88 DISPC_TABLE_BA_OFFSET(n))
89#define DISPC_OVL_FIR(n) DISPC_REG(DISPC_OVL_BASE(n) + \
90 DISPC_FIR_OFFSET(n))
91#define DISPC_OVL_PICTURE_SIZE(n) DISPC_REG(DISPC_OVL_BASE(n) + \
92 DISPC_PIC_SIZE_OFFSET(n))
93#define DISPC_OVL_ACCU0(n) DISPC_REG(DISPC_OVL_BASE(n) + \
94 DISPC_ACCU0_OFFSET(n))
95#define DISPC_OVL_ACCU1(n) DISPC_REG(DISPC_OVL_BASE(n) + \
96 DISPC_ACCU1_OFFSET(n))
97#define DISPC_OVL_FIR_COEF_H(n, i) DISPC_REG(DISPC_OVL_BASE(n) + \
98 DISPC_FIR_COEF_H_OFFSET(n, i))
99#define DISPC_OVL_FIR_COEF_HV(n, i) DISPC_REG(DISPC_OVL_BASE(n) + \
100 DISPC_FIR_COEF_HV_OFFSET(n, i))
101#define DISPC_OVL_CONV_COEF(n, i) DISPC_REG(DISPC_OVL_BASE(n) + \
102 DISPC_CONV_COEF_OFFSET(n, i))
103#define DISPC_OVL_FIR_COEF_V(n, i) DISPC_REG(DISPC_OVL_BASE(n) + \
104 DISPC_FIR_COEF_V_OFFSET(n, i))
105#define DISPC_OVL_PRELOAD(n) DISPC_REG(DISPC_OVL_BASE(n) + \
106 DISPC_PRELOAD_OFFSET(n))
107
108/* DISPC overlay register base addresses */
109static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
110{
111 switch (plane) {
112 case OMAP_DSS_GFX:
113 return 0x0080;
114 case OMAP_DSS_VIDEO1:
115 return 0x00BC;
116 case OMAP_DSS_VIDEO2:
117 return 0x014C;
118 default:
119 BUG();
120 }
121}
122
123/* DISPC overlay register offsets */
124static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
125{
126 switch (plane) {
127 case OMAP_DSS_GFX:
128 case OMAP_DSS_VIDEO1:
129 case OMAP_DSS_VIDEO2:
130 return 0x0000;
131 default:
132 BUG();
133 }
134}
135
136static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
137{
138 switch (plane) {
139 case OMAP_DSS_GFX:
140 case OMAP_DSS_VIDEO1:
141 case OMAP_DSS_VIDEO2:
142 return 0x0004;
143 default:
144 BUG();
145 }
146}
147
148static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
149{
150 switch (plane) {
151 case OMAP_DSS_GFX:
152 case OMAP_DSS_VIDEO1:
153 case OMAP_DSS_VIDEO2:
154 return 0x0008;
155 default:
156 BUG();
157 }
158}
159
160static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
161{
162 switch (plane) {
163 case OMAP_DSS_GFX:
164 case OMAP_DSS_VIDEO1:
165 case OMAP_DSS_VIDEO2:
166 return 0x000C;
167 default:
168 BUG();
169 }
170}
171
172static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
173{
174 switch (plane) {
175 case OMAP_DSS_GFX:
176 return 0x0020;
177 case OMAP_DSS_VIDEO1:
178 case OMAP_DSS_VIDEO2:
179 return 0x0010;
180 default:
181 BUG();
182 }
183}
184
185static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
186{
187 switch (plane) {
188 case OMAP_DSS_GFX:
189 return 0x0024;
190 case OMAP_DSS_VIDEO1:
191 case OMAP_DSS_VIDEO2:
192 return 0x0014;
193 default:
194 BUG();
195 }
196}
197
198static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
199{
200 switch (plane) {
201 case OMAP_DSS_GFX:
202 return 0x0028;
203 case OMAP_DSS_VIDEO1:
204 case OMAP_DSS_VIDEO2:
205 return 0x0018;
206 default:
207 BUG();
208 }
209}
210
211static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
212{
213 switch (plane) {
214 case OMAP_DSS_GFX:
215 return 0x002C;
216 case OMAP_DSS_VIDEO1:
217 case OMAP_DSS_VIDEO2:
218 return 0x001C;
219 default:
220 BUG();
221 }
222}
223
224static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
225{
226 switch (plane) {
227 case OMAP_DSS_GFX:
228 return 0x0030;
229 case OMAP_DSS_VIDEO1:
230 case OMAP_DSS_VIDEO2:
231 return 0x0020;
232 default:
233 BUG();
234 }
235}
236
237static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
238{
239 switch (plane) {
240 case OMAP_DSS_GFX:
241 return 0x0034;
242 case OMAP_DSS_VIDEO1:
243 case OMAP_DSS_VIDEO2:
244 BUG();
245 default:
246 BUG();
247 }
248}
249
250static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
251{
252 switch (plane) {
253 case OMAP_DSS_GFX:
254 return 0x0038;
255 case OMAP_DSS_VIDEO1:
256 case OMAP_DSS_VIDEO2:
257 BUG();
258 default:
259 BUG();
260 }
261}
262
263static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
264{
265 switch (plane) {
266 case OMAP_DSS_GFX:
267 BUG();
268 case OMAP_DSS_VIDEO1:
269 case OMAP_DSS_VIDEO2:
270 return 0x0024;
271 default:
272 BUG();
273 }
274}
275
276static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
277{
278 switch (plane) {
279 case OMAP_DSS_GFX:
280 BUG();
281 case OMAP_DSS_VIDEO1:
282 case OMAP_DSS_VIDEO2:
283 return 0x0028;
284 default:
285 BUG();
286 }
287}
288
289
290static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
291{
292 switch (plane) {
293 case OMAP_DSS_GFX:
294 BUG();
295 case OMAP_DSS_VIDEO1:
296 case OMAP_DSS_VIDEO2:
297 return 0x002C;
298 default:
299 BUG();
300 }
301}
302
303static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
304{
305 switch (plane) {
306 case OMAP_DSS_GFX:
307 BUG();
308 case OMAP_DSS_VIDEO1:
309 case OMAP_DSS_VIDEO2:
310 return 0x0030;
311 default:
312 BUG();
313 }
314}
315
316/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
317static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
318{
319 switch (plane) {
320 case OMAP_DSS_GFX:
321 BUG();
322 case OMAP_DSS_VIDEO1:
323 case OMAP_DSS_VIDEO2:
324 return 0x0034 + i * 0x8;
325 default:
326 BUG();
327 }
328}
329
330/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
331static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
332{
333 switch (plane) {
334 case OMAP_DSS_GFX:
335 BUG();
336 case OMAP_DSS_VIDEO1:
337 case OMAP_DSS_VIDEO2:
338 return 0x0038 + i * 0x8;
339 default:
340 BUG();
341 }
342}
343
344/* coef index i = {0, 1, 2, 3, 4,} */
345static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
346{
347 switch (plane) {
348 case OMAP_DSS_GFX:
349 BUG();
350 case OMAP_DSS_VIDEO1:
351 case OMAP_DSS_VIDEO2:
352 return 0x0074 + i * 0x4;
353 default:
354 BUG();
355 }
356}
357
358/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
359static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
360{
361 switch (plane) {
362 case OMAP_DSS_GFX:
363 BUG();
364 case OMAP_DSS_VIDEO1:
365 return 0x0124 + i * 0x4;
366 case OMAP_DSS_VIDEO2:
367 return 0x00B4 + i * 0x4;
368 default:
369 BUG();
370 }
371}
372
373static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
374{
375 switch (plane) {
376 case OMAP_DSS_GFX:
377 return 0x01AC;
378 case OMAP_DSS_VIDEO1:
379 return 0x0174;
380 case OMAP_DSS_VIDEO2:
381 return 0x00E8;
382 default:
383 BUG();
384 }
385}
386#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 08:33:55 -0500