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authorArchit Taneja <archit@ti.com>2011-08-25 08:55:03 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-09-30 09:16:25 -0400
commit7a7c48f9ab374f5fb279f31634d857adc3f0c78c (patch)
tree739aea107141f5f0918b5407849a65ca48baecb8 /drivers/video/omap2/dss/dsi.c
parentcc11aaf867e777dfa0f14d9bedead895f5e541b7 (diff)
OMAP: DSS2: Use MIPI DSI enums from include/video/mipi_display.h
MIPI DSI Transaction types and DCS commands are currently defined as macros in dsi.c and panel-taal.c, remove these and replace them with enum members defined in include/video/mipi_display.h. Signed-off-by: Archit Taneja <archit@ti.com> [tomi.valkeinen@ti.com: reformatted the commit message] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dsi.c')
-rw-r--r--drivers/video/omap2/dss/dsi.c48
1 files changed, 19 insertions, 29 deletions
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 52a4a0274c7a..6735e0c8bdf7 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -39,6 +39,7 @@
39#include <linux/pm_runtime.h> 39#include <linux/pm_runtime.h>
40 40
41#include <video/omapdss.h> 41#include <video/omapdss.h>
42#include <video/mipi_display.h>
42#include <plat/clock.h> 43#include <plat/clock.h>
43 44
44#include "dss.h" 45#include "dss.h"
@@ -198,18 +199,6 @@ struct dsi_reg { u16 idx; };
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ 199 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 200 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
200 201
201#define DSI_DT_DCS_SHORT_WRITE_0 0x05
202#define DSI_DT_DCS_SHORT_WRITE_1 0x15
203#define DSI_DT_DCS_READ 0x06
204#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
205#define DSI_DT_NULL_PACKET 0x09
206#define DSI_DT_DCS_LONG_WRITE 0x39
207
208#define DSI_DT_RX_ACK_WITH_ERR 0x02
209#define DSI_DT_RX_DCS_LONG_READ 0x1c
210#define DSI_DT_RX_SHORT_READ_1 0x21
211#define DSI_DT_RX_SHORT_READ_2 0x22
212
213typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 202typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
214 203
215#define DSI_MAX_NR_ISRS 2 204#define DSI_MAX_NR_ISRS 2
@@ -2887,16 +2876,16 @@ static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2887 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2876 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2888 DSSERR("\trawval %#08x\n", val); 2877 DSSERR("\trawval %#08x\n", val);
2889 dt = FLD_GET(val, 5, 0); 2878 dt = FLD_GET(val, 5, 0);
2890 if (dt == DSI_DT_RX_ACK_WITH_ERR) { 2879 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2891 u16 err = FLD_GET(val, 23, 8); 2880 u16 err = FLD_GET(val, 23, 8);
2892 dsi_show_rx_ack_with_err(err); 2881 dsi_show_rx_ack_with_err(err);
2893 } else if (dt == DSI_DT_RX_SHORT_READ_1) { 2882 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2894 DSSERR("\tDCS short response, 1 byte: %#x\n", 2883 DSSERR("\tDCS short response, 1 byte: %#x\n",
2895 FLD_GET(val, 23, 8)); 2884 FLD_GET(val, 23, 8));
2896 } else if (dt == DSI_DT_RX_SHORT_READ_2) { 2885 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2897 DSSERR("\tDCS short response, 2 byte: %#x\n", 2886 DSSERR("\tDCS short response, 2 byte: %#x\n",
2898 FLD_GET(val, 23, 8)); 2887 FLD_GET(val, 23, 8));
2899 } else if (dt == DSI_DT_RX_DCS_LONG_READ) { 2888 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2900 DSSERR("\tDCS long response, len %d\n", 2889 DSSERR("\tDCS long response, len %d\n",
2901 FLD_GET(val, 23, 8)); 2890 FLD_GET(val, 23, 8));
2902 dsi_vc_flush_long_data(dsidev, channel); 2891 dsi_vc_flush_long_data(dsidev, channel);
@@ -3101,7 +3090,7 @@ int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3101 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3090 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3102 u8 nullpkg[] = {0, 0, 0, 0}; 3091 u8 nullpkg[] = {0, 0, 0, 0};
3103 3092
3104 return dsi_vc_send_long(dsidev, channel, DSI_DT_NULL_PACKET, nullpkg, 3093 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, nullpkg,
3105 4, 0); 3094 4, 0);
3106} 3095}
3107EXPORT_SYMBOL(dsi_vc_send_null); 3096EXPORT_SYMBOL(dsi_vc_send_null);
@@ -3115,14 +3104,15 @@ int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3115 BUG_ON(len == 0); 3104 BUG_ON(len == 0);
3116 3105
3117 if (len == 1) { 3106 if (len == 1) {
3118 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_0, 3107 r = dsi_vc_send_short(dsidev, channel,
3119 data[0], 0); 3108 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3120 } else if (len == 2) { 3109 } else if (len == 2) {
3121 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_1, 3110 r = dsi_vc_send_short(dsidev, channel,
3111 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3122 data[0] | (data[1] << 8), 0); 3112 data[0] | (data[1] << 8), 0);
3123 } else { 3113 } else {
3124 /* 0x39 = DCS Long Write */ 3114 /* 0x39 = DCS Long Write */
3125 r = dsi_vc_send_long(dsidev, channel, DSI_DT_DCS_LONG_WRITE, 3115 r = dsi_vc_send_long(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3126 data, len, 0); 3116 data, len, 0);
3127 } 3117 }
3128 3118
@@ -3188,7 +3178,7 @@ int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3188 if (dsi->debug_read) 3178 if (dsi->debug_read)
3189 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd); 3179 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
3190 3180
3191 r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_READ, dcs_cmd, 0); 3181 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3192 if (r) 3182 if (r)
3193 goto err; 3183 goto err;
3194 3184
@@ -3207,13 +3197,13 @@ int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3207 if (dsi->debug_read) 3197 if (dsi->debug_read)
3208 DSSDBG("\theader: %08x\n", val); 3198 DSSDBG("\theader: %08x\n", val);
3209 dt = FLD_GET(val, 5, 0); 3199 dt = FLD_GET(val, 5, 0);
3210 if (dt == DSI_DT_RX_ACK_WITH_ERR) { 3200 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3211 u16 err = FLD_GET(val, 23, 8); 3201 u16 err = FLD_GET(val, 23, 8);
3212 dsi_show_rx_ack_with_err(err); 3202 dsi_show_rx_ack_with_err(err);
3213 r = -EIO; 3203 r = -EIO;
3214 goto err; 3204 goto err;
3215 3205
3216 } else if (dt == DSI_DT_RX_SHORT_READ_1) { 3206 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
3217 u8 data = FLD_GET(val, 15, 8); 3207 u8 data = FLD_GET(val, 15, 8);
3218 if (dsi->debug_read) 3208 if (dsi->debug_read)
3219 DSSDBG("\tDCS short response, 1 byte: %02x\n", data); 3209 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
@@ -3226,7 +3216,7 @@ int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3226 buf[0] = data; 3216 buf[0] = data;
3227 3217
3228 return 1; 3218 return 1;
3229 } else if (dt == DSI_DT_RX_SHORT_READ_2) { 3219 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
3230 u16 data = FLD_GET(val, 23, 8); 3220 u16 data = FLD_GET(val, 23, 8);
3231 if (dsi->debug_read) 3221 if (dsi->debug_read)
3232 DSSDBG("\tDCS short response, 2 byte: %04x\n", data); 3222 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
@@ -3240,7 +3230,7 @@ int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3240 buf[1] = (data >> 8) & 0xff; 3230 buf[1] = (data >> 8) & 0xff;
3241 3231
3242 return 2; 3232 return 2;
3243 } else if (dt == DSI_DT_RX_DCS_LONG_READ) { 3233 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
3244 int w; 3234 int w;
3245 int len = FLD_GET(val, 23, 8); 3235 int len = FLD_GET(val, 23, 8);
3246 if (dsi->debug_read) 3236 if (dsi->debug_read)
@@ -3330,8 +3320,8 @@ int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3330{ 3320{
3331 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3321 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3332 3322
3333 return dsi_vc_send_short(dsidev, channel, DSI_DT_SET_MAX_RET_PKG_SIZE, 3323 return dsi_vc_send_short(dsidev, channel,
3334 len, 0); 3324 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3335} 3325}
3336EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); 3326EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3337 3327
@@ -3690,7 +3680,7 @@ static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
3690 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3680 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3691 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3681 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3692 3682
3693 dsi_vc_write_long_header(dsidev, channel, DSI_DT_DCS_LONG_WRITE, 3683 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3694 packet_len, 0); 3684 packet_len, 0);
3695 3685
3696 if (dsi->te_enabled) 3686 if (dsi->te_enabled)