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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-02-13 08:31:38 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-04-17 01:10:19 -0400
commitf7018c21350204c4cf628462f229d44d03545254 (patch)
tree408787177164cf51cc06f7aabdb04fcff8d2b6aa /drivers/video/nvidia
parentc26ef3eb3c11274bad1b64498d0a134f85755250 (diff)
video: move fbdev to drivers/video/fbdev
The drivers/video directory is a mess. It contains generic video related files, directories for backlight, console, linux logo, lots of fbdev device drivers, fbdev framework files. Make some order into the chaos by creating drivers/video/fbdev directory, and move all fbdev related files there. No functionality is changed, although I guess it is possible that some subtle Makefile build order related issue could be created by this patch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Clark <robdclark@gmail.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/video/nvidia')
-rw-r--r--drivers/video/nvidia/Makefile13
-rw-r--r--drivers/video/nvidia/nv_accel.c416
-rw-r--r--drivers/video/nvidia/nv_backlight.c148
-rw-r--r--drivers/video/nvidia/nv_dma.h188
-rw-r--r--drivers/video/nvidia/nv_hw.c1687
-rw-r--r--drivers/video/nvidia/nv_i2c.c171
-rw-r--r--drivers/video/nvidia/nv_local.h114
-rw-r--r--drivers/video/nvidia/nv_of.c82
-rw-r--r--drivers/video/nvidia/nv_proto.h75
-rw-r--r--drivers/video/nvidia/nv_setup.c675
-rw-r--r--drivers/video/nvidia/nv_type.h180
-rw-r--r--drivers/video/nvidia/nvidia.c1607
12 files changed, 0 insertions, 5356 deletions
diff --git a/drivers/video/nvidia/Makefile b/drivers/video/nvidia/Makefile
deleted file mode 100644
index ca47432113e0..000000000000
--- a/drivers/video/nvidia/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
1#
2# Makefile for the nVidia framebuffer driver
3#
4
5obj-$(CONFIG_FB_NVIDIA) += nvidiafb.o
6
7nvidiafb-y := nvidia.o nv_hw.o nv_setup.o \
8 nv_accel.o
9nvidiafb-$(CONFIG_FB_NVIDIA_I2C) += nv_i2c.o
10nvidiafb-$(CONFIG_FB_NVIDIA_BACKLIGHT) += nv_backlight.o
11nvidiafb-$(CONFIG_PPC_OF) += nv_of.o
12
13nvidiafb-objs := $(nvidiafb-y)
diff --git a/drivers/video/nvidia/nv_accel.c b/drivers/video/nvidia/nv_accel.c
deleted file mode 100644
index ad6472a894ea..000000000000
--- a/drivers/video/nvidia/nv_accel.c
+++ /dev/null
@@ -1,416 +0,0 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50#include <linux/fb.h>
51#include "nv_type.h"
52#include "nv_proto.h"
53#include "nv_dma.h"
54#include "nv_local.h"
55
56/* There is a HW race condition with videoram command buffers.
57 You can't jump to the location of your put offset. We write put
58 at the jump offset + SKIPS dwords with noop padding in between
59 to solve this problem */
60#define SKIPS 8
61
62static const int NVCopyROP[16] = {
63 0xCC, /* copy */
64 0x55 /* invert */
65};
66
67static const int NVCopyROP_PM[16] = {
68 0xCA, /* copy */
69 0x5A, /* invert */
70};
71
72static inline void nvidiafb_safe_mode(struct fb_info *info)
73{
74 struct nvidia_par *par = info->par;
75
76 touch_softlockup_watchdog();
77 info->pixmap.scan_align = 1;
78 par->lockup = 1;
79}
80
81static inline void NVFlush(struct fb_info *info)
82{
83 struct nvidia_par *par = info->par;
84 int count = 1000000000;
85
86 while (--count && READ_GET(par) != par->dmaPut) ;
87
88 if (!count) {
89 printk("nvidiafb: DMA Flush lockup\n");
90 nvidiafb_safe_mode(info);
91 }
92}
93
94static inline void NVSync(struct fb_info *info)
95{
96 struct nvidia_par *par = info->par;
97 int count = 1000000000;
98
99 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;
100
101 if (!count) {
102 printk("nvidiafb: DMA Sync lockup\n");
103 nvidiafb_safe_mode(info);
104 }
105}
106
107static void NVDmaKickoff(struct nvidia_par *par)
108{
109 if (par->dmaCurrent != par->dmaPut) {
110 par->dmaPut = par->dmaCurrent;
111 WRITE_PUT(par, par->dmaPut);
112 }
113}
114
115static void NVDmaWait(struct fb_info *info, int size)
116{
117 struct nvidia_par *par = info->par;
118 int dmaGet;
119 int count = 1000000000, cnt;
120 size++;
121
122 while (par->dmaFree < size && --count && !par->lockup) {
123 dmaGet = READ_GET(par);
124
125 if (par->dmaPut >= dmaGet) {
126 par->dmaFree = par->dmaMax - par->dmaCurrent;
127 if (par->dmaFree < size) {
128 NVDmaNext(par, 0x20000000);
129 if (dmaGet <= SKIPS) {
130 if (par->dmaPut <= SKIPS)
131 WRITE_PUT(par, SKIPS + 1);
132 cnt = 1000000000;
133 do {
134 dmaGet = READ_GET(par);
135 } while (--cnt && dmaGet <= SKIPS);
136 if (!cnt) {
137 printk("DMA Get lockup\n");
138 par->lockup = 1;
139 }
140 }
141 WRITE_PUT(par, SKIPS);
142 par->dmaCurrent = par->dmaPut = SKIPS;
143 par->dmaFree = dmaGet - (SKIPS + 1);
144 }
145 } else
146 par->dmaFree = dmaGet - par->dmaCurrent - 1;
147 }
148
149 if (!count) {
150 printk("nvidiafb: DMA Wait Lockup\n");
151 nvidiafb_safe_mode(info);
152 }
153}
154
155static void NVSetPattern(struct fb_info *info, u32 clr0, u32 clr1,
156 u32 pat0, u32 pat1)
157{
158 struct nvidia_par *par = info->par;
159
160 NVDmaStart(info, par, PATTERN_COLOR_0, 4);
161 NVDmaNext(par, clr0);
162 NVDmaNext(par, clr1);
163 NVDmaNext(par, pat0);
164 NVDmaNext(par, pat1);
165}
166
167static void NVSetRopSolid(struct fb_info *info, u32 rop, u32 planemask)
168{
169 struct nvidia_par *par = info->par;
170
171 if (planemask != ~0) {
172 NVSetPattern(info, 0, planemask, ~0, ~0);
173 if (par->currentRop != (rop + 32)) {
174 NVDmaStart(info, par, ROP_SET, 1);
175 NVDmaNext(par, NVCopyROP_PM[rop]);
176 par->currentRop = rop + 32;
177 }
178 } else if (par->currentRop != rop) {
179 if (par->currentRop >= 16)
180 NVSetPattern(info, ~0, ~0, ~0, ~0);
181 NVDmaStart(info, par, ROP_SET, 1);
182 NVDmaNext(par, NVCopyROP[rop]);
183 par->currentRop = rop;
184 }
185}
186
187static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
188 int x2, int y2)
189{
190 struct nvidia_par *par = info->par;
191 int h = y2 - y1 + 1;
192 int w = x2 - x1 + 1;
193
194 NVDmaStart(info, par, CLIP_POINT, 2);
195 NVDmaNext(par, (y1 << 16) | x1);
196 NVDmaNext(par, (h << 16) | w);
197}
198
199void NVResetGraphics(struct fb_info *info)
200{
201 struct nvidia_par *par = info->par;
202 u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
203 int pitch, i;
204
205 pitch = info->fix.line_length;
206
207 par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);
208
209 for (i = 0; i < SKIPS; i++)
210 NV_WR32(&par->dmaBase[i], 0, 0x00000000);
211
212 NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
213 NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
214 NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
215 NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
216 NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
217 NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
218 NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
219 NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
220 NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
221 NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
222 NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
223 NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
224 NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
225 NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
226 NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
227 NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);
228
229 par->dmaPut = 0;
230 par->dmaCurrent = 16 + SKIPS;
231 par->dmaMax = 8191;
232 par->dmaFree = par->dmaMax - par->dmaCurrent;
233
234 switch (info->var.bits_per_pixel) {
235 case 32:
236 case 24:
237 surfaceFormat = SURFACE_FORMAT_DEPTH24;
238 patternFormat = PATTERN_FORMAT_DEPTH24;
239 rectFormat = RECT_FORMAT_DEPTH24;
240 lineFormat = LINE_FORMAT_DEPTH24;
241 break;
242 case 16:
243 surfaceFormat = SURFACE_FORMAT_DEPTH16;
244 patternFormat = PATTERN_FORMAT_DEPTH16;
245 rectFormat = RECT_FORMAT_DEPTH16;
246 lineFormat = LINE_FORMAT_DEPTH16;
247 break;
248 default:
249 surfaceFormat = SURFACE_FORMAT_DEPTH8;
250 patternFormat = PATTERN_FORMAT_DEPTH8;
251 rectFormat = RECT_FORMAT_DEPTH8;
252 lineFormat = LINE_FORMAT_DEPTH8;
253 break;
254 }
255
256 NVDmaStart(info, par, SURFACE_FORMAT, 4);
257 NVDmaNext(par, surfaceFormat);
258 NVDmaNext(par, pitch | (pitch << 16));
259 NVDmaNext(par, 0);
260 NVDmaNext(par, 0);
261
262 NVDmaStart(info, par, PATTERN_FORMAT, 1);
263 NVDmaNext(par, patternFormat);
264
265 NVDmaStart(info, par, RECT_FORMAT, 1);
266 NVDmaNext(par, rectFormat);
267
268 NVDmaStart(info, par, LINE_FORMAT, 1);
269 NVDmaNext(par, lineFormat);
270
271 par->currentRop = ~0; /* set to something invalid */
272 NVSetRopSolid(info, ROP_COPY, ~0);
273
274 NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
275 info->var.yres_virtual);
276
277 NVDmaKickoff(par);
278}
279
280int nvidiafb_sync(struct fb_info *info)
281{
282 struct nvidia_par *par = info->par;
283
284 if (info->state != FBINFO_STATE_RUNNING)
285 return 0;
286
287 if (!par->lockup)
288 NVFlush(info);
289
290 if (!par->lockup)
291 NVSync(info);
292
293 return 0;
294}
295
296void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
297{
298 struct nvidia_par *par = info->par;
299
300 if (info->state != FBINFO_STATE_RUNNING)
301 return;
302
303 if (par->lockup) {
304 cfb_copyarea(info, region);
305 return;
306 }
307
308 NVDmaStart(info, par, BLIT_POINT_SRC, 3);
309 NVDmaNext(par, (region->sy << 16) | region->sx);
310 NVDmaNext(par, (region->dy << 16) | region->dx);
311 NVDmaNext(par, (region->height << 16) | region->width);
312
313 NVDmaKickoff(par);
314}
315
316void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
317{
318 struct nvidia_par *par = info->par;
319 u32 color;
320
321 if (info->state != FBINFO_STATE_RUNNING)
322 return;
323
324 if (par->lockup) {
325 cfb_fillrect(info, rect);
326 return;
327 }
328
329 if (info->var.bits_per_pixel == 8)
330 color = rect->color;
331 else
332 color = ((u32 *) info->pseudo_palette)[rect->color];
333
334 if (rect->rop != ROP_COPY)
335 NVSetRopSolid(info, rect->rop, ~0);
336
337 NVDmaStart(info, par, RECT_SOLID_COLOR, 1);
338 NVDmaNext(par, color);
339
340 NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2);
341 NVDmaNext(par, (rect->dx << 16) | rect->dy);
342 NVDmaNext(par, (rect->width << 16) | rect->height);
343
344 NVDmaKickoff(par);
345
346 if (rect->rop != ROP_COPY)
347 NVSetRopSolid(info, ROP_COPY, ~0);
348}
349
350static void nvidiafb_mono_color_expand(struct fb_info *info,
351 const struct fb_image *image)
352{
353 struct nvidia_par *par = info->par;
354 u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
355 u32 dsize, width, *data = (u32 *) image->data, tmp;
356 int j, k = 0;
357
358 width = (image->width + 31) & ~31;
359 dsize = (width * image->height) >> 5;
360
361 if (info->var.bits_per_pixel == 8) {
362 fg = image->fg_color | mask;
363 bg = image->bg_color | mask;
364 } else {
365 fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask;
366 bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask;
367 }
368
369 NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
370 NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
371 NVDmaNext(par, ((image->dy + image->height) << 16) |
372 ((image->dx + image->width) & 0xffff));
373 NVDmaNext(par, bg);
374 NVDmaNext(par, fg);
375 NVDmaNext(par, (image->height << 16) | width);
376 NVDmaNext(par, (image->height << 16) | width);
377 NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
378
379 while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
380 NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0),
381 RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);
382
383 for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
384 tmp = data[k++];
385 reverse_order(&tmp);
386 NVDmaNext(par, tmp);
387 }
388
389 dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
390 }
391
392 if (dsize) {
393 NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);
394
395 for (j = dsize; j--;) {
396 tmp = data[k++];
397 reverse_order(&tmp);
398 NVDmaNext(par, tmp);
399 }
400 }
401
402 NVDmaKickoff(par);
403}
404
405void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
406{
407 struct nvidia_par *par = info->par;
408
409 if (info->state != FBINFO_STATE_RUNNING)
410 return;
411
412 if (image->depth == 1 && !par->lockup)
413 nvidiafb_mono_color_expand(info, image);
414 else
415 cfb_imageblit(info, image);
416}
diff --git a/drivers/video/nvidia/nv_backlight.c b/drivers/video/nvidia/nv_backlight.c
deleted file mode 100644
index 8471008aa6ff..000000000000
--- a/drivers/video/nvidia/nv_backlight.c
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Backlight code for nVidia based graphic cards
3 *
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
5 * Copyright (c) 2006 Michael Hanselmann <linux-kernel@hansmi.ch>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/backlight.h>
13#include <linux/fb.h>
14#include <linux/pci.h>
15
16#ifdef CONFIG_PMAC_BACKLIGHT
17#include <asm/backlight.h>
18#endif
19
20#include "nv_local.h"
21#include "nv_type.h"
22#include "nv_proto.h"
23
24/* We do not have any information about which values are allowed, thus
25 * we used safe values.
26 */
27#define MIN_LEVEL 0x158
28#define MAX_LEVEL 0x534
29#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
30
31static int nvidia_bl_get_level_brightness(struct nvidia_par *par,
32 int level)
33{
34 struct fb_info *info = pci_get_drvdata(par->pci_dev);
35 int nlevel;
36
37 /* Get and convert the value */
38 /* No locking of bl_curve since we read a single value */
39 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
40
41 if (nlevel < 0)
42 nlevel = 0;
43 else if (nlevel < MIN_LEVEL)
44 nlevel = MIN_LEVEL;
45 else if (nlevel > MAX_LEVEL)
46 nlevel = MAX_LEVEL;
47
48 return nlevel;
49}
50
51static int nvidia_bl_update_status(struct backlight_device *bd)
52{
53 struct nvidia_par *par = bl_get_data(bd);
54 u32 tmp_pcrt, tmp_pmc, fpcontrol;
55 int level;
56
57 if (!par->FlatPanel)
58 return 0;
59
60 if (bd->props.power != FB_BLANK_UNBLANK ||
61 bd->props.fb_blank != FB_BLANK_UNBLANK)
62 level = 0;
63 else
64 level = bd->props.brightness;
65
66 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
67 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
68 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
69
70 if (level > 0) {
71 tmp_pcrt |= 0x1;
72 tmp_pmc |= (1 << 31); /* backlight bit */
73 tmp_pmc |= nvidia_bl_get_level_brightness(par, level) << 16;
74 fpcontrol |= par->fpSyncs;
75 } else
76 fpcontrol |= 0x20000022;
77
78 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
79 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
80 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
81
82 return 0;
83}
84
85static int nvidia_bl_get_brightness(struct backlight_device *bd)
86{
87 return bd->props.brightness;
88}
89
90static const struct backlight_ops nvidia_bl_ops = {
91 .get_brightness = nvidia_bl_get_brightness,
92 .update_status = nvidia_bl_update_status,
93};
94
95void nvidia_bl_init(struct nvidia_par *par)
96{
97 struct backlight_properties props;
98 struct fb_info *info = pci_get_drvdata(par->pci_dev);
99 struct backlight_device *bd;
100 char name[12];
101
102 if (!par->FlatPanel)
103 return;
104
105#ifdef CONFIG_PMAC_BACKLIGHT
106 if (!machine_is(powermac) ||
107 !pmac_has_backlight_type("mnca"))
108 return;
109#endif
110
111 snprintf(name, sizeof(name), "nvidiabl%d", info->node);
112
113 memset(&props, 0, sizeof(struct backlight_properties));
114 props.type = BACKLIGHT_RAW;
115 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
116 bd = backlight_device_register(name, info->dev, par, &nvidia_bl_ops,
117 &props);
118 if (IS_ERR(bd)) {
119 info->bl_dev = NULL;
120 printk(KERN_WARNING "nvidia: Backlight registration failed\n");
121 goto error;
122 }
123
124 info->bl_dev = bd;
125 fb_bl_default_curve(info, 0,
126 0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL,
127 0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL);
128
129 bd->props.brightness = bd->props.max_brightness;
130 bd->props.power = FB_BLANK_UNBLANK;
131 backlight_update_status(bd);
132
133 printk("nvidia: Backlight initialized (%s)\n", name);
134
135 return;
136
137error:
138 return;
139}
140
141void nvidia_bl_exit(struct nvidia_par *par)
142{
143 struct fb_info *info = pci_get_drvdata(par->pci_dev);
144 struct backlight_device *bd = info->bl_dev;
145
146 backlight_device_unregister(bd);
147 printk("nvidia: Backlight unloaded\n");
148}
diff --git a/drivers/video/nvidia/nv_dma.h b/drivers/video/nvidia/nv_dma.h
deleted file mode 100644
index a7ed1c0acbbb..000000000000
--- a/drivers/video/nvidia/nv_dma.h
+++ /dev/null
@@ -1,188 +0,0 @@
1
2 /***************************************************************************\
3|* *|
4|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
5|* *|
6|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
7|* international laws. Users and possessors of this source code are *|
8|* hereby granted a nonexclusive, royalty-free copyright license to *|
9|* use this code in individual and commercial software. *|
10|* *|
11|* Any use of this source code must include, in the user documenta- *|
12|* tion and internal comments to the code, notices to the end user *|
13|* as follows: *|
14|* *|
15|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
16|* *|
17|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
18|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
19|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
21|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
23|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
25|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
26|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
27|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
28|* *|
29|* U.S. Government End Users. This source code is a "commercial *|
30|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
31|* consisting of "commercial computer software" and "commercial *|
32|* computer software documentation," as such terms are used in *|
33|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
35|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
36|* all U.S. Government End Users acquire the source code with only *|
37|* those rights set forth herein. *|
38|* *|
39 \***************************************************************************/
40
41/*
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
44 * where the source code is provided "as is" without warranty of any kind.
45 * The only usage restriction is for the copyright notices to be retained
46 * whenever code is used.
47 *
48 * Antonino Daplas <adaplas@pol.net> 2005-03-11
49 */
50
51#define SURFACE_FORMAT 0x00000300
52#define SURFACE_FORMAT_DEPTH8 0x00000001
53#define SURFACE_FORMAT_DEPTH15 0x00000002
54#define SURFACE_FORMAT_DEPTH16 0x00000004
55#define SURFACE_FORMAT_DEPTH24 0x00000006
56#define SURFACE_PITCH 0x00000304
57#define SURFACE_PITCH_SRC 15:0
58#define SURFACE_PITCH_DST 31:16
59#define SURFACE_OFFSET_SRC 0x00000308
60#define SURFACE_OFFSET_DST 0x0000030C
61
62#define ROP_SET 0x00002300
63
64#define PATTERN_FORMAT 0x00004300
65#define PATTERN_FORMAT_DEPTH8 0x00000003
66#define PATTERN_FORMAT_DEPTH16 0x00000001
67#define PATTERN_FORMAT_DEPTH24 0x00000003
68#define PATTERN_COLOR_0 0x00004310
69#define PATTERN_COLOR_1 0x00004314
70#define PATTERN_PATTERN_0 0x00004318
71#define PATTERN_PATTERN_1 0x0000431C
72
73#define CLIP_POINT 0x00006300
74#define CLIP_POINT_X 15:0
75#define CLIP_POINT_Y 31:16
76#define CLIP_SIZE 0x00006304
77#define CLIP_SIZE_WIDTH 15:0
78#define CLIP_SIZE_HEIGHT 31:16
79
80#define LINE_FORMAT 0x00008300
81#define LINE_FORMAT_DEPTH8 0x00000003
82#define LINE_FORMAT_DEPTH16 0x00000001
83#define LINE_FORMAT_DEPTH24 0x00000003
84#define LINE_COLOR 0x00008304
85#define LINE_MAX_LINES 16
86#define LINE_LINES(i) 0x00008400\
87 +(i)*8
88#define LINE_LINES_POINT0_X 15:0
89#define LINE_LINES_POINT0_Y 31:16
90#define LINE_LINES_POINT1_X 47:32
91#define LINE_LINES_POINT1_Y 63:48
92
93#define BLIT_POINT_SRC 0x0000A300
94#define BLIT_POINT_SRC_X 15:0
95#define BLIT_POINT_SRC_Y 31:16
96#define BLIT_POINT_DST 0x0000A304
97#define BLIT_POINT_DST_X 15:0
98#define BLIT_POINT_DST_Y 31:16
99#define BLIT_SIZE 0x0000A308
100#define BLIT_SIZE_WIDTH 15:0
101#define BLIT_SIZE_HEIGHT 31:16
102
103#define RECT_FORMAT 0x0000C300
104#define RECT_FORMAT_DEPTH8 0x00000003
105#define RECT_FORMAT_DEPTH16 0x00000001
106#define RECT_FORMAT_DEPTH24 0x00000003
107#define RECT_SOLID_COLOR 0x0000C3FC
108#define RECT_SOLID_RECTS_MAX_RECTS 32
109#define RECT_SOLID_RECTS(i) 0x0000C400\
110 +(i)*8
111#define RECT_SOLID_RECTS_Y 15:0
112#define RECT_SOLID_RECTS_X 31:16
113#define RECT_SOLID_RECTS_HEIGHT 47:32
114#define RECT_SOLID_RECTS_WIDTH 63:48
115
116#define RECT_EXPAND_ONE_COLOR_CLIP 0x0000C7EC
117#define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_X 15:0
118#define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_Y 31:16
119#define RECT_EXPAND_ONE_COLOR_CLIP_POINT1_X 47:32
120#define RECT_EXPAND_ONE_COLOR_CLIP_POINT1_Y 63:48
121#define RECT_EXPAND_ONE_COLOR_COLOR 0x0000C7F4
122#define RECT_EXPAND_ONE_COLOR_SIZE 0x0000C7F8
123#define RECT_EXPAND_ONE_COLOR_SIZE_WIDTH 15:0
124#define RECT_EXPAND_ONE_COLOR_SIZE_HEIGHT 31:16
125#define RECT_EXPAND_ONE_COLOR_POINT 0x0000C7FC
126#define RECT_EXPAND_ONE_COLOR_POINT_X 15:0
127#define RECT_EXPAND_ONE_COLOR_POINT_Y 31:16
128#define RECT_EXPAND_ONE_COLOR_DATA_MAX_DWORDS 128
129#define RECT_EXPAND_ONE_COLOR_DATA(i) 0x0000C800\
130 +(i)*4
131
132#define RECT_EXPAND_TWO_COLOR_CLIP 0x0000CBE4
133#define RECT_EXPAND_TWO_COLOR_CLIP_POINT0_X 15:0
134#define RECT_EXPAND_TWO_COLOR_CLIP_POINT0_Y 31:16
135#define RECT_EXPAND_TWO_COLOR_CLIP_POINT1_X 47:32
136#define RECT_EXPAND_TWO_COLOR_CLIP_POINT1_Y 63:48
137#define RECT_EXPAND_TWO_COLOR_COLOR_0 0x0000CBEC
138#define RECT_EXPAND_TWO_COLOR_COLOR_1 0x0000CBF0
139#define RECT_EXPAND_TWO_COLOR_SIZE_IN 0x0000CBF4
140#define RECT_EXPAND_TWO_COLOR_SIZE_IN_WIDTH 15:0
141#define RECT_EXPAND_TWO_COLOR_SIZE_IN_HEIGHT 31:16
142#define RECT_EXPAND_TWO_COLOR_SIZE_OUT 0x0000CBF8
143#define RECT_EXPAND_TWO_COLOR_SIZE_OUT_WIDTH 15:0
144#define RECT_EXPAND_TWO_COLOR_SIZE_OUT_HEIGHT 31:16
145#define RECT_EXPAND_TWO_COLOR_POINT 0x0000CBFC
146#define RECT_EXPAND_TWO_COLOR_POINT_X 15:0
147#define RECT_EXPAND_TWO_COLOR_POINT_Y 31:16
148#define RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS 128
149#define RECT_EXPAND_TWO_COLOR_DATA(i) 0x0000CC00\
150 +(i)*4
151
152#define STRETCH_BLIT_FORMAT 0x0000E300
153#define STRETCH_BLIT_FORMAT_DEPTH8 0x00000004
154#define STRETCH_BLIT_FORMAT_DEPTH16 0x00000007
155#define STRETCH_BLIT_FORMAT_DEPTH24 0x00000004
156#define STRETCH_BLIT_FORMAT_X8R8G8B8 0x00000004
157#define STRETCH_BLIT_FORMAT_YUYV 0x00000005
158#define STRETCH_BLIT_FORMAT_UYVY 0x00000006
159#define STRETCH_BLIT_CLIP_POINT 0x0000E308
160#define STRETCH_BLIT_CLIP_POINT_X 15:0
161#define STRETCH_BLIT_CLIP_POINT_Y 31:16
162#define STRETCH_BLIT_CLIP_POINT 0x0000E308
163#define STRETCH_BLIT_CLIP_SIZE 0x0000E30C
164#define STRETCH_BLIT_CLIP_SIZE_WIDTH 15:0
165#define STRETCH_BLIT_CLIP_SIZE_HEIGHT 31:16
166#define STRETCH_BLIT_DST_POINT 0x0000E310
167#define STRETCH_BLIT_DST_POINT_X 15:0
168#define STRETCH_BLIT_DST_POINT_Y 31:16
169#define STRETCH_BLIT_DST_SIZE 0x0000E314
170#define STRETCH_BLIT_DST_SIZE_WIDTH 15:0
171#define STRETCH_BLIT_DST_SIZE_HEIGHT 31:16
172#define STRETCH_BLIT_DU_DX 0x0000E318
173#define STRETCH_BLIT_DV_DY 0x0000E31C
174#define STRETCH_BLIT_SRC_SIZE 0x0000E400
175#define STRETCH_BLIT_SRC_SIZE_WIDTH 15:0
176#define STRETCH_BLIT_SRC_SIZE_HEIGHT 31:16
177#define STRETCH_BLIT_SRC_FORMAT 0x0000E404
178#define STRETCH_BLIT_SRC_FORMAT_PITCH 15:0
179#define STRETCH_BLIT_SRC_FORMAT_ORIGIN 23:16
180#define STRETCH_BLIT_SRC_FORMAT_ORIGIN_CENTER 0x00000001
181#define STRETCH_BLIT_SRC_FORMAT_ORIGIN_CORNER 0x00000002
182#define STRETCH_BLIT_SRC_FORMAT_FILTER 31:24
183#define STRETCH_BLIT_SRC_FORMAT_FILTER_POINT_SAMPLE 0x00000000
184#define STRETCH_BLIT_SRC_FORMAT_FILTER_BILINEAR 0x00000001
185#define STRETCH_BLIT_SRC_OFFSET 0x0000E408
186#define STRETCH_BLIT_SRC_POINT 0x0000E40C
187#define STRETCH_BLIT_SRC_POINT_U 15:0
188#define STRETCH_BLIT_SRC_POINT_V 31:16
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c
deleted file mode 100644
index 81c80ac3c76f..000000000000
--- a/drivers/video/nvidia/nv_hw.c
+++ /dev/null
@@ -1,1687 +0,0 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */
51
52#include <linux/pci.h>
53#include "nv_type.h"
54#include "nv_local.h"
55#include "nv_proto.h"
56
57void NVLockUnlock(struct nvidia_par *par, int Lock)
58{
59 u8 cr11;
60
61 VGA_WR08(par->PCIO, 0x3D4, 0x1F);
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
63
64 VGA_WR08(par->PCIO, 0x3D4, 0x11);
65 cr11 = VGA_RD08(par->PCIO, 0x3D5);
66 if (Lock)
67 cr11 |= 0x80;
68 else
69 cr11 &= ~0x80;
70 VGA_WR08(par->PCIO, 0x3D5, cr11);
71}
72
73int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
74{
75 int cur = par->CurrentState->cursor1;
76
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
78 (ShowHide & 0x01);
79 VGA_WR08(par->PCIO, 0x3D4, 0x31);
80 VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
81
82 if (par->Architecture == NV_ARCH_40)
83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
84
85 return (cur & 0x01);
86}
87
88/****************************************************************************\
89* *
90* The video arbitration routines calculate some "magic" numbers. Fixes *
91* the snow seen when accessing the framebuffer without it. *
92* It just works (I hope). *
93* *
94\****************************************************************************/
95
96typedef struct {
97 int graphics_lwm;
98 int video_lwm;
99 int graphics_burst_size;
100 int video_burst_size;
101 int valid;
102} nv4_fifo_info;
103
104typedef struct {
105 int pclk_khz;
106 int mclk_khz;
107 int nvclk_khz;
108 char mem_page_miss;
109 char mem_latency;
110 int memory_width;
111 char enable_video;
112 char gr_during_vid;
113 char pix_bpp;
114 char mem_aligned;
115 char enable_mp;
116} nv4_sim_state;
117
118typedef struct {
119 int graphics_lwm;
120 int video_lwm;
121 int graphics_burst_size;
122 int video_burst_size;
123 int valid;
124} nv10_fifo_info;
125
126typedef struct {
127 int pclk_khz;
128 int mclk_khz;
129 int nvclk_khz;
130 char mem_page_miss;
131 char mem_latency;
132 u32 memory_type;
133 int memory_width;
134 char enable_video;
135 char gr_during_vid;
136 char pix_bpp;
137 char mem_aligned;
138 char enable_mp;
139} nv10_sim_state;
140
141static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
142 unsigned int *NVClk)
143{
144 unsigned int pll, N, M, MB, NB, P;
145
146 if (par->Architecture >= NV_ARCH_40) {
147 pll = NV_RD32(par->PMC, 0x4020);
148 P = (pll >> 16) & 0x07;
149 pll = NV_RD32(par->PMC, 0x4024);
150 M = pll & 0xFF;
151 N = (pll >> 8) & 0xFF;
152 if (((par->Chipset & 0xfff0) == 0x0290) ||
153 ((par->Chipset & 0xfff0) == 0x0390)) {
154 MB = 1;
155 NB = 1;
156 } else {
157 MB = (pll >> 16) & 0xFF;
158 NB = (pll >> 24) & 0xFF;
159 }
160 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
161
162 pll = NV_RD32(par->PMC, 0x4000);
163 P = (pll >> 16) & 0x07;
164 pll = NV_RD32(par->PMC, 0x4004);
165 M = pll & 0xFF;
166 N = (pll >> 8) & 0xFF;
167 MB = (pll >> 16) & 0xFF;
168 NB = (pll >> 24) & 0xFF;
169
170 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
171 } else if (par->twoStagePLL) {
172 pll = NV_RD32(par->PRAMDAC0, 0x0504);
173 M = pll & 0xFF;
174 N = (pll >> 8) & 0xFF;
175 P = (pll >> 16) & 0x0F;
176 pll = NV_RD32(par->PRAMDAC0, 0x0574);
177 if (pll & 0x80000000) {
178 MB = pll & 0xFF;
179 NB = (pll >> 8) & 0xFF;
180 } else {
181 MB = 1;
182 NB = 1;
183 }
184 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
185
186 pll = NV_RD32(par->PRAMDAC0, 0x0500);
187 M = pll & 0xFF;
188 N = (pll >> 8) & 0xFF;
189 P = (pll >> 16) & 0x0F;
190 pll = NV_RD32(par->PRAMDAC0, 0x0570);
191 if (pll & 0x80000000) {
192 MB = pll & 0xFF;
193 NB = (pll >> 8) & 0xFF;
194 } else {
195 MB = 1;
196 NB = 1;
197 }
198 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
199 } else
200 if (((par->Chipset & 0x0ff0) == 0x0300) ||
201 ((par->Chipset & 0x0ff0) == 0x0330)) {
202 pll = NV_RD32(par->PRAMDAC0, 0x0504);
203 M = pll & 0x0F;
204 N = (pll >> 8) & 0xFF;
205 P = (pll >> 16) & 0x07;
206 if (pll & 0x00000080) {
207 MB = (pll >> 4) & 0x07;
208 NB = (pll >> 19) & 0x1f;
209 } else {
210 MB = 1;
211 NB = 1;
212 }
213 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
214
215 pll = NV_RD32(par->PRAMDAC0, 0x0500);
216 M = pll & 0x0F;
217 N = (pll >> 8) & 0xFF;
218 P = (pll >> 16) & 0x07;
219 if (pll & 0x00000080) {
220 MB = (pll >> 4) & 0x07;
221 NB = (pll >> 19) & 0x1f;
222 } else {
223 MB = 1;
224 NB = 1;
225 }
226 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
227 } else {
228 pll = NV_RD32(par->PRAMDAC0, 0x0504);
229 M = pll & 0xFF;
230 N = (pll >> 8) & 0xFF;
231 P = (pll >> 16) & 0x0F;
232 *MClk = (N * par->CrystalFreqKHz / M) >> P;
233
234 pll = NV_RD32(par->PRAMDAC0, 0x0500);
235 M = pll & 0xFF;
236 N = (pll >> 8) & 0xFF;
237 P = (pll >> 16) & 0x0F;
238 *NVClk = (N * par->CrystalFreqKHz / M) >> P;
239 }
240}
241
242static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb)
243{
244 int data, pagemiss, cas, width, video_enable, bpp;
245 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
246 int found, mclk_extra, mclk_loop, cbs, m1, p1;
247 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
248 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
249 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
250
251 fifo->valid = 1;
252 pclk_freq = arb->pclk_khz;
253 mclk_freq = arb->mclk_khz;
254 nvclk_freq = arb->nvclk_khz;
255 pagemiss = arb->mem_page_miss;
256 cas = arb->mem_latency;
257 width = arb->memory_width >> 6;
258 video_enable = arb->enable_video;
259 bpp = arb->pix_bpp;
260 mp_enable = arb->enable_mp;
261 clwm = 0;
262 vlwm = 0;
263 cbs = 128;
264 pclks = 2;
265 nvclks = 2;
266 nvclks += 2;
267 nvclks += 1;
268 mclks = 5;
269 mclks += 3;
270 mclks += 1;
271 mclks += cas;
272 mclks += 1;
273 mclks += 1;
274 mclks += 1;
275 mclks += 1;
276 mclk_extra = 3;
277 nvclks += 2;
278 nvclks += 1;
279 nvclks += 1;
280 nvclks += 1;
281 if (mp_enable)
282 mclks += 4;
283 nvclks += 0;
284 pclks += 0;
285 found = 0;
286 vbs = 0;
287 while (found != 1) {
288 fifo->valid = 1;
289 found = 1;
290 mclk_loop = mclks + mclk_extra;
291 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
292 us_n = nvclks * 1000 * 1000 / nvclk_freq;
293 us_p = nvclks * 1000 * 1000 / pclk_freq;
294 if (video_enable) {
295 video_drain_rate = pclk_freq * 2;
296 crtc_drain_rate = pclk_freq * bpp / 8;
297 vpagemiss = 2;
298 vpagemiss += 1;
299 crtpagemiss = 2;
300 vpm_us =
301 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
302 if (nvclk_freq * 2 > mclk_freq * width)
303 video_fill_us =
304 cbs * 1000 * 1000 / 16 / nvclk_freq;
305 else
306 video_fill_us =
307 cbs * 1000 * 1000 / (8 * width) /
308 mclk_freq;
309 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
310 vlwm = us_video * video_drain_rate / (1000 * 1000);
311 vlwm++;
312 vbs = 128;
313 if (vlwm > 128)
314 vbs = 64;
315 if (vlwm > (256 - 64))
316 vbs = 32;
317 if (nvclk_freq * 2 > mclk_freq * width)
318 video_fill_us =
319 vbs * 1000 * 1000 / 16 / nvclk_freq;
320 else
321 video_fill_us =
322 vbs * 1000 * 1000 / (8 * width) /
323 mclk_freq;
324 cpm_us =
325 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
326 us_crt =
327 us_video + video_fill_us + cpm_us + us_m + us_n +
328 us_p;
329 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
330 clwm++;
331 } else {
332 crtc_drain_rate = pclk_freq * bpp / 8;
333 crtpagemiss = 2;
334 crtpagemiss += 1;
335 cpm_us =
336 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
337 us_crt = cpm_us + us_m + us_n + us_p;
338 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
339 clwm++;
340 }
341 m1 = clwm + cbs - 512;
342 p1 = m1 * pclk_freq / mclk_freq;
343 p1 = p1 * bpp / 8;
344 if ((p1 < m1) && (m1 > 0)) {
345 fifo->valid = 0;
346 found = 0;
347 if (mclk_extra == 0)
348 found = 1;
349 mclk_extra--;
350 } else if (video_enable) {
351 if ((clwm > 511) || (vlwm > 255)) {
352 fifo->valid = 0;
353 found = 0;
354 if (mclk_extra == 0)
355 found = 1;
356 mclk_extra--;
357 }
358 } else {
359 if (clwm > 519) {
360 fifo->valid = 0;
361 found = 0;
362 if (mclk_extra == 0)
363 found = 1;
364 mclk_extra--;
365 }
366 }
367 if (clwm < 384)
368 clwm = 384;
369 if (vlwm < 128)
370 vlwm = 128;
371 data = (int)(clwm);
372 fifo->graphics_lwm = data;
373 fifo->graphics_burst_size = 128;
374 data = (int)((vlwm + 15));
375 fifo->video_lwm = data;
376 fifo->video_burst_size = vbs;
377 }
378}
379
380static void nv4UpdateArbitrationSettings(unsigned VClk,
381 unsigned pixelDepth,
382 unsigned *burst,
383 unsigned *lwm, struct nvidia_par *par)
384{
385 nv4_fifo_info fifo_data;
386 nv4_sim_state sim_data;
387 unsigned int MClk, NVClk, cfg1;
388
389 nvGetClocks(par, &MClk, &NVClk);
390
391 cfg1 = NV_RD32(par->PFB, 0x00000204);
392 sim_data.pix_bpp = (char)pixelDepth;
393 sim_data.enable_video = 0;
394 sim_data.enable_mp = 0;
395 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
396 128 : 64;
397 sim_data.mem_latency = (char)cfg1 & 0x0F;
398 sim_data.mem_aligned = 1;
399 sim_data.mem_page_miss =
400 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
401 sim_data.gr_during_vid = 0;
402 sim_data.pclk_khz = VClk;
403 sim_data.mclk_khz = MClk;
404 sim_data.nvclk_khz = NVClk;
405 nv4CalcArbitration(&fifo_data, &sim_data);
406 if (fifo_data.valid) {
407 int b = fifo_data.graphics_burst_size >> 4;
408 *burst = 0;
409 while (b >>= 1)
410 (*burst)++;
411 *lwm = fifo_data.graphics_lwm >> 3;
412 }
413}
414
415static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb)
416{
417 int data, pagemiss, width, video_enable, bpp;
418 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
419 int nvclk_fill;
420 int found, mclk_extra, mclk_loop, cbs, m1;
421 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
422 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
423 int vus_m;
424 int vpm_us, us_video, cpm_us, us_crt, clwm;
425 int clwm_rnd_down;
426 int m2us, us_pipe_min, p1clk, p2;
427 int min_mclk_extra;
428 int us_min_mclk_extra;
429
430 fifo->valid = 1;
431 pclk_freq = arb->pclk_khz; /* freq in KHz */
432 mclk_freq = arb->mclk_khz;
433 nvclk_freq = arb->nvclk_khz;
434 pagemiss = arb->mem_page_miss;
435 width = arb->memory_width / 64;
436 video_enable = arb->enable_video;
437 bpp = arb->pix_bpp;
438 mp_enable = arb->enable_mp;
439 clwm = 0;
440
441 cbs = 512;
442
443 pclks = 4; /* lwm detect. */
444
445 nvclks = 3; /* lwm -> sync. */
446 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
447 /* 2 edge sync. may be very close to edge so just put one. */
448 mclks = 1;
449 mclks += 1; /* arb_hp_req */
450 mclks += 5; /* ap_hp_req tiling pipeline */
451
452 mclks += 2; /* tc_req latency fifo */
453 mclks += 2; /* fb_cas_n_ memory request to fbio block */
454 mclks += 7; /* sm_d_rdv data returned from fbio block */
455
456 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
457 if (arb->memory_type == 0)
458 if (arb->memory_width == 64) /* 64 bit bus */
459 mclks += 4;
460 else
461 mclks += 2;
462 else if (arb->memory_width == 64) /* 64 bit bus */
463 mclks += 2;
464 else
465 mclks += 1;
466
467 if ((!video_enable) && (arb->memory_width == 128)) {
468 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
469 min_mclk_extra = 17;
470 } else {
471 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
472 /* mclk_extra = 4; *//* Margin of error */
473 min_mclk_extra = 18;
474 }
475
476 /* 2 edge sync. may be very close to edge so just put one. */
477 nvclks += 1;
478 nvclks += 1; /* fbi_d_rdv_n */
479 nvclks += 1; /* Fbi_d_rdata */
480 nvclks += 1; /* crtfifo load */
481
482 if (mp_enable)
483 mclks += 4; /* Mp can get in with a burst of 8. */
484 /* Extra clocks determined by heuristics */
485
486 nvclks += 0;
487 pclks += 0;
488 found = 0;
489 while (found != 1) {
490 fifo->valid = 1;
491 found = 1;
492 mclk_loop = mclks + mclk_extra;
493 /* Mclk latency in us */
494 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
495 /* Minimum Mclk latency in us */
496 us_m_min = mclks * 1000 * 1000 / mclk_freq;
497 us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
498 /* nvclk latency in us */
499 us_n = nvclks * 1000 * 1000 / nvclk_freq;
500 /* nvclk latency in us */
501 us_p = pclks * 1000 * 1000 / pclk_freq;
502 us_pipe_min = us_m_min + us_n + us_p;
503
504 /* Mclk latency in us */
505 vus_m = mclk_loop * 1000 * 1000 / mclk_freq;
506
507 if (video_enable) {
508 crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */
509
510 vpagemiss = 1; /* self generating page miss */
511 vpagemiss += 1; /* One higher priority before */
512
513 crtpagemiss = 2; /* self generating page miss */
514 if (mp_enable)
515 crtpagemiss += 1; /* if MA0 conflict */
516
517 vpm_us =
518 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
519
520 /* Video has separate read return path */
521 us_video = vpm_us + vus_m;
522
523 cpm_us =
524 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
525 /* Wait for video */
526 us_crt = us_video
527 + cpm_us /* CRT Page miss */
528 + us_m + us_n + us_p /* other latency */
529 ;
530
531 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
532 /* fixed point <= float_point - 1. Fixes that */
533 clwm++;
534 } else {
535 /* bpp * pclk/8 */
536 crtc_drain_rate = pclk_freq * bpp / 8;
537
538 crtpagemiss = 1; /* self generating page miss */
539 crtpagemiss += 1; /* MA0 page miss */
540 if (mp_enable)
541 crtpagemiss += 1; /* if MA0 conflict */
542 cpm_us =
543 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
544 us_crt = cpm_us + us_m + us_n + us_p;
545 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
546 /* fixed point <= float_point - 1. Fixes that */
547 clwm++;
548
549 /* Finally, a heuristic check when width == 64 bits */
550 if (width == 1) {
551 nvclk_fill = nvclk_freq * 8;
552 if (crtc_drain_rate * 100 >= nvclk_fill * 102)
553 /*Large number to fail */
554 clwm = 0xfff;
555
556 else if (crtc_drain_rate * 100 >=
557 nvclk_fill * 98) {
558 clwm = 1024;
559 cbs = 512;
560 }
561 }
562 }
563
564 /*
565 Overfill check:
566 */
567
568 clwm_rnd_down = ((int)clwm / 8) * 8;
569 if (clwm_rnd_down < clwm)
570 clwm += 8;
571
572 m1 = clwm + cbs - 1024; /* Amount of overfill */
573 m2us = us_pipe_min + us_min_mclk_extra;
574
575 /* pclk cycles to drain */
576 p1clk = m2us * pclk_freq / (1000 * 1000);
577 p2 = p1clk * bpp / 8; /* bytes drained. */
578
579 if ((p2 < m1) && (m1 > 0)) {
580 fifo->valid = 0;
581 found = 0;
582 if (min_mclk_extra == 0) {
583 if (cbs <= 32) {
584 /* Can't adjust anymore! */
585 found = 1;
586 } else {
587 /* reduce the burst size */
588 cbs = cbs / 2;
589 }
590 } else {
591 min_mclk_extra--;
592 }
593 } else {
594 if (clwm > 1023) { /* Have some margin */
595 fifo->valid = 0;
596 found = 0;
597 if (min_mclk_extra == 0)
598 /* Can't adjust anymore! */
599 found = 1;
600 else
601 min_mclk_extra--;
602 }
603 }
604
605 if (clwm < (1024 - cbs + 8))
606 clwm = 1024 - cbs + 8;
607 data = (int)(clwm);
608 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n",
609 clwm, data ); */
610 fifo->graphics_lwm = data;
611 fifo->graphics_burst_size = cbs;
612
613 fifo->video_lwm = 1024;
614 fifo->video_burst_size = 512;
615 }
616}
617
618static void nv10UpdateArbitrationSettings(unsigned VClk,
619 unsigned pixelDepth,
620 unsigned *burst,
621 unsigned *lwm,
622 struct nvidia_par *par)
623{
624 nv10_fifo_info fifo_data;
625 nv10_sim_state sim_data;
626 unsigned int MClk, NVClk, cfg1;
627
628 nvGetClocks(par, &MClk, &NVClk);
629
630 cfg1 = NV_RD32(par->PFB, 0x0204);
631 sim_data.pix_bpp = (char)pixelDepth;
632 sim_data.enable_video = 1;
633 sim_data.enable_mp = 0;
634 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
635 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
636 128 : 64;
637 sim_data.mem_latency = (char)cfg1 & 0x0F;
638 sim_data.mem_aligned = 1;
639 sim_data.mem_page_miss =
640 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
641 sim_data.gr_during_vid = 0;
642 sim_data.pclk_khz = VClk;
643 sim_data.mclk_khz = MClk;
644 sim_data.nvclk_khz = NVClk;
645 nv10CalcArbitration(&fifo_data, &sim_data);
646 if (fifo_data.valid) {
647 int b = fifo_data.graphics_burst_size >> 4;
648 *burst = 0;
649 while (b >>= 1)
650 (*burst)++;
651 *lwm = fifo_data.graphics_lwm >> 3;
652 }
653}
654
655static void nv30UpdateArbitrationSettings (
656 struct nvidia_par *par,
657 unsigned int *burst,
658 unsigned int *lwm
659)
660{
661 unsigned int MClk, NVClk;
662 unsigned int fifo_size, burst_size, graphics_lwm;
663
664 fifo_size = 2048;
665 burst_size = 512;
666 graphics_lwm = fifo_size - burst_size;
667
668 nvGetClocks(par, &MClk, &NVClk);
669
670 *burst = 0;
671 burst_size >>= 5;
672 while(burst_size >>= 1) (*burst)++;
673 *lwm = graphics_lwm >> 3;
674}
675
676static void nForceUpdateArbitrationSettings(unsigned VClk,
677 unsigned pixelDepth,
678 unsigned *burst,
679 unsigned *lwm,
680 struct nvidia_par *par)
681{
682 nv10_fifo_info fifo_data;
683 nv10_sim_state sim_data;
684 unsigned int M, N, P, pll, MClk, NVClk, memctrl;
685 struct pci_dev *dev;
686
687 if ((par->Chipset & 0x0FF0) == 0x01A0) {
688 unsigned int uMClkPostDiv;
689 dev = pci_get_bus_and_slot(0, 3);
690 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
691 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
692
693 if (!uMClkPostDiv)
694 uMClkPostDiv = 4;
695 MClk = 400000 / uMClkPostDiv;
696 } else {
697 dev = pci_get_bus_and_slot(0, 5);
698 pci_read_config_dword(dev, 0x4c, &MClk);
699 MClk /= 1000;
700 }
701 pci_dev_put(dev);
702 pll = NV_RD32(par->PRAMDAC0, 0x0500);
703 M = (pll >> 0) & 0xFF;
704 N = (pll >> 8) & 0xFF;
705 P = (pll >> 16) & 0x0F;
706 NVClk = (N * par->CrystalFreqKHz / M) >> P;
707 sim_data.pix_bpp = (char)pixelDepth;
708 sim_data.enable_video = 0;
709 sim_data.enable_mp = 0;
710 dev = pci_get_bus_and_slot(0, 1);
711 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
712 pci_dev_put(dev);
713 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
714 sim_data.memory_width = 64;
715
716 dev = pci_get_bus_and_slot(0, 3);
717 pci_read_config_dword(dev, 0, &memctrl);
718 pci_dev_put(dev);
719 memctrl >>= 16;
720
721 if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
722 u32 dimm[3];
723
724 dev = pci_get_bus_and_slot(0, 2);
725 pci_read_config_dword(dev, 0x40, &dimm[0]);
726 dimm[0] = (dimm[0] >> 8) & 0x4f;
727 pci_read_config_dword(dev, 0x44, &dimm[1]);
728 dimm[1] = (dimm[1] >> 8) & 0x4f;
729 pci_read_config_dword(dev, 0x48, &dimm[2]);
730 dimm[2] = (dimm[2] >> 8) & 0x4f;
731
732 if ((dimm[0] + dimm[1]) != dimm[2]) {
733 printk("nvidiafb: your nForce DIMMs are not arranged "
734 "in optimal banks!\n");
735 }
736 pci_dev_put(dev);
737 }
738
739 sim_data.mem_latency = 3;
740 sim_data.mem_aligned = 1;
741 sim_data.mem_page_miss = 10;
742 sim_data.gr_during_vid = 0;
743 sim_data.pclk_khz = VClk;
744 sim_data.mclk_khz = MClk;
745 sim_data.nvclk_khz = NVClk;
746 nv10CalcArbitration(&fifo_data, &sim_data);
747 if (fifo_data.valid) {
748 int b = fifo_data.graphics_burst_size >> 4;
749 *burst = 0;
750 while (b >>= 1)
751 (*burst)++;
752 *lwm = fifo_data.graphics_lwm >> 3;
753 }
754}
755
756/****************************************************************************\
757* *
758* RIVA Mode State Routines *
759* *
760\****************************************************************************/
761
762/*
763 * Calculate the Video Clock parameters for the PLL.
764 */
765static void CalcVClock(int clockIn,
766 int *clockOut, u32 * pllOut, struct nvidia_par *par)
767{
768 unsigned lowM, highM;
769 unsigned DeltaNew, DeltaOld;
770 unsigned VClk, Freq;
771 unsigned M, N, P;
772
773 DeltaOld = 0xFFFFFFFF;
774
775 VClk = (unsigned)clockIn;
776
777 if (par->CrystalFreqKHz == 13500) {
778 lowM = 7;
779 highM = 13;
780 } else {
781 lowM = 8;
782 highM = 14;
783 }
784
785 for (P = 0; P <= 4; P++) {
786 Freq = VClk << P;
787 if ((Freq >= 128000) && (Freq <= 350000)) {
788 for (M = lowM; M <= highM; M++) {
789 N = ((VClk << P) * M) / par->CrystalFreqKHz;
790 if (N <= 255) {
791 Freq =
792 ((par->CrystalFreqKHz * N) /
793 M) >> P;
794 if (Freq > VClk)
795 DeltaNew = Freq - VClk;
796 else
797 DeltaNew = VClk - Freq;
798 if (DeltaNew < DeltaOld) {
799 *pllOut =
800 (P << 16) | (N << 8) | M;
801 *clockOut = Freq;
802 DeltaOld = DeltaNew;
803 }
804 }
805 }
806 }
807 }
808}
809
810static void CalcVClock2Stage(int clockIn,
811 int *clockOut,
812 u32 * pllOut,
813 u32 * pllBOut, struct nvidia_par *par)
814{
815 unsigned DeltaNew, DeltaOld;
816 unsigned VClk, Freq;
817 unsigned M, N, P;
818
819 DeltaOld = 0xFFFFFFFF;
820
821 *pllBOut = 0x80000401; /* fixed at x4 for now */
822
823 VClk = (unsigned)clockIn;
824
825 for (P = 0; P <= 6; P++) {
826 Freq = VClk << P;
827 if ((Freq >= 400000) && (Freq <= 1000000)) {
828 for (M = 1; M <= 13; M++) {
829 N = ((VClk << P) * M) /
830 (par->CrystalFreqKHz << 2);
831 if ((N >= 5) && (N <= 255)) {
832 Freq =
833 (((par->CrystalFreqKHz << 2) * N) /
834 M) >> P;
835 if (Freq > VClk)
836 DeltaNew = Freq - VClk;
837 else
838 DeltaNew = VClk - Freq;
839 if (DeltaNew < DeltaOld) {
840 *pllOut =
841 (P << 16) | (N << 8) | M;
842 *clockOut = Freq;
843 DeltaOld = DeltaNew;
844 }
845 }
846 }
847 }
848 }
849}
850
851/*
852 * Calculate extended mode parameters (SVGA) and save in a
853 * mode state structure.
854 */
855void NVCalcStateExt(struct nvidia_par *par,
856 RIVA_HW_STATE * state,
857 int bpp,
858 int width,
859 int hDisplaySize, int height, int dotClock, int flags)
860{
861 int pixelDepth, VClk = 0;
862 /*
863 * Save mode parameters.
864 */
865 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
866 state->width = width;
867 state->height = height;
868 /*
869 * Extended RIVA registers.
870 */
871 pixelDepth = (bpp + 1) / 8;
872 if (par->twoStagePLL)
873 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
874 par);
875 else
876 CalcVClock(dotClock, &VClk, &state->pll, par);
877
878 switch (par->Architecture) {
879 case NV_ARCH_04:
880 nv4UpdateArbitrationSettings(VClk,
881 pixelDepth * 8,
882 &(state->arbitration0),
883 &(state->arbitration1), par);
884 state->cursor0 = 0x00;
885 state->cursor1 = 0xbC;
886 if (flags & FB_VMODE_DOUBLE)
887 state->cursor1 |= 2;
888 state->cursor2 = 0x00000000;
889 state->pllsel = 0x10000700;
890 state->config = 0x00001114;
891 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
892 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
893 break;
894 case NV_ARCH_40:
895 if (!par->FlatPanel)
896 state->control = NV_RD32(par->PRAMDAC0, 0x0580) &
897 0xeffffeff;
898 /* fallthrough */
899 case NV_ARCH_10:
900 case NV_ARCH_20:
901 case NV_ARCH_30:
902 default:
903 if ((par->Chipset & 0xfff0) == 0x0240 ||
904 (par->Chipset & 0xfff0) == 0x03d0) {
905 state->arbitration0 = 256;
906 state->arbitration1 = 0x0480;
907 } else if (((par->Chipset & 0xffff) == 0x01A0) ||
908 ((par->Chipset & 0xffff) == 0x01f0)) {
909 nForceUpdateArbitrationSettings(VClk,
910 pixelDepth * 8,
911 &(state->arbitration0),
912 &(state->arbitration1),
913 par);
914 } else if (par->Architecture < NV_ARCH_30) {
915 nv10UpdateArbitrationSettings(VClk,
916 pixelDepth * 8,
917 &(state->arbitration0),
918 &(state->arbitration1),
919 par);
920 } else {
921 nv30UpdateArbitrationSettings(par,
922 &(state->arbitration0),
923 &(state->arbitration1));
924 }
925
926 state->cursor0 = 0x80 | (par->CursorStart >> 17);
927 state->cursor1 = (par->CursorStart >> 11) << 2;
928 state->cursor2 = par->CursorStart >> 24;
929 if (flags & FB_VMODE_DOUBLE)
930 state->cursor1 |= 2;
931 state->pllsel = 0x10000700;
932 state->config = NV_RD32(par->PFB, 0x00000200);
933 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
934 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
935 break;
936 }
937
938 if (bpp != 8) /* DirectColor */
939 state->general |= 0x00000030;
940
941 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
942 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
943}
944
945void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
946{
947 int i, j;
948
949 NV_WR32(par->PMC, 0x0140, 0x00000000);
950 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
951 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
952
953 NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
954 NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
955 NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
956 NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
957
958 if (par->Architecture == NV_ARCH_04) {
959 if (state)
960 NV_WR32(par->PFB, 0x0200, state->config);
961 } else if ((par->Architecture < NV_ARCH_40) ||
962 (par->Chipset & 0xfff0) == 0x0040) {
963 for (i = 0; i < 8; i++) {
964 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
965 NV_WR32(par->PFB, 0x0244 + (i * 0x10),
966 par->FbMapSize - 1);
967 }
968 } else {
969 int regions = 12;
970
971 if (((par->Chipset & 0xfff0) == 0x0090) ||
972 ((par->Chipset & 0xfff0) == 0x01D0) ||
973 ((par->Chipset & 0xfff0) == 0x0290) ||
974 ((par->Chipset & 0xfff0) == 0x0390) ||
975 ((par->Chipset & 0xfff0) == 0x03D0))
976 regions = 15;
977 for(i = 0; i < regions; i++) {
978 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
979 NV_WR32(par->PFB, 0x0604 + (i * 0x10),
980 par->FbMapSize - 1);
981 }
982 }
983
984 if (par->Architecture >= NV_ARCH_40) {
985 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
986 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
987 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
988 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
989 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
990 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
991 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
992 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
993 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
994 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
995 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
996 NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
997 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
998 NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
999 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1000 NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
1001 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1002 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1003 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1004 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
1005 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1006 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
1007 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
1008 NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
1009 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
1010 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
1011 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1012 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1013 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1014 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
1015 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1016 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
1017 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
1018 NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
1019 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1020 NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
1021 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
1022 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
1023 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1024 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
1025 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1026 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
1027 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
1028 NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
1029 NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
1030 NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
1031 NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
1032 NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
1033 NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
1034 NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
1035 NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
1036 NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
1037 NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
1038 NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
1039 NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
1040 NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
1041 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
1042 NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
1043 NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
1044 NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
1045 NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
1046 NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
1047 NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
1048 NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
1049 NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
1050 NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
1051 NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
1052 NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
1053 NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
1054 NV_WR32(par->PRAMIN, 0x084E * 4,
1055 par->FbUsableSize | 0x00000002);
1056
1057#ifdef __BIG_ENDIAN
1058 NV_WR32(par->PRAMIN, 0x080A * 4,
1059 NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
1060 NV_WR32(par->PRAMIN, 0x0812 * 4,
1061 NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
1062 NV_WR32(par->PRAMIN, 0x081A * 4,
1063 NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
1064 NV_WR32(par->PRAMIN, 0x0822 * 4,
1065 NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
1066 NV_WR32(par->PRAMIN, 0x082A * 4,
1067 NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
1068 NV_WR32(par->PRAMIN, 0x0832 * 4,
1069 NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
1070 NV_WR32(par->PRAMIN, 0x083A * 4,
1071 NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
1072 NV_WR32(par->PRAMIN, 0x0842 * 4,
1073 NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
1074 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
1075 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
1076#endif
1077 } else {
1078 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
1079 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
1080 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
1081 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
1082 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
1083 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
1084 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
1085 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
1086 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
1087 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
1088 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
1089 NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
1090 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
1091 NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
1092 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1093 NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
1094 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1095 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1096 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1097 NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
1098 if (par->Architecture >= NV_ARCH_10)
1099 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
1100 else
1101 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
1102 NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
1103 NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
1104 NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
1105 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
1106 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1107 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
1108 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
1109 NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
1110 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
1111 NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
1112 NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
1113 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
1114 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1115 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1116 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1117 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
1118 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1119 NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
1120 NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
1121 if (par->WaitVSyncPossible)
1122 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
1123 else
1124 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
1125 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
1126 NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
1127 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1128 NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
1129 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
1130 NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
1131 NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
1132 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
1133 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1134 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
1135 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1136 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
1137 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
1138 NV_WR32(par->PRAMIN, 0x0826 * 4,
1139 par->FbUsableSize | 0x00000002);
1140 NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
1141#ifdef __BIG_ENDIAN
1142 NV_WR32(par->PRAMIN, 0x0804 * 4,
1143 NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
1144 NV_WR32(par->PRAMIN, 0x0808 * 4,
1145 NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
1146 NV_WR32(par->PRAMIN, 0x080C * 4,
1147 NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
1148 NV_WR32(par->PRAMIN, 0x0810 * 4,
1149 NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
1150 NV_WR32(par->PRAMIN, 0x0814 * 4,
1151 NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
1152 NV_WR32(par->PRAMIN, 0x0818 * 4,
1153 NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
1154 NV_WR32(par->PRAMIN, 0x081C * 4,
1155 NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
1156 NV_WR32(par->PRAMIN, 0x0820 * 4,
1157 NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
1158 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
1159 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
1160#endif
1161 }
1162 if (par->Architecture < NV_ARCH_10) {
1163 if ((par->Chipset & 0x0fff) == 0x0020) {
1164 NV_WR32(par->PRAMIN, 0x0824 * 4,
1165 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
1166 NV_WR32(par->PRAMIN, 0x0826 * 4,
1167 NV_RD32(par->PRAMIN,
1168 0x0826 * 4) + par->FbAddress);
1169 }
1170 NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
1171 NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
1172 NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
1173 NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
1174 NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
1175 NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
1176 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1177 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1178 NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
1179 NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
1180 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1181 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1182 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1183 } else {
1184 NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
1185 NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
1186
1187 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1188 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1189 NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
1190 NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
1191 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1192 NV_WR32(par->PGRAPH, 0x0710,
1193 NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
1194 NV_WR32(par->PGRAPH, 0x0710,
1195 NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
1196
1197 if (par->Architecture == NV_ARCH_10) {
1198 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1199 NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
1200 NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
1201
1202 for (i = 0; i < 32; i++)
1203 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
1204 NV_RD32(&par->PFB[(0x0240 / 4) + i],
1205 0));
1206
1207 NV_WR32(par->PGRAPH, 0x640, 0);
1208 NV_WR32(par->PGRAPH, 0x644, 0);
1209 NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
1210 NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
1211
1212 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1213 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1214 } else {
1215 if (par->Architecture >= NV_ARCH_40) {
1216 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1217 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1218 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1219 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1220 NV_WR32(par->PGRAPH, 0x0bc4,
1221 NV_RD32(par->PGRAPH, 0x0bc4) |
1222 0x00008000);
1223
1224 j = NV_RD32(par->REGS, 0x1540) & 0xff;
1225
1226 if (j) {
1227 for (i = 0; !(j & 1); j >>= 1, i++);
1228 NV_WR32(par->PGRAPH, 0x5000, i);
1229 }
1230
1231 if ((par->Chipset & 0xfff0) == 0x0040) {
1232 NV_WR32(par->PGRAPH, 0x09b0,
1233 0x83280fff);
1234 NV_WR32(par->PGRAPH, 0x09b4,
1235 0x000000a0);
1236 } else {
1237 NV_WR32(par->PGRAPH, 0x0820,
1238 0x83280eff);
1239 NV_WR32(par->PGRAPH, 0x0824,
1240 0x000000a0);
1241 }
1242
1243 switch (par->Chipset & 0xfff0) {
1244 case 0x0040:
1245 case 0x0210:
1246 NV_WR32(par->PGRAPH, 0x09b8,
1247 0x0078e366);
1248 NV_WR32(par->PGRAPH, 0x09bc,
1249 0x0000014c);
1250 NV_WR32(par->PFB, 0x033C,
1251 NV_RD32(par->PFB, 0x33C) &
1252 0xffff7fff);
1253 break;
1254 case 0x00C0:
1255 case 0x0120:
1256 NV_WR32(par->PGRAPH, 0x0828,
1257 0x007596ff);
1258 NV_WR32(par->PGRAPH, 0x082C,
1259 0x00000108);
1260 break;
1261 case 0x0160:
1262 case 0x01D0:
1263 case 0x0240:
1264 case 0x03D0:
1265 NV_WR32(par->PMC, 0x1700,
1266 NV_RD32(par->PFB, 0x020C));
1267 NV_WR32(par->PMC, 0x1704, 0);
1268 NV_WR32(par->PMC, 0x1708, 0);
1269 NV_WR32(par->PMC, 0x170C,
1270 NV_RD32(par->PFB, 0x020C));
1271 NV_WR32(par->PGRAPH, 0x0860, 0);
1272 NV_WR32(par->PGRAPH, 0x0864, 0);
1273 NV_WR32(par->PRAMDAC, 0x0608,
1274 NV_RD32(par->PRAMDAC,
1275 0x0608) | 0x00100000);
1276 break;
1277 case 0x0140:
1278 NV_WR32(par->PGRAPH, 0x0828,
1279 0x0072cb77);
1280 NV_WR32(par->PGRAPH, 0x082C,
1281 0x00000108);
1282 break;
1283 case 0x0220:
1284 NV_WR32(par->PGRAPH, 0x0860, 0);
1285 NV_WR32(par->PGRAPH, 0x0864, 0);
1286 NV_WR32(par->PRAMDAC, 0x0608,
1287 NV_RD32(par->PRAMDAC, 0x0608) |
1288 0x00100000);
1289 break;
1290 case 0x0090:
1291 case 0x0290:
1292 case 0x0390:
1293 NV_WR32(par->PRAMDAC, 0x0608,
1294 NV_RD32(par->PRAMDAC, 0x0608) |
1295 0x00100000);
1296 NV_WR32(par->PGRAPH, 0x0828,
1297 0x07830610);
1298 NV_WR32(par->PGRAPH, 0x082C,
1299 0x0000016A);
1300 break;
1301 default:
1302 break;
1303 }
1304
1305 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
1306 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
1307 NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
1308 NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
1309 } else if (par->Architecture == NV_ARCH_30) {
1310 NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
1311 NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
1312 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
1313 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1314 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
1315 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
1316 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
1317 } else {
1318 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1319 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
1320 NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
1321 NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
1322
1323 if ((par->Chipset & 0x0ff0) >= 0x0250) {
1324 NV_WR32(par->PGRAPH, 0x0890,
1325 0x00080000);
1326 NV_WR32(par->PGRAPH, 0x0610,
1327 0x304B1FB6);
1328 NV_WR32(par->PGRAPH, 0x0B80,
1329 0x18B82880);
1330 NV_WR32(par->PGRAPH, 0x0B84,
1331 0x44000000);
1332 NV_WR32(par->PGRAPH, 0x0098,
1333 0x40000080);
1334 NV_WR32(par->PGRAPH, 0x0B88,
1335 0x000000ff);
1336 } else {
1337 NV_WR32(par->PGRAPH, 0x0880,
1338 0x00080000);
1339 NV_WR32(par->PGRAPH, 0x0094,
1340 0x00000005);
1341 NV_WR32(par->PGRAPH, 0x0B80,
1342 0x45CAA208);
1343 NV_WR32(par->PGRAPH, 0x0B84,
1344 0x24000000);
1345 NV_WR32(par->PGRAPH, 0x0098,
1346 0x00000040);
1347 NV_WR32(par->PGRAPH, 0x0750,
1348 0x00E00038);
1349 NV_WR32(par->PGRAPH, 0x0754,
1350 0x00000030);
1351 NV_WR32(par->PGRAPH, 0x0750,
1352 0x00E10038);
1353 NV_WR32(par->PGRAPH, 0x0754,
1354 0x00000030);
1355 }
1356 }
1357
1358 if ((par->Architecture < NV_ARCH_40) ||
1359 ((par->Chipset & 0xfff0) == 0x0040)) {
1360 for (i = 0; i < 32; i++) {
1361 NV_WR32(par->PGRAPH, 0x0900 + i*4,
1362 NV_RD32(par->PFB, 0x0240 +i*4));
1363 NV_WR32(par->PGRAPH, 0x6900 + i*4,
1364 NV_RD32(par->PFB, 0x0240 +i*4));
1365 }
1366 } else {
1367 if (((par->Chipset & 0xfff0) == 0x0090) ||
1368 ((par->Chipset & 0xfff0) == 0x01D0) ||
1369 ((par->Chipset & 0xfff0) == 0x0290) ||
1370 ((par->Chipset & 0xfff0) == 0x0390) ||
1371 ((par->Chipset & 0xfff0) == 0x03D0)) {
1372 for (i = 0; i < 60; i++) {
1373 NV_WR32(par->PGRAPH,
1374 0x0D00 + i*4,
1375 NV_RD32(par->PFB,
1376 0x0600 + i*4));
1377 NV_WR32(par->PGRAPH,
1378 0x6900 + i*4,
1379 NV_RD32(par->PFB,
1380 0x0600 + i*4));
1381 }
1382 } else {
1383 for (i = 0; i < 48; i++) {
1384 NV_WR32(par->PGRAPH,
1385 0x0900 + i*4,
1386 NV_RD32(par->PFB,
1387 0x0600 + i*4));
1388 if(((par->Chipset & 0xfff0)
1389 != 0x0160) &&
1390 ((par->Chipset & 0xfff0)
1391 != 0x0220) &&
1392 ((par->Chipset & 0xfff0)
1393 != 0x240))
1394 NV_WR32(par->PGRAPH,
1395 0x6900 + i*4,
1396 NV_RD32(par->PFB,
1397 0x0600 + i*4));
1398 }
1399 }
1400 }
1401
1402 if (par->Architecture >= NV_ARCH_40) {
1403 if ((par->Chipset & 0xfff0) == 0x0040) {
1404 NV_WR32(par->PGRAPH, 0x09A4,
1405 NV_RD32(par->PFB, 0x0200));
1406 NV_WR32(par->PGRAPH, 0x09A8,
1407 NV_RD32(par->PFB, 0x0204));
1408 NV_WR32(par->PGRAPH, 0x69A4,
1409 NV_RD32(par->PFB, 0x0200));
1410 NV_WR32(par->PGRAPH, 0x69A8,
1411 NV_RD32(par->PFB, 0x0204));
1412
1413 NV_WR32(par->PGRAPH, 0x0820, 0);
1414 NV_WR32(par->PGRAPH, 0x0824, 0);
1415 NV_WR32(par->PGRAPH, 0x0864,
1416 par->FbMapSize - 1);
1417 NV_WR32(par->PGRAPH, 0x0868,
1418 par->FbMapSize - 1);
1419 } else {
1420 if ((par->Chipset & 0xfff0) == 0x0090 ||
1421 (par->Chipset & 0xfff0) == 0x01D0 ||
1422 (par->Chipset & 0xfff0) == 0x0290 ||
1423 (par->Chipset & 0xfff0) == 0x0390) {
1424 NV_WR32(par->PGRAPH, 0x0DF0,
1425 NV_RD32(par->PFB, 0x0200));
1426 NV_WR32(par->PGRAPH, 0x0DF4,
1427 NV_RD32(par->PFB, 0x0204));
1428 } else {
1429 NV_WR32(par->PGRAPH, 0x09F0,
1430 NV_RD32(par->PFB, 0x0200));
1431 NV_WR32(par->PGRAPH, 0x09F4,
1432 NV_RD32(par->PFB, 0x0204));
1433 }
1434 NV_WR32(par->PGRAPH, 0x69F0,
1435 NV_RD32(par->PFB, 0x0200));
1436 NV_WR32(par->PGRAPH, 0x69F4,
1437 NV_RD32(par->PFB, 0x0204));
1438
1439 NV_WR32(par->PGRAPH, 0x0840, 0);
1440 NV_WR32(par->PGRAPH, 0x0844, 0);
1441 NV_WR32(par->PGRAPH, 0x08a0,
1442 par->FbMapSize - 1);
1443 NV_WR32(par->PGRAPH, 0x08a4,
1444 par->FbMapSize - 1);
1445 }
1446 } else {
1447 NV_WR32(par->PGRAPH, 0x09A4,
1448 NV_RD32(par->PFB, 0x0200));
1449 NV_WR32(par->PGRAPH, 0x09A8,
1450 NV_RD32(par->PFB, 0x0204));
1451 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
1452 NV_WR32(par->PGRAPH, 0x0754,
1453 NV_RD32(par->PFB, 0x0200));
1454 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
1455 NV_WR32(par->PGRAPH, 0x0754,
1456 NV_RD32(par->PFB, 0x0204));
1457
1458 NV_WR32(par->PGRAPH, 0x0820, 0);
1459 NV_WR32(par->PGRAPH, 0x0824, 0);
1460 NV_WR32(par->PGRAPH, 0x0864,
1461 par->FbMapSize - 1);
1462 NV_WR32(par->PGRAPH, 0x0868,
1463 par->FbMapSize - 1);
1464 }
1465 NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
1466 NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
1467 }
1468 }
1469 NV_WR32(par->PGRAPH, 0x053C, 0);
1470 NV_WR32(par->PGRAPH, 0x0540, 0);
1471 NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
1472 NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
1473
1474 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
1475 NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
1476 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
1477 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
1478 if (par->Architecture >= NV_ARCH_40)
1479 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
1480 else
1481 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
1482 NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
1483 NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
1484 if (par->Architecture >= NV_ARCH_40)
1485 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
1486 else
1487 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
1488 NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
1489 NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
1490 NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
1491 NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
1492 NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
1493 NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
1494 NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
1495 NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
1496 NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
1497 NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
1498 NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
1499 NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
1500#ifdef __BIG_ENDIAN
1501 NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
1502#else
1503 NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
1504#endif
1505 NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
1506 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
1507 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
1508 NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
1509 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
1510
1511 if (!state) {
1512 par->CurrentState = NULL;
1513 return;
1514 }
1515
1516 if (par->Architecture >= NV_ARCH_10) {
1517 if (par->twoHeads) {
1518 NV_WR32(par->PCRTC0, 0x0860, state->head);
1519 NV_WR32(par->PCRTC0, 0x2860, state->head2);
1520 }
1521 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
1522 (1 << 25));
1523
1524 NV_WR32(par->PMC, 0x8704, 1);
1525 NV_WR32(par->PMC, 0x8140, 0);
1526 NV_WR32(par->PMC, 0x8920, 0);
1527 NV_WR32(par->PMC, 0x8924, 0);
1528 NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
1529 NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
1530 NV_WR32(par->PMC, 0x1588, 0);
1531
1532 NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
1533 NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
1534 NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
1535
1536 if (par->FlatPanel) {
1537 if ((par->Chipset & 0x0ff0) == 0x0110) {
1538 NV_WR32(par->PRAMDAC, 0x0528, state->dither);
1539 } else if (par->twoHeads) {
1540 NV_WR32(par->PRAMDAC, 0x083C, state->dither);
1541 }
1542
1543 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1544 VGA_WR08(par->PCIO, 0x03D5, state->timingH);
1545 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1546 VGA_WR08(par->PCIO, 0x03D5, state->timingV);
1547 VGA_WR08(par->PCIO, 0x03D4, 0x21);
1548 VGA_WR08(par->PCIO, 0x03D5, 0xfa);
1549 }
1550
1551 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1552 VGA_WR08(par->PCIO, 0x03D5, state->extra);
1553 }
1554
1555 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1556 VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
1557 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1558 VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
1559 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1560 VGA_WR08(par->PCIO, 0x03D5, state->screen);
1561 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1562 VGA_WR08(par->PCIO, 0x03D5, state->pixel);
1563 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1564 VGA_WR08(par->PCIO, 0x03D5, state->horiz);
1565 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1566 VGA_WR08(par->PCIO, 0x03D5, state->fifo);
1567 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1568 VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
1569 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1570 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
1571
1572 if(par->Architecture >= NV_ARCH_30) {
1573 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1574 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
1575 }
1576
1577 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1578 VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
1579 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1580 VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
1581 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1582 VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
1583 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1584 VGA_WR08(par->PCIO, 0x03D5, state->interlace);
1585
1586 if (!par->FlatPanel) {
1587 if (par->Architecture >= NV_ARCH_40)
1588 NV_WR32(par->PRAMDAC0, 0x0580, state->control);
1589
1590 NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
1591 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
1592 if (par->twoHeads)
1593 NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
1594 if (par->twoStagePLL) {
1595 NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
1596 NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
1597 }
1598 } else {
1599 NV_WR32(par->PRAMDAC, 0x0848, state->scale);
1600 NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
1601 par->PanelTweak);
1602 }
1603
1604 NV_WR32(par->PRAMDAC, 0x0600, state->general);
1605
1606 NV_WR32(par->PCRTC, 0x0140, 0);
1607 NV_WR32(par->PCRTC, 0x0100, 1);
1608
1609 par->CurrentState = state;
1610}
1611
1612void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
1613 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1614 state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
1615 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1616 state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
1617 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1618 state->screen = VGA_RD08(par->PCIO, 0x03D5);
1619 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1620 state->pixel = VGA_RD08(par->PCIO, 0x03D5);
1621 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1622 state->horiz = VGA_RD08(par->PCIO, 0x03D5);
1623 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1624 state->fifo = VGA_RD08(par->PCIO, 0x03D5);
1625 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1626 state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
1627 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1628 state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
1629
1630 if(par->Architecture >= NV_ARCH_30) {
1631 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1632 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
1633 }
1634
1635 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1636 state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
1637 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1638 state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
1639 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1640 state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
1641 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1642 state->interlace = VGA_RD08(par->PCIO, 0x03D5);
1643 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
1644 if (par->twoHeads)
1645 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
1646 if (par->twoStagePLL) {
1647 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
1648 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
1649 }
1650 state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
1651 state->general = NV_RD32(par->PRAMDAC, 0x0600);
1652 state->scale = NV_RD32(par->PRAMDAC, 0x0848);
1653 state->config = NV_RD32(par->PFB, 0x0200);
1654
1655 if (par->Architecture >= NV_ARCH_40 && !par->FlatPanel)
1656 state->control = NV_RD32(par->PRAMDAC0, 0x0580);
1657
1658 if (par->Architecture >= NV_ARCH_10) {
1659 if (par->twoHeads) {
1660 state->head = NV_RD32(par->PCRTC0, 0x0860);
1661 state->head2 = NV_RD32(par->PCRTC0, 0x2860);
1662 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1663 state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
1664 }
1665 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1666 state->extra = VGA_RD08(par->PCIO, 0x03D5);
1667 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
1668
1669 if ((par->Chipset & 0x0ff0) == 0x0110) {
1670 state->dither = NV_RD32(par->PRAMDAC, 0x0528);
1671 } else if (par->twoHeads) {
1672 state->dither = NV_RD32(par->PRAMDAC, 0x083C);
1673 }
1674
1675 if (par->FlatPanel) {
1676 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1677 state->timingH = VGA_RD08(par->PCIO, 0x03D5);
1678 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1679 state->timingV = VGA_RD08(par->PCIO, 0x03D5);
1680 }
1681 }
1682}
1683
1684void NVSetStartAddress(struct nvidia_par *par, u32 start)
1685{
1686 NV_WR32(par->PCRTC, 0x800, start);
1687}
diff --git a/drivers/video/nvidia/nv_i2c.c b/drivers/video/nvidia/nv_i2c.c
deleted file mode 100644
index d7994a173245..000000000000
--- a/drivers/video/nvidia/nv_i2c.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * linux/drivers/video/nvidia/nvidia-i2c.c - nVidia i2c
3 *
4 * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
5 *
6 * Based on rivafb-i2c.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/gfp.h>
17#include <linux/pci.h>
18#include <linux/fb.h>
19
20#include <asm/io.h>
21
22#include "nv_type.h"
23#include "nv_local.h"
24#include "nv_proto.h"
25
26#include "../edid.h"
27
28static void nvidia_gpio_setscl(void *data, int state)
29{
30 struct nvidia_i2c_chan *chan = data;
31 struct nvidia_par *par = chan->par;
32 u32 val;
33
34 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
35
36 if (state)
37 val |= 0x20;
38 else
39 val &= ~0x20;
40
41 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
42}
43
44static void nvidia_gpio_setsda(void *data, int state)
45{
46 struct nvidia_i2c_chan *chan = data;
47 struct nvidia_par *par = chan->par;
48 u32 val;
49
50 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
51
52 if (state)
53 val |= 0x10;
54 else
55 val &= ~0x10;
56
57 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
58}
59
60static int nvidia_gpio_getscl(void *data)
61{
62 struct nvidia_i2c_chan *chan = data;
63 struct nvidia_par *par = chan->par;
64 u32 val = 0;
65
66 if (NVReadCrtc(par, chan->ddc_base) & 0x04)
67 val = 1;
68
69 return val;
70}
71
72static int nvidia_gpio_getsda(void *data)
73{
74 struct nvidia_i2c_chan *chan = data;
75 struct nvidia_par *par = chan->par;
76 u32 val = 0;
77
78 if (NVReadCrtc(par, chan->ddc_base) & 0x08)
79 val = 1;
80
81 return val;
82}
83
84static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name,
85 unsigned int i2c_class)
86{
87 int rc;
88
89 strcpy(chan->adapter.name, name);
90 chan->adapter.owner = THIS_MODULE;
91 chan->adapter.class = i2c_class;
92 chan->adapter.algo_data = &chan->algo;
93 chan->adapter.dev.parent = &chan->par->pci_dev->dev;
94 chan->algo.setsda = nvidia_gpio_setsda;
95 chan->algo.setscl = nvidia_gpio_setscl;
96 chan->algo.getsda = nvidia_gpio_getsda;
97 chan->algo.getscl = nvidia_gpio_getscl;
98 chan->algo.udelay = 40;
99 chan->algo.timeout = msecs_to_jiffies(2);
100 chan->algo.data = chan;
101
102 i2c_set_adapdata(&chan->adapter, chan);
103
104 /* Raise SCL and SDA */
105 nvidia_gpio_setsda(chan, 1);
106 nvidia_gpio_setscl(chan, 1);
107 udelay(20);
108
109 rc = i2c_bit_add_bus(&chan->adapter);
110 if (rc == 0)
111 dev_dbg(&chan->par->pci_dev->dev,
112 "I2C bus %s registered.\n", name);
113 else {
114 dev_warn(&chan->par->pci_dev->dev,
115 "Failed to register I2C bus %s.\n", name);
116 chan->par = NULL;
117 }
118
119 return rc;
120}
121
122void nvidia_create_i2c_busses(struct nvidia_par *par)
123{
124 par->chan[0].par = par;
125 par->chan[1].par = par;
126 par->chan[2].par = par;
127
128 par->chan[0].ddc_base = (par->reverse_i2c) ? 0x36 : 0x3e;
129 nvidia_setup_i2c_bus(&par->chan[0], "nvidia #0",
130 (par->reverse_i2c) ? I2C_CLASS_HWMON : 0);
131
132 par->chan[1].ddc_base = (par->reverse_i2c) ? 0x3e : 0x36;
133 nvidia_setup_i2c_bus(&par->chan[1], "nvidia #1",
134 (par->reverse_i2c) ? 0 : I2C_CLASS_HWMON);
135
136 par->chan[2].ddc_base = 0x50;
137 nvidia_setup_i2c_bus(&par->chan[2], "nvidia #2", 0);
138}
139
140void nvidia_delete_i2c_busses(struct nvidia_par *par)
141{
142 int i;
143
144 for (i = 0; i < 3; i++) {
145 if (!par->chan[i].par)
146 continue;
147 i2c_del_adapter(&par->chan[i].adapter);
148 par->chan[i].par = NULL;
149 }
150}
151
152int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid)
153{
154 struct nvidia_par *par = info->par;
155 u8 *edid = NULL;
156
157 if (par->chan[conn - 1].par)
158 edid = fb_ddc_read(&par->chan[conn - 1].adapter);
159
160 if (!edid && conn == 1) {
161 /* try to get from firmware */
162 const u8 *e = fb_firmware_edid(info->device);
163
164 if (e != NULL)
165 edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
166 }
167
168 *out_edid = edid;
169
170 return (edid) ? 0 : 1;
171}
diff --git a/drivers/video/nvidia/nv_local.h b/drivers/video/nvidia/nv_local.h
deleted file mode 100644
index 68e508daa417..000000000000
--- a/drivers/video/nvidia/nv_local.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/***************************************************************************\
2|* *|
3|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50#ifndef __NV_LOCAL_H__
51#define __NV_LOCAL_H__
52
53/*
54 * This file includes any environment or machine specific values to access the
55 * HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files
56 * can stay generic in nature.
57 */
58
59/*
60 * HW access macros. These assume memory-mapped I/O, and not normal I/O space.
61 */
62#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
63#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
64#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
65#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
66#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
67#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
68
69/* VGA I/O is now always done through MMIO */
70#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
71#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
72
73#define NVDmaNext(par, data) \
74 NV_WR32(&(par)->dmaBase[(par)->dmaCurrent++], 0, (data))
75
76#define NVDmaStart(info, par, tag, size) { \
77 if((par)->dmaFree <= (size)) \
78 NVDmaWait(info, size); \
79 NVDmaNext(par, ((size) << 18) | (tag)); \
80 (par)->dmaFree -= ((size) + 1); \
81}
82
83#if defined(__i386__)
84#define _NV_FENCE() outb(0, 0x3D0);
85#else
86#define _NV_FENCE() mb();
87#endif
88
89#define WRITE_PUT(par, data) { \
90 _NV_FENCE() \
91 NV_RD08((par)->FbStart, 0); \
92 NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \
93 mb(); \
94}
95
96#define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
97
98#ifdef __LITTLE_ENDIAN
99
100#include <linux/bitrev.h>
101
102#define reverse_order(l) \
103do { \
104 u8 *a = (u8 *)(l); \
105 a[0] = bitrev8(a[0]); \
106 a[1] = bitrev8(a[1]); \
107 a[2] = bitrev8(a[2]); \
108 a[3] = bitrev8(a[3]); \
109} while(0)
110#else
111#define reverse_order(l) do { } while(0)
112#endif /* __LITTLE_ENDIAN */
113
114#endif /* __NV_LOCAL_H__ */
diff --git a/drivers/video/nvidia/nv_of.c b/drivers/video/nvidia/nv_of.c
deleted file mode 100644
index 3bc13df4b120..000000000000
--- a/drivers/video/nvidia/nv_of.c
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * linux/drivers/video/nvidia/nv_of.c
3 *
4 * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
5 *
6 * Based on rivafb-i2c.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/gfp.h>
17#include <linux/pci.h>
18#include <linux/fb.h>
19
20#include <asm/io.h>
21
22#include <asm/prom.h>
23#include <asm/pci-bridge.h>
24
25#include "nv_type.h"
26#include "nv_local.h"
27#include "nv_proto.h"
28
29#include "../edid.h"
30
31int nvidia_probe_of_connector(struct fb_info *info, int conn, u8 **out_edid)
32{
33 struct nvidia_par *par = info->par;
34 struct device_node *parent, *dp;
35 const unsigned char *pedid = NULL;
36 static char *propnames[] = {
37 "DFP,EDID", "LCD,EDID", "EDID", "EDID1",
38 "EDID,B", "EDID,A", NULL };
39 int i;
40
41 parent = pci_device_to_OF_node(par->pci_dev);
42 if (parent == NULL)
43 return -1;
44 if (par->twoHeads) {
45 const char *pname;
46 int len;
47
48 for (dp = NULL;
49 (dp = of_get_next_child(parent, dp)) != NULL;) {
50 pname = of_get_property(dp, "name", NULL);
51 if (!pname)
52 continue;
53 len = strlen(pname);
54 if ((pname[len-1] == 'A' && conn == 1) ||
55 (pname[len-1] == 'B' && conn == 2)) {
56 for (i = 0; propnames[i] != NULL; ++i) {
57 pedid = of_get_property(dp,
58 propnames[i], NULL);
59 if (pedid != NULL)
60 break;
61 }
62 of_node_put(dp);
63 break;
64 }
65 }
66 }
67 if (pedid == NULL) {
68 for (i = 0; propnames[i] != NULL; ++i) {
69 pedid = of_get_property(parent, propnames[i], NULL);
70 if (pedid != NULL)
71 break;
72 }
73 }
74 if (pedid) {
75 *out_edid = kmemdup(pedid, EDID_LENGTH, GFP_KERNEL);
76 if (*out_edid == NULL)
77 return -1;
78 printk(KERN_DEBUG "nvidiafb: Found OF EDID for head %d\n", conn);
79 return 0;
80 }
81 return -1;
82}
diff --git a/drivers/video/nvidia/nv_proto.h b/drivers/video/nvidia/nv_proto.h
deleted file mode 100644
index ff5c410355ea..000000000000
--- a/drivers/video/nvidia/nv_proto.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h,v 1.10 2003/07/31 20:24:29 mvojkovi Exp $ */
2
3#ifndef __NV_PROTO_H__
4#define __NV_PROTO_H__
5
6/* in nv_setup.c */
7int NVCommonSetup(struct fb_info *info);
8void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value);
9u8 NVReadCrtc(struct nvidia_par *par, u8 index);
10void NVWriteGr(struct nvidia_par *par, u8 index, u8 value);
11u8 NVReadGr(struct nvidia_par *par, u8 index);
12void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value);
13u8 NVReadSeq(struct nvidia_par *par, u8 index);
14void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value);
15u8 NVReadAttr(struct nvidia_par *par, u8 index);
16void NVWriteMiscOut(struct nvidia_par *par, u8 value);
17u8 NVReadMiscOut(struct nvidia_par *par);
18void NVWriteDacMask(struct nvidia_par *par, u8 value);
19void NVWriteDacReadAddr(struct nvidia_par *par, u8 value);
20void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value);
21void NVWriteDacData(struct nvidia_par *par, u8 value);
22u8 NVReadDacData(struct nvidia_par *par);
23
24/* in nv_hw.c */
25void NVCalcStateExt(struct nvidia_par *par, struct _riva_hw_state *,
26 int, int, int, int, int, int);
27void NVLoadStateExt(struct nvidia_par *par, struct _riva_hw_state *);
28void NVUnloadStateExt(struct nvidia_par *par, struct _riva_hw_state *);
29void NVSetStartAddress(struct nvidia_par *par, u32);
30int NVShowHideCursor(struct nvidia_par *par, int);
31void NVLockUnlock(struct nvidia_par *par, int);
32
33/* in nvidia-i2c.c */
34#ifdef CONFIG_FB_NVIDIA_I2C
35void nvidia_create_i2c_busses(struct nvidia_par *par);
36void nvidia_delete_i2c_busses(struct nvidia_par *par);
37int nvidia_probe_i2c_connector(struct fb_info *info, int conn,
38 u8 ** out_edid);
39#else
40#define nvidia_create_i2c_busses(...)
41#define nvidia_delete_i2c_busses(...)
42#define nvidia_probe_i2c_connector(p, c, edid) (-1)
43#endif
44
45#ifdef CONFIG_PPC_OF
46int nvidia_probe_of_connector(struct fb_info *info, int conn,
47 u8 ** out_edid);
48#else
49static inline int nvidia_probe_of_connector(struct fb_info *info, int conn,
50 u8 ** out_edid)
51{
52 return -1;
53}
54#endif
55
56/* in nv_accel.c */
57extern void NVResetGraphics(struct fb_info *info);
58extern void nvidiafb_copyarea(struct fb_info *info,
59 const struct fb_copyarea *region);
60extern void nvidiafb_fillrect(struct fb_info *info,
61 const struct fb_fillrect *rect);
62extern void nvidiafb_imageblit(struct fb_info *info,
63 const struct fb_image *image);
64extern int nvidiafb_sync(struct fb_info *info);
65
66/* in nv_backlight.h */
67#ifdef CONFIG_FB_NVIDIA_BACKLIGHT
68extern void nvidia_bl_init(struct nvidia_par *par);
69extern void nvidia_bl_exit(struct nvidia_par *par);
70#else
71static inline void nvidia_bl_init(struct nvidia_par *par) {}
72static inline void nvidia_bl_exit(struct nvidia_par *par) {}
73#endif
74
75#endif /* __NV_PROTO_H__ */
diff --git a/drivers/video/nvidia/nv_setup.c b/drivers/video/nvidia/nv_setup.c
deleted file mode 100644
index 2f2e162134fa..000000000000
--- a/drivers/video/nvidia/nv_setup.c
+++ /dev/null
@@ -1,675 +0,0 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50#include <video/vga.h>
51#include <linux/delay.h>
52#include <linux/pci.h>
53#include <linux/slab.h>
54#include "nv_type.h"
55#include "nv_local.h"
56#include "nv_proto.h"
57/*
58 * Override VGA I/O routines.
59 */
60void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
61{
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
64}
65u8 NVReadCrtc(struct nvidia_par *par, u8 index)
66{
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
69}
70void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
71{
72 VGA_WR08(par->PVIO, VGA_GFX_I, index);
73 VGA_WR08(par->PVIO, VGA_GFX_D, value);
74}
75u8 NVReadGr(struct nvidia_par *par, u8 index)
76{
77 VGA_WR08(par->PVIO, VGA_GFX_I, index);
78 return (VGA_RD08(par->PVIO, VGA_GFX_D));
79}
80void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
81{
82 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
83 VGA_WR08(par->PVIO, VGA_SEQ_D, value);
84}
85u8 NVReadSeq(struct nvidia_par *par, u8 index)
86{
87 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
88 return (VGA_RD08(par->PVIO, VGA_SEQ_D));
89}
90void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
91{
92 volatile u8 tmp;
93
94 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
95 if (par->paletteEnabled)
96 index &= ~0x20;
97 else
98 index |= 0x20;
99 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
100 VGA_WR08(par->PCIO, VGA_ATT_W, value);
101}
102u8 NVReadAttr(struct nvidia_par *par, u8 index)
103{
104 volatile u8 tmp;
105
106 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
107 if (par->paletteEnabled)
108 index &= ~0x20;
109 else
110 index |= 0x20;
111 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
112 return (VGA_RD08(par->PCIO, VGA_ATT_R));
113}
114void NVWriteMiscOut(struct nvidia_par *par, u8 value)
115{
116 VGA_WR08(par->PVIO, VGA_MIS_W, value);
117}
118u8 NVReadMiscOut(struct nvidia_par *par)
119{
120 return (VGA_RD08(par->PVIO, VGA_MIS_R));
121}
122#if 0
123void NVEnablePalette(struct nvidia_par *par)
124{
125 volatile u8 tmp;
126
127 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
128 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
129 par->paletteEnabled = 1;
130}
131void NVDisablePalette(struct nvidia_par *par)
132{
133 volatile u8 tmp;
134
135 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
136 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
137 par->paletteEnabled = 0;
138}
139#endif /* 0 */
140void NVWriteDacMask(struct nvidia_par *par, u8 value)
141{
142 VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
143}
144#if 0
145u8 NVReadDacMask(struct nvidia_par *par)
146{
147 return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
148}
149#endif /* 0 */
150void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
151{
152 VGA_WR08(par->PDIO, VGA_PEL_IR, value);
153}
154void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
155{
156 VGA_WR08(par->PDIO, VGA_PEL_IW, value);
157}
158void NVWriteDacData(struct nvidia_par *par, u8 value)
159{
160 VGA_WR08(par->PDIO, VGA_PEL_D, value);
161}
162u8 NVReadDacData(struct nvidia_par *par)
163{
164 return (VGA_RD08(par->PDIO, VGA_PEL_D));
165}
166
167static int NVIsConnected(struct nvidia_par *par, int output)
168{
169 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
170 u32 reg52C, reg608, dac0_reg608 = 0;
171 int present;
172
173 if (output) {
174 dac0_reg608 = NV_RD32(PRAMDAC, 0x0608);
175 PRAMDAC += 0x800;
176 }
177
178 reg52C = NV_RD32(PRAMDAC, 0x052C);
179 reg608 = NV_RD32(PRAMDAC, 0x0608);
180
181 NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
182
183 NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
184 msleep(1);
185 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
186
187 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
188 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
189 0x00001000);
190
191 msleep(1);
192
193 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
194
195 if (present)
196 printk("nvidiafb: CRTC%i analog found\n", output);
197 else
198 printk("nvidiafb: CRTC%i analog not found\n", output);
199
200 if (output)
201 NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
202
203 NV_WR32(PRAMDAC, 0x052C, reg52C);
204 NV_WR32(PRAMDAC, 0x0608, reg608);
205
206 return present;
207}
208
209static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
210{
211 if (head) {
212 par->PCIO = par->PCIO0 + 0x2000;
213 par->PCRTC = par->PCRTC0 + 0x800;
214 par->PRAMDAC = par->PRAMDAC0 + 0x800;
215 par->PDIO = par->PDIO0 + 0x2000;
216 } else {
217 par->PCIO = par->PCIO0;
218 par->PCRTC = par->PCRTC0;
219 par->PRAMDAC = par->PRAMDAC0;
220 par->PDIO = par->PDIO0;
221 }
222}
223
224static void nv4GetConfig(struct nvidia_par *par)
225{
226 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
227 par->RamAmountKBytes =
228 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
229 1024 * 2;
230 } else {
231 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
232 case 0:
233 par->RamAmountKBytes = 1024 * 32;
234 break;
235 case 1:
236 par->RamAmountKBytes = 1024 * 4;
237 break;
238 case 2:
239 par->RamAmountKBytes = 1024 * 8;
240 break;
241 case 3:
242 default:
243 par->RamAmountKBytes = 1024 * 16;
244 break;
245 }
246 }
247 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
248 14318 : 13500;
249 par->CURSOR = &par->PRAMIN[0x1E00];
250 par->MinVClockFreqKHz = 12000;
251 par->MaxVClockFreqKHz = 350000;
252}
253
254static void nv10GetConfig(struct nvidia_par *par)
255{
256 struct pci_dev *dev;
257 u32 implementation = par->Chipset & 0x0ff0;
258
259#ifdef __BIG_ENDIAN
260 /* turn on big endian register access */
261 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
262 NV_WR32(par->PMC, 0x0004, 0x01000001);
263 mb();
264 }
265#endif
266
267 dev = pci_get_bus_and_slot(0, 1);
268 if ((par->Chipset & 0xffff) == 0x01a0) {
269 u32 amt;
270
271 pci_read_config_dword(dev, 0x7c, &amt);
272 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
273 } else if ((par->Chipset & 0xffff) == 0x01f0) {
274 u32 amt;
275
276 pci_read_config_dword(dev, 0x84, &amt);
277 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
278 } else {
279 par->RamAmountKBytes =
280 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
281 }
282 pci_dev_put(dev);
283
284 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
285 14318 : 13500;
286
287 if (par->twoHeads && (implementation != 0x0110)) {
288 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
289 par->CrystalFreqKHz = 27000;
290 }
291
292 par->CURSOR = NULL; /* can't set this here */
293 par->MinVClockFreqKHz = 12000;
294 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
295}
296
297int NVCommonSetup(struct fb_info *info)
298{
299 struct nvidia_par *par = info->par;
300 struct fb_var_screeninfo *var;
301 u16 implementation = par->Chipset & 0x0ff0;
302 u8 *edidA = NULL, *edidB = NULL;
303 struct fb_monspecs *monitorA, *monitorB;
304 struct fb_monspecs *monA = NULL, *monB = NULL;
305 int mobile = 0;
306 int tvA = 0;
307 int tvB = 0;
308 int FlatPanel = -1; /* really means the CRTC is slaved */
309 int Television = 0;
310 int err = 0;
311
312 var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
313 monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
314 monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
315
316 if (!var || !monitorA || !monitorB) {
317 err = -ENOMEM;
318 goto done;
319 }
320
321 par->PRAMIN = par->REGS + (0x00710000 / 4);
322 par->PCRTC0 = par->REGS + (0x00600000 / 4);
323 par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
324 par->PFB = par->REGS + (0x00100000 / 4);
325 par->PFIFO = par->REGS + (0x00002000 / 4);
326 par->PGRAPH = par->REGS + (0x00400000 / 4);
327 par->PEXTDEV = par->REGS + (0x00101000 / 4);
328 par->PTIMER = par->REGS + (0x00009000 / 4);
329 par->PMC = par->REGS + (0x00000000 / 4);
330 par->FIFO = par->REGS + (0x00800000 / 4);
331
332 /* 8 bit registers */
333 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
334 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
335 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
336
337 par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
338 (implementation != 0x0100) &&
339 (implementation != 0x0150) &&
340 (implementation != 0x01A0) && (implementation != 0x0200);
341
342 par->fpScaler = (par->FpScale && par->twoHeads &&
343 (implementation != 0x0110));
344
345 par->twoStagePLL = (implementation == 0x0310) ||
346 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
347
348 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
349 (implementation != 0x0100);
350
351 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
352
353 /* look for known laptop chips */
354 switch (par->Chipset & 0xffff) {
355 case 0x0112:
356 case 0x0174:
357 case 0x0175:
358 case 0x0176:
359 case 0x0177:
360 case 0x0179:
361 case 0x017C:
362 case 0x017D:
363 case 0x0186:
364 case 0x0187:
365 case 0x018D:
366 case 0x01D7:
367 case 0x0228:
368 case 0x0286:
369 case 0x028C:
370 case 0x0316:
371 case 0x0317:
372 case 0x031A:
373 case 0x031B:
374 case 0x031C:
375 case 0x031D:
376 case 0x031E:
377 case 0x031F:
378 case 0x0324:
379 case 0x0325:
380 case 0x0328:
381 case 0x0329:
382 case 0x032C:
383 case 0x032D:
384 case 0x0347:
385 case 0x0348:
386 case 0x0349:
387 case 0x034B:
388 case 0x034C:
389 case 0x0160:
390 case 0x0166:
391 case 0x0169:
392 case 0x016B:
393 case 0x016C:
394 case 0x016D:
395 case 0x00C8:
396 case 0x00CC:
397 case 0x0144:
398 case 0x0146:
399 case 0x0147:
400 case 0x0148:
401 case 0x0098:
402 case 0x0099:
403 mobile = 1;
404 break;
405 default:
406 break;
407 }
408
409 if (par->Architecture == NV_ARCH_04)
410 nv4GetConfig(par);
411 else
412 nv10GetConfig(par);
413
414 NVSelectHeadRegisters(par, 0);
415
416 NVLockUnlock(par, 0);
417
418 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
419
420 par->Television = 0;
421
422 nvidia_create_i2c_busses(par);
423 if (!par->twoHeads) {
424 par->CRTCnumber = 0;
425 if (nvidia_probe_i2c_connector(info, 1, &edidA))
426 nvidia_probe_of_connector(info, 1, &edidA);
427 if (edidA && !fb_parse_edid(edidA, var)) {
428 printk("nvidiafb: EDID found from BUS1\n");
429 monA = monitorA;
430 fb_edid_to_monspecs(edidA, monA);
431 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
432
433 /* NV4 doesn't support FlatPanels */
434 if ((par->Chipset & 0x0fff) <= 0x0020)
435 FlatPanel = 0;
436 } else {
437 VGA_WR08(par->PCIO, 0x03D4, 0x28);
438 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
439 VGA_WR08(par->PCIO, 0x03D4, 0x33);
440 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
441 Television = 1;
442 FlatPanel = 1;
443 } else {
444 FlatPanel = 0;
445 }
446 printk("nvidiafb: HW is currently programmed for %s\n",
447 FlatPanel ? (Television ? "TV" : "DFP") :
448 "CRT");
449 }
450
451 if (par->FlatPanel == -1) {
452 par->FlatPanel = FlatPanel;
453 par->Television = Television;
454 } else {
455 printk("nvidiafb: Forcing display type to %s as "
456 "specified\n", par->FlatPanel ? "DFP" : "CRT");
457 }
458 } else {
459 u8 outputAfromCRTC, outputBfromCRTC;
460 int CRTCnumber = -1;
461 u8 slaved_on_A, slaved_on_B;
462 int analog_on_A, analog_on_B;
463 u32 oldhead;
464 u8 cr44;
465
466 if (implementation != 0x0110) {
467 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
468 outputAfromCRTC = 1;
469 else
470 outputAfromCRTC = 0;
471 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
472 outputBfromCRTC = 1;
473 else
474 outputBfromCRTC = 0;
475 analog_on_A = NVIsConnected(par, 0);
476 analog_on_B = NVIsConnected(par, 1);
477 } else {
478 outputAfromCRTC = 0;
479 outputBfromCRTC = 1;
480 analog_on_A = 0;
481 analog_on_B = 0;
482 }
483
484 VGA_WR08(par->PCIO, 0x03D4, 0x44);
485 cr44 = VGA_RD08(par->PCIO, 0x03D5);
486
487 VGA_WR08(par->PCIO, 0x03D5, 3);
488 NVSelectHeadRegisters(par, 1);
489 NVLockUnlock(par, 0);
490
491 VGA_WR08(par->PCIO, 0x03D4, 0x28);
492 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
493 if (slaved_on_B) {
494 VGA_WR08(par->PCIO, 0x03D4, 0x33);
495 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
496 }
497
498 VGA_WR08(par->PCIO, 0x03D4, 0x44);
499 VGA_WR08(par->PCIO, 0x03D5, 0);
500 NVSelectHeadRegisters(par, 0);
501 NVLockUnlock(par, 0);
502
503 VGA_WR08(par->PCIO, 0x03D4, 0x28);
504 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
505 if (slaved_on_A) {
506 VGA_WR08(par->PCIO, 0x03D4, 0x33);
507 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
508 }
509
510 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
511 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
512
513 if (nvidia_probe_i2c_connector(info, 1, &edidA))
514 nvidia_probe_of_connector(info, 1, &edidA);
515 if (edidA && !fb_parse_edid(edidA, var)) {
516 printk("nvidiafb: EDID found from BUS1\n");
517 monA = monitorA;
518 fb_edid_to_monspecs(edidA, monA);
519 }
520
521 if (nvidia_probe_i2c_connector(info, 2, &edidB))
522 nvidia_probe_of_connector(info, 2, &edidB);
523 if (edidB && !fb_parse_edid(edidB, var)) {
524 printk("nvidiafb: EDID found from BUS2\n");
525 monB = monitorB;
526 fb_edid_to_monspecs(edidB, monB);
527 }
528
529 if (slaved_on_A && !tvA) {
530 CRTCnumber = 0;
531 FlatPanel = 1;
532 printk("nvidiafb: CRTC 0 is currently programmed for "
533 "DFP\n");
534 } else if (slaved_on_B && !tvB) {
535 CRTCnumber = 1;
536 FlatPanel = 1;
537 printk("nvidiafb: CRTC 1 is currently programmed "
538 "for DFP\n");
539 } else if (analog_on_A) {
540 CRTCnumber = outputAfromCRTC;
541 FlatPanel = 0;
542 printk("nvidiafb: CRTC %i appears to have a "
543 "CRT attached\n", CRTCnumber);
544 } else if (analog_on_B) {
545 CRTCnumber = outputBfromCRTC;
546 FlatPanel = 0;
547 printk("nvidiafb: CRTC %i appears to have a "
548 "CRT attached\n", CRTCnumber);
549 } else if (slaved_on_A) {
550 CRTCnumber = 0;
551 FlatPanel = 1;
552 Television = 1;
553 printk("nvidiafb: CRTC 0 is currently programmed "
554 "for TV\n");
555 } else if (slaved_on_B) {
556 CRTCnumber = 1;
557 FlatPanel = 1;
558 Television = 1;
559 printk("nvidiafb: CRTC 1 is currently programmed for "
560 "TV\n");
561 } else if (monA) {
562 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
563 } else if (monB) {
564 FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
565 }
566
567 if (par->FlatPanel == -1) {
568 if (FlatPanel != -1) {
569 par->FlatPanel = FlatPanel;
570 par->Television = Television;
571 } else {
572 printk("nvidiafb: Unable to detect display "
573 "type...\n");
574 if (mobile) {
575 printk("...On a laptop, assuming "
576 "DFP\n");
577 par->FlatPanel = 1;
578 } else {
579 printk("...Using default of CRT\n");
580 par->FlatPanel = 0;
581 }
582 }
583 } else {
584 printk("nvidiafb: Forcing display type to %s as "
585 "specified\n", par->FlatPanel ? "DFP" : "CRT");
586 }
587
588 if (par->CRTCnumber == -1) {
589 if (CRTCnumber != -1)
590 par->CRTCnumber = CRTCnumber;
591 else {
592 printk("nvidiafb: Unable to detect which "
593 "CRTCNumber...\n");
594 if (par->FlatPanel)
595 par->CRTCnumber = 1;
596 else
597 par->CRTCnumber = 0;
598 printk("...Defaulting to CRTCNumber %i\n",
599 par->CRTCnumber);
600 }
601 } else {
602 printk("nvidiafb: Forcing CRTCNumber %i as "
603 "specified\n", par->CRTCnumber);
604 }
605
606 if (monA) {
607 if (((monA->input & FB_DISP_DDI) &&
608 par->FlatPanel) ||
609 ((!(monA->input & FB_DISP_DDI)) &&
610 !par->FlatPanel)) {
611 if (monB) {
612 fb_destroy_modedb(monB->modedb);
613 monB = NULL;
614 }
615 } else {
616 fb_destroy_modedb(monA->modedb);
617 monA = NULL;
618 }
619 }
620
621 if (monB) {
622 if (((monB->input & FB_DISP_DDI) &&
623 !par->FlatPanel) ||
624 ((!(monB->input & FB_DISP_DDI)) &&
625 par->FlatPanel)) {
626 fb_destroy_modedb(monB->modedb);
627 monB = NULL;
628 } else
629 monA = monB;
630 }
631
632 if (implementation == 0x0110)
633 cr44 = par->CRTCnumber * 0x3;
634
635 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
636
637 VGA_WR08(par->PCIO, 0x03D4, 0x44);
638 VGA_WR08(par->PCIO, 0x03D5, cr44);
639 NVSelectHeadRegisters(par, par->CRTCnumber);
640 }
641
642 printk("nvidiafb: Using %s on CRTC %i\n",
643 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
644 par->CRTCnumber);
645
646 if (par->FlatPanel && !par->Television) {
647 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
648 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
649 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
650
651 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
652 }
653
654 if (monA)
655 info->monspecs = *monA;
656
657 if (!par->FlatPanel || !par->twoHeads)
658 par->FPDither = 0;
659
660 par->LVDS = 0;
661 if (par->FlatPanel && par->twoHeads) {
662 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
663 if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
664 par->LVDS = 1;
665 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");
666 }
667
668 kfree(edidA);
669 kfree(edidB);
670done:
671 kfree(var);
672 kfree(monitorA);
673 kfree(monitorB);
674 return err;
675}
diff --git a/drivers/video/nvidia/nv_type.h b/drivers/video/nvidia/nv_type.h
deleted file mode 100644
index c03f7f55c76d..000000000000
--- a/drivers/video/nvidia/nv_type.h
+++ /dev/null
@@ -1,180 +0,0 @@
1#ifndef __NV_TYPE_H__
2#define __NV_TYPE_H__
3
4#include <linux/fb.h>
5#include <linux/types.h>
6#include <linux/i2c.h>
7#include <linux/i2c-algo-bit.h>
8#include <video/vga.h>
9
10#define NV_ARCH_04 0x04
11#define NV_ARCH_10 0x10
12#define NV_ARCH_20 0x20
13#define NV_ARCH_30 0x30
14#define NV_ARCH_40 0x40
15
16#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
17#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
18#define SetBF(mask,value) ((value) << (0?mask))
19#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
20#define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
21#define SetBit(n) (1<<(n))
22#define Set8Bits(value) ((value)&0xff)
23
24#define V_DBLSCAN 1
25
26typedef struct {
27 int bitsPerPixel;
28 int depth;
29 int displayWidth;
30 int weight;
31} NVFBLayout;
32
33#define NUM_SEQ_REGS 0x05
34#define NUM_CRT_REGS 0x41
35#define NUM_GRC_REGS 0x09
36#define NUM_ATC_REGS 0x15
37
38struct nvidia_par;
39
40struct nvidia_i2c_chan {
41 struct nvidia_par *par;
42 unsigned long ddc_base;
43 struct i2c_adapter adapter;
44 struct i2c_algo_bit_data algo;
45};
46
47typedef struct _riva_hw_state {
48 u8 attr[NUM_ATC_REGS];
49 u8 crtc[NUM_CRT_REGS];
50 u8 gra[NUM_GRC_REGS];
51 u8 seq[NUM_SEQ_REGS];
52 u8 misc_output;
53 u32 bpp;
54 u32 width;
55 u32 height;
56 u32 interlace;
57 u32 repaint0;
58 u32 repaint1;
59 u32 screen;
60 u32 scale;
61 u32 dither;
62 u32 extra;
63 u32 fifo;
64 u32 pixel;
65 u32 horiz;
66 u32 arbitration0;
67 u32 arbitration1;
68 u32 pll;
69 u32 pllB;
70 u32 vpll;
71 u32 vpll2;
72 u32 vpllB;
73 u32 vpll2B;
74 u32 pllsel;
75 u32 general;
76 u32 crtcOwner;
77 u32 head;
78 u32 head2;
79 u32 config;
80 u32 cursorConfig;
81 u32 cursor0;
82 u32 cursor1;
83 u32 cursor2;
84 u32 timingH;
85 u32 timingV;
86 u32 displayV;
87 u32 crtcSync;
88 u32 control;
89} RIVA_HW_STATE;
90
91struct riva_regs {
92 RIVA_HW_STATE ext;
93};
94
95struct nvidia_par {
96 RIVA_HW_STATE SavedReg;
97 RIVA_HW_STATE ModeReg;
98 RIVA_HW_STATE initial_state;
99 RIVA_HW_STATE *CurrentState;
100 struct vgastate vgastate;
101 u32 pseudo_palette[16];
102 struct pci_dev *pci_dev;
103 u32 Architecture;
104 u32 CursorStart;
105 int Chipset;
106 unsigned long FbAddress;
107 u8 __iomem *FbStart;
108 u32 FbMapSize;
109 u32 FbUsableSize;
110 u32 ScratchBufferSize;
111 u32 ScratchBufferStart;
112 int FpScale;
113 u32 MinVClockFreqKHz;
114 u32 MaxVClockFreqKHz;
115 u32 CrystalFreqKHz;
116 u32 RamAmountKBytes;
117 u32 IOBase;
118 NVFBLayout CurrentLayout;
119 int cursor_reset;
120 int lockup;
121 int videoKey;
122 int FlatPanel;
123 int FPDither;
124 int Television;
125 int CRTCnumber;
126 int alphaCursor;
127 int twoHeads;
128 int twoStagePLL;
129 int fpScaler;
130 int fpWidth;
131 int fpHeight;
132 int PanelTweak;
133 int paneltweak;
134 int LVDS;
135 int pm_state;
136 int reverse_i2c;
137 u32 crtcSync_read;
138 u32 fpSyncs;
139 u32 dmaPut;
140 u32 dmaCurrent;
141 u32 dmaFree;
142 u32 dmaMax;
143 u32 __iomem *dmaBase;
144 u32 currentRop;
145 int WaitVSyncPossible;
146 int BlendingPossible;
147 u32 paletteEnabled;
148 u32 forceCRTC;
149 u32 open_count;
150 u8 DDCBase;
151#ifdef CONFIG_MTRR
152 struct {
153 int vram;
154 int vram_valid;
155 } mtrr;
156#endif
157 struct nvidia_i2c_chan chan[3];
158
159 volatile u32 __iomem *REGS;
160 volatile u32 __iomem *PCRTC0;
161 volatile u32 __iomem *PCRTC;
162 volatile u32 __iomem *PRAMDAC0;
163 volatile u32 __iomem *PFB;
164 volatile u32 __iomem *PFIFO;
165 volatile u32 __iomem *PGRAPH;
166 volatile u32 __iomem *PEXTDEV;
167 volatile u32 __iomem *PTIMER;
168 volatile u32 __iomem *PMC;
169 volatile u32 __iomem *PRAMIN;
170 volatile u32 __iomem *FIFO;
171 volatile u32 __iomem *CURSOR;
172 volatile u8 __iomem *PCIO0;
173 volatile u8 __iomem *PCIO;
174 volatile u8 __iomem *PVIO;
175 volatile u8 __iomem *PDIO0;
176 volatile u8 __iomem *PDIO;
177 volatile u32 __iomem *PRAMDAC;
178};
179
180#endif /* __NV_TYPE_H__ */
diff --git a/drivers/video/nvidia/nvidia.c b/drivers/video/nvidia/nvidia.c
deleted file mode 100644
index def041204676..000000000000
--- a/drivers/video/nvidia/nvidia.c
+++ /dev/null
@@ -1,1607 +0,0 @@
1/*
2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
3 *
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 *
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/string.h>
16#include <linux/mm.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/fb.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <linux/console.h>
23#include <linux/backlight.h>
24#ifdef CONFIG_MTRR
25#include <asm/mtrr.h>
26#endif
27#ifdef CONFIG_PPC_OF
28#include <asm/prom.h>
29#include <asm/pci-bridge.h>
30#endif
31#ifdef CONFIG_BOOTX_TEXT
32#include <asm/btext.h>
33#endif
34
35#include "nv_local.h"
36#include "nv_type.h"
37#include "nv_proto.h"
38#include "nv_dma.h"
39
40#ifdef CONFIG_FB_NVIDIA_DEBUG
41#define NVTRACE printk
42#else
43#define NVTRACE if (0) printk
44#endif
45
46#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
47#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
48
49#ifdef CONFIG_FB_NVIDIA_DEBUG
50#define assert(expr) \
51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
53 #expr,__FILE__,__func__,__LINE__); \
54 BUG(); \
55 }
56#else
57#define assert(expr)
58#endif
59
60#define PFX "nvidiafb: "
61
62/* HW cursor parameters */
63#define MAX_CURS 32
64
65static struct pci_device_id nvidiafb_pci_tbl[] = {
66 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
67 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
68 { 0, }
69};
70MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
71
72/* command line data, set in nvidiafb_setup() */
73static int flatpanel = -1; /* Autodetect later */
74static int fpdither = -1;
75static int forceCRTC = -1;
76static int hwcur = 0;
77static int noaccel = 0;
78static int noscale = 0;
79static int paneltweak = 0;
80static int vram = 0;
81static int bpp = 8;
82static int reverse_i2c;
83#ifdef CONFIG_MTRR
84static bool nomtrr = false;
85#endif
86#ifdef CONFIG_PMAC_BACKLIGHT
87static int backlight = 1;
88#else
89static int backlight = 0;
90#endif
91
92static char *mode_option = NULL;
93
94static struct fb_fix_screeninfo nvidiafb_fix = {
95 .type = FB_TYPE_PACKED_PIXELS,
96 .xpanstep = 8,
97 .ypanstep = 1,
98};
99
100static struct fb_var_screeninfo nvidiafb_default_var = {
101 .xres = 640,
102 .yres = 480,
103 .xres_virtual = 640,
104 .yres_virtual = 480,
105 .bits_per_pixel = 8,
106 .red = {0, 8, 0},
107 .green = {0, 8, 0},
108 .blue = {0, 8, 0},
109 .transp = {0, 0, 0},
110 .activate = FB_ACTIVATE_NOW,
111 .height = -1,
112 .width = -1,
113 .pixclock = 39721,
114 .left_margin = 40,
115 .right_margin = 24,
116 .upper_margin = 32,
117 .lower_margin = 11,
118 .hsync_len = 96,
119 .vsync_len = 2,
120 .vmode = FB_VMODE_NONINTERLACED
121};
122
123static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
124 u16 bg, u16 fg, u32 w, u32 h)
125{
126 u32 *data = (u32 *) data8;
127 int i, j, k = 0;
128 u32 b, tmp;
129
130 w = (w + 1) & ~1;
131
132 for (i = 0; i < h; i++) {
133 b = *data++;
134 reverse_order(&b);
135
136 for (j = 0; j < w / 2; j++) {
137 tmp = 0;
138#if defined (__BIG_ENDIAN)
139 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
140 b <<= 1;
141 tmp |= (b & (1 << 31)) ? fg : bg;
142 b <<= 1;
143#else
144 tmp = (b & 1) ? fg : bg;
145 b >>= 1;
146 tmp |= (b & 1) ? fg << 16 : bg << 16;
147 b >>= 1;
148#endif
149 NV_WR32(&par->CURSOR[k++], 0, tmp);
150 }
151 k += (MAX_CURS - w) / 2;
152 }
153}
154
155static void nvidia_write_clut(struct nvidia_par *par,
156 u8 regnum, u8 red, u8 green, u8 blue)
157{
158 NVWriteDacMask(par, 0xff);
159 NVWriteDacWriteAddr(par, regnum);
160 NVWriteDacData(par, red);
161 NVWriteDacData(par, green);
162 NVWriteDacData(par, blue);
163}
164
165static void nvidia_read_clut(struct nvidia_par *par,
166 u8 regnum, u8 * red, u8 * green, u8 * blue)
167{
168 NVWriteDacMask(par, 0xff);
169 NVWriteDacReadAddr(par, regnum);
170 *red = NVReadDacData(par);
171 *green = NVReadDacData(par);
172 *blue = NVReadDacData(par);
173}
174
175static int nvidia_panel_tweak(struct nvidia_par *par,
176 struct _riva_hw_state *state)
177{
178 int tweak = 0;
179
180 if (par->paneltweak) {
181 tweak = par->paneltweak;
182 } else {
183 /* begin flat panel hacks */
184 /* This is unfortunate, but some chips need this register
185 tweaked or else you get artifacts where adjacent pixels are
186 swapped. There are no hard rules for what to set here so all
187 we can do is experiment and apply hacks. */
188
189 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
190 /* At least one NV34 laptop needs this workaround. */
191 tweak = -1;
192 }
193
194 if((par->Chipset & 0xfff0) == 0x0310) {
195 tweak = 1;
196 }
197 /* end flat panel hacks */
198 }
199
200 return tweak;
201}
202
203static void nvidia_screen_off(struct nvidia_par *par, int on)
204{
205 unsigned char tmp;
206
207 if (on) {
208 /*
209 * Turn off screen and disable sequencer.
210 */
211 tmp = NVReadSeq(par, 0x01);
212
213 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
214 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
215 } else {
216 /*
217 * Reenable sequencer, then turn on screen.
218 */
219
220 tmp = NVReadSeq(par, 0x01);
221
222 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
223 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
224 }
225}
226
227static void nvidia_save_vga(struct nvidia_par *par,
228 struct _riva_hw_state *state)
229{
230 int i;
231
232 NVTRACE_ENTER();
233 NVLockUnlock(par, 0);
234
235 NVUnloadStateExt(par, state);
236
237 state->misc_output = NVReadMiscOut(par);
238
239 for (i = 0; i < NUM_CRT_REGS; i++)
240 state->crtc[i] = NVReadCrtc(par, i);
241
242 for (i = 0; i < NUM_ATC_REGS; i++)
243 state->attr[i] = NVReadAttr(par, i);
244
245 for (i = 0; i < NUM_GRC_REGS; i++)
246 state->gra[i] = NVReadGr(par, i);
247
248 for (i = 0; i < NUM_SEQ_REGS; i++)
249 state->seq[i] = NVReadSeq(par, i);
250 NVTRACE_LEAVE();
251}
252
253#undef DUMP_REG
254
255static void nvidia_write_regs(struct nvidia_par *par,
256 struct _riva_hw_state *state)
257{
258 int i;
259
260 NVTRACE_ENTER();
261
262 NVLoadStateExt(par, state);
263
264 NVWriteMiscOut(par, state->misc_output);
265
266 for (i = 1; i < NUM_SEQ_REGS; i++) {
267#ifdef DUMP_REG
268 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
269#endif
270 NVWriteSeq(par, i, state->seq[i]);
271 }
272
273 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
274 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
275
276 for (i = 0; i < NUM_CRT_REGS; i++) {
277 switch (i) {
278 case 0x19:
279 case 0x20 ... 0x40:
280 break;
281 default:
282#ifdef DUMP_REG
283 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
284#endif
285 NVWriteCrtc(par, i, state->crtc[i]);
286 }
287 }
288
289 for (i = 0; i < NUM_GRC_REGS; i++) {
290#ifdef DUMP_REG
291 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
292#endif
293 NVWriteGr(par, i, state->gra[i]);
294 }
295
296 for (i = 0; i < NUM_ATC_REGS; i++) {
297#ifdef DUMP_REG
298 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
299#endif
300 NVWriteAttr(par, i, state->attr[i]);
301 }
302
303 NVTRACE_LEAVE();
304}
305
306static int nvidia_calc_regs(struct fb_info *info)
307{
308 struct nvidia_par *par = info->par;
309 struct _riva_hw_state *state = &par->ModeReg;
310 int i, depth = fb_get_color_depth(&info->var, &info->fix);
311 int h_display = info->var.xres / 8 - 1;
312 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
313 int h_end = (info->var.xres + info->var.right_margin +
314 info->var.hsync_len) / 8 - 1;
315 int h_total = (info->var.xres + info->var.right_margin +
316 info->var.hsync_len + info->var.left_margin) / 8 - 5;
317 int h_blank_s = h_display;
318 int h_blank_e = h_total + 4;
319 int v_display = info->var.yres - 1;
320 int v_start = info->var.yres + info->var.lower_margin - 1;
321 int v_end = (info->var.yres + info->var.lower_margin +
322 info->var.vsync_len) - 1;
323 int v_total = (info->var.yres + info->var.lower_margin +
324 info->var.vsync_len + info->var.upper_margin) - 2;
325 int v_blank_s = v_display;
326 int v_blank_e = v_total + 1;
327
328 /*
329 * Set all CRTC values.
330 */
331
332 if (info->var.vmode & FB_VMODE_INTERLACED)
333 v_total |= 1;
334
335 if (par->FlatPanel == 1) {
336 v_start = v_total - 3;
337 v_end = v_total - 2;
338 v_blank_s = v_start;
339 h_start = h_total - 5;
340 h_end = h_total - 2;
341 h_blank_e = h_total + 4;
342 }
343
344 state->crtc[0x0] = Set8Bits(h_total);
345 state->crtc[0x1] = Set8Bits(h_display);
346 state->crtc[0x2] = Set8Bits(h_blank_s);
347 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
348 | SetBit(7);
349 state->crtc[0x4] = Set8Bits(h_start);
350 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
351 | SetBitField(h_end, 4: 0, 4:0);
352 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
353 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
354 | SetBitField(v_display, 8: 8, 1:1)
355 | SetBitField(v_start, 8: 8, 2:2)
356 | SetBitField(v_blank_s, 8: 8, 3:3)
357 | SetBit(4)
358 | SetBitField(v_total, 9: 9, 5:5)
359 | SetBitField(v_display, 9: 9, 6:6)
360 | SetBitField(v_start, 9: 9, 7:7);
361 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
362 | SetBit(6)
363 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
364 state->crtc[0x10] = Set8Bits(v_start);
365 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
366 state->crtc[0x12] = Set8Bits(v_display);
367 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
368 (info->var.bits_per_pixel / 8));
369 state->crtc[0x15] = Set8Bits(v_blank_s);
370 state->crtc[0x16] = Set8Bits(v_blank_e);
371
372 state->attr[0x10] = 0x01;
373
374 if (par->Television)
375 state->attr[0x11] = 0x00;
376
377 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
378 | SetBitField(v_blank_s, 10: 10, 3:3)
379 | SetBitField(v_start, 10: 10, 2:2)
380 | SetBitField(v_display, 10: 10, 1:1)
381 | SetBitField(v_total, 10: 10, 0:0);
382
383 state->horiz = SetBitField(h_total, 8: 8, 0:0)
384 | SetBitField(h_display, 8: 8, 1:1)
385 | SetBitField(h_blank_s, 8: 8, 2:2)
386 | SetBitField(h_start, 8: 8, 3:3);
387
388 state->extra = SetBitField(v_total, 11: 11, 0:0)
389 | SetBitField(v_display, 11: 11, 2:2)
390 | SetBitField(v_start, 11: 11, 4:4)
391 | SetBitField(v_blank_s, 11: 11, 6:6);
392
393 if (info->var.vmode & FB_VMODE_INTERLACED) {
394 h_total = (h_total >> 1) & ~1;
395 state->interlace = Set8Bits(h_total);
396 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
397 } else {
398 state->interlace = 0xff; /* interlace off */
399 }
400
401 /*
402 * Calculate the extended registers.
403 */
404
405 if (depth < 24)
406 i = depth;
407 else
408 i = 32;
409
410 if (par->Architecture >= NV_ARCH_10)
411 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
412 par->CursorStart);
413
414 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
415 state->misc_output &= ~0x40;
416 else
417 state->misc_output |= 0x40;
418 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
419 state->misc_output &= ~0x80;
420 else
421 state->misc_output |= 0x80;
422
423 NVCalcStateExt(par, state, i, info->var.xres_virtual,
424 info->var.xres, info->var.yres_virtual,
425 1000000000 / info->var.pixclock, info->var.vmode);
426
427 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
428 if (par->FlatPanel == 1) {
429 state->pixel |= (1 << 7);
430
431 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
432 || (par->fpHeight <= info->var.yres)) {
433 state->scale |= (1 << 8);
434 }
435
436 if (!par->crtcSync_read) {
437 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
438 par->crtcSync_read = 1;
439 }
440
441 par->PanelTweak = nvidia_panel_tweak(par, state);
442 }
443
444 state->vpll = state->pll;
445 state->vpll2 = state->pll;
446 state->vpllB = state->pllB;
447 state->vpll2B = state->pllB;
448
449 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
450 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
451
452 if (par->CRTCnumber) {
453 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
454 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
455 state->crtcOwner = 3;
456 state->pllsel |= 0x20000800;
457 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
458 if (par->twoStagePLL)
459 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
460 } else if (par->twoHeads) {
461 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
462 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
463 state->crtcOwner = 0;
464 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
465 if (par->twoStagePLL)
466 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
467 }
468
469 state->cursorConfig = 0x00000100;
470
471 if (info->var.vmode & FB_VMODE_DOUBLE)
472 state->cursorConfig |= (1 << 4);
473
474 if (par->alphaCursor) {
475 if ((par->Chipset & 0x0ff0) != 0x0110)
476 state->cursorConfig |= 0x04011000;
477 else
478 state->cursorConfig |= 0x14011000;
479 state->general |= (1 << 29);
480 } else
481 state->cursorConfig |= 0x02000000;
482
483 if (par->twoHeads) {
484 if ((par->Chipset & 0x0ff0) == 0x0110) {
485 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
486 ~0x00010000;
487 if (par->FPDither)
488 state->dither |= 0x00010000;
489 } else {
490 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
491 if (par->FPDither)
492 state->dither |= 1;
493 }
494 }
495
496 state->timingH = 0;
497 state->timingV = 0;
498 state->displayV = info->var.xres;
499
500 return 0;
501}
502
503static void nvidia_init_vga(struct fb_info *info)
504{
505 struct nvidia_par *par = info->par;
506 struct _riva_hw_state *state = &par->ModeReg;
507 int i;
508
509 for (i = 0; i < 0x10; i++)
510 state->attr[i] = i;
511 state->attr[0x10] = 0x41;
512 state->attr[0x11] = 0xff;
513 state->attr[0x12] = 0x0f;
514 state->attr[0x13] = 0x00;
515 state->attr[0x14] = 0x00;
516
517 memset(state->crtc, 0x00, NUM_CRT_REGS);
518 state->crtc[0x0a] = 0x20;
519 state->crtc[0x17] = 0xe3;
520 state->crtc[0x18] = 0xff;
521 state->crtc[0x28] = 0x40;
522
523 memset(state->gra, 0x00, NUM_GRC_REGS);
524 state->gra[0x05] = 0x40;
525 state->gra[0x06] = 0x05;
526 state->gra[0x07] = 0x0f;
527 state->gra[0x08] = 0xff;
528
529 state->seq[0x00] = 0x03;
530 state->seq[0x01] = 0x01;
531 state->seq[0x02] = 0x0f;
532 state->seq[0x03] = 0x00;
533 state->seq[0x04] = 0x0e;
534
535 state->misc_output = 0xeb;
536}
537
538static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
539{
540 struct nvidia_par *par = info->par;
541 u8 data[MAX_CURS * MAX_CURS / 8];
542 int i, set = cursor->set;
543 u16 fg, bg;
544
545 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
546 return -ENXIO;
547
548 NVShowHideCursor(par, 0);
549
550 if (par->cursor_reset) {
551 set = FB_CUR_SETALL;
552 par->cursor_reset = 0;
553 }
554
555 if (set & FB_CUR_SETSIZE)
556 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
557
558 if (set & FB_CUR_SETPOS) {
559 u32 xx, yy, temp;
560
561 yy = cursor->image.dy - info->var.yoffset;
562 xx = cursor->image.dx - info->var.xoffset;
563 temp = xx & 0xFFFF;
564 temp |= yy << 16;
565
566 NV_WR32(par->PRAMDAC, 0x0000300, temp);
567 }
568
569 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
570 u32 bg_idx = cursor->image.bg_color;
571 u32 fg_idx = cursor->image.fg_color;
572 u32 s_pitch = (cursor->image.width + 7) >> 3;
573 u32 d_pitch = MAX_CURS / 8;
574 u8 *dat = (u8 *) cursor->image.data;
575 u8 *msk = (u8 *) cursor->mask;
576 u8 *src;
577
578 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
579
580 if (src) {
581 switch (cursor->rop) {
582 case ROP_XOR:
583 for (i = 0; i < s_pitch * cursor->image.height; i++)
584 src[i] = dat[i] ^ msk[i];
585 break;
586 case ROP_COPY:
587 default:
588 for (i = 0; i < s_pitch * cursor->image.height; i++)
589 src[i] = dat[i] & msk[i];
590 break;
591 }
592
593 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
594 cursor->image.height);
595
596 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
597 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
598 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
599
600 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
601 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
602 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
603
604 NVLockUnlock(par, 0);
605
606 nvidiafb_load_cursor_image(par, data, bg, fg,
607 cursor->image.width,
608 cursor->image.height);
609 kfree(src);
610 }
611 }
612
613 if (cursor->enable)
614 NVShowHideCursor(par, 1);
615
616 return 0;
617}
618
619static int nvidiafb_set_par(struct fb_info *info)
620{
621 struct nvidia_par *par = info->par;
622
623 NVTRACE_ENTER();
624
625 NVLockUnlock(par, 1);
626 if (!par->FlatPanel || !par->twoHeads)
627 par->FPDither = 0;
628
629 if (par->FPDither < 0) {
630 if ((par->Chipset & 0x0ff0) == 0x0110)
631 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
632 & 0x00010000);
633 else
634 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
635 printk(KERN_INFO PFX "Flat panel dithering %s\n",
636 par->FPDither ? "enabled" : "disabled");
637 }
638
639 info->fix.visual = (info->var.bits_per_pixel == 8) ?
640 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
641
642 nvidia_init_vga(info);
643 nvidia_calc_regs(info);
644
645 NVLockUnlock(par, 0);
646 if (par->twoHeads) {
647 VGA_WR08(par->PCIO, 0x03D4, 0x44);
648 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
649 NVLockUnlock(par, 0);
650 }
651
652 nvidia_screen_off(par, 1);
653
654 nvidia_write_regs(par, &par->ModeReg);
655 NVSetStartAddress(par, 0);
656
657#if defined (__BIG_ENDIAN)
658 /* turn on LFB swapping */
659 {
660 unsigned char tmp;
661
662 VGA_WR08(par->PCIO, 0x3d4, 0x46);
663 tmp = VGA_RD08(par->PCIO, 0x3d5);
664 tmp |= (1 << 7);
665 VGA_WR08(par->PCIO, 0x3d5, tmp);
666 }
667#endif
668
669 info->fix.line_length = (info->var.xres_virtual *
670 info->var.bits_per_pixel) >> 3;
671 if (info->var.accel_flags) {
672 info->fbops->fb_imageblit = nvidiafb_imageblit;
673 info->fbops->fb_fillrect = nvidiafb_fillrect;
674 info->fbops->fb_copyarea = nvidiafb_copyarea;
675 info->fbops->fb_sync = nvidiafb_sync;
676 info->pixmap.scan_align = 4;
677 info->flags &= ~FBINFO_HWACCEL_DISABLED;
678 info->flags |= FBINFO_READS_FAST;
679 NVResetGraphics(info);
680 } else {
681 info->fbops->fb_imageblit = cfb_imageblit;
682 info->fbops->fb_fillrect = cfb_fillrect;
683 info->fbops->fb_copyarea = cfb_copyarea;
684 info->fbops->fb_sync = NULL;
685 info->pixmap.scan_align = 1;
686 info->flags |= FBINFO_HWACCEL_DISABLED;
687 info->flags &= ~FBINFO_READS_FAST;
688 }
689
690 par->cursor_reset = 1;
691
692 nvidia_screen_off(par, 0);
693
694#ifdef CONFIG_BOOTX_TEXT
695 /* Update debug text engine */
696 btext_update_display(info->fix.smem_start,
697 info->var.xres, info->var.yres,
698 info->var.bits_per_pixel, info->fix.line_length);
699#endif
700
701 NVLockUnlock(par, 0);
702 NVTRACE_LEAVE();
703 return 0;
704}
705
706static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
707 unsigned blue, unsigned transp,
708 struct fb_info *info)
709{
710 struct nvidia_par *par = info->par;
711 int i;
712
713 NVTRACE_ENTER();
714 if (regno >= (1 << info->var.green.length))
715 return -EINVAL;
716
717 if (info->var.grayscale) {
718 /* gray = 0.30*R + 0.59*G + 0.11*B */
719 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
720 }
721
722 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
723 ((u32 *) info->pseudo_palette)[regno] =
724 (regno << info->var.red.offset) |
725 (regno << info->var.green.offset) |
726 (regno << info->var.blue.offset);
727 }
728
729 switch (info->var.bits_per_pixel) {
730 case 8:
731 /* "transparent" stuff is completely ignored. */
732 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
733 break;
734 case 16:
735 if (info->var.green.length == 5) {
736 for (i = 0; i < 8; i++) {
737 nvidia_write_clut(par, regno * 8 + i, red >> 8,
738 green >> 8, blue >> 8);
739 }
740 } else {
741 u8 r, g, b;
742
743 if (regno < 32) {
744 for (i = 0; i < 8; i++) {
745 nvidia_write_clut(par, regno * 8 + i,
746 red >> 8, green >> 8,
747 blue >> 8);
748 }
749 }
750
751 nvidia_read_clut(par, regno * 4, &r, &g, &b);
752
753 for (i = 0; i < 4; i++)
754 nvidia_write_clut(par, regno * 4 + i, r,
755 green >> 8, b);
756 }
757 break;
758 case 32:
759 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
760 break;
761 default:
762 /* do nothing */
763 break;
764 }
765
766 NVTRACE_LEAVE();
767 return 0;
768}
769
770static int nvidiafb_check_var(struct fb_var_screeninfo *var,
771 struct fb_info *info)
772{
773 struct nvidia_par *par = info->par;
774 int memlen, vramlen, mode_valid = 0;
775 int pitch, err = 0;
776
777 NVTRACE_ENTER();
778
779 var->transp.offset = 0;
780 var->transp.length = 0;
781
782 var->xres &= ~7;
783
784 if (var->bits_per_pixel <= 8)
785 var->bits_per_pixel = 8;
786 else if (var->bits_per_pixel <= 16)
787 var->bits_per_pixel = 16;
788 else
789 var->bits_per_pixel = 32;
790
791 switch (var->bits_per_pixel) {
792 case 8:
793 var->red.offset = 0;
794 var->red.length = 8;
795 var->green.offset = 0;
796 var->green.length = 8;
797 var->blue.offset = 0;
798 var->blue.length = 8;
799 var->transp.offset = 0;
800 var->transp.length = 0;
801 break;
802 case 16:
803 var->green.length = (var->green.length < 6) ? 5 : 6;
804 var->red.length = 5;
805 var->blue.length = 5;
806 var->transp.length = 6 - var->green.length;
807 var->blue.offset = 0;
808 var->green.offset = 5;
809 var->red.offset = 5 + var->green.length;
810 var->transp.offset = (5 + var->red.offset) & 15;
811 break;
812 case 32: /* RGBA 8888 */
813 var->red.offset = 16;
814 var->red.length = 8;
815 var->green.offset = 8;
816 var->green.length = 8;
817 var->blue.offset = 0;
818 var->blue.length = 8;
819 var->transp.length = 8;
820 var->transp.offset = 24;
821 break;
822 }
823
824 var->red.msb_right = 0;
825 var->green.msb_right = 0;
826 var->blue.msb_right = 0;
827 var->transp.msb_right = 0;
828
829 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
830 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
831 mode_valid = 1;
832
833 /* calculate modeline if supported by monitor */
834 if (!mode_valid && info->monspecs.gtf) {
835 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
836 mode_valid = 1;
837 }
838
839 if (!mode_valid) {
840 const struct fb_videomode *mode;
841
842 mode = fb_find_best_mode(var, &info->modelist);
843 if (mode) {
844 fb_videomode_to_var(var, mode);
845 mode_valid = 1;
846 }
847 }
848
849 if (!mode_valid && info->monspecs.modedb_len)
850 return -EINVAL;
851
852 /*
853 * If we're on a flat panel, check if the mode is outside of the
854 * panel dimensions. If so, cap it and try for the next best mode
855 * before bailing out.
856 */
857 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
858 par->fpHeight < var->yres)) {
859 const struct fb_videomode *mode;
860
861 var->xres = par->fpWidth;
862 var->yres = par->fpHeight;
863
864 mode = fb_find_best_mode(var, &info->modelist);
865 if (!mode) {
866 printk(KERN_ERR PFX "mode out of range of flat "
867 "panel dimensions\n");
868 return -EINVAL;
869 }
870
871 fb_videomode_to_var(var, mode);
872 }
873
874 if (var->yres_virtual < var->yres)
875 var->yres_virtual = var->yres;
876
877 if (var->xres_virtual < var->xres)
878 var->xres_virtual = var->xres;
879
880 var->xres_virtual = (var->xres_virtual + 63) & ~63;
881
882 vramlen = info->screen_size;
883 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
884 memlen = pitch * var->yres_virtual;
885
886 if (memlen > vramlen) {
887 var->yres_virtual = vramlen / pitch;
888
889 if (var->yres_virtual < var->yres) {
890 var->yres_virtual = var->yres;
891 var->xres_virtual = vramlen / var->yres_virtual;
892 var->xres_virtual /= var->bits_per_pixel / 8;
893 var->xres_virtual &= ~63;
894 pitch = (var->xres_virtual *
895 var->bits_per_pixel + 7) / 8;
896 memlen = pitch * var->yres;
897
898 if (var->xres_virtual < var->xres) {
899 printk("nvidiafb: required video memory, "
900 "%d bytes, for %dx%d-%d (virtual) "
901 "is out of range\n",
902 memlen, var->xres_virtual,
903 var->yres_virtual, var->bits_per_pixel);
904 err = -ENOMEM;
905 }
906 }
907 }
908
909 if (var->accel_flags) {
910 if (var->yres_virtual > 0x7fff)
911 var->yres_virtual = 0x7fff;
912 if (var->xres_virtual > 0x7fff)
913 var->xres_virtual = 0x7fff;
914 }
915
916 var->xres_virtual &= ~63;
917
918 NVTRACE_LEAVE();
919
920 return err;
921}
922
923static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
924 struct fb_info *info)
925{
926 struct nvidia_par *par = info->par;
927 u32 total;
928
929 total = var->yoffset * info->fix.line_length + var->xoffset;
930
931 NVSetStartAddress(par, total);
932
933 return 0;
934}
935
936static int nvidiafb_blank(int blank, struct fb_info *info)
937{
938 struct nvidia_par *par = info->par;
939 unsigned char tmp, vesa;
940
941 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
942 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
943
944 NVTRACE_ENTER();
945
946 if (blank)
947 tmp |= 0x20;
948
949 switch (blank) {
950 case FB_BLANK_UNBLANK:
951 case FB_BLANK_NORMAL:
952 break;
953 case FB_BLANK_VSYNC_SUSPEND:
954 vesa |= 0x80;
955 break;
956 case FB_BLANK_HSYNC_SUSPEND:
957 vesa |= 0x40;
958 break;
959 case FB_BLANK_POWERDOWN:
960 vesa |= 0xc0;
961 break;
962 }
963
964 NVWriteSeq(par, 0x01, tmp);
965 NVWriteCrtc(par, 0x1a, vesa);
966
967 NVTRACE_LEAVE();
968
969 return 0;
970}
971
972/*
973 * Because the VGA registers are not mapped linearly in its MMIO space,
974 * restrict VGA register saving and restore to x86 only, where legacy VGA IO
975 * access is legal. Consequently, we must also check if the device is the
976 * primary display.
977 */
978#ifdef CONFIG_X86
979static void save_vga_x86(struct nvidia_par *par)
980{
981 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
982
983 if (res && res->flags & IORESOURCE_ROM_SHADOW) {
984 memset(&par->vgastate, 0, sizeof(par->vgastate));
985 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
986 VGA_SAVE_CMAP;
987 save_vga(&par->vgastate);
988 }
989}
990
991static void restore_vga_x86(struct nvidia_par *par)
992{
993 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
994
995 if (res && res->flags & IORESOURCE_ROM_SHADOW)
996 restore_vga(&par->vgastate);
997}
998#else
999#define save_vga_x86(x) do {} while (0)
1000#define restore_vga_x86(x) do {} while (0)
1001#endif /* X86 */
1002
1003static int nvidiafb_open(struct fb_info *info, int user)
1004{
1005 struct nvidia_par *par = info->par;
1006
1007 if (!par->open_count) {
1008 save_vga_x86(par);
1009 nvidia_save_vga(par, &par->initial_state);
1010 }
1011
1012 par->open_count++;
1013 return 0;
1014}
1015
1016static int nvidiafb_release(struct fb_info *info, int user)
1017{
1018 struct nvidia_par *par = info->par;
1019 int err = 0;
1020
1021 if (!par->open_count) {
1022 err = -EINVAL;
1023 goto done;
1024 }
1025
1026 if (par->open_count == 1) {
1027 nvidia_write_regs(par, &par->initial_state);
1028 restore_vga_x86(par);
1029 }
1030
1031 par->open_count--;
1032done:
1033 return err;
1034}
1035
1036static struct fb_ops nvidia_fb_ops = {
1037 .owner = THIS_MODULE,
1038 .fb_open = nvidiafb_open,
1039 .fb_release = nvidiafb_release,
1040 .fb_check_var = nvidiafb_check_var,
1041 .fb_set_par = nvidiafb_set_par,
1042 .fb_setcolreg = nvidiafb_setcolreg,
1043 .fb_pan_display = nvidiafb_pan_display,
1044 .fb_blank = nvidiafb_blank,
1045 .fb_fillrect = nvidiafb_fillrect,
1046 .fb_copyarea = nvidiafb_copyarea,
1047 .fb_imageblit = nvidiafb_imageblit,
1048 .fb_cursor = nvidiafb_cursor,
1049 .fb_sync = nvidiafb_sync,
1050};
1051
1052#ifdef CONFIG_PM
1053static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg)
1054{
1055 struct fb_info *info = pci_get_drvdata(dev);
1056 struct nvidia_par *par = info->par;
1057
1058 if (mesg.event == PM_EVENT_PRETHAW)
1059 mesg.event = PM_EVENT_FREEZE;
1060 console_lock();
1061 par->pm_state = mesg.event;
1062
1063 if (mesg.event & PM_EVENT_SLEEP) {
1064 fb_set_suspend(info, 1);
1065 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1066 nvidia_write_regs(par, &par->SavedReg);
1067 pci_save_state(dev);
1068 pci_disable_device(dev);
1069 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1070 }
1071 dev->dev.power.power_state = mesg;
1072
1073 console_unlock();
1074 return 0;
1075}
1076
1077static int nvidiafb_resume(struct pci_dev *dev)
1078{
1079 struct fb_info *info = pci_get_drvdata(dev);
1080 struct nvidia_par *par = info->par;
1081
1082 console_lock();
1083 pci_set_power_state(dev, PCI_D0);
1084
1085 if (par->pm_state != PM_EVENT_FREEZE) {
1086 pci_restore_state(dev);
1087
1088 if (pci_enable_device(dev))
1089 goto fail;
1090
1091 pci_set_master(dev);
1092 }
1093
1094 par->pm_state = PM_EVENT_ON;
1095 nvidiafb_set_par(info);
1096 fb_set_suspend (info, 0);
1097 nvidiafb_blank(FB_BLANK_UNBLANK, info);
1098
1099fail:
1100 console_unlock();
1101 return 0;
1102}
1103#else
1104#define nvidiafb_suspend NULL
1105#define nvidiafb_resume NULL
1106#endif
1107
1108static int nvidia_set_fbinfo(struct fb_info *info)
1109{
1110 struct fb_monspecs *specs = &info->monspecs;
1111 struct fb_videomode modedb;
1112 struct nvidia_par *par = info->par;
1113 int lpitch;
1114
1115 NVTRACE_ENTER();
1116 info->flags = FBINFO_DEFAULT
1117 | FBINFO_HWACCEL_IMAGEBLIT
1118 | FBINFO_HWACCEL_FILLRECT
1119 | FBINFO_HWACCEL_COPYAREA
1120 | FBINFO_HWACCEL_YPAN;
1121
1122 fb_videomode_to_modelist(info->monspecs.modedb,
1123 info->monspecs.modedb_len, &info->modelist);
1124 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1125
1126 switch (bpp) {
1127 case 0 ... 8:
1128 bpp = 8;
1129 break;
1130 case 9 ... 16:
1131 bpp = 16;
1132 break;
1133 default:
1134 bpp = 32;
1135 break;
1136 }
1137
1138 if (specs->modedb != NULL) {
1139 const struct fb_videomode *mode;
1140
1141 mode = fb_find_best_display(specs, &info->modelist);
1142 fb_videomode_to_var(&nvidiafb_default_var, mode);
1143 nvidiafb_default_var.bits_per_pixel = bpp;
1144 } else if (par->fpWidth && par->fpHeight) {
1145 char buf[16];
1146
1147 memset(buf, 0, 16);
1148 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1149 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1150 specs->modedb_len, &modedb, bpp);
1151 }
1152
1153 if (mode_option)
1154 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1155 specs->modedb, specs->modedb_len, &modedb, bpp);
1156
1157 info->var = nvidiafb_default_var;
1158 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1159 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1160 info->pseudo_palette = par->pseudo_palette;
1161 fb_alloc_cmap(&info->cmap, 256, 0);
1162 fb_destroy_modedb(info->monspecs.modedb);
1163 info->monspecs.modedb = NULL;
1164
1165 /* maximize virtual vertical length */
1166 lpitch = info->var.xres_virtual *
1167 ((info->var.bits_per_pixel + 7) >> 3);
1168 info->var.yres_virtual = info->screen_size / lpitch;
1169
1170 info->pixmap.scan_align = 4;
1171 info->pixmap.buf_align = 4;
1172 info->pixmap.access_align = 32;
1173 info->pixmap.size = 8 * 1024;
1174 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1175
1176 if (!hwcur)
1177 info->fbops->fb_cursor = NULL;
1178
1179 info->var.accel_flags = (!noaccel);
1180
1181 switch (par->Architecture) {
1182 case NV_ARCH_04:
1183 info->fix.accel = FB_ACCEL_NV4;
1184 break;
1185 case NV_ARCH_10:
1186 info->fix.accel = FB_ACCEL_NV_10;
1187 break;
1188 case NV_ARCH_20:
1189 info->fix.accel = FB_ACCEL_NV_20;
1190 break;
1191 case NV_ARCH_30:
1192 info->fix.accel = FB_ACCEL_NV_30;
1193 break;
1194 case NV_ARCH_40:
1195 info->fix.accel = FB_ACCEL_NV_40;
1196 break;
1197 }
1198
1199 NVTRACE_LEAVE();
1200
1201 return nvidiafb_check_var(&info->var, info);
1202}
1203
1204static u32 nvidia_get_chipset(struct fb_info *info)
1205{
1206 struct nvidia_par *par = info->par;
1207 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1208
1209 printk(KERN_INFO PFX "Device ID: %x \n", id);
1210
1211 if ((id & 0xfff0) == 0x00f0 ||
1212 (id & 0xfff0) == 0x02e0) {
1213 /* pci-e */
1214 id = NV_RD32(par->REGS, 0x1800);
1215
1216 if ((id & 0x0000ffff) == 0x000010DE)
1217 id = 0x10DE0000 | (id >> 16);
1218 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1219 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1220 ((id >> 8) & 0x000000ff);
1221 printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1222 }
1223
1224 return id;
1225}
1226
1227static u32 nvidia_get_arch(struct fb_info *info)
1228{
1229 struct nvidia_par *par = info->par;
1230 u32 arch = 0;
1231
1232 switch (par->Chipset & 0x0ff0) {
1233 case 0x0100: /* GeForce 256 */
1234 case 0x0110: /* GeForce2 MX */
1235 case 0x0150: /* GeForce2 */
1236 case 0x0170: /* GeForce4 MX */
1237 case 0x0180: /* GeForce4 MX (8x AGP) */
1238 case 0x01A0: /* nForce */
1239 case 0x01F0: /* nForce2 */
1240 arch = NV_ARCH_10;
1241 break;
1242 case 0x0200: /* GeForce3 */
1243 case 0x0250: /* GeForce4 Ti */
1244 case 0x0280: /* GeForce4 Ti (8x AGP) */
1245 arch = NV_ARCH_20;
1246 break;
1247 case 0x0300: /* GeForceFX 5800 */
1248 case 0x0310: /* GeForceFX 5600 */
1249 case 0x0320: /* GeForceFX 5200 */
1250 case 0x0330: /* GeForceFX 5900 */
1251 case 0x0340: /* GeForceFX 5700 */
1252 arch = NV_ARCH_30;
1253 break;
1254 case 0x0040: /* GeForce 6800 */
1255 case 0x00C0: /* GeForce 6800 */
1256 case 0x0120: /* GeForce 6800 */
1257 case 0x0140: /* GeForce 6600 */
1258 case 0x0160: /* GeForce 6200 */
1259 case 0x01D0: /* GeForce 7200, 7300, 7400 */
1260 case 0x0090: /* GeForce 7800 */
1261 case 0x0210: /* GeForce 6800 */
1262 case 0x0220: /* GeForce 6200 */
1263 case 0x0240: /* GeForce 6100 */
1264 case 0x0290: /* GeForce 7900 */
1265 case 0x0390: /* GeForce 7600 */
1266 case 0x03D0:
1267 arch = NV_ARCH_40;
1268 break;
1269 case 0x0020: /* TNT, TNT2 */
1270 arch = NV_ARCH_04;
1271 break;
1272 default: /* unknown architecture */
1273 break;
1274 }
1275
1276 return arch;
1277}
1278
1279static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1280{
1281 struct nvidia_par *par;
1282 struct fb_info *info;
1283 unsigned short cmd;
1284
1285
1286 NVTRACE_ENTER();
1287 assert(pd != NULL);
1288
1289 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1290
1291 if (!info)
1292 goto err_out;
1293
1294 par = info->par;
1295 par->pci_dev = pd;
1296 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1297
1298 if (info->pixmap.addr == NULL)
1299 goto err_out_kfree;
1300
1301 if (pci_enable_device(pd)) {
1302 printk(KERN_ERR PFX "cannot enable PCI device\n");
1303 goto err_out_enable;
1304 }
1305
1306 if (pci_request_regions(pd, "nvidiafb")) {
1307 printk(KERN_ERR PFX "cannot request PCI regions\n");
1308 goto err_out_enable;
1309 }
1310
1311 par->FlatPanel = flatpanel;
1312 if (flatpanel == 1)
1313 printk(KERN_INFO PFX "flatpanel support enabled\n");
1314 par->FPDither = fpdither;
1315
1316 par->CRTCnumber = forceCRTC;
1317 par->FpScale = (!noscale);
1318 par->paneltweak = paneltweak;
1319 par->reverse_i2c = reverse_i2c;
1320
1321 /* enable IO and mem if not already done */
1322 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1323 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1324 pci_write_config_word(pd, PCI_COMMAND, cmd);
1325
1326 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1327 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1328 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1329
1330 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1331
1332 if (!par->REGS) {
1333 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1334 goto err_out_free_base0;
1335 }
1336
1337 par->Chipset = nvidia_get_chipset(info);
1338 par->Architecture = nvidia_get_arch(info);
1339
1340 if (par->Architecture == 0) {
1341 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1342 goto err_out_arch;
1343 }
1344
1345 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1346
1347 if (NVCommonSetup(info))
1348 goto err_out_arch;
1349
1350 par->FbAddress = nvidiafb_fix.smem_start;
1351 par->FbMapSize = par->RamAmountKBytes * 1024;
1352 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1353 par->FbMapSize = vram * 1024 * 1024;
1354
1355 /* Limit amount of vram to 64 MB */
1356 if (par->FbMapSize > 64 * 1024 * 1024)
1357 par->FbMapSize = 64 * 1024 * 1024;
1358
1359 if(par->Architecture >= NV_ARCH_40)
1360 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1361 else
1362 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1363 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1364 16 * 1024;
1365 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1366 par->CursorStart = par->FbUsableSize + (32 * 1024);
1367
1368 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1369 info->screen_size = par->FbUsableSize;
1370 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1371
1372 if (!info->screen_base) {
1373 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1374 goto err_out_free_base1;
1375 }
1376
1377 par->FbStart = info->screen_base;
1378
1379#ifdef CONFIG_MTRR
1380 if (!nomtrr) {
1381 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1382 par->RamAmountKBytes * 1024,
1383 MTRR_TYPE_WRCOMB, 1);
1384 if (par->mtrr.vram < 0) {
1385 printk(KERN_ERR PFX "unable to setup MTRR\n");
1386 } else {
1387 par->mtrr.vram_valid = 1;
1388 /* let there be speed */
1389 printk(KERN_INFO PFX "MTRR set to ON\n");
1390 }
1391 }
1392#endif /* CONFIG_MTRR */
1393
1394 info->fbops = &nvidia_fb_ops;
1395 info->fix = nvidiafb_fix;
1396
1397 if (nvidia_set_fbinfo(info) < 0) {
1398 printk(KERN_ERR PFX "error setting initial video mode\n");
1399 goto err_out_iounmap_fb;
1400 }
1401
1402 nvidia_save_vga(par, &par->SavedReg);
1403
1404 pci_set_drvdata(pd, info);
1405
1406 if (backlight)
1407 nvidia_bl_init(par);
1408
1409 if (register_framebuffer(info) < 0) {
1410 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1411 goto err_out_iounmap_fb;
1412 }
1413
1414
1415 printk(KERN_INFO PFX
1416 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1417 info->fix.id,
1418 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1419
1420 NVTRACE_LEAVE();
1421 return 0;
1422
1423err_out_iounmap_fb:
1424 iounmap(info->screen_base);
1425err_out_free_base1:
1426 fb_destroy_modedb(info->monspecs.modedb);
1427 nvidia_delete_i2c_busses(par);
1428err_out_arch:
1429 iounmap(par->REGS);
1430 err_out_free_base0:
1431 pci_release_regions(pd);
1432err_out_enable:
1433 kfree(info->pixmap.addr);
1434err_out_kfree:
1435 framebuffer_release(info);
1436err_out:
1437 return -ENODEV;
1438}
1439
1440static void nvidiafb_remove(struct pci_dev *pd)
1441{
1442 struct fb_info *info = pci_get_drvdata(pd);
1443 struct nvidia_par *par = info->par;
1444
1445 NVTRACE_ENTER();
1446
1447 unregister_framebuffer(info);
1448
1449 nvidia_bl_exit(par);
1450
1451#ifdef CONFIG_MTRR
1452 if (par->mtrr.vram_valid)
1453 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1454 info->fix.smem_len);
1455#endif /* CONFIG_MTRR */
1456
1457 iounmap(info->screen_base);
1458 fb_destroy_modedb(info->monspecs.modedb);
1459 nvidia_delete_i2c_busses(par);
1460 iounmap(par->REGS);
1461 pci_release_regions(pd);
1462 kfree(info->pixmap.addr);
1463 framebuffer_release(info);
1464 NVTRACE_LEAVE();
1465}
1466
1467/* ------------------------------------------------------------------------- *
1468 *
1469 * initialization
1470 *
1471 * ------------------------------------------------------------------------- */
1472
1473#ifndef MODULE
1474static int nvidiafb_setup(char *options)
1475{
1476 char *this_opt;
1477
1478 NVTRACE_ENTER();
1479 if (!options || !*options)
1480 return 0;
1481
1482 while ((this_opt = strsep(&options, ",")) != NULL) {
1483 if (!strncmp(this_opt, "forceCRTC", 9)) {
1484 char *p;
1485
1486 p = this_opt + 9;
1487 if (!*p || !*(++p))
1488 continue;
1489 forceCRTC = *p - '0';
1490 if (forceCRTC < 0 || forceCRTC > 1)
1491 forceCRTC = -1;
1492 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1493 flatpanel = 1;
1494 } else if (!strncmp(this_opt, "hwcur", 5)) {
1495 hwcur = 1;
1496 } else if (!strncmp(this_opt, "noaccel", 6)) {
1497 noaccel = 1;
1498 } else if (!strncmp(this_opt, "noscale", 7)) {
1499 noscale = 1;
1500 } else if (!strncmp(this_opt, "reverse_i2c", 11)) {
1501 reverse_i2c = 1;
1502 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1503 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1504 } else if (!strncmp(this_opt, "vram:", 5)) {
1505 vram = simple_strtoul(this_opt+5, NULL, 0);
1506 } else if (!strncmp(this_opt, "backlight:", 10)) {
1507 backlight = simple_strtoul(this_opt+10, NULL, 0);
1508#ifdef CONFIG_MTRR
1509 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1510 nomtrr = true;
1511#endif
1512 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1513 fpdither = simple_strtol(this_opt+9, NULL, 0);
1514 } else if (!strncmp(this_opt, "bpp:", 4)) {
1515 bpp = simple_strtoul(this_opt+4, NULL, 0);
1516 } else
1517 mode_option = this_opt;
1518 }
1519 NVTRACE_LEAVE();
1520 return 0;
1521}
1522#endif /* !MODULE */
1523
1524static struct pci_driver nvidiafb_driver = {
1525 .name = "nvidiafb",
1526 .id_table = nvidiafb_pci_tbl,
1527 .probe = nvidiafb_probe,
1528 .suspend = nvidiafb_suspend,
1529 .resume = nvidiafb_resume,
1530 .remove = nvidiafb_remove,
1531};
1532
1533/* ------------------------------------------------------------------------- *
1534 *
1535 * modularization
1536 *
1537 * ------------------------------------------------------------------------- */
1538
1539static int nvidiafb_init(void)
1540{
1541#ifndef MODULE
1542 char *option = NULL;
1543
1544 if (fb_get_options("nvidiafb", &option))
1545 return -ENODEV;
1546 nvidiafb_setup(option);
1547#endif
1548 return pci_register_driver(&nvidiafb_driver);
1549}
1550
1551module_init(nvidiafb_init);
1552
1553static void __exit nvidiafb_exit(void)
1554{
1555 pci_unregister_driver(&nvidiafb_driver);
1556}
1557
1558module_exit(nvidiafb_exit);
1559
1560module_param(flatpanel, int, 0);
1561MODULE_PARM_DESC(flatpanel,
1562 "Enables experimental flat panel support for some chipsets. "
1563 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1564module_param(fpdither, int, 0);
1565MODULE_PARM_DESC(fpdither,
1566 "Enables dithering of flat panel for 6 bits panels. "
1567 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1568module_param(hwcur, int, 0);
1569MODULE_PARM_DESC(hwcur,
1570 "Enables hardware cursor implementation. (0 or 1=enabled) "
1571 "(default=0)");
1572module_param(noaccel, int, 0);
1573MODULE_PARM_DESC(noaccel,
1574 "Disables hardware acceleration. (0 or 1=disable) "
1575 "(default=0)");
1576module_param(noscale, int, 0);
1577MODULE_PARM_DESC(noscale,
1578 "Disables screen scaleing. (0 or 1=disable) "
1579 "(default=0, do scaling)");
1580module_param(paneltweak, int, 0);
1581MODULE_PARM_DESC(paneltweak,
1582 "Tweak display settings for flatpanels. "
1583 "(default=0, no tweaks)");
1584module_param(forceCRTC, int, 0);
1585MODULE_PARM_DESC(forceCRTC,
1586 "Forces usage of a particular CRTC in case autodetection "
1587 "fails. (0 or 1) (default=autodetect)");
1588module_param(vram, int, 0);
1589MODULE_PARM_DESC(vram,
1590 "amount of framebuffer memory to remap in MiB"
1591 "(default=0 - remap entire memory)");
1592module_param(mode_option, charp, 0);
1593MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1594module_param(bpp, int, 0);
1595MODULE_PARM_DESC(bpp, "pixel width in bits"
1596 "(default=8)");
1597module_param(reverse_i2c, int, 0);
1598MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus");
1599#ifdef CONFIG_MTRR
1600module_param(nomtrr, bool, false);
1601MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1602 "(default=0)");
1603#endif
1604
1605MODULE_AUTHOR("Antonino Daplas");
1606MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1607MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 22:12:43 -0400