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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-11 21:21:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-11 21:21:02 -0400
commit5f76945a9c978b8b8bf8eb7fe3b17b9981240a97 (patch)
treedf61aca168df657bc71ce8b578bcb0c81b0622ee /drivers/video/exynos
parent940e3a8dd6683a3787faf769b3df7a06f1c2fa31 (diff)
parentcd9d6f10d07f26dd8a70e519c22b6b4f8a9e3e7a (diff)
Merge tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6
Pull fbdev updates from Florian Tobias Schandinat: "This includes: - large updates for OMAP - basic OMAP5 DSS support for DPI and DSI outputs - large cleanups and restructuring - some update to Exynos and da8xx-fb - removal of the pnx4008 driver (arch removed) - various other small patches" Fix up some trivial conflicts (mostly just include line changes, but also some due to the renaming of the deferred work functions by Tejun). * tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6: (193 commits) gbefb: fix compile error video: mark nuc900fb_map_video_memory as __devinit video/mx3fb: set .owner to prevent module unloading while being used video: exynos_dp: use clk_prepare_enable and clk_disable_unprepare drivers/video/exynos/exynos_mipi_dsi.c: fix error return code drivers/video/savage/savagefb_driver.c: fix error return code video: s3c-fb: use clk_prepare_enable and clk_disable_unprepare da8xx-fb: save and restore LCDC context across suspend/resume cycle da8xx-fb: add pm_runtime support video/udlfb: fix line counting in fb_write OMAPDSS: add missing include for string.h OMAPDSS: DISPC: Configure color conversion coefficients for writeback OMAPDSS: DISPC: Add manager like functions for writeback OMAPDSS: DISPC: Configure writeback FIFOs OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup OMAPDSS: DISPC: Add function to set channel in for writeback OMAPDSS: DISPC: Don't set chroma resampling bit for writeback OMAPDSS: DISPC: Downscale chroma if plane is writeback OMAPDSS: DISPC: Configure input and output sizes for writeback ...
Diffstat (limited to 'drivers/video/exynos')
-rw-r--r--drivers/video/exynos/exynos_dp_core.c322
-rw-r--r--drivers/video/exynos/exynos_dp_core.h6
-rw-r--r--drivers/video/exynos/exynos_dp_reg.c58
-rw-r--r--drivers/video/exynos/exynos_dp_reg.h3
-rw-r--r--drivers/video/exynos/exynos_mipi_dsi.c9
-rw-r--r--drivers/video/exynos/exynos_mipi_dsi_common.c8
6 files changed, 208 insertions, 198 deletions
diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c
index c6c016a506ce..d55470e75412 100644
--- a/drivers/video/exynos/exynos_dp_core.c
+++ b/drivers/video/exynos/exynos_dp_core.c
@@ -29,6 +29,9 @@ static int exynos_dp_init_dp(struct exynos_dp_device *dp)
29 29
30 exynos_dp_swreset(dp); 30 exynos_dp_swreset(dp);
31 31
32 exynos_dp_init_analog_param(dp);
33 exynos_dp_init_interrupt(dp);
34
32 /* SW defined function Normal operation */ 35 /* SW defined function Normal operation */
33 exynos_dp_enable_sw_function(dp); 36 exynos_dp_enable_sw_function(dp);
34 37
@@ -260,7 +263,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
260 263
261static void exynos_dp_link_start(struct exynos_dp_device *dp) 264static void exynos_dp_link_start(struct exynos_dp_device *dp)
262{ 265{
263 u8 buf[5]; 266 u8 buf[4];
264 int lane; 267 int lane;
265 int lane_count; 268 int lane_count;
266 269
@@ -295,10 +298,10 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
295 exynos_dp_set_training_pattern(dp, TRAINING_PTN1); 298 exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
296 299
297 /* Set RX training pattern */ 300 /* Set RX training pattern */
298 buf[0] = DPCD_SCRAMBLING_DISABLED |
299 DPCD_TRAINING_PATTERN_1;
300 exynos_dp_write_byte_to_dpcd(dp, 301 exynos_dp_write_byte_to_dpcd(dp,
301 DPCD_ADDR_TRAINING_PATTERN_SET, buf[0]); 302 DPCD_ADDR_TRAINING_PATTERN_SET,
303 DPCD_SCRAMBLING_DISABLED |
304 DPCD_TRAINING_PATTERN_1);
302 305
303 for (lane = 0; lane < lane_count; lane++) 306 for (lane = 0; lane < lane_count; lane++)
304 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 | 307 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
@@ -308,7 +311,7 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
308 lane_count, buf); 311 lane_count, buf);
309} 312}
310 313
311static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane) 314static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
312{ 315{
313 int shift = (lane & 1) * 4; 316 int shift = (lane & 1) * 4;
314 u8 link_value = link_status[lane>>1]; 317 u8 link_value = link_status[lane>>1];
@@ -316,7 +319,7 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
316 return (link_value >> shift) & 0xf; 319 return (link_value >> shift) & 0xf;
317} 320}
318 321
319static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count) 322static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
320{ 323{
321 int lane; 324 int lane;
322 u8 lane_status; 325 u8 lane_status;
@@ -329,22 +332,23 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
329 return 0; 332 return 0;
330} 333}
331 334
332static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count) 335static int exynos_dp_channel_eq_ok(u8 link_align[3], int lane_count)
333{ 336{
334 int lane; 337 int lane;
335 u8 lane_align; 338 u8 lane_align;
336 u8 lane_status; 339 u8 lane_status;
337 340
338 lane_align = link_status[2]; 341 lane_align = link_align[2];
339 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0) 342 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
340 return -EINVAL; 343 return -EINVAL;
341 344
342 for (lane = 0; lane < lane_count; lane++) { 345 for (lane = 0; lane < lane_count; lane++) {
343 lane_status = exynos_dp_get_lane_status(link_status, lane); 346 lane_status = exynos_dp_get_lane_status(link_align, lane);
344 lane_status &= DPCD_CHANNEL_EQ_BITS; 347 lane_status &= DPCD_CHANNEL_EQ_BITS;
345 if (lane_status != DPCD_CHANNEL_EQ_BITS) 348 if (lane_status != DPCD_CHANNEL_EQ_BITS)
346 return -EINVAL; 349 return -EINVAL;
347 } 350 }
351
348 return 0; 352 return 0;
349} 353}
350 354
@@ -417,69 +421,17 @@ static unsigned int exynos_dp_get_lane_link_training(
417 421
418static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp) 422static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
419{ 423{
420 if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) { 424 exynos_dp_training_pattern_dis(dp);
421 /* set to reduced bit rate */ 425 exynos_dp_set_enhanced_mode(dp);
422 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
423 dev_err(dp->dev, "set to bandwidth %.2x\n",
424 dp->link_train.link_rate);
425 dp->link_train.lt_state = START;
426 } else {
427 exynos_dp_training_pattern_dis(dp);
428 /* set enhanced mode if available */
429 exynos_dp_set_enhanced_mode(dp);
430 dp->link_train.lt_state = FAILED;
431 }
432}
433 426
434static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp, 427 dp->link_train.lt_state = FAILED;
435 u8 adjust_request[2])
436{
437 int lane;
438 int lane_count;
439 u8 voltage_swing;
440 u8 pre_emphasis;
441 u8 training_lane;
442
443 lane_count = dp->link_train.lane_count;
444 for (lane = 0; lane < lane_count; lane++) {
445 voltage_swing = exynos_dp_get_adjust_request_voltage(
446 adjust_request, lane);
447 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
448 adjust_request, lane);
449 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
450 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
451
452 if (voltage_swing == VOLTAGE_LEVEL_3 ||
453 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
454 training_lane |= DPCD_MAX_SWING_REACHED;
455 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
456 }
457 dp->link_train.training_lane[lane] = training_lane;
458 }
459}
460
461static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
462 u8 voltage_swing)
463{
464 int lane;
465 int lane_count;
466
467 lane_count = dp->link_train.lane_count;
468 for (lane = 0; lane < lane_count; lane++) {
469 if (voltage_swing == VOLTAGE_LEVEL_3 ||
470 dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
471 return -EINVAL;
472 }
473 return 0;
474} 428}
475 429
476static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) 430static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
477{ 431{
478 u8 data; 432 u8 link_status[2];
479 u8 link_status[6];
480 int lane; 433 int lane;
481 int lane_count; 434 int lane_count;
482 u8 buf[5];
483 435
484 u8 adjust_request[2]; 436 u8 adjust_request[2];
485 u8 voltage_swing; 437 u8 voltage_swing;
@@ -488,100 +440,154 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
488 440
489 usleep_range(100, 101); 441 usleep_range(100, 101);
490 442
491 exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
492 6, link_status);
493 lane_count = dp->link_train.lane_count; 443 lane_count = dp->link_train.lane_count;
494 444
445 exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
446 2, link_status);
447
495 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { 448 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
496 /* set training pattern 2 for EQ */ 449 /* set training pattern 2 for EQ */
497 exynos_dp_set_training_pattern(dp, TRAINING_PTN2); 450 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
498 451
499 adjust_request[0] = link_status[4]; 452 for (lane = 0; lane < lane_count; lane++) {
500 adjust_request[1] = link_status[5]; 453 exynos_dp_read_bytes_from_dpcd(dp,
454 DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
455 2, adjust_request);
456 voltage_swing = exynos_dp_get_adjust_request_voltage(
457 adjust_request, lane);
458 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
459 adjust_request, lane);
460 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
461 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
501 462
502 exynos_dp_get_adjust_train(dp, adjust_request); 463 if (voltage_swing == VOLTAGE_LEVEL_3)
464 training_lane |= DPCD_MAX_SWING_REACHED;
465 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
466 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
503 467
504 buf[0] = DPCD_SCRAMBLING_DISABLED | 468 dp->link_train.training_lane[lane] = training_lane;
505 DPCD_TRAINING_PATTERN_2;
506 exynos_dp_write_byte_to_dpcd(dp,
507 DPCD_ADDR_TRAINING_PATTERN_SET,
508 buf[0]);
509 469
510 for (lane = 0; lane < lane_count; lane++) {
511 exynos_dp_set_lane_link_training(dp, 470 exynos_dp_set_lane_link_training(dp,
512 dp->link_train.training_lane[lane], 471 dp->link_train.training_lane[lane],
513 lane); 472 lane);
514 buf[lane] = dp->link_train.training_lane[lane];
515 exynos_dp_write_byte_to_dpcd(dp,
516 DPCD_ADDR_TRAINING_LANE0_SET + lane,
517 buf[lane]);
518 } 473 }
519 dp->link_train.lt_state = EQUALIZER_TRAINING;
520 } else {
521 exynos_dp_read_byte_from_dpcd(dp,
522 DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
523 &data);
524 adjust_request[0] = data;
525 474
526 exynos_dp_read_byte_from_dpcd(dp, 475 exynos_dp_write_byte_to_dpcd(dp,
527 DPCD_ADDR_ADJUST_REQUEST_LANE2_3, 476 DPCD_ADDR_TRAINING_PATTERN_SET,
528 &data); 477 DPCD_SCRAMBLING_DISABLED |
529 adjust_request[1] = data; 478 DPCD_TRAINING_PATTERN_2);
479
480 exynos_dp_write_bytes_to_dpcd(dp,
481 DPCD_ADDR_TRAINING_LANE0_SET,
482 lane_count,
483 dp->link_train.training_lane);
530 484
485 dev_info(dp->dev, "Link Training Clock Recovery success\n");
486 dp->link_train.lt_state = EQUALIZER_TRAINING;
487 } else {
531 for (lane = 0; lane < lane_count; lane++) { 488 for (lane = 0; lane < lane_count; lane++) {
532 training_lane = exynos_dp_get_lane_link_training( 489 training_lane = exynos_dp_get_lane_link_training(
533 dp, lane); 490 dp, lane);
491 exynos_dp_read_bytes_from_dpcd(dp,
492 DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
493 2, adjust_request);
534 voltage_swing = exynos_dp_get_adjust_request_voltage( 494 voltage_swing = exynos_dp_get_adjust_request_voltage(
535 adjust_request, lane); 495 adjust_request, lane);
536 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( 496 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
537 adjust_request, lane); 497 adjust_request, lane);
538 if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
539 (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
540 dp->link_train.cr_loop[lane]++;
541 dp->link_train.training_lane[lane] = training_lane;
542 }
543 498
544 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) { 499 if (voltage_swing == VOLTAGE_LEVEL_3 ||
545 exynos_dp_reduce_link_rate(dp); 500 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
546 } else { 501 dev_err(dp->dev, "voltage or pre emphasis reached max level\n");
547 exynos_dp_get_adjust_train(dp, adjust_request); 502 goto reduce_link_rate;
503 }
548 504
549 for (lane = 0; lane < lane_count; lane++) { 505 if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
550 exynos_dp_set_lane_link_training(dp, 506 voltage_swing) &&
551 dp->link_train.training_lane[lane], 507 (DPCD_PRE_EMPHASIS_GET(training_lane) ==
552 lane); 508 pre_emphasis)) {
553 buf[lane] = dp->link_train.training_lane[lane]; 509 dp->link_train.cr_loop[lane]++;
554 exynos_dp_write_byte_to_dpcd(dp, 510 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
555 DPCD_ADDR_TRAINING_LANE0_SET + lane, 511 dev_err(dp->dev, "CR Max loop\n");
556 buf[lane]); 512 goto reduce_link_rate;
513 }
557 } 514 }
515
516 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
517 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
518
519 if (voltage_swing == VOLTAGE_LEVEL_3)
520 training_lane |= DPCD_MAX_SWING_REACHED;
521 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
522 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
523
524 dp->link_train.training_lane[lane] = training_lane;
525
526 exynos_dp_set_lane_link_training(dp,
527 dp->link_train.training_lane[lane], lane);
558 } 528 }
529
530 exynos_dp_write_bytes_to_dpcd(dp,
531 DPCD_ADDR_TRAINING_LANE0_SET,
532 lane_count,
533 dp->link_train.training_lane);
559 } 534 }
560 535
561 return 0; 536 return 0;
537
538reduce_link_rate:
539 exynos_dp_reduce_link_rate(dp);
540 return -EIO;
562} 541}
563 542
564static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) 543static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
565{ 544{
566 u8 link_status[6]; 545 u8 link_status[2];
546 u8 link_align[3];
567 int lane; 547 int lane;
568 int lane_count; 548 int lane_count;
569 u8 buf[5];
570 u32 reg; 549 u32 reg;
571 550
572 u8 adjust_request[2]; 551 u8 adjust_request[2];
552 u8 voltage_swing;
553 u8 pre_emphasis;
554 u8 training_lane;
573 555
574 usleep_range(400, 401); 556 usleep_range(400, 401);
575 557
576 exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
577 6, link_status);
578 lane_count = dp->link_train.lane_count; 558 lane_count = dp->link_train.lane_count;
579 559
560 exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
561 2, link_status);
562
580 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { 563 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
581 adjust_request[0] = link_status[4]; 564 link_align[0] = link_status[0];
582 adjust_request[1] = link_status[5]; 565 link_align[1] = link_status[1];
583 566
584 if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) { 567 exynos_dp_read_byte_from_dpcd(dp,
568 DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED,
569 &link_align[2]);
570
571 for (lane = 0; lane < lane_count; lane++) {
572 exynos_dp_read_bytes_from_dpcd(dp,
573 DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
574 2, adjust_request);
575 voltage_swing = exynos_dp_get_adjust_request_voltage(
576 adjust_request, lane);
577 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
578 adjust_request, lane);
579 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
580 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
581
582 if (voltage_swing == VOLTAGE_LEVEL_3)
583 training_lane |= DPCD_MAX_SWING_REACHED;
584 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
585 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
586
587 dp->link_train.training_lane[lane] = training_lane;
588 }
589
590 if (exynos_dp_channel_eq_ok(link_align, lane_count) == 0) {
585 /* traing pattern Set to Normal */ 591 /* traing pattern Set to Normal */
586 exynos_dp_training_pattern_dis(dp); 592 exynos_dp_training_pattern_dis(dp);
587 593
@@ -596,39 +602,42 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
596 dp->link_train.lane_count = reg; 602 dp->link_train.lane_count = reg;
597 dev_dbg(dp->dev, "final lane count = %.2x\n", 603 dev_dbg(dp->dev, "final lane count = %.2x\n",
598 dp->link_train.lane_count); 604 dp->link_train.lane_count);
605
599 /* set enhanced mode if available */ 606 /* set enhanced mode if available */
600 exynos_dp_set_enhanced_mode(dp); 607 exynos_dp_set_enhanced_mode(dp);
601
602 dp->link_train.lt_state = FINISHED; 608 dp->link_train.lt_state = FINISHED;
603 } else { 609 } else {
604 /* not all locked */ 610 /* not all locked */
605 dp->link_train.eq_loop++; 611 dp->link_train.eq_loop++;
606 612
607 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 613 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
608 exynos_dp_reduce_link_rate(dp); 614 dev_err(dp->dev, "EQ Max loop\n");
609 } else { 615 goto reduce_link_rate;
610 exynos_dp_get_adjust_train(dp, adjust_request);
611
612 for (lane = 0; lane < lane_count; lane++) {
613 exynos_dp_set_lane_link_training(dp,
614 dp->link_train.training_lane[lane],
615 lane);
616 buf[lane] = dp->link_train.training_lane[lane];
617 exynos_dp_write_byte_to_dpcd(dp,
618 DPCD_ADDR_TRAINING_LANE0_SET + lane,
619 buf[lane]);
620 }
621 } 616 }
617
618 for (lane = 0; lane < lane_count; lane++)
619 exynos_dp_set_lane_link_training(dp,
620 dp->link_train.training_lane[lane],
621 lane);
622
623 exynos_dp_write_bytes_to_dpcd(dp,
624 DPCD_ADDR_TRAINING_LANE0_SET,
625 lane_count,
626 dp->link_train.training_lane);
622 } 627 }
623 } else { 628 } else {
624 exynos_dp_reduce_link_rate(dp); 629 goto reduce_link_rate;
625 } 630 }
626 631
627 return 0; 632 return 0;
633
634reduce_link_rate:
635 exynos_dp_reduce_link_rate(dp);
636 return -EIO;
628} 637}
629 638
630static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp, 639static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
631 u8 *bandwidth) 640 u8 *bandwidth)
632{ 641{
633 u8 data; 642 u8 data;
634 643
@@ -641,7 +650,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
641} 650}
642 651
643static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, 652static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
644 u8 *lane_count) 653 u8 *lane_count)
645{ 654{
646 u8 data; 655 u8 data;
647 656
@@ -693,13 +702,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
693static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) 702static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
694{ 703{
695 int retval = 0; 704 int retval = 0;
696 int training_finished; 705 int training_finished = 0;
697
698 /* Turn off unnecessary lane */
699 if (dp->link_train.lane_count == 1)
700 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
701
702 training_finished = 0;
703 706
704 dp->link_train.lt_state = START; 707 dp->link_train.lt_state = START;
705 708
@@ -710,10 +713,14 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
710 exynos_dp_link_start(dp); 713 exynos_dp_link_start(dp);
711 break; 714 break;
712 case CLOCK_RECOVERY: 715 case CLOCK_RECOVERY:
713 exynos_dp_process_clock_recovery(dp); 716 retval = exynos_dp_process_clock_recovery(dp);
717 if (retval)
718 dev_err(dp->dev, "LT CR failed!\n");
714 break; 719 break;
715 case EQUALIZER_TRAINING: 720 case EQUALIZER_TRAINING:
716 exynos_dp_process_equalizer_training(dp); 721 retval = exynos_dp_process_equalizer_training(dp);
722 if (retval)
723 dev_err(dp->dev, "LT EQ failed!\n");
717 break; 724 break;
718 case FINISHED: 725 case FINISHED:
719 training_finished = 1; 726 training_finished = 1;
@@ -872,40 +879,33 @@ static int __devinit exynos_dp_probe(struct platform_device *pdev)
872 879
873 dp->dev = &pdev->dev; 880 dp->dev = &pdev->dev;
874 881
875 dp->clock = clk_get(&pdev->dev, "dp"); 882 dp->clock = devm_clk_get(&pdev->dev, "dp");
876 if (IS_ERR(dp->clock)) { 883 if (IS_ERR(dp->clock)) {
877 dev_err(&pdev->dev, "failed to get clock\n"); 884 dev_err(&pdev->dev, "failed to get clock\n");
878 return PTR_ERR(dp->clock); 885 return PTR_ERR(dp->clock);
879 } 886 }
880 887
881 clk_enable(dp->clock); 888 clk_prepare_enable(dp->clock);
882 889
883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 890 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
884 if (!res) {
885 dev_err(&pdev->dev, "failed to get registers\n");
886 ret = -EINVAL;
887 goto err_clock;
888 }
889 891
890 dp->reg_base = devm_request_and_ioremap(&pdev->dev, res); 892 dp->reg_base = devm_request_and_ioremap(&pdev->dev, res);
891 if (!dp->reg_base) { 893 if (!dp->reg_base) {
892 dev_err(&pdev->dev, "failed to ioremap\n"); 894 dev_err(&pdev->dev, "failed to ioremap\n");
893 ret = -ENOMEM; 895 return -ENOMEM;
894 goto err_clock;
895 } 896 }
896 897
897 dp->irq = platform_get_irq(pdev, 0); 898 dp->irq = platform_get_irq(pdev, 0);
898 if (!dp->irq) { 899 if (!dp->irq) {
899 dev_err(&pdev->dev, "failed to get irq\n"); 900 dev_err(&pdev->dev, "failed to get irq\n");
900 ret = -ENODEV; 901 return -ENODEV;
901 goto err_clock;
902 } 902 }
903 903
904 ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0, 904 ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0,
905 "exynos-dp", dp); 905 "exynos-dp", dp);
906 if (ret) { 906 if (ret) {
907 dev_err(&pdev->dev, "failed to request irq\n"); 907 dev_err(&pdev->dev, "failed to request irq\n");
908 goto err_clock; 908 return ret;
909 } 909 }
910 910
911 dp->video_info = pdata->video_info; 911 dp->video_info = pdata->video_info;
@@ -917,7 +917,7 @@ static int __devinit exynos_dp_probe(struct platform_device *pdev)
917 ret = exynos_dp_detect_hpd(dp); 917 ret = exynos_dp_detect_hpd(dp);
918 if (ret) { 918 if (ret) {
919 dev_err(&pdev->dev, "unable to detect hpd\n"); 919 dev_err(&pdev->dev, "unable to detect hpd\n");
920 goto err_clock; 920 return ret;
921 } 921 }
922 922
923 exynos_dp_handle_edid(dp); 923 exynos_dp_handle_edid(dp);
@@ -926,7 +926,7 @@ static int __devinit exynos_dp_probe(struct platform_device *pdev)
926 dp->video_info->link_rate); 926 dp->video_info->link_rate);
927 if (ret) { 927 if (ret) {
928 dev_err(&pdev->dev, "unable to do link train\n"); 928 dev_err(&pdev->dev, "unable to do link train\n");
929 goto err_clock; 929 return ret;
930 } 930 }
931 931
932 exynos_dp_enable_scramble(dp, 1); 932 exynos_dp_enable_scramble(dp, 1);
@@ -940,17 +940,12 @@ static int __devinit exynos_dp_probe(struct platform_device *pdev)
940 ret = exynos_dp_config_video(dp, dp->video_info); 940 ret = exynos_dp_config_video(dp, dp->video_info);
941 if (ret) { 941 if (ret) {
942 dev_err(&pdev->dev, "unable to config video\n"); 942 dev_err(&pdev->dev, "unable to config video\n");
943 goto err_clock; 943 return ret;
944 } 944 }
945 945
946 platform_set_drvdata(pdev, dp); 946 platform_set_drvdata(pdev, dp);
947 947
948 return 0; 948 return 0;
949
950err_clock:
951 clk_put(dp->clock);
952
953 return ret;
954} 949}
955 950
956static int __devexit exynos_dp_remove(struct platform_device *pdev) 951static int __devexit exynos_dp_remove(struct platform_device *pdev)
@@ -961,8 +956,7 @@ static int __devexit exynos_dp_remove(struct platform_device *pdev)
961 if (pdata && pdata->phy_exit) 956 if (pdata && pdata->phy_exit)
962 pdata->phy_exit(); 957 pdata->phy_exit();
963 958
964 clk_disable(dp->clock); 959 clk_disable_unprepare(dp->clock);
965 clk_put(dp->clock);
966 960
967 return 0; 961 return 0;
968} 962}
@@ -977,7 +971,7 @@ static int exynos_dp_suspend(struct device *dev)
977 if (pdata && pdata->phy_exit) 971 if (pdata && pdata->phy_exit)
978 pdata->phy_exit(); 972 pdata->phy_exit();
979 973
980 clk_disable(dp->clock); 974 clk_disable_unprepare(dp->clock);
981 975
982 return 0; 976 return 0;
983} 977}
@@ -991,7 +985,7 @@ static int exynos_dp_resume(struct device *dev)
991 if (pdata && pdata->phy_init) 985 if (pdata && pdata->phy_init)
992 pdata->phy_init(); 986 pdata->phy_init();
993 987
994 clk_enable(dp->clock); 988 clk_prepare_enable(dp->clock);
995 989
996 exynos_dp_init_dp(dp); 990 exynos_dp_init_dp(dp);
997 991
diff --git a/drivers/video/exynos/exynos_dp_core.h b/drivers/video/exynos/exynos_dp_core.h
index 8526e548c385..57b8a6531c0e 100644
--- a/drivers/video/exynos/exynos_dp_core.h
+++ b/drivers/video/exynos/exynos_dp_core.h
@@ -43,7 +43,7 @@ void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
43void exynos_dp_reset(struct exynos_dp_device *dp); 43void exynos_dp_reset(struct exynos_dp_device *dp);
44void exynos_dp_swreset(struct exynos_dp_device *dp); 44void exynos_dp_swreset(struct exynos_dp_device *dp);
45void exynos_dp_config_interrupt(struct exynos_dp_device *dp); 45void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
46u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp); 46enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
47void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable); 47void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
48void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp, 48void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
49 enum analog_power_block block, 49 enum analog_power_block block,
@@ -105,7 +105,7 @@ u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
105u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp); 105u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
106u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp); 106u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
107void exynos_dp_reset_macro(struct exynos_dp_device *dp); 107void exynos_dp_reset_macro(struct exynos_dp_device *dp);
108int exynos_dp_init_video(struct exynos_dp_device *dp); 108void exynos_dp_init_video(struct exynos_dp_device *dp);
109 109
110void exynos_dp_set_video_color_format(struct exynos_dp_device *dp, 110void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
111 u32 color_depth, 111 u32 color_depth,
@@ -144,7 +144,7 @@ void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
144#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102 144#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
145#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103 145#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
146#define DPCD_ADDR_LANE0_1_STATUS 0x0202 146#define DPCD_ADDR_LANE0_1_STATUS 0x0202
147#define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204 147#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
148#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206 148#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
149#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207 149#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
150#define DPCD_ADDR_TEST_REQUEST 0x0218 150#define DPCD_ADDR_TEST_REQUEST 0x0218
diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c
index 2db5b9aa250a..3f5ca8a0d5ea 100644
--- a/drivers/video/exynos/exynos_dp_reg.c
+++ b/drivers/video/exynos/exynos_dp_reg.c
@@ -77,7 +77,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); 77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
78 78
79 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 79 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
80 TX_CUR1_2X | TX_CUR_8_MA; 80 TX_CUR1_2X | TX_CUR_16_MA;
81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); 81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
82 82
83 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 83 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
@@ -148,9 +148,6 @@ void exynos_dp_reset(struct exynos_dp_device *dp)
148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH); 148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
149 149
150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); 150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
151
152 exynos_dp_init_analog_param(dp);
153 exynos_dp_init_interrupt(dp);
154} 151}
155 152
156void exynos_dp_swreset(struct exynos_dp_device *dp) 153void exynos_dp_swreset(struct exynos_dp_device *dp)
@@ -179,7 +176,7 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
179 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); 176 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
180} 177}
181 178
182u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp) 179enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
183{ 180{
184 u32 reg; 181 u32 reg;
185 182
@@ -401,6 +398,7 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
401{ 398{
402 int reg; 399 int reg;
403 int retval = 0; 400 int retval = 0;
401 int timeout_loop = 0;
404 402
405 /* Enable AUX CH operation */ 403 /* Enable AUX CH operation */
406 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); 404 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
@@ -409,8 +407,15 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
409 407
410 /* Is AUX CH command reply received? */ 408 /* Is AUX CH command reply received? */
411 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); 409 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
412 while (!(reg & RPLY_RECEIV)) 410 while (!(reg & RPLY_RECEIV)) {
411 timeout_loop++;
412 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
413 dev_err(dp->dev, "AUX CH command reply failed!\n");
414 return -ETIMEDOUT;
415 }
413 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); 416 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
417 usleep_range(10, 11);
418 }
414 419
415 /* Clear interrupt source for AUX CH command reply */ 420 /* Clear interrupt source for AUX CH command reply */
416 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA); 421 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
@@ -471,7 +476,8 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
471 if (retval == 0) 476 if (retval == 0)
472 break; 477 break;
473 else 478 else
474 dev_err(dp->dev, "Aux Transaction fail!\n"); 479 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
480 __func__);
475 } 481 }
476 482
477 return retval; 483 return retval;
@@ -511,7 +517,8 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
511 if (retval == 0) 517 if (retval == 0)
512 break; 518 break;
513 else 519 else
514 dev_err(dp->dev, "Aux Transaction fail!\n"); 520 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
521 __func__);
515 } 522 }
516 523
517 /* Read data buffer */ 524 /* Read data buffer */
@@ -575,7 +582,8 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
575 if (retval == 0) 582 if (retval == 0)
576 break; 583 break;
577 else 584 else
578 dev_err(dp->dev, "Aux Transaction fail!\n"); 585 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
586 __func__);
579 } 587 }
580 588
581 start_offset += cur_data_count; 589 start_offset += cur_data_count;
@@ -632,7 +640,8 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
632 if (retval == 0) 640 if (retval == 0)
633 break; 641 break;
634 else 642 else
635 dev_err(dp->dev, "Aux Transaction fail!\n"); 643 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
644 __func__);
636 } 645 }
637 646
638 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 647 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -677,7 +686,7 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
677 /* Start AUX transaction */ 686 /* Start AUX transaction */
678 retval = exynos_dp_start_aux_transaction(dp); 687 retval = exynos_dp_start_aux_transaction(dp);
679 if (retval != 0) 688 if (retval != 0)
680 dev_err(dp->dev, "Aux Transaction fail!\n"); 689 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
681 690
682 return retval; 691 return retval;
683} 692}
@@ -717,7 +726,8 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
717 if (retval == 0) 726 if (retval == 0)
718 break; 727 break;
719 else 728 else
720 dev_err(dp->dev, "Aux Transaction fail!\n"); 729 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
730 __func__);
721 } 731 }
722 732
723 /* Read data */ 733 /* Read data */
@@ -777,7 +787,9 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
777 if (retval == 0) 787 if (retval == 0)
778 break; 788 break;
779 else 789 else
780 dev_err(dp->dev, "Aux Transaction fail!\n"); 790 dev_dbg(dp->dev,
791 "%s: Aux Transaction fail!\n",
792 __func__);
781 } 793 }
782 /* Check if Rx sends defer */ 794 /* Check if Rx sends defer */
783 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM); 795 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
@@ -883,7 +895,9 @@ void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
883{ 895{
884 u32 reg; 896 u32 reg;
885 897
886 reg = level << PRE_EMPHASIS_SET_SHIFT; 898 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
899 reg &= ~PRE_EMPHASIS_SET_MASK;
900 reg |= level << PRE_EMPHASIS_SET_SHIFT;
887 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); 901 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
888} 902}
889 903
@@ -891,7 +905,9 @@ void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
891{ 905{
892 u32 reg; 906 u32 reg;
893 907
894 reg = level << PRE_EMPHASIS_SET_SHIFT; 908 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
909 reg &= ~PRE_EMPHASIS_SET_MASK;
910 reg |= level << PRE_EMPHASIS_SET_SHIFT;
895 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); 911 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
896} 912}
897 913
@@ -899,7 +915,9 @@ void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
899{ 915{
900 u32 reg; 916 u32 reg;
901 917
902 reg = level << PRE_EMPHASIS_SET_SHIFT; 918 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
919 reg &= ~PRE_EMPHASIS_SET_MASK;
920 reg |= level << PRE_EMPHASIS_SET_SHIFT;
903 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); 921 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
904} 922}
905 923
@@ -907,7 +925,9 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
907{ 925{
908 u32 reg; 926 u32 reg;
909 927
910 reg = level << PRE_EMPHASIS_SET_SHIFT; 928 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
929 reg &= ~PRE_EMPHASIS_SET_MASK;
930 reg |= level << PRE_EMPHASIS_SET_SHIFT;
911 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); 931 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
912} 932}
913 933
@@ -994,7 +1014,7 @@ void exynos_dp_reset_macro(struct exynos_dp_device *dp)
994 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); 1014 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
995} 1015}
996 1016
997int exynos_dp_init_video(struct exynos_dp_device *dp) 1017void exynos_dp_init_video(struct exynos_dp_device *dp)
998{ 1018{
999 u32 reg; 1019 u32 reg;
1000 1020
@@ -1012,8 +1032,6 @@ int exynos_dp_init_video(struct exynos_dp_device *dp)
1012 1032
1013 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1033 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1014 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); 1034 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1015
1016 return 0;
1017} 1035}
1018 1036
1019void exynos_dp_set_video_color_format(struct exynos_dp_device *dp, 1037void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h
index 125b27cd57ae..1f2f014cfe88 100644
--- a/drivers/video/exynos/exynos_dp_reg.h
+++ b/drivers/video/exynos/exynos_dp_reg.h
@@ -187,7 +187,7 @@
187#define PD_RING_OSC (0x1 << 6) 187#define PD_RING_OSC (0x1 << 6)
188#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 188#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
189#define TX_CUR1_2X (0x1 << 2) 189#define TX_CUR1_2X (0x1 << 2)
190#define TX_CUR_8_MA (0x2 << 0) 190#define TX_CUR_16_MA (0x3 << 0)
191 191
192/* EXYNOS_DP_TX_AMP_TUNING_CTL */ 192/* EXYNOS_DP_TX_AMP_TUNING_CTL */
193#define CH3_AMP_400_MV (0x0 << 24) 193#define CH3_AMP_400_MV (0x0 << 24)
@@ -285,6 +285,7 @@
285#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 285#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
286 286
287/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ 287/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
288#define PRE_EMPHASIS_SET_MASK (0x3 << 3)
288#define PRE_EMPHASIS_SET_SHIFT (3) 289#define PRE_EMPHASIS_SET_SHIFT (3)
289 290
290/* EXYNOS_DP_DEBUG_CTL */ 291/* EXYNOS_DP_DEBUG_CTL */
diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c
index 663c308d0e73..07d70a3a628b 100644
--- a/drivers/video/exynos/exynos_mipi_dsi.c
+++ b/drivers/video/exynos/exynos_mipi_dsi.c
@@ -205,7 +205,8 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev)
205 return 0; 205 return 0;
206} 206}
207 207
208struct mipi_dsim_ddi *exynos_mipi_dsi_find_lcd_device(struct mipi_dsim_lcd_driver *lcd_drv) 208static struct mipi_dsim_ddi *exynos_mipi_dsi_find_lcd_device(
209 struct mipi_dsim_lcd_driver *lcd_drv)
209{ 210{
210 struct mipi_dsim_ddi *dsim_ddi, *next; 211 struct mipi_dsim_ddi *dsim_ddi, *next;
211 struct mipi_dsim_lcd_device *lcd_dev; 212 struct mipi_dsim_lcd_device *lcd_dev;
@@ -265,7 +266,8 @@ int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv)
265 266
266} 267}
267 268
268struct mipi_dsim_ddi *exynos_mipi_dsi_bind_lcd_ddi(struct mipi_dsim_device *dsim, 269static struct mipi_dsim_ddi *exynos_mipi_dsi_bind_lcd_ddi(
270 struct mipi_dsim_device *dsim,
269 const char *name) 271 const char *name)
270{ 272{
271 struct mipi_dsim_ddi *dsim_ddi, *next; 273 struct mipi_dsim_ddi *dsim_ddi, *next;
@@ -373,6 +375,7 @@ static int exynos_mipi_dsi_probe(struct platform_device *pdev)
373 dsim->clock = clk_get(&pdev->dev, "dsim0"); 375 dsim->clock = clk_get(&pdev->dev, "dsim0");
374 if (IS_ERR(dsim->clock)) { 376 if (IS_ERR(dsim->clock)) {
375 dev_err(&pdev->dev, "failed to get dsim clock source\n"); 377 dev_err(&pdev->dev, "failed to get dsim clock source\n");
378 ret = -ENODEV;
376 goto err_clock_get; 379 goto err_clock_get;
377 } 380 }
378 381
@@ -381,6 +384,7 @@ static int exynos_mipi_dsi_probe(struct platform_device *pdev)
381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 384 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
382 if (!res) { 385 if (!res) {
383 dev_err(&pdev->dev, "failed to get io memory region\n"); 386 dev_err(&pdev->dev, "failed to get io memory region\n");
387 ret = -ENODEV;
384 goto err_platform_get; 388 goto err_platform_get;
385 } 389 }
386 390
@@ -405,6 +409,7 @@ static int exynos_mipi_dsi_probe(struct platform_device *pdev)
405 dsim_ddi = exynos_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name); 409 dsim_ddi = exynos_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name);
406 if (!dsim_ddi) { 410 if (!dsim_ddi) {
407 dev_err(&pdev->dev, "mipi_dsim_ddi object not found.\n"); 411 dev_err(&pdev->dev, "mipi_dsim_ddi object not found.\n");
412 ret = -EINVAL;
408 goto err_bind; 413 goto err_bind;
409 } 414 }
410 415
diff --git a/drivers/video/exynos/exynos_mipi_dsi_common.c b/drivers/video/exynos/exynos_mipi_dsi_common.c
index 47b533a183be..3cd29a4fc10a 100644
--- a/drivers/video/exynos/exynos_mipi_dsi_common.c
+++ b/drivers/video/exynos/exynos_mipi_dsi_common.c
@@ -79,11 +79,6 @@ irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id)
79 struct mipi_dsim_device *dsim = dev_id; 79 struct mipi_dsim_device *dsim = dev_id;
80 unsigned int intsrc, intmsk; 80 unsigned int intsrc, intmsk;
81 81
82 if (dsim == NULL) {
83 dev_err(dsim->dev, "%s: wrong parameter\n", __func__);
84 return IRQ_NONE;
85 }
86
87 intsrc = exynos_mipi_dsi_read_interrupt(dsim); 82 intsrc = exynos_mipi_dsi_read_interrupt(dsim);
88 intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim); 83 intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);
89 intmsk = ~intmsk & intsrc; 84 intmsk = ~intmsk & intsrc;
@@ -288,9 +283,6 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
288 mutex_unlock(&dsim->lock); 283 mutex_unlock(&dsim->lock);
289 return -EINVAL; 284 return -EINVAL;
290 } 285 }
291
292 mutex_unlock(&dsim->lock);
293 return 0;
294} 286}
295 287
296static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim, 288static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 01:20:13 -0500