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authorAjay Kumar <ajaykumar.rs@samsung.com>2012-11-05 02:47:00 -0500
committerJingoo Han <jg1.han@samsung.com>2012-11-28 20:33:28 -0500
commit2f85f97e460a4bcfad678151fcc13dbf0b8181b3 (patch)
tree3a0f87511387925ff9ad5f502f1edfce821d468d /drivers/video/exynos/exynos_dp_reg.h
parent22ce19cb43e2df5b0b17159e94244d1151ea250b (diff)
video: exynos_dp: Fix incorrect setting for INT_CTL
INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL. This patch fixes the wrong register setting for INT_CTL. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Diffstat (limited to 'drivers/video/exynos/exynos_dp_reg.h')
-rw-r--r--drivers/video/exynos/exynos_dp_reg.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h
index 1f2f014cfe88..2e9bd0e0b9f2 100644
--- a/drivers/video/exynos/exynos_dp_reg.h
+++ b/drivers/video/exynos/exynos_dp_reg.h
@@ -242,7 +242,8 @@
242 242
243/* EXYNOS_DP_INT_CTL */ 243/* EXYNOS_DP_INT_CTL */
244#define SOFT_INT_CTRL (0x1 << 2) 244#define SOFT_INT_CTRL (0x1 << 2)
245#define INT_POL (0x1 << 0) 245#define INT_POL1 (0x1 << 1)
246#define INT_POL0 (0x1 << 0)
246 247
247/* EXYNOS_DP_SYS_CTL_1 */ 248/* EXYNOS_DP_SYS_CTL_1 */
248#define DET_STA (0x1 << 2) 249#define DET_STA (0x1 << 2)