radeonfb: misc cleanup of engine and dst cache handling

Fix a couple of incomplete tests of the chip families in the engine
init/reset code and proper initialization of the destination cache mode.
The result should better match what the latest X radeon driver does.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David S. Miller <davem@davemloft.net>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 13 insertions, 9 deletions

diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
index aa95f8350242..a469a3d6edcb 100644
--- a/drivers/video/aty/radeon_accel.c
+++ b/drivers/video/aty/radeon_accel.c
@@ -211,9 +211,7 @@ void radeonfb_engine_reset(struct radeonfb_info *rinfo)
         host_path_cntl = INREG(HOST_PATH_CNTL);
         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
 
-        if (rinfo->family == CHIP_FAMILY_R300 ||
-            rinfo->family == CHIP_FAMILY_R350 ||
-            rinfo->family == CHIP_FAMILY_RV350) {
+        if (IS_R300_VARIANT(rinfo)) {
                 u32 tmp;
 
                 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
@@ -249,9 +247,7 @@ void radeonfb_engine_reset(struct radeonfb_info *rinfo)
         INREG(HOST_PATH_CNTL);
         OUTREG(HOST_PATH_CNTL, host_path_cntl);
 
-        if (rinfo->family != CHIP_FAMILY_R300 &&
-            rinfo->family != CHIP_FAMILY_R350 &&
-            rinfo->family != CHIP_FAMILY_RV350)
+        if (!IS_R300_VARIANT(rinfo))
                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
 
         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
@@ -268,10 +264,18 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
         radeonfb_engine_reset(rinfo);
 
         radeon_fifo_wait (1);
-        if ((rinfo->family != CHIP_FAMILY_R300) &&
-            (rinfo->family != CHIP_FAMILY_R350) &&
-            (rinfo->family != CHIP_FAMILY_RV350))
+        if (IS_R300_VARIANT(rinfo)) {
+                OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) |
+                       RB2D_DC_AUTOFLUSH_ENABLE |
+                       RB2D_DC_DC_DISABLE_IGNORE_PE);
+        } else {
+                /* This needs to be double checked with ATI. Latest X driver
+                 * completely "forgets" to set this register on < r3xx, and
+                 * we used to just write 0 there... I'll keep the 0 and update
+                 * that when we have sorted things out on X side.
+                 */
                 OUTREG(RB2D_DSTCACHE_MODE, 0);
+        }
 
         radeon_fifo_wait (3);
         /* We re-read MC_FB_LOCATION from card as it can have been