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authorMian Yousaf Kaukab <yousaf.kaukab@intel.com>2015-01-30 03:09:35 -0500
committerFelipe Balbi <balbi@ti.com>2015-01-30 11:33:54 -0500
commitfa4a8d722bc2f0b1887ea929874a0f6754eda8b4 (patch)
tree6582579df9dbd6dd855187e219005b4fc03b4362 /drivers/usb
parentccb34a9101b340885b1ca3ec766e8544a6a433a7 (diff)
usb: dwc2: gadget: fix phy interface configuration
hsotg->phyif is set in dwc2_gadget_init according to phy interface width. Use it for configuration instead of hardcoded value. Moreover, set USB turnaround time according to phy width. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/dwc2/gadget.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 38ba0221482e..8c3f8f8f769a 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -2290,8 +2290,9 @@ void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2290 */ 2290 */
2291 2291
2292 /* set the PLL on, remove the HNP/SRP and set the PHY */ 2292 /* set the PLL on, remove the HNP/SRP and set the PHY */
2293 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2293 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | 2294 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2294 (0x5 << 10), hsotg->regs + GUSBCFG); 2295 (val << 10), hsotg->regs + GUSBCFG);
2295 2296
2296 s3c_hsotg_init_fifo(hsotg); 2297 s3c_hsotg_init_fifo(hsotg);
2297 2298
@@ -2978,6 +2979,7 @@ static void s3c_hsotg_phy_disable(struct dwc2_hsotg *hsotg)
2978 */ 2979 */
2979static void s3c_hsotg_init(struct dwc2_hsotg *hsotg) 2980static void s3c_hsotg_init(struct dwc2_hsotg *hsotg)
2980{ 2981{
2982 u32 trdtim;
2981 /* unmask subset of endpoint interrupts */ 2983 /* unmask subset of endpoint interrupts */
2982 2984
2983 writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | 2985 writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
@@ -3002,8 +3004,10 @@ static void s3c_hsotg_init(struct dwc2_hsotg *hsotg)
3002 s3c_hsotg_init_fifo(hsotg); 3004 s3c_hsotg_init_fifo(hsotg);
3003 3005
3004 /* set the PLL on, remove the HNP/SRP and set the PHY */ 3006 /* set the PLL on, remove the HNP/SRP and set the PHY */
3005 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), 3007 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3006 hsotg->regs + GUSBCFG); 3008 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3009 (trdtim << 10),
3010 hsotg->regs + GUSBCFG);
3007 3011
3008 if (using_dma(hsotg)) 3012 if (using_dma(hsotg))
3009 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); 3013 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);