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authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-03 12:11:20 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-03 12:11:20 -0400
commite5c4ecdc55b6d824365ba7964bcd3185223f9688 (patch)
tree405556c9fe703094dd0fc07bc89d9a2fdb5ee525 /drivers/usb/phy
parent49eb7b0750d9483c74e9c14ae6ea1e9d62481c3c (diff)
parent4a95b1fce97756d0333f8232eb7ed6974e93b054 (diff)
Merge tag 'usb-3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb into next
Pull USB driver updates from Greg KH: "Here is the big USB driver pull request for 3.16-rc1. Nothing huge here, but lots of little things in the USB core, and in lots of drivers. Hopefully the USB power management will be work better now that it has been reworked to do per-port power control dynamically. There's also a raft of gadget driver updates and fixes, CONFIG_USB_DEBUG is finally gone now that everything has been converted over to the dynamic debug inteface, the last hold-out drivers were cleaned up and the config option removed. There were also other minor things all through the drivers/usb/ tree, the shortlog shows this pretty well. All have been in linux-next, including the very last patch, which came from linux-next to fix a build issue on some platforms" * tag 'usb-3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (314 commits) usb: hub_handle_remote_wakeup() only exists for CONFIG_PM=y USB: orinoco_usb: remove CONFIG_USB_DEBUG support USB: media: lirc: igorplugusb: remove CONFIG_USB_DEBUG support USB: media: streamzap: remove CONFIG_USB_DEBUG USB: media: redrat3: remove CONFIG_USB_DEBUG usage USB: media: redrat3: remove unneeded tracing macro usb: qcserial: add additional Sierra Wireless QMI devices usb: host: max3421-hcd: Use module_spi_driver usb: host: max3421-hcd: Allow platform-data to specify Vbus polarity usb: host: max3421-hcd: fix "spi_rd8" uses dynamic stack allocation warning usb: host: max3421-hcd: Fix missing unlock in max3421_urb_enqueue() usb: qcserial: add Netgear AirCard 341U Documentation: dt-bindings: update xhci-platform DT binding for R-Car H2 and M2 usb: host: xhci-plat: add xhci_plat_start() usb: host: max3421-hcd: Fix potential NULL urb dereference Revert "usb: gadget: net2280: Add support for PLX USB338X" USB: usbip: remove CONFIG_USB_DEBUG reference USB: remove CONFIG_USB_DEBUG from defconfig files usb: resume child device when port is powered on usb: hub_handle_remote_wakeup() depends on CONFIG_PM_RUNTIME=y ...
Diffstat (limited to 'drivers/usb/phy')
-rw-r--r--drivers/usb/phy/Kconfig27
-rw-r--r--drivers/usb/phy/Makefile2
-rw-r--r--drivers/usb/phy/phy-am335x.c4
-rw-r--r--drivers/usb/phy/phy-fsm-usb.c366
-rw-r--r--drivers/usb/phy/phy-generic.c65
-rw-r--r--drivers/usb/phy/phy-generic.h8
-rw-r--r--drivers/usb/phy/phy-keystone.c4
-rw-r--r--drivers/usb/phy/phy-msm-usb.c702
-rw-r--r--drivers/usb/phy/phy-mv-u3d-usb.c338
-rw-r--r--drivers/usb/phy/phy-mv-u3d-usb.h105
-rw-r--r--drivers/usb/phy/phy-ulpi.c1
11 files changed, 441 insertions, 1181 deletions
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 416e0c8cf6ff..e253fa05be68 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -6,15 +6,6 @@ menu "USB Physical Layer drivers"
6config USB_PHY 6config USB_PHY
7 def_bool n 7 def_bool n
8 8
9config USB_OTG_FSM
10 tristate "USB 2.0 OTG FSM implementation"
11 depends on USB
12 select USB_OTG
13 select USB_PHY
14 help
15 Implements OTG Final State Machine as specified in On-The-Go
16 and Embedded Host Supplement to the USB Revision 2.0 Specification.
17
18# 9#
19# USB Transceiver Drivers 10# USB Transceiver Drivers
20# 11#
@@ -59,14 +50,6 @@ config KEYSTONE_USB_PHY
59 interface to interact with USB 2.0 and USB 3.0 PHY that is part 50 interface to interact with USB 2.0 and USB 3.0 PHY that is part
60 of the Keystone SOC. 51 of the Keystone SOC.
61 52
62config MV_U3D_PHY
63 bool "Marvell USB 3.0 PHY controller Driver"
64 depends on CPU_MMP3
65 select USB_PHY
66 help
67 Enable this to support Marvell USB 3.0 phy controller for Marvell
68 SoC.
69
70config NOP_USB_XCEIV 53config NOP_USB_XCEIV
71 tristate "NOP USB Transceiver Driver" 54 tristate "NOP USB Transceiver Driver"
72 select USB_PHY 55 select USB_PHY
@@ -171,11 +154,12 @@ config USB_ISP1301
171 module will be called phy-isp1301. 154 module will be called phy-isp1301.
172 155
173config USB_MSM_OTG 156config USB_MSM_OTG
174 tristate "OTG support for Qualcomm on-chip USB controller" 157 tristate "Qualcomm on-chip USB OTG controller support"
175 depends on (USB || USB_GADGET) && ARCH_MSM 158 depends on (USB || USB_GADGET) && (ARCH_MSM || ARCH_QCOM || COMPILE_TEST)
159 depends on RESET_CONTROLLER
176 select USB_PHY 160 select USB_PHY
177 help 161 help
178 Enable this to support the USB OTG transceiver on MSM chips. It 162 Enable this to support the USB OTG transceiver on Qualcomm chips. It
179 handles PHY initialization, clock management, and workarounds 163 handles PHY initialization, clock management, and workarounds
180 required after resetting the hardware and power management. 164 required after resetting the hardware and power management.
181 This driver is required even for peripheral only or host only 165 This driver is required even for peripheral only or host only
@@ -208,6 +192,7 @@ config USB_MXS_PHY
208config USB_RCAR_PHY 192config USB_RCAR_PHY
209 tristate "Renesas R-Car USB PHY support" 193 tristate "Renesas R-Car USB PHY support"
210 depends on USB || USB_GADGET 194 depends on USB || USB_GADGET
195 depends on ARCH_R8A7778 || ARCH_R8A7779 || COMPILE_TEST
211 select USB_PHY 196 select USB_PHY
212 help 197 help
213 Say Y here to add support for the Renesas R-Car USB common PHY driver. 198 Say Y here to add support for the Renesas R-Car USB common PHY driver.
@@ -232,7 +217,7 @@ config USB_RCAR_GEN2_PHY
232 217
233config USB_ULPI 218config USB_ULPI
234 bool "Generic ULPI Transceiver Driver" 219 bool "Generic ULPI Transceiver Driver"
235 depends on ARM 220 depends on ARM || ARM64
236 help 221 help
237 Enable this to support ULPI connected USB OTG transceivers which 222 Enable this to support ULPI connected USB OTG transceivers which
238 are likely found on embedded boards. 223 are likely found on embedded boards.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index f8fa719a31b9..24a91332d4ad 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -3,14 +3,12 @@
3# 3#
4obj-$(CONFIG_USB_PHY) += phy.o 4obj-$(CONFIG_USB_PHY) += phy.o
5obj-$(CONFIG_OF) += of.o 5obj-$(CONFIG_OF) += of.o
6obj-$(CONFIG_USB_OTG_FSM) += phy-fsm-usb.o
7 6
8# transceiver drivers, keep the list sorted 7# transceiver drivers, keep the list sorted
9 8
10obj-$(CONFIG_AB8500_USB) += phy-ab8500-usb.o 9obj-$(CONFIG_AB8500_USB) += phy-ab8500-usb.o
11obj-$(CONFIG_FSL_USB2_OTG) += phy-fsl-usb.o 10obj-$(CONFIG_FSL_USB2_OTG) += phy-fsl-usb.o
12obj-$(CONFIG_ISP1301_OMAP) += phy-isp1301-omap.o 11obj-$(CONFIG_ISP1301_OMAP) += phy-isp1301-omap.o
13obj-$(CONFIG_MV_U3D_PHY) += phy-mv-u3d-usb.o
14obj-$(CONFIG_NOP_USB_XCEIV) += phy-generic.o 12obj-$(CONFIG_NOP_USB_XCEIV) += phy-generic.o
15obj-$(CONFIG_TAHVO_USB) += phy-tahvo.o 13obj-$(CONFIG_TAHVO_USB) += phy-tahvo.o
16obj-$(CONFIG_AM335X_CONTROL_USB) += phy-am335x-control.o 14obj-$(CONFIG_AM335X_CONTROL_USB) += phy-am335x-control.o
diff --git a/drivers/usb/phy/phy-am335x.c b/drivers/usb/phy/phy-am335x.c
index 12fc3468a01e..585e50cb1980 100644
--- a/drivers/usb/phy/phy-am335x.c
+++ b/drivers/usb/phy/phy-am335x.c
@@ -2,7 +2,7 @@
2#include <linux/platform_device.h> 2#include <linux/platform_device.h>
3#include <linux/dma-mapping.h> 3#include <linux/dma-mapping.h>
4#include <linux/usb/otg.h> 4#include <linux/usb/otg.h>
5#include <linux/usb/usb_phy_gen_xceiv.h> 5#include <linux/usb/usb_phy_generic.h>
6#include <linux/slab.h> 6#include <linux/slab.h>
7#include <linux/clk.h> 7#include <linux/clk.h>
8#include <linux/regulator/consumer.h> 8#include <linux/regulator/consumer.h>
@@ -13,7 +13,7 @@
13#include "phy-generic.h" 13#include "phy-generic.h"
14 14
15struct am335x_phy { 15struct am335x_phy {
16 struct usb_phy_gen_xceiv usb_phy_gen; 16 struct usb_phy_generic usb_phy_gen;
17 struct phy_control *phy_ctrl; 17 struct phy_control *phy_ctrl;
18 int id; 18 int id;
19}; 19};
diff --git a/drivers/usb/phy/phy-fsm-usb.c b/drivers/usb/phy/phy-fsm-usb.c
deleted file mode 100644
index d03fadd2629f..000000000000
--- a/drivers/usb/phy/phy-fsm-usb.c
+++ /dev/null
@@ -1,366 +0,0 @@
1/*
2 * OTG Finite State Machine from OTG spec
3 *
4 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
5 *
6 * Author: Li Yang <LeoLi@freescale.com>
7 * Jerry Huang <Chang-Ming.Huang@freescale.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/mutex.h>
27#include <linux/delay.h>
28#include <linux/usb.h>
29#include <linux/usb/gadget.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/otg-fsm.h>
32
33/* Change USB protocol when there is a protocol change */
34static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
35{
36 int ret = 0;
37
38 if (fsm->protocol != protocol) {
39 VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
40 fsm->protocol, protocol);
41 /* stop old protocol */
42 if (fsm->protocol == PROTO_HOST)
43 ret = otg_start_host(fsm, 0);
44 else if (fsm->protocol == PROTO_GADGET)
45 ret = otg_start_gadget(fsm, 0);
46 if (ret)
47 return ret;
48
49 /* start new protocol */
50 if (protocol == PROTO_HOST)
51 ret = otg_start_host(fsm, 1);
52 else if (protocol == PROTO_GADGET)
53 ret = otg_start_gadget(fsm, 1);
54 if (ret)
55 return ret;
56
57 fsm->protocol = protocol;
58 return 0;
59 }
60
61 return 0;
62}
63
64static int state_changed;
65
66/* Called when leaving a state. Do state clean up jobs here */
67static void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
68{
69 switch (old_state) {
70 case OTG_STATE_B_IDLE:
71 otg_del_timer(fsm, B_SE0_SRP);
72 fsm->b_se0_srp = 0;
73 fsm->adp_sns = 0;
74 fsm->adp_prb = 0;
75 break;
76 case OTG_STATE_B_SRP_INIT:
77 fsm->data_pulse = 0;
78 fsm->b_srp_done = 0;
79 break;
80 case OTG_STATE_B_PERIPHERAL:
81 break;
82 case OTG_STATE_B_WAIT_ACON:
83 otg_del_timer(fsm, B_ASE0_BRST);
84 fsm->b_ase0_brst_tmout = 0;
85 break;
86 case OTG_STATE_B_HOST:
87 break;
88 case OTG_STATE_A_IDLE:
89 fsm->adp_prb = 0;
90 break;
91 case OTG_STATE_A_WAIT_VRISE:
92 otg_del_timer(fsm, A_WAIT_VRISE);
93 fsm->a_wait_vrise_tmout = 0;
94 break;
95 case OTG_STATE_A_WAIT_BCON:
96 otg_del_timer(fsm, A_WAIT_BCON);
97 fsm->a_wait_bcon_tmout = 0;
98 break;
99 case OTG_STATE_A_HOST:
100 otg_del_timer(fsm, A_WAIT_ENUM);
101 break;
102 case OTG_STATE_A_SUSPEND:
103 otg_del_timer(fsm, A_AIDL_BDIS);
104 fsm->a_aidl_bdis_tmout = 0;
105 fsm->a_suspend_req_inf = 0;
106 break;
107 case OTG_STATE_A_PERIPHERAL:
108 otg_del_timer(fsm, A_BIDL_ADIS);
109 fsm->a_bidl_adis_tmout = 0;
110 break;
111 case OTG_STATE_A_WAIT_VFALL:
112 otg_del_timer(fsm, A_WAIT_VFALL);
113 fsm->a_wait_vfall_tmout = 0;
114 otg_del_timer(fsm, A_WAIT_VRISE);
115 break;
116 case OTG_STATE_A_VBUS_ERR:
117 break;
118 default:
119 break;
120 }
121}
122
123/* Called when entering a state */
124static int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
125{
126 state_changed = 1;
127 if (fsm->otg->phy->state == new_state)
128 return 0;
129 VDBG("Set state: %s\n", usb_otg_state_string(new_state));
130 otg_leave_state(fsm, fsm->otg->phy->state);
131 switch (new_state) {
132 case OTG_STATE_B_IDLE:
133 otg_drv_vbus(fsm, 0);
134 otg_chrg_vbus(fsm, 0);
135 otg_loc_conn(fsm, 0);
136 otg_loc_sof(fsm, 0);
137 /*
138 * Driver is responsible for starting ADP probing
139 * if ADP sensing times out.
140 */
141 otg_start_adp_sns(fsm);
142 otg_set_protocol(fsm, PROTO_UNDEF);
143 otg_add_timer(fsm, B_SE0_SRP);
144 break;
145 case OTG_STATE_B_SRP_INIT:
146 otg_start_pulse(fsm);
147 otg_loc_sof(fsm, 0);
148 otg_set_protocol(fsm, PROTO_UNDEF);
149 otg_add_timer(fsm, B_SRP_FAIL);
150 break;
151 case OTG_STATE_B_PERIPHERAL:
152 otg_chrg_vbus(fsm, 0);
153 otg_loc_conn(fsm, 1);
154 otg_loc_sof(fsm, 0);
155 otg_set_protocol(fsm, PROTO_GADGET);
156 break;
157 case OTG_STATE_B_WAIT_ACON:
158 otg_chrg_vbus(fsm, 0);
159 otg_loc_conn(fsm, 0);
160 otg_loc_sof(fsm, 0);
161 otg_set_protocol(fsm, PROTO_HOST);
162 otg_add_timer(fsm, B_ASE0_BRST);
163 fsm->a_bus_suspend = 0;
164 break;
165 case OTG_STATE_B_HOST:
166 otg_chrg_vbus(fsm, 0);
167 otg_loc_conn(fsm, 0);
168 otg_loc_sof(fsm, 1);
169 otg_set_protocol(fsm, PROTO_HOST);
170 usb_bus_start_enum(fsm->otg->host,
171 fsm->otg->host->otg_port);
172 break;
173 case OTG_STATE_A_IDLE:
174 otg_drv_vbus(fsm, 0);
175 otg_chrg_vbus(fsm, 0);
176 otg_loc_conn(fsm, 0);
177 otg_loc_sof(fsm, 0);
178 otg_start_adp_prb(fsm);
179 otg_set_protocol(fsm, PROTO_HOST);
180 break;
181 case OTG_STATE_A_WAIT_VRISE:
182 otg_drv_vbus(fsm, 1);
183 otg_loc_conn(fsm, 0);
184 otg_loc_sof(fsm, 0);
185 otg_set_protocol(fsm, PROTO_HOST);
186 otg_add_timer(fsm, A_WAIT_VRISE);
187 break;
188 case OTG_STATE_A_WAIT_BCON:
189 otg_drv_vbus(fsm, 1);
190 otg_loc_conn(fsm, 0);
191 otg_loc_sof(fsm, 0);
192 otg_set_protocol(fsm, PROTO_HOST);
193 otg_add_timer(fsm, A_WAIT_BCON);
194 break;
195 case OTG_STATE_A_HOST:
196 otg_drv_vbus(fsm, 1);
197 otg_loc_conn(fsm, 0);
198 otg_loc_sof(fsm, 1);
199 otg_set_protocol(fsm, PROTO_HOST);
200 /*
201 * When HNP is triggered while a_bus_req = 0, a_host will
202 * suspend too fast to complete a_set_b_hnp_en
203 */
204 if (!fsm->a_bus_req || fsm->a_suspend_req_inf)
205 otg_add_timer(fsm, A_WAIT_ENUM);
206 break;
207 case OTG_STATE_A_SUSPEND:
208 otg_drv_vbus(fsm, 1);
209 otg_loc_conn(fsm, 0);
210 otg_loc_sof(fsm, 0);
211 otg_set_protocol(fsm, PROTO_HOST);
212 otg_add_timer(fsm, A_AIDL_BDIS);
213
214 break;
215 case OTG_STATE_A_PERIPHERAL:
216 otg_loc_conn(fsm, 1);
217 otg_loc_sof(fsm, 0);
218 otg_set_protocol(fsm, PROTO_GADGET);
219 otg_drv_vbus(fsm, 1);
220 otg_add_timer(fsm, A_BIDL_ADIS);
221 break;
222 case OTG_STATE_A_WAIT_VFALL:
223 otg_drv_vbus(fsm, 0);
224 otg_loc_conn(fsm, 0);
225 otg_loc_sof(fsm, 0);
226 otg_set_protocol(fsm, PROTO_HOST);
227 otg_add_timer(fsm, A_WAIT_VFALL);
228 break;
229 case OTG_STATE_A_VBUS_ERR:
230 otg_drv_vbus(fsm, 0);
231 otg_loc_conn(fsm, 0);
232 otg_loc_sof(fsm, 0);
233 otg_set_protocol(fsm, PROTO_UNDEF);
234 break;
235 default:
236 break;
237 }
238
239 fsm->otg->phy->state = new_state;
240 return 0;
241}
242
243/* State change judgement */
244int otg_statemachine(struct otg_fsm *fsm)
245{
246 enum usb_otg_state state;
247
248 mutex_lock(&fsm->lock);
249
250 state = fsm->otg->phy->state;
251 state_changed = 0;
252 /* State machine state change judgement */
253
254 switch (state) {
255 case OTG_STATE_UNDEFINED:
256 VDBG("fsm->id = %d\n", fsm->id);
257 if (fsm->id)
258 otg_set_state(fsm, OTG_STATE_B_IDLE);
259 else
260 otg_set_state(fsm, OTG_STATE_A_IDLE);
261 break;
262 case OTG_STATE_B_IDLE:
263 if (!fsm->id)
264 otg_set_state(fsm, OTG_STATE_A_IDLE);
265 else if (fsm->b_sess_vld && fsm->otg->gadget)
266 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
267 else if ((fsm->b_bus_req || fsm->adp_change || fsm->power_up) &&
268 fsm->b_ssend_srp && fsm->b_se0_srp)
269 otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
270 break;
271 case OTG_STATE_B_SRP_INIT:
272 if (!fsm->id || fsm->b_srp_done)
273 otg_set_state(fsm, OTG_STATE_B_IDLE);
274 break;
275 case OTG_STATE_B_PERIPHERAL:
276 if (!fsm->id || !fsm->b_sess_vld)
277 otg_set_state(fsm, OTG_STATE_B_IDLE);
278 else if (fsm->b_bus_req && fsm->otg->
279 gadget->b_hnp_enable && fsm->a_bus_suspend)
280 otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
281 break;
282 case OTG_STATE_B_WAIT_ACON:
283 if (fsm->a_conn)
284 otg_set_state(fsm, OTG_STATE_B_HOST);
285 else if (!fsm->id || !fsm->b_sess_vld)
286 otg_set_state(fsm, OTG_STATE_B_IDLE);
287 else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
288 fsm->b_ase0_brst_tmout = 0;
289 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
290 }
291 break;
292 case OTG_STATE_B_HOST:
293 if (!fsm->id || !fsm->b_sess_vld)
294 otg_set_state(fsm, OTG_STATE_B_IDLE);
295 else if (!fsm->b_bus_req || !fsm->a_conn || fsm->test_device)
296 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
297 break;
298 case OTG_STATE_A_IDLE:
299 if (fsm->id)
300 otg_set_state(fsm, OTG_STATE_B_IDLE);
301 else if (!fsm->a_bus_drop && (fsm->a_bus_req ||
302 fsm->a_srp_det || fsm->adp_change || fsm->power_up))
303 otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
304 break;
305 case OTG_STATE_A_WAIT_VRISE:
306 if (fsm->a_vbus_vld)
307 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
308 else if (fsm->id || fsm->a_bus_drop ||
309 fsm->a_wait_vrise_tmout)
310 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
311 break;
312 case OTG_STATE_A_WAIT_BCON:
313 if (!fsm->a_vbus_vld)
314 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
315 else if (fsm->b_conn)
316 otg_set_state(fsm, OTG_STATE_A_HOST);
317 else if (fsm->id || fsm->a_bus_drop || fsm->a_wait_bcon_tmout)
318 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
319 break;
320 case OTG_STATE_A_HOST:
321 if (fsm->id || fsm->a_bus_drop)
322 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
323 else if ((!fsm->a_bus_req || fsm->a_suspend_req_inf) &&
324 fsm->otg->host->b_hnp_enable)
325 otg_set_state(fsm, OTG_STATE_A_SUSPEND);
326 else if (!fsm->b_conn)
327 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
328 else if (!fsm->a_vbus_vld)
329 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
330 break;
331 case OTG_STATE_A_SUSPEND:
332 if (!fsm->b_conn && fsm->otg->host->b_hnp_enable)
333 otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
334 else if (!fsm->b_conn && !fsm->otg->host->b_hnp_enable)
335 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
336 else if (fsm->a_bus_req || fsm->b_bus_resume)
337 otg_set_state(fsm, OTG_STATE_A_HOST);
338 else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
339 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
340 else if (!fsm->a_vbus_vld)
341 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
342 break;
343 case OTG_STATE_A_PERIPHERAL:
344 if (fsm->id || fsm->a_bus_drop)
345 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
346 else if (fsm->a_bidl_adis_tmout || fsm->b_bus_suspend)
347 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
348 else if (!fsm->a_vbus_vld)
349 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
350 break;
351 case OTG_STATE_A_WAIT_VFALL:
352 if (fsm->a_wait_vfall_tmout)
353 otg_set_state(fsm, OTG_STATE_A_IDLE);
354 break;
355 case OTG_STATE_A_VBUS_ERR:
356 if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
357 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
358 break;
359 default:
360 break;
361 }
362 mutex_unlock(&fsm->lock);
363
364 VDBG("quit statemachine, changed = %d\n", state_changed);
365 return state_changed;
366}
diff --git a/drivers/usb/phy/phy-generic.c b/drivers/usb/phy/phy-generic.c
index bb394980532b..7594e5069ae5 100644
--- a/drivers/usb/phy/phy-generic.c
+++ b/drivers/usb/phy/phy-generic.c
@@ -30,7 +30,7 @@
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
32#include <linux/usb/otg.h> 32#include <linux/usb/otg.h>
33#include <linux/usb/usb_phy_gen_xceiv.h> 33#include <linux/usb/usb_phy_generic.h>
34#include <linux/slab.h> 34#include <linux/slab.h>
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/regulator/consumer.h> 36#include <linux/regulator/consumer.h>
@@ -41,34 +41,25 @@
41 41
42#include "phy-generic.h" 42#include "phy-generic.h"
43 43
44static struct platform_device *pd; 44struct platform_device *usb_phy_generic_register(void)
45
46void usb_nop_xceiv_register(void)
47{ 45{
48 if (pd) 46 return platform_device_register_simple("usb_phy_generic",
49 return; 47 PLATFORM_DEVID_AUTO, NULL, 0);
50 pd = platform_device_register_simple("usb_phy_gen_xceiv", -1, NULL, 0);
51 if (IS_ERR(pd)) {
52 pr_err("Unable to register generic usb transceiver\n");
53 pd = NULL;
54 return;
55 }
56} 48}
57EXPORT_SYMBOL(usb_nop_xceiv_register); 49EXPORT_SYMBOL_GPL(usb_phy_generic_register);
58 50
59void usb_nop_xceiv_unregister(void) 51void usb_phy_generic_unregister(struct platform_device *pdev)
60{ 52{
61 platform_device_unregister(pd); 53 platform_device_unregister(pdev);
62 pd = NULL;
63} 54}
64EXPORT_SYMBOL(usb_nop_xceiv_unregister); 55EXPORT_SYMBOL_GPL(usb_phy_generic_unregister);
65 56
66static int nop_set_suspend(struct usb_phy *x, int suspend) 57static int nop_set_suspend(struct usb_phy *x, int suspend)
67{ 58{
68 return 0; 59 return 0;
69} 60}
70 61
71static void nop_reset_set(struct usb_phy_gen_xceiv *nop, int asserted) 62static void nop_reset_set(struct usb_phy_generic *nop, int asserted)
72{ 63{
73 int value; 64 int value;
74 65
@@ -87,7 +78,7 @@ static void nop_reset_set(struct usb_phy_gen_xceiv *nop, int asserted)
87 78
88int usb_gen_phy_init(struct usb_phy *phy) 79int usb_gen_phy_init(struct usb_phy *phy)
89{ 80{
90 struct usb_phy_gen_xceiv *nop = dev_get_drvdata(phy->dev); 81 struct usb_phy_generic *nop = dev_get_drvdata(phy->dev);
91 82
92 if (!IS_ERR(nop->vcc)) { 83 if (!IS_ERR(nop->vcc)) {
93 if (regulator_enable(nop->vcc)) 84 if (regulator_enable(nop->vcc))
@@ -106,7 +97,7 @@ EXPORT_SYMBOL_GPL(usb_gen_phy_init);
106 97
107void usb_gen_phy_shutdown(struct usb_phy *phy) 98void usb_gen_phy_shutdown(struct usb_phy *phy)
108{ 99{
109 struct usb_phy_gen_xceiv *nop = dev_get_drvdata(phy->dev); 100 struct usb_phy_generic *nop = dev_get_drvdata(phy->dev);
110 101
111 /* Assert RESET */ 102 /* Assert RESET */
112 nop_reset_set(nop, 1); 103 nop_reset_set(nop, 1);
@@ -150,8 +141,8 @@ static int nop_set_host(struct usb_otg *otg, struct usb_bus *host)
150 return 0; 141 return 0;
151} 142}
152 143
153int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_gen_xceiv *nop, 144int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_generic *nop,
154 struct usb_phy_gen_xceiv_platform_data *pdata) 145 struct usb_phy_generic_platform_data *pdata)
155{ 146{
156 enum usb_phy_type type = USB_PHY_TYPE_USB2; 147 enum usb_phy_type type = USB_PHY_TYPE_USB2;
157 int err; 148 int err;
@@ -245,10 +236,10 @@ int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_gen_xceiv *nop,
245} 236}
246EXPORT_SYMBOL_GPL(usb_phy_gen_create_phy); 237EXPORT_SYMBOL_GPL(usb_phy_gen_create_phy);
247 238
248static int usb_phy_gen_xceiv_probe(struct platform_device *pdev) 239static int usb_phy_generic_probe(struct platform_device *pdev)
249{ 240{
250 struct device *dev = &pdev->dev; 241 struct device *dev = &pdev->dev;
251 struct usb_phy_gen_xceiv *nop; 242 struct usb_phy_generic *nop;
252 int err; 243 int err;
253 244
254 nop = devm_kzalloc(dev, sizeof(*nop), GFP_KERNEL); 245 nop = devm_kzalloc(dev, sizeof(*nop), GFP_KERNEL);
@@ -274,9 +265,9 @@ static int usb_phy_gen_xceiv_probe(struct platform_device *pdev)
274 return 0; 265 return 0;
275} 266}
276 267
277static int usb_phy_gen_xceiv_remove(struct platform_device *pdev) 268static int usb_phy_generic_remove(struct platform_device *pdev)
278{ 269{
279 struct usb_phy_gen_xceiv *nop = platform_get_drvdata(pdev); 270 struct usb_phy_generic *nop = platform_get_drvdata(pdev);
280 271
281 usb_remove_phy(&nop->phy); 272 usb_remove_phy(&nop->phy);
282 273
@@ -290,29 +281,29 @@ static const struct of_device_id nop_xceiv_dt_ids[] = {
290 281
291MODULE_DEVICE_TABLE(of, nop_xceiv_dt_ids); 282MODULE_DEVICE_TABLE(of, nop_xceiv_dt_ids);
292 283
293static struct platform_driver usb_phy_gen_xceiv_driver = { 284static struct platform_driver usb_phy_generic_driver = {
294 .probe = usb_phy_gen_xceiv_probe, 285 .probe = usb_phy_generic_probe,
295 .remove = usb_phy_gen_xceiv_remove, 286 .remove = usb_phy_generic_remove,
296 .driver = { 287 .driver = {
297 .name = "usb_phy_gen_xceiv", 288 .name = "usb_phy_generic",
298 .owner = THIS_MODULE, 289 .owner = THIS_MODULE,
299 .of_match_table = nop_xceiv_dt_ids, 290 .of_match_table = nop_xceiv_dt_ids,
300 }, 291 },
301}; 292};
302 293
303static int __init usb_phy_gen_xceiv_init(void) 294static int __init usb_phy_generic_init(void)
304{ 295{
305 return platform_driver_register(&usb_phy_gen_xceiv_driver); 296 return platform_driver_register(&usb_phy_generic_driver);
306} 297}
307subsys_initcall(usb_phy_gen_xceiv_init); 298subsys_initcall(usb_phy_generic_init);
308 299
309static void __exit usb_phy_gen_xceiv_exit(void) 300static void __exit usb_phy_generic_exit(void)
310{ 301{
311 platform_driver_unregister(&usb_phy_gen_xceiv_driver); 302 platform_driver_unregister(&usb_phy_generic_driver);
312} 303}
313module_exit(usb_phy_gen_xceiv_exit); 304module_exit(usb_phy_generic_exit);
314 305
315MODULE_ALIAS("platform:usb_phy_gen_xceiv"); 306MODULE_ALIAS("platform:usb_phy_generic");
316MODULE_AUTHOR("Texas Instruments Inc"); 307MODULE_AUTHOR("Texas Instruments Inc");
317MODULE_DESCRIPTION("NOP USB Transceiver driver"); 308MODULE_DESCRIPTION("NOP USB Transceiver driver");
318MODULE_LICENSE("GPL"); 309MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/phy-generic.h b/drivers/usb/phy/phy-generic.h
index 38a81f307b82..d8feacc0b7fb 100644
--- a/drivers/usb/phy/phy-generic.h
+++ b/drivers/usb/phy/phy-generic.h
@@ -1,9 +1,9 @@
1#ifndef _PHY_GENERIC_H_ 1#ifndef _PHY_GENERIC_H_
2#define _PHY_GENERIC_H_ 2#define _PHY_GENERIC_H_
3 3
4#include <linux/usb/usb_phy_gen_xceiv.h> 4#include <linux/usb/usb_phy_generic.h>
5 5
6struct usb_phy_gen_xceiv { 6struct usb_phy_generic {
7 struct usb_phy phy; 7 struct usb_phy phy;
8 struct device *dev; 8 struct device *dev;
9 struct clk *clk; 9 struct clk *clk;
@@ -15,7 +15,7 @@ struct usb_phy_gen_xceiv {
15int usb_gen_phy_init(struct usb_phy *phy); 15int usb_gen_phy_init(struct usb_phy *phy);
16void usb_gen_phy_shutdown(struct usb_phy *phy); 16void usb_gen_phy_shutdown(struct usb_phy *phy);
17 17
18int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_gen_xceiv *nop, 18int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_generic *nop,
19 struct usb_phy_gen_xceiv_platform_data *pdata); 19 struct usb_phy_generic_platform_data *pdata);
20 20
21#endif 21#endif
diff --git a/drivers/usb/phy/phy-keystone.c b/drivers/usb/phy/phy-keystone.c
index d762003896c0..f4d722de912b 100644
--- a/drivers/usb/phy/phy-keystone.c
+++ b/drivers/usb/phy/phy-keystone.c
@@ -18,7 +18,7 @@
18 18
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/usb/usb_phy_gen_xceiv.h> 21#include <linux/usb/usb_phy_generic.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/of.h> 23#include <linux/of.h>
24 24
@@ -35,7 +35,7 @@
35#define PHY_REF_SSP_EN BIT(29) 35#define PHY_REF_SSP_EN BIT(29)
36 36
37struct keystone_usbphy { 37struct keystone_usbphy {
38 struct usb_phy_gen_xceiv usb_phy_gen; 38 struct usb_phy_generic usb_phy_gen;
39 void __iomem *phy_ctrl; 39 void __iomem *phy_ctrl;
40}; 40};
41 41
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 5b37b81f2ef6..ced34f39bdd4 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -30,9 +30,13 @@
30#include <linux/debugfs.h> 30#include <linux/debugfs.h>
31#include <linux/seq_file.h> 31#include <linux/seq_file.h>
32#include <linux/pm_runtime.h> 32#include <linux/pm_runtime.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/reset.h>
33 36
34#include <linux/usb.h> 37#include <linux/usb.h>
35#include <linux/usb/otg.h> 38#include <linux/usb/otg.h>
39#include <linux/usb/of.h>
36#include <linux/usb/ulpi.h> 40#include <linux/usb/ulpi.h>
37#include <linux/usb/gadget.h> 41#include <linux/usb/gadget.h>
38#include <linux/usb/hcd.h> 42#include <linux/usb/hcd.h>
@@ -44,6 +48,7 @@
44#define DRIVER_NAME "msm_otg" 48#define DRIVER_NAME "msm_otg"
45 49
46#define ULPI_IO_TIMEOUT_USEC (10 * 1000) 50#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
51#define LINK_RESET_TIMEOUT_USEC (250 * 1000)
47 52
48#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */ 53#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
49#define USB_PHY_3P3_VOL_MAX 3300000 /* uV */ 54#define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
@@ -57,48 +62,38 @@
57 62
58#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */ 63#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
59#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */ 64#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
65#define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
60 66
61static struct regulator *hsusb_3p3; 67enum vdd_levels {
62static struct regulator *hsusb_1p8; 68 VDD_LEVEL_NONE = 0,
63static struct regulator *hsusb_vddcx; 69 VDD_LEVEL_MIN,
70 VDD_LEVEL_MAX,
71};
64 72
65static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init) 73static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
66{ 74{
67 int ret = 0; 75 int ret = 0;
68 76
69 if (init) { 77 if (init) {
70 hsusb_vddcx = regulator_get(motg->phy.dev, "HSUSB_VDDCX"); 78 ret = regulator_set_voltage(motg->vddcx,
71 if (IS_ERR(hsusb_vddcx)) { 79 motg->vdd_levels[VDD_LEVEL_MIN],
72 dev_err(motg->phy.dev, "unable to get hsusb vddcx\n"); 80 motg->vdd_levels[VDD_LEVEL_MAX]);
73 return PTR_ERR(hsusb_vddcx);
74 }
75
76 ret = regulator_set_voltage(hsusb_vddcx,
77 USB_PHY_VDD_DIG_VOL_MIN,
78 USB_PHY_VDD_DIG_VOL_MAX);
79 if (ret) { 81 if (ret) {
80 dev_err(motg->phy.dev, "unable to set the voltage " 82 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
81 "for hsusb vddcx\n");
82 regulator_put(hsusb_vddcx);
83 return ret; 83 return ret;
84 } 84 }
85 85
86 ret = regulator_enable(hsusb_vddcx); 86 ret = regulator_enable(motg->vddcx);
87 if (ret) { 87 if (ret)
88 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n"); 88 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
89 regulator_put(hsusb_vddcx);
90 }
91 } else { 89 } else {
92 ret = regulator_set_voltage(hsusb_vddcx, 0, 90 ret = regulator_set_voltage(motg->vddcx, 0,
93 USB_PHY_VDD_DIG_VOL_MAX); 91 motg->vdd_levels[VDD_LEVEL_MAX]);
94 if (ret) 92 if (ret)
95 dev_err(motg->phy.dev, "unable to set the voltage " 93 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
96 "for hsusb vddcx\n"); 94 ret = regulator_disable(motg->vddcx);
97 ret = regulator_disable(hsusb_vddcx);
98 if (ret) 95 if (ret)
99 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n"); 96 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
100
101 regulator_put(hsusb_vddcx);
102 } 97 }
103 98
104 return ret; 99 return ret;
@@ -109,98 +104,67 @@ static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
109 int rc = 0; 104 int rc = 0;
110 105
111 if (init) { 106 if (init) {
112 hsusb_3p3 = regulator_get(motg->phy.dev, "HSUSB_3p3"); 107 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
113 if (IS_ERR(hsusb_3p3)) {
114 dev_err(motg->phy.dev, "unable to get hsusb 3p3\n");
115 return PTR_ERR(hsusb_3p3);
116 }
117
118 rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
119 USB_PHY_3P3_VOL_MAX); 108 USB_PHY_3P3_VOL_MAX);
120 if (rc) { 109 if (rc) {
121 dev_err(motg->phy.dev, "unable to set voltage level " 110 dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
122 "for hsusb 3p3\n"); 111 goto exit;
123 goto put_3p3;
124 } 112 }
125 rc = regulator_enable(hsusb_3p3); 113 rc = regulator_enable(motg->v3p3);
126 if (rc) { 114 if (rc) {
127 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n"); 115 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
128 goto put_3p3; 116 goto exit;
129 } 117 }
130 hsusb_1p8 = regulator_get(motg->phy.dev, "HSUSB_1p8"); 118 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
131 if (IS_ERR(hsusb_1p8)) {
132 dev_err(motg->phy.dev, "unable to get hsusb 1p8\n");
133 rc = PTR_ERR(hsusb_1p8);
134 goto disable_3p3;
135 }
136 rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
137 USB_PHY_1P8_VOL_MAX); 119 USB_PHY_1P8_VOL_MAX);
138 if (rc) { 120 if (rc) {
139 dev_err(motg->phy.dev, "unable to set voltage level " 121 dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
140 "for hsusb 1p8\n"); 122 goto disable_3p3;
141 goto put_1p8;
142 } 123 }
143 rc = regulator_enable(hsusb_1p8); 124 rc = regulator_enable(motg->v1p8);
144 if (rc) { 125 if (rc) {
145 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n"); 126 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
146 goto put_1p8; 127 goto disable_3p3;
147 } 128 }
148 129
149 return 0; 130 return 0;
150 } 131 }
151 132
152 regulator_disable(hsusb_1p8); 133 regulator_disable(motg->v1p8);
153put_1p8:
154 regulator_put(hsusb_1p8);
155disable_3p3: 134disable_3p3:
156 regulator_disable(hsusb_3p3); 135 regulator_disable(motg->v3p3);
157put_3p3: 136exit:
158 regulator_put(hsusb_3p3);
159 return rc; 137 return rc;
160} 138}
161 139
162static int msm_hsusb_ldo_set_mode(int on) 140static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
163{ 141{
164 int ret = 0; 142 int ret = 0;
165 143
166 if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
167 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
168 return -ENODEV;
169 }
170
171 if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
172 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
173 return -ENODEV;
174 }
175
176 if (on) { 144 if (on) {
177 ret = regulator_set_optimum_mode(hsusb_1p8, 145 ret = regulator_set_optimum_mode(motg->v1p8,
178 USB_PHY_1P8_HPM_LOAD); 146 USB_PHY_1P8_HPM_LOAD);
179 if (ret < 0) { 147 if (ret < 0) {
180 pr_err("%s: Unable to set HPM of the regulator " 148 pr_err("Could not set HPM for v1p8\n");
181 "HSUSB_1p8\n", __func__);
182 return ret; 149 return ret;
183 } 150 }
184 ret = regulator_set_optimum_mode(hsusb_3p3, 151 ret = regulator_set_optimum_mode(motg->v3p3,
185 USB_PHY_3P3_HPM_LOAD); 152 USB_PHY_3P3_HPM_LOAD);
186 if (ret < 0) { 153 if (ret < 0) {
187 pr_err("%s: Unable to set HPM of the regulator " 154 pr_err("Could not set HPM for v3p3\n");
188 "HSUSB_3p3\n", __func__); 155 regulator_set_optimum_mode(motg->v1p8,
189 regulator_set_optimum_mode(hsusb_1p8,
190 USB_PHY_1P8_LPM_LOAD); 156 USB_PHY_1P8_LPM_LOAD);
191 return ret; 157 return ret;
192 } 158 }
193 } else { 159 } else {
194 ret = regulator_set_optimum_mode(hsusb_1p8, 160 ret = regulator_set_optimum_mode(motg->v1p8,
195 USB_PHY_1P8_LPM_LOAD); 161 USB_PHY_1P8_LPM_LOAD);
196 if (ret < 0) 162 if (ret < 0)
197 pr_err("%s: Unable to set LPM of the regulator " 163 pr_err("Could not set LPM for v1p8\n");
198 "HSUSB_1p8\n", __func__); 164 ret = regulator_set_optimum_mode(motg->v3p3,
199 ret = regulator_set_optimum_mode(hsusb_3p3,
200 USB_PHY_3P3_LPM_LOAD); 165 USB_PHY_3P3_LPM_LOAD);
201 if (ret < 0) 166 if (ret < 0)
202 pr_err("%s: Unable to set LPM of the regulator " 167 pr_err("Could not set LPM for v3p3\n");
203 "HSUSB_3p3\n", __func__);
204 } 168 }
205 169
206 pr_debug("reg (%s)\n", on ? "HPM" : "LPM"); 170 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
@@ -265,27 +229,47 @@ static struct usb_phy_io_ops msm_otg_io_ops = {
265static void ulpi_init(struct msm_otg *motg) 229static void ulpi_init(struct msm_otg *motg)
266{ 230{
267 struct msm_otg_platform_data *pdata = motg->pdata; 231 struct msm_otg_platform_data *pdata = motg->pdata;
268 int *seq = pdata->phy_init_seq; 232 int *seq = pdata->phy_init_seq, idx;
233 u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
269 234
270 if (!seq) 235 for (idx = 0; idx < pdata->phy_init_sz; idx++) {
271 return; 236 if (seq[idx] == -1)
237 continue;
272 238
273 while (seq[0] >= 0) {
274 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n", 239 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
275 seq[0], seq[1]); 240 seq[idx], addr + idx);
276 ulpi_write(&motg->phy, seq[0], seq[1]); 241 ulpi_write(&motg->phy, seq[idx], addr + idx);
277 seq += 2;
278 } 242 }
279} 243}
280 244
245static int msm_phy_notify_disconnect(struct usb_phy *phy,
246 enum usb_device_speed speed)
247{
248 int val;
249
250 /*
251 * Put the transceiver in non-driving mode. Otherwise host
252 * may not detect soft-disconnection.
253 */
254 val = ulpi_read(phy, ULPI_FUNC_CTRL);
255 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
256 val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
257 ulpi_write(phy, val, ULPI_FUNC_CTRL);
258
259 return 0;
260}
261
281static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert) 262static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
282{ 263{
283 int ret = 0; 264 int ret;
284 265
285 if (!motg->pdata->link_clk_reset) 266 if (motg->pdata->link_clk_reset)
286 return ret; 267 ret = motg->pdata->link_clk_reset(motg->clk, assert);
268 else if (assert)
269 ret = reset_control_assert(motg->link_rst);
270 else
271 ret = reset_control_deassert(motg->link_rst);
287 272
288 ret = motg->pdata->link_clk_reset(motg->clk, assert);
289 if (ret) 273 if (ret)
290 dev_err(motg->phy.dev, "usb link clk reset %s failed\n", 274 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
291 assert ? "assert" : "deassert"); 275 assert ? "assert" : "deassert");
@@ -295,111 +279,150 @@ static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
295 279
296static int msm_otg_phy_clk_reset(struct msm_otg *motg) 280static int msm_otg_phy_clk_reset(struct msm_otg *motg)
297{ 281{
298 int ret = 0; 282 int ret;
299 283
300 if (!motg->pdata->phy_clk_reset) 284 if (motg->pdata->phy_clk_reset)
301 return ret; 285 ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
286 else
287 ret = reset_control_reset(motg->phy_rst);
302 288
303 ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
304 if (ret) 289 if (ret)
305 dev_err(motg->phy.dev, "usb phy clk reset failed\n"); 290 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
306 291
307 return ret; 292 return ret;
308} 293}
309 294
310static int msm_otg_phy_reset(struct msm_otg *motg) 295static int msm_link_reset(struct msm_otg *motg)
311{ 296{
312 u32 val; 297 u32 val;
313 int ret; 298 int ret;
314 int retries;
315 299
316 ret = msm_otg_link_clk_reset(motg, 1); 300 ret = msm_otg_link_clk_reset(motg, 1);
317 if (ret) 301 if (ret)
318 return ret; 302 return ret;
319 ret = msm_otg_phy_clk_reset(motg); 303
320 if (ret) 304 /* wait for 1ms delay as suggested in HPG. */
321 return ret; 305 usleep_range(1000, 1200);
306
322 ret = msm_otg_link_clk_reset(motg, 0); 307 ret = msm_otg_link_clk_reset(motg, 0);
323 if (ret) 308 if (ret)
324 return ret; 309 return ret;
325 310
311 if (motg->phy_number)
312 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
313
314 /* put transceiver in serial mode as part of reset */
326 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK; 315 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
327 writel(val | PORTSC_PTS_ULPI, USB_PORTSC); 316 writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
328 317
329 for (retries = 3; retries > 0; retries--) { 318 return 0;
330 ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM, 319}
331 ULPI_CLR(ULPI_FUNC_CTRL));
332 if (!ret)
333 break;
334 ret = msm_otg_phy_clk_reset(motg);
335 if (ret)
336 return ret;
337 }
338 if (!retries)
339 return -ETIMEDOUT;
340 320
341 /* This reset calibrates the phy, if the above write succeeded */ 321static int msm_otg_reset(struct usb_phy *phy)
342 ret = msm_otg_phy_clk_reset(motg); 322{
343 if (ret) 323 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
344 return ret; 324 int cnt = 0;
345 325
346 for (retries = 3; retries > 0; retries--) { 326 writel(USBCMD_RESET, USB_USBCMD);
347 ret = ulpi_read(&motg->phy, ULPI_DEBUG); 327 while (cnt < LINK_RESET_TIMEOUT_USEC) {
348 if (ret != -ETIMEDOUT) 328 if (!(readl(USB_USBCMD) & USBCMD_RESET))
349 break; 329 break;
350 ret = msm_otg_phy_clk_reset(motg); 330 udelay(1);
351 if (ret) 331 cnt++;
352 return ret;
353 } 332 }
354 if (!retries) 333 if (cnt >= LINK_RESET_TIMEOUT_USEC)
355 return -ETIMEDOUT; 334 return -ETIMEDOUT;
356 335
357 dev_info(motg->phy.dev, "phy_reset: success\n"); 336 /* select ULPI phy and clear other status/control bits in PORTSC */
337 writel(PORTSC_PTS_ULPI, USB_PORTSC);
338
339 writel(0x0, USB_AHBBURST);
340 writel(0x08, USB_AHBMODE);
341
342 if (motg->phy_number)
343 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
358 return 0; 344 return 0;
359} 345}
360 346
361#define LINK_RESET_TIMEOUT_USEC (250 * 1000) 347static void msm_phy_reset(struct msm_otg *motg)
362static int msm_otg_reset(struct usb_phy *phy) 348{
349 void __iomem *addr;
350
351 if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
352 msm_otg_phy_clk_reset(motg);
353 return;
354 }
355
356 addr = USB_PHY_CTRL;
357 if (motg->phy_number)
358 addr = USB_PHY_CTRL2;
359
360 /* Assert USB PHY_POR */
361 writel(readl(addr) | PHY_POR_ASSERT, addr);
362
363 /*
364 * wait for minimum 10 microseconds as suggested in HPG.
365 * Use a slightly larger value since the exact value didn't
366 * work 100% of the time.
367 */
368 udelay(12);
369
370 /* Deassert USB PHY_POR */
371 writel(readl(addr) & ~PHY_POR_ASSERT, addr);
372}
373
374static int msm_usb_reset(struct usb_phy *phy)
363{ 375{
364 struct msm_otg *motg = container_of(phy, struct msm_otg, phy); 376 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
365 struct msm_otg_platform_data *pdata = motg->pdata;
366 int cnt = 0;
367 int ret; 377 int ret;
368 u32 val = 0;
369 u32 ulpi_val = 0;
370 378
371 ret = msm_otg_phy_reset(motg); 379 if (!IS_ERR(motg->core_clk))
380 clk_prepare_enable(motg->core_clk);
381
382 ret = msm_link_reset(motg);
372 if (ret) { 383 if (ret) {
373 dev_err(phy->dev, "phy_reset failed\n"); 384 dev_err(phy->dev, "phy_reset failed\n");
374 return ret; 385 return ret;
375 } 386 }
376 387
377 ulpi_init(motg); 388 ret = msm_otg_reset(&motg->phy);
378 389 if (ret) {
379 writel(USBCMD_RESET, USB_USBCMD); 390 dev_err(phy->dev, "link reset failed\n");
380 while (cnt < LINK_RESET_TIMEOUT_USEC) { 391 return ret;
381 if (!(readl(USB_USBCMD) & USBCMD_RESET))
382 break;
383 udelay(1);
384 cnt++;
385 } 392 }
386 if (cnt >= LINK_RESET_TIMEOUT_USEC)
387 return -ETIMEDOUT;
388
389 /* select ULPI phy */
390 writel(0x80000000, USB_PORTSC);
391 393
392 msleep(100); 394 msleep(100);
393 395
394 writel(0x0, USB_AHBBURST); 396 /* Reset USB PHY after performing USB Link RESET */
395 writel(0x00, USB_AHBMODE); 397 msm_phy_reset(motg);
398
399 if (!IS_ERR(motg->core_clk))
400 clk_disable_unprepare(motg->core_clk);
401
402 return 0;
403}
404
405static int msm_phy_init(struct usb_phy *phy)
406{
407 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
408 struct msm_otg_platform_data *pdata = motg->pdata;
409 u32 val, ulpi_val = 0;
410
411 /* Program USB PHY Override registers. */
412 ulpi_init(motg);
413
414 /*
415 * It is recommended in HPG to reset USB PHY after programming
416 * USB PHY Override registers.
417 */
418 msm_phy_reset(motg);
396 419
397 if (pdata->otg_control == OTG_PHY_CONTROL) { 420 if (pdata->otg_control == OTG_PHY_CONTROL) {
398 val = readl(USB_OTGSC); 421 val = readl(USB_OTGSC);
399 if (pdata->mode == USB_OTG) { 422 if (pdata->mode == USB_DR_MODE_OTG) {
400 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID; 423 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
401 val |= OTGSC_IDIE | OTGSC_BSVIE; 424 val |= OTGSC_IDIE | OTGSC_BSVIE;
402 } else if (pdata->mode == USB_PERIPHERAL) { 425 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
403 ulpi_val = ULPI_INT_SESS_VALID; 426 ulpi_val = ULPI_INT_SESS_VALID;
404 val |= OTGSC_BSVIE; 427 val |= OTGSC_BSVIE;
405 } 428 }
@@ -408,6 +431,9 @@ static int msm_otg_reset(struct usb_phy *phy)
408 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL); 431 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
409 } 432 }
410 433
434 if (motg->phy_number)
435 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
436
411 return 0; 437 return 0;
412} 438}
413 439
@@ -416,22 +442,20 @@ static int msm_otg_reset(struct usb_phy *phy)
416 442
417#ifdef CONFIG_PM 443#ifdef CONFIG_PM
418 444
419#define USB_PHY_SUSP_DIG_VOL 500000 445static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
420static int msm_hsusb_config_vddcx(int high)
421{ 446{
422 int max_vol = USB_PHY_VDD_DIG_VOL_MAX; 447 int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
423 int min_vol; 448 int min_vol;
424 int ret; 449 int ret;
425 450
426 if (high) 451 if (high)
427 min_vol = USB_PHY_VDD_DIG_VOL_MIN; 452 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
428 else 453 else
429 min_vol = USB_PHY_SUSP_DIG_VOL; 454 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
430 455
431 ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol); 456 ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
432 if (ret) { 457 if (ret) {
433 pr_err("%s: unable to set the voltage for regulator " 458 pr_err("Cannot set vddcx voltage\n");
434 "HSUSB_VDDCX\n", __func__);
435 return ret; 459 return ret;
436 } 460 }
437 461
@@ -445,6 +469,7 @@ static int msm_otg_suspend(struct msm_otg *motg)
445 struct usb_phy *phy = &motg->phy; 469 struct usb_phy *phy = &motg->phy;
446 struct usb_bus *bus = phy->otg->host; 470 struct usb_bus *bus = phy->otg->host;
447 struct msm_otg_platform_data *pdata = motg->pdata; 471 struct msm_otg_platform_data *pdata = motg->pdata;
472 void __iomem *addr;
448 int cnt = 0; 473 int cnt = 0;
449 474
450 if (atomic_read(&motg->in_lpm)) 475 if (atomic_read(&motg->in_lpm))
@@ -504,22 +529,23 @@ static int msm_otg_suspend(struct msm_otg *motg)
504 */ 529 */
505 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD); 530 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
506 531
532 addr = USB_PHY_CTRL;
533 if (motg->phy_number)
534 addr = USB_PHY_CTRL2;
535
507 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && 536 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
508 motg->pdata->otg_control == OTG_PMIC_CONTROL) 537 motg->pdata->otg_control == OTG_PMIC_CONTROL)
509 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL); 538 writel(readl(addr) | PHY_RETEN, addr);
510 539
511 clk_disable_unprepare(motg->pclk); 540 clk_disable_unprepare(motg->pclk);
512 clk_disable_unprepare(motg->clk); 541 clk_disable_unprepare(motg->clk);
513 if (motg->core_clk) 542 if (!IS_ERR(motg->core_clk))
514 clk_disable_unprepare(motg->core_clk); 543 clk_disable_unprepare(motg->core_clk);
515 544
516 if (!IS_ERR(motg->pclk_src))
517 clk_disable_unprepare(motg->pclk_src);
518
519 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && 545 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
520 motg->pdata->otg_control == OTG_PMIC_CONTROL) { 546 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
521 msm_hsusb_ldo_set_mode(0); 547 msm_hsusb_ldo_set_mode(motg, 0);
522 msm_hsusb_config_vddcx(0); 548 msm_hsusb_config_vddcx(motg, 0);
523 } 549 }
524 550
525 if (device_may_wakeup(phy->dev)) 551 if (device_may_wakeup(phy->dev))
@@ -539,25 +565,28 @@ static int msm_otg_resume(struct msm_otg *motg)
539{ 565{
540 struct usb_phy *phy = &motg->phy; 566 struct usb_phy *phy = &motg->phy;
541 struct usb_bus *bus = phy->otg->host; 567 struct usb_bus *bus = phy->otg->host;
568 void __iomem *addr;
542 int cnt = 0; 569 int cnt = 0;
543 unsigned temp; 570 unsigned temp;
544 571
545 if (!atomic_read(&motg->in_lpm)) 572 if (!atomic_read(&motg->in_lpm))
546 return 0; 573 return 0;
547 574
548 if (!IS_ERR(motg->pclk_src))
549 clk_prepare_enable(motg->pclk_src);
550
551 clk_prepare_enable(motg->pclk); 575 clk_prepare_enable(motg->pclk);
552 clk_prepare_enable(motg->clk); 576 clk_prepare_enable(motg->clk);
553 if (motg->core_clk) 577 if (!IS_ERR(motg->core_clk))
554 clk_prepare_enable(motg->core_clk); 578 clk_prepare_enable(motg->core_clk);
555 579
556 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && 580 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
557 motg->pdata->otg_control == OTG_PMIC_CONTROL) { 581 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
558 msm_hsusb_ldo_set_mode(1); 582
559 msm_hsusb_config_vddcx(1); 583 addr = USB_PHY_CTRL;
560 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL); 584 if (motg->phy_number)
585 addr = USB_PHY_CTRL2;
586
587 msm_hsusb_ldo_set_mode(motg, 1);
588 msm_hsusb_config_vddcx(motg, 1);
589 writel(readl(addr) & ~PHY_RETEN, addr);
561 } 590 }
562 591
563 temp = readl(USB_USBCMD); 592 temp = readl(USB_USBCMD);
@@ -586,8 +615,7 @@ static int msm_otg_resume(struct msm_otg *motg)
586 * PHY. USB state can not be restored. Re-insertion 615 * PHY. USB state can not be restored. Re-insertion
587 * of USB cable is the only way to get USB working. 616 * of USB cable is the only way to get USB working.
588 */ 617 */
589 dev_err(phy->dev, "Unable to resume USB." 618 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
590 "Re-plugin the cable\n");
591 msm_otg_reset(phy); 619 msm_otg_reset(phy);
592 } 620 }
593 621
@@ -687,7 +715,7 @@ static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
687 * Fail host registration if this board can support 715 * Fail host registration if this board can support
688 * only peripheral configuration. 716 * only peripheral configuration.
689 */ 717 */
690 if (motg->pdata->mode == USB_PERIPHERAL) { 718 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
691 dev_info(otg->phy->dev, "Host mode is not supported\n"); 719 dev_info(otg->phy->dev, "Host mode is not supported\n");
692 return -ENODEV; 720 return -ENODEV;
693 } 721 }
@@ -716,7 +744,7 @@ static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
716 * Kick the state machine work, if peripheral is not supported 744 * Kick the state machine work, if peripheral is not supported
717 * or peripheral is already registered with us. 745 * or peripheral is already registered with us.
718 */ 746 */
719 if (motg->pdata->mode == USB_HOST || otg->gadget) { 747 if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
720 pm_runtime_get_sync(otg->phy->dev); 748 pm_runtime_get_sync(otg->phy->dev);
721 schedule_work(&motg->sm_work); 749 schedule_work(&motg->sm_work);
722 } 750 }
@@ -760,7 +788,7 @@ static int msm_otg_set_peripheral(struct usb_otg *otg,
760 * Fail peripheral registration if this board can support 788 * Fail peripheral registration if this board can support
761 * only host configuration. 789 * only host configuration.
762 */ 790 */
763 if (motg->pdata->mode == USB_HOST) { 791 if (motg->pdata->mode == USB_DR_MODE_HOST) {
764 dev_info(otg->phy->dev, "Peripheral mode is not supported\n"); 792 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
765 return -ENODEV; 793 return -ENODEV;
766 } 794 }
@@ -785,7 +813,7 @@ static int msm_otg_set_peripheral(struct usb_otg *otg,
785 * Kick the state machine work, if host is not supported 813 * Kick the state machine work, if host is not supported
786 * or host is already registered with us. 814 * or host is already registered with us.
787 */ 815 */
788 if (motg->pdata->mode == USB_PERIPHERAL || otg->host) { 816 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
789 pm_runtime_get_sync(otg->phy->dev); 817 pm_runtime_get_sync(otg->phy->dev);
790 schedule_work(&motg->sm_work); 818 schedule_work(&motg->sm_work);
791 } 819 }
@@ -1106,7 +1134,7 @@ static void msm_otg_init_sm(struct msm_otg *motg)
1106 u32 otgsc = readl(USB_OTGSC); 1134 u32 otgsc = readl(USB_OTGSC);
1107 1135
1108 switch (pdata->mode) { 1136 switch (pdata->mode) {
1109 case USB_OTG: 1137 case USB_DR_MODE_OTG:
1110 if (pdata->otg_control == OTG_PHY_CONTROL) { 1138 if (pdata->otg_control == OTG_PHY_CONTROL) {
1111 if (otgsc & OTGSC_ID) 1139 if (otgsc & OTGSC_ID)
1112 set_bit(ID, &motg->inputs); 1140 set_bit(ID, &motg->inputs);
@@ -1118,21 +1146,14 @@ static void msm_otg_init_sm(struct msm_otg *motg)
1118 else 1146 else
1119 clear_bit(B_SESS_VLD, &motg->inputs); 1147 clear_bit(B_SESS_VLD, &motg->inputs);
1120 } else if (pdata->otg_control == OTG_USER_CONTROL) { 1148 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1121 if (pdata->default_mode == USB_HOST) {
1122 clear_bit(ID, &motg->inputs);
1123 } else if (pdata->default_mode == USB_PERIPHERAL) {
1124 set_bit(ID, &motg->inputs);
1125 set_bit(B_SESS_VLD, &motg->inputs);
1126 } else {
1127 set_bit(ID, &motg->inputs); 1149 set_bit(ID, &motg->inputs);
1128 clear_bit(B_SESS_VLD, &motg->inputs); 1150 clear_bit(B_SESS_VLD, &motg->inputs);
1129 }
1130 } 1151 }
1131 break; 1152 break;
1132 case USB_HOST: 1153 case USB_DR_MODE_HOST:
1133 clear_bit(ID, &motg->inputs); 1154 clear_bit(ID, &motg->inputs);
1134 break; 1155 break;
1135 case USB_PERIPHERAL: 1156 case USB_DR_MODE_PERIPHERAL:
1136 set_bit(ID, &motg->inputs); 1157 set_bit(ID, &motg->inputs);
1137 if (otgsc & OTGSC_BSV) 1158 if (otgsc & OTGSC_BSV)
1138 set_bit(B_SESS_VLD, &motg->inputs); 1159 set_bit(B_SESS_VLD, &motg->inputs);
@@ -1282,13 +1303,13 @@ static int msm_otg_mode_show(struct seq_file *s, void *unused)
1282 1303
1283 switch (otg->phy->state) { 1304 switch (otg->phy->state) {
1284 case OTG_STATE_A_HOST: 1305 case OTG_STATE_A_HOST:
1285 seq_printf(s, "host\n"); 1306 seq_puts(s, "host\n");
1286 break; 1307 break;
1287 case OTG_STATE_B_PERIPHERAL: 1308 case OTG_STATE_B_PERIPHERAL:
1288 seq_printf(s, "peripheral\n"); 1309 seq_puts(s, "peripheral\n");
1289 break; 1310 break;
1290 default: 1311 default:
1291 seq_printf(s, "none\n"); 1312 seq_puts(s, "none\n");
1292 break; 1313 break;
1293 } 1314 }
1294 1315
@@ -1308,7 +1329,7 @@ static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1308 char buf[16]; 1329 char buf[16];
1309 struct usb_otg *otg = motg->phy.otg; 1330 struct usb_otg *otg = motg->phy.otg;
1310 int status = count; 1331 int status = count;
1311 enum usb_mode_type req_mode; 1332 enum usb_dr_mode req_mode;
1312 1333
1313 memset(buf, 0x00, sizeof(buf)); 1334 memset(buf, 0x00, sizeof(buf));
1314 1335
@@ -1318,18 +1339,18 @@ static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1318 } 1339 }
1319 1340
1320 if (!strncmp(buf, "host", 4)) { 1341 if (!strncmp(buf, "host", 4)) {
1321 req_mode = USB_HOST; 1342 req_mode = USB_DR_MODE_HOST;
1322 } else if (!strncmp(buf, "peripheral", 10)) { 1343 } else if (!strncmp(buf, "peripheral", 10)) {
1323 req_mode = USB_PERIPHERAL; 1344 req_mode = USB_DR_MODE_PERIPHERAL;
1324 } else if (!strncmp(buf, "none", 4)) { 1345 } else if (!strncmp(buf, "none", 4)) {
1325 req_mode = USB_NONE; 1346 req_mode = USB_DR_MODE_UNKNOWN;
1326 } else { 1347 } else {
1327 status = -EINVAL; 1348 status = -EINVAL;
1328 goto out; 1349 goto out;
1329 } 1350 }
1330 1351
1331 switch (req_mode) { 1352 switch (req_mode) {
1332 case USB_NONE: 1353 case USB_DR_MODE_UNKNOWN:
1333 switch (otg->phy->state) { 1354 switch (otg->phy->state) {
1334 case OTG_STATE_A_HOST: 1355 case OTG_STATE_A_HOST:
1335 case OTG_STATE_B_PERIPHERAL: 1356 case OTG_STATE_B_PERIPHERAL:
@@ -1340,7 +1361,7 @@ static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1340 goto out; 1361 goto out;
1341 } 1362 }
1342 break; 1363 break;
1343 case USB_PERIPHERAL: 1364 case USB_DR_MODE_PERIPHERAL:
1344 switch (otg->phy->state) { 1365 switch (otg->phy->state) {
1345 case OTG_STATE_B_IDLE: 1366 case OTG_STATE_B_IDLE:
1346 case OTG_STATE_A_HOST: 1367 case OTG_STATE_A_HOST:
@@ -1351,7 +1372,7 @@ static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1351 goto out; 1372 goto out;
1352 } 1373 }
1353 break; 1374 break;
1354 case USB_HOST: 1375 case USB_DR_MODE_HOST:
1355 switch (otg->phy->state) { 1376 switch (otg->phy->state) {
1356 case OTG_STATE_B_IDLE: 1377 case OTG_STATE_B_IDLE:
1357 case OTG_STATE_B_PERIPHERAL: 1378 case OTG_STATE_B_PERIPHERAL:
@@ -1406,74 +1427,154 @@ static void msm_otg_debugfs_cleanup(void)
1406 debugfs_remove(msm_otg_dbg_root); 1427 debugfs_remove(msm_otg_dbg_root);
1407} 1428}
1408 1429
1409static int __init msm_otg_probe(struct platform_device *pdev) 1430static struct of_device_id msm_otg_dt_match[] = {
1431 {
1432 .compatible = "qcom,usb-otg-ci",
1433 .data = (void *) CI_45NM_INTEGRATED_PHY
1434 },
1435 {
1436 .compatible = "qcom,usb-otg-snps",
1437 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1438 },
1439 { }
1440};
1441MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1442
1443static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1444{
1445 struct msm_otg_platform_data *pdata;
1446 const struct of_device_id *id;
1447 struct device_node *node = pdev->dev.of_node;
1448 struct property *prop;
1449 int len, ret, words;
1450 u32 val, tmp[3];
1451
1452 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1453 if (!pdata)
1454 return -ENOMEM;
1455
1456 motg->pdata = pdata;
1457
1458 id = of_match_device(msm_otg_dt_match, &pdev->dev);
1459 pdata->phy_type = (enum msm_usb_phy_type) id->data;
1460
1461 motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1462 if (IS_ERR(motg->link_rst))
1463 return PTR_ERR(motg->link_rst);
1464
1465 motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1466 if (IS_ERR(motg->phy_rst))
1467 return PTR_ERR(motg->phy_rst);
1468
1469 pdata->mode = of_usb_get_dr_mode(node);
1470 if (pdata->mode == USB_DR_MODE_UNKNOWN)
1471 pdata->mode = USB_DR_MODE_OTG;
1472
1473 pdata->otg_control = OTG_PHY_CONTROL;
1474 if (!of_property_read_u32(node, "qcom,otg-control", &val))
1475 if (val == OTG_PMIC_CONTROL)
1476 pdata->otg_control = val;
1477
1478 if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1479 motg->phy_number = val;
1480
1481 motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1482 motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1483 motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1484
1485 if (of_get_property(node, "qcom,vdd-levels", &len) &&
1486 len == sizeof(tmp)) {
1487 of_property_read_u32_array(node, "qcom,vdd-levels",
1488 tmp, len / sizeof(*tmp));
1489 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1490 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1491 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1492 }
1493
1494 prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1495 if (!prop || !len)
1496 return 0;
1497
1498 words = len / sizeof(u32);
1499
1500 if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1501 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1502 return 0;
1503 }
1504
1505 pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1506 if (!pdata->phy_init_seq) {
1507 dev_warn(&pdev->dev, "No space for PHY init sequence\n");
1508 return 0;
1509 }
1510
1511 ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1512 pdata->phy_init_seq, words);
1513 if (!ret)
1514 pdata->phy_init_sz = words;
1515
1516 return 0;
1517}
1518
1519static int msm_otg_probe(struct platform_device *pdev)
1410{ 1520{
1521 struct regulator_bulk_data regs[3];
1411 int ret = 0; 1522 int ret = 0;
1523 struct device_node *np = pdev->dev.of_node;
1524 struct msm_otg_platform_data *pdata;
1412 struct resource *res; 1525 struct resource *res;
1413 struct msm_otg *motg; 1526 struct msm_otg *motg;
1414 struct usb_phy *phy; 1527 struct usb_phy *phy;
1528 void __iomem *phy_select;
1415 1529
1416 dev_info(&pdev->dev, "msm_otg probe\n"); 1530 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1417 if (!dev_get_platdata(&pdev->dev)) {
1418 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1419 return -ENODEV;
1420 }
1421
1422 motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
1423 if (!motg) { 1531 if (!motg) {
1424 dev_err(&pdev->dev, "unable to allocate msm_otg\n"); 1532 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1425 return -ENOMEM; 1533 return -ENOMEM;
1426 } 1534 }
1427 1535
1428 motg->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); 1536 pdata = dev_get_platdata(&pdev->dev);
1537 if (!pdata) {
1538 if (!np)
1539 return -ENXIO;
1540 ret = msm_otg_read_dt(pdev, motg);
1541 if (ret)
1542 return ret;
1543 }
1544
1545 motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1546 GFP_KERNEL);
1429 if (!motg->phy.otg) { 1547 if (!motg->phy.otg) {
1430 dev_err(&pdev->dev, "unable to allocate msm_otg\n"); 1548 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1431 ret = -ENOMEM; 1549 return -ENOMEM;
1432 goto free_motg;
1433 } 1550 }
1434 1551
1435 motg->pdata = dev_get_platdata(&pdev->dev);
1436 phy = &motg->phy; 1552 phy = &motg->phy;
1437 phy->dev = &pdev->dev; 1553 phy->dev = &pdev->dev;
1438 1554
1439 motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk"); 1555 motg->phy_reset_clk = devm_clk_get(&pdev->dev,
1556 np ? "phy" : "usb_phy_clk");
1440 if (IS_ERR(motg->phy_reset_clk)) { 1557 if (IS_ERR(motg->phy_reset_clk)) {
1441 dev_err(&pdev->dev, "failed to get usb_phy_clk\n"); 1558 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1442 ret = PTR_ERR(motg->phy_reset_clk); 1559 return PTR_ERR(motg->phy_reset_clk);
1443 goto free_motg;
1444 } 1560 }
1445 1561
1446 motg->clk = clk_get(&pdev->dev, "usb_hs_clk"); 1562 motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1447 if (IS_ERR(motg->clk)) { 1563 if (IS_ERR(motg->clk)) {
1448 dev_err(&pdev->dev, "failed to get usb_hs_clk\n"); 1564 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1449 ret = PTR_ERR(motg->clk); 1565 return PTR_ERR(motg->clk);
1450 goto put_phy_reset_clk;
1451 } 1566 }
1452 clk_set_rate(motg->clk, 60000000);
1453 1567
1454 /* 1568 /*
1455 * If USB Core is running its protocol engine based on CORE CLK, 1569 * If USB Core is running its protocol engine based on CORE CLK,
1456 * CORE CLK must be running at >55Mhz for correct HSUSB 1570 * CORE CLK must be running at >55Mhz for correct HSUSB
1457 * operation and USB core cannot tolerate frequency changes on 1571 * operation and USB core cannot tolerate frequency changes on
1458 * CORE CLK. For such USB cores, vote for maximum clk frequency 1572 * CORE CLK.
1459 * on pclk source
1460 */ 1573 */
1461 if (motg->pdata->pclk_src_name) { 1574 motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1462 motg->pclk_src = clk_get(&pdev->dev,
1463 motg->pdata->pclk_src_name);
1464 if (IS_ERR(motg->pclk_src))
1465 goto put_clk;
1466 clk_set_rate(motg->pclk_src, INT_MAX);
1467 clk_prepare_enable(motg->pclk_src);
1468 } else
1469 motg->pclk_src = ERR_PTR(-ENOENT);
1470
1471
1472 motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
1473 if (IS_ERR(motg->pclk)) { 1575 if (IS_ERR(motg->pclk)) {
1474 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n"); 1576 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1475 ret = PTR_ERR(motg->pclk); 1577 return PTR_ERR(motg->pclk);
1476 goto put_pclk_src;
1477 } 1578 }
1478 1579
1479 /* 1580 /*
@@ -1481,69 +1582,90 @@ static int __init msm_otg_probe(struct platform_device *pdev)
1481 * clock is introduced to remove the dependency on AXI 1582 * clock is introduced to remove the dependency on AXI
1482 * bus frequency. 1583 * bus frequency.
1483 */ 1584 */
1484 motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk"); 1585 motg->core_clk = devm_clk_get(&pdev->dev,
1485 if (IS_ERR(motg->core_clk)) 1586 np ? "alt_core" : "usb_hs_core_clk");
1486 motg->core_clk = NULL;
1487 1587
1488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1588 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1489 if (!res) { 1589 if (!res)
1490 dev_err(&pdev->dev, "failed to get platform resource mem\n"); 1590 return -EINVAL;
1491 ret = -ENODEV; 1591 motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1492 goto put_core_clk; 1592 if (!motg->regs)
1493 } 1593 return -ENOMEM;
1494 1594
1495 motg->regs = ioremap(res->start, resource_size(res)); 1595 /*
1496 if (!motg->regs) { 1596 * NOTE: The PHYs can be multiplexed between the chipidea controller
1497 dev_err(&pdev->dev, "ioremap failed\n"); 1597 * and the dwc3 controller, using a single bit. It is important that
1498 ret = -ENOMEM; 1598 * the dwc3 driver does not set this bit in an incompatible way.
1499 goto put_core_clk; 1599 */
1600 if (motg->phy_number) {
1601 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1602 if (IS_ERR(phy_select))
1603 return PTR_ERR(phy_select);
1604 /* Enable second PHY with the OTG port */
1605 writel(0x1, phy_select);
1500 } 1606 }
1607
1501 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs); 1608 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1502 1609
1503 motg->irq = platform_get_irq(pdev, 0); 1610 motg->irq = platform_get_irq(pdev, 0);
1504 if (!motg->irq) { 1611 if (motg->irq < 0) {
1505 dev_err(&pdev->dev, "platform_get_irq failed\n"); 1612 dev_err(&pdev->dev, "platform_get_irq failed\n");
1506 ret = -ENODEV; 1613 return motg->irq;
1507 goto free_regs;
1508 } 1614 }
1509 1615
1616 regs[0].supply = "vddcx";
1617 regs[1].supply = "v3p3";
1618 regs[2].supply = "v1p8";
1619
1620 ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1621 if (ret)
1622 return ret;
1623
1624 motg->vddcx = regs[0].consumer;
1625 motg->v3p3 = regs[1].consumer;
1626 motg->v1p8 = regs[2].consumer;
1627
1628 clk_set_rate(motg->clk, 60000000);
1629
1510 clk_prepare_enable(motg->clk); 1630 clk_prepare_enable(motg->clk);
1511 clk_prepare_enable(motg->pclk); 1631 clk_prepare_enable(motg->pclk);
1512 1632
1633 if (!IS_ERR(motg->core_clk))
1634 clk_prepare_enable(motg->core_clk);
1635
1513 ret = msm_hsusb_init_vddcx(motg, 1); 1636 ret = msm_hsusb_init_vddcx(motg, 1);
1514 if (ret) { 1637 if (ret) {
1515 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n"); 1638 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1516 goto free_regs; 1639 goto disable_clks;
1517 } 1640 }
1518 1641
1519 ret = msm_hsusb_ldo_init(motg, 1); 1642 ret = msm_hsusb_ldo_init(motg, 1);
1520 if (ret) { 1643 if (ret) {
1521 dev_err(&pdev->dev, "hsusb vreg configuration failed\n"); 1644 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1522 goto vddcx_exit; 1645 goto disable_vddcx;
1523 } 1646 }
1524 ret = msm_hsusb_ldo_set_mode(1); 1647 ret = msm_hsusb_ldo_set_mode(motg, 1);
1525 if (ret) { 1648 if (ret) {
1526 dev_err(&pdev->dev, "hsusb vreg enable failed\n"); 1649 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1527 goto ldo_exit; 1650 goto disable_ldo;
1528 } 1651 }
1529 1652
1530 if (motg->core_clk)
1531 clk_prepare_enable(motg->core_clk);
1532
1533 writel(0, USB_USBINTR); 1653 writel(0, USB_USBINTR);
1534 writel(0, USB_OTGSC); 1654 writel(0, USB_OTGSC);
1535 1655
1536 INIT_WORK(&motg->sm_work, msm_otg_sm_work); 1656 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1537 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work); 1657 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1538 ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED, 1658 ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1539 "msm_otg", motg); 1659 "msm_otg", motg);
1540 if (ret) { 1660 if (ret) {
1541 dev_err(&pdev->dev, "request irq failed\n"); 1661 dev_err(&pdev->dev, "request irq failed\n");
1542 goto disable_clks; 1662 goto disable_ldo;
1543 } 1663 }
1544 1664
1545 phy->init = msm_otg_reset; 1665 phy->init = msm_phy_init;
1546 phy->set_power = msm_otg_set_power; 1666 phy->set_power = msm_otg_set_power;
1667 phy->notify_disconnect = msm_phy_notify_disconnect;
1668 phy->type = USB_PHY_TYPE_USB2;
1547 1669
1548 phy->io_ops = &msm_otg_io_ops; 1670 phy->io_ops = &msm_otg_io_ops;
1549 1671
@@ -1551,54 +1673,38 @@ static int __init msm_otg_probe(struct platform_device *pdev)
1551 phy->otg->set_host = msm_otg_set_host; 1673 phy->otg->set_host = msm_otg_set_host;
1552 phy->otg->set_peripheral = msm_otg_set_peripheral; 1674 phy->otg->set_peripheral = msm_otg_set_peripheral;
1553 1675
1554 ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2); 1676 msm_usb_reset(phy);
1677
1678 ret = usb_add_phy_dev(&motg->phy);
1555 if (ret) { 1679 if (ret) {
1556 dev_err(&pdev->dev, "usb_add_phy failed\n"); 1680 dev_err(&pdev->dev, "usb_add_phy failed\n");
1557 goto free_irq; 1681 goto disable_ldo;
1558 } 1682 }
1559 1683
1560 platform_set_drvdata(pdev, motg); 1684 platform_set_drvdata(pdev, motg);
1561 device_init_wakeup(&pdev->dev, 1); 1685 device_init_wakeup(&pdev->dev, 1);
1562 1686
1563 if (motg->pdata->mode == USB_OTG && 1687 if (motg->pdata->mode == USB_DR_MODE_OTG &&
1564 motg->pdata->otg_control == OTG_USER_CONTROL) { 1688 motg->pdata->otg_control == OTG_USER_CONTROL) {
1565 ret = msm_otg_debugfs_init(motg); 1689 ret = msm_otg_debugfs_init(motg);
1566 if (ret) 1690 if (ret)
1567 dev_dbg(&pdev->dev, "mode debugfs file is" 1691 dev_dbg(&pdev->dev, "Can not create mode change file\n");
1568 "not available\n");
1569 } 1692 }
1570 1693
1571 pm_runtime_set_active(&pdev->dev); 1694 pm_runtime_set_active(&pdev->dev);
1572 pm_runtime_enable(&pdev->dev); 1695 pm_runtime_enable(&pdev->dev);
1573 1696
1574 return 0; 1697 return 0;
1575free_irq: 1698
1576 free_irq(motg->irq, motg); 1699disable_ldo:
1700 msm_hsusb_ldo_init(motg, 0);
1701disable_vddcx:
1702 msm_hsusb_init_vddcx(motg, 0);
1577disable_clks: 1703disable_clks:
1578 clk_disable_unprepare(motg->pclk); 1704 clk_disable_unprepare(motg->pclk);
1579 clk_disable_unprepare(motg->clk); 1705 clk_disable_unprepare(motg->clk);
1580ldo_exit: 1706 if (!IS_ERR(motg->core_clk))
1581 msm_hsusb_ldo_init(motg, 0); 1707 clk_disable_unprepare(motg->core_clk);
1582vddcx_exit:
1583 msm_hsusb_init_vddcx(motg, 0);
1584free_regs:
1585 iounmap(motg->regs);
1586put_core_clk:
1587 if (motg->core_clk)
1588 clk_put(motg->core_clk);
1589 clk_put(motg->pclk);
1590put_pclk_src:
1591 if (!IS_ERR(motg->pclk_src)) {
1592 clk_disable_unprepare(motg->pclk_src);
1593 clk_put(motg->pclk_src);
1594 }
1595put_clk:
1596 clk_put(motg->clk);
1597put_phy_reset_clk:
1598 clk_put(motg->phy_reset_clk);
1599free_motg:
1600 kfree(motg->phy.otg);
1601 kfree(motg);
1602 return ret; 1708 return ret;
1603} 1709}
1604 1710
@@ -1621,7 +1727,7 @@ static int msm_otg_remove(struct platform_device *pdev)
1621 pm_runtime_disable(&pdev->dev); 1727 pm_runtime_disable(&pdev->dev);
1622 1728
1623 usb_remove_phy(phy); 1729 usb_remove_phy(phy);
1624 free_irq(motg->irq, motg); 1730 disable_irq(motg->irq);
1625 1731
1626 /* 1732 /*
1627 * Put PHY in low power mode. 1733 * Put PHY in low power mode.
@@ -1641,26 +1747,12 @@ static int msm_otg_remove(struct platform_device *pdev)
1641 1747
1642 clk_disable_unprepare(motg->pclk); 1748 clk_disable_unprepare(motg->pclk);
1643 clk_disable_unprepare(motg->clk); 1749 clk_disable_unprepare(motg->clk);
1644 if (motg->core_clk) 1750 if (!IS_ERR(motg->core_clk))
1645 clk_disable_unprepare(motg->core_clk); 1751 clk_disable_unprepare(motg->core_clk);
1646 if (!IS_ERR(motg->pclk_src)) {
1647 clk_disable_unprepare(motg->pclk_src);
1648 clk_put(motg->pclk_src);
1649 }
1650 msm_hsusb_ldo_init(motg, 0); 1752 msm_hsusb_ldo_init(motg, 0);
1651 1753
1652 iounmap(motg->regs);
1653 pm_runtime_set_suspended(&pdev->dev); 1754 pm_runtime_set_suspended(&pdev->dev);
1654 1755
1655 clk_put(motg->phy_reset_clk);
1656 clk_put(motg->pclk);
1657 clk_put(motg->clk);
1658 if (motg->core_clk)
1659 clk_put(motg->core_clk);
1660
1661 kfree(motg->phy.otg);
1662 kfree(motg);
1663
1664 return 0; 1756 return 0;
1665} 1757}
1666 1758
@@ -1740,15 +1832,17 @@ static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1740}; 1832};
1741 1833
1742static struct platform_driver msm_otg_driver = { 1834static struct platform_driver msm_otg_driver = {
1835 .probe = msm_otg_probe,
1743 .remove = msm_otg_remove, 1836 .remove = msm_otg_remove,
1744 .driver = { 1837 .driver = {
1745 .name = DRIVER_NAME, 1838 .name = DRIVER_NAME,
1746 .owner = THIS_MODULE, 1839 .owner = THIS_MODULE,
1747 .pm = &msm_otg_dev_pm_ops, 1840 .pm = &msm_otg_dev_pm_ops,
1841 .of_match_table = msm_otg_dt_match,
1748 }, 1842 },
1749}; 1843};
1750 1844
1751module_platform_driver_probe(msm_otg_driver, msm_otg_probe); 1845module_platform_driver(msm_otg_driver);
1752 1846
1753MODULE_LICENSE("GPL v2"); 1847MODULE_LICENSE("GPL v2");
1754MODULE_DESCRIPTION("MSM USB transceiver driver"); 1848MODULE_DESCRIPTION("MSM USB transceiver driver");
diff --git a/drivers/usb/phy/phy-mv-u3d-usb.c b/drivers/usb/phy/phy-mv-u3d-usb.c
deleted file mode 100644
index d317903022bf..000000000000
--- a/drivers/usb/phy/phy-mv-u3d-usb.c
+++ /dev/null
@@ -1,338 +0,0 @@
1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/usb/otg.h>
16#include <linux/platform_data/mv_usb.h>
17
18#include "phy-mv-u3d-usb.h"
19
20/*
21 * struct mv_u3d_phy - transceiver driver state
22 * @phy: transceiver structure
23 * @dev: The parent device supplied to the probe function
24 * @clk: usb phy clock
25 * @base: usb phy register memory base
26 */
27struct mv_u3d_phy {
28 struct usb_phy phy;
29 struct mv_usb_platform_data *plat;
30 struct device *dev;
31 struct clk *clk;
32 void __iomem *base;
33};
34
35static u32 mv_u3d_phy_read(void __iomem *base, u32 reg)
36{
37 void __iomem *addr, *data;
38
39 addr = base;
40 data = base + 0x4;
41
42 writel_relaxed(reg, addr);
43 return readl_relaxed(data);
44}
45
46static void mv_u3d_phy_set(void __iomem *base, u32 reg, u32 value)
47{
48 void __iomem *addr, *data;
49 u32 tmp;
50
51 addr = base;
52 data = base + 0x4;
53
54 writel_relaxed(reg, addr);
55 tmp = readl_relaxed(data);
56 tmp |= value;
57 writel_relaxed(tmp, data);
58}
59
60static void mv_u3d_phy_clear(void __iomem *base, u32 reg, u32 value)
61{
62 void __iomem *addr, *data;
63 u32 tmp;
64
65 addr = base;
66 data = base + 0x4;
67
68 writel_relaxed(reg, addr);
69 tmp = readl_relaxed(data);
70 tmp &= ~value;
71 writel_relaxed(tmp, data);
72}
73
74static void mv_u3d_phy_write(void __iomem *base, u32 reg, u32 value)
75{
76 void __iomem *addr, *data;
77
78 addr = base;
79 data = base + 0x4;
80
81 writel_relaxed(reg, addr);
82 writel_relaxed(value, data);
83}
84
85static void mv_u3d_phy_shutdown(struct usb_phy *phy)
86{
87 struct mv_u3d_phy *mv_u3d_phy;
88 void __iomem *base;
89 u32 val;
90
91 mv_u3d_phy = container_of(phy, struct mv_u3d_phy, phy);
92 base = mv_u3d_phy->base;
93
94 /* Power down Reference Analog current, bit 15
95 * Power down PLL, bit 14
96 * Power down Receiver, bit 13
97 * Power down Transmitter, bit 12
98 * of USB3_POWER_PLL_CONTROL register
99 */
100 val = mv_u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
101 val &= ~(USB3_POWER_PLL_CONTROL_PU);
102 mv_u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
103
104 if (mv_u3d_phy->clk)
105 clk_disable(mv_u3d_phy->clk);
106}
107
108static int mv_u3d_phy_init(struct usb_phy *phy)
109{
110 struct mv_u3d_phy *mv_u3d_phy;
111 void __iomem *base;
112 u32 val, count;
113
114 /* enable usb3 phy */
115 mv_u3d_phy = container_of(phy, struct mv_u3d_phy, phy);
116
117 if (mv_u3d_phy->clk)
118 clk_enable(mv_u3d_phy->clk);
119
120 base = mv_u3d_phy->base;
121
122 val = mv_u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
123 val &= ~(USB3_POWER_PLL_CONTROL_PU_MASK);
124 val |= 0xF << USB3_POWER_PLL_CONTROL_PU_SHIFT;
125 mv_u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
126 udelay(100);
127
128 mv_u3d_phy_write(base, USB3_RESET_CONTROL,
129 USB3_RESET_CONTROL_RESET_PIPE);
130 udelay(100);
131
132 mv_u3d_phy_write(base, USB3_RESET_CONTROL,
133 USB3_RESET_CONTROL_RESET_PIPE
134 | USB3_RESET_CONTROL_RESET_PHY);
135 udelay(100);
136
137 val = mv_u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
138 val &= ~(USB3_POWER_PLL_CONTROL_REF_FREF_SEL_MASK
139 | USB3_POWER_PLL_CONTROL_PHY_MODE_MASK);
140 val |= (USB3_PLL_25MHZ << USB3_POWER_PLL_CONTROL_REF_FREF_SEL_SHIFT)
141 | (0x5 << USB3_POWER_PLL_CONTROL_PHY_MODE_SHIFT);
142 mv_u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
143 udelay(100);
144
145 mv_u3d_phy_clear(base, USB3_KVCO_CALI_CONTROL,
146 USB3_KVCO_CALI_CONTROL_USE_MAX_PLL_RATE_MASK);
147 udelay(100);
148
149 val = mv_u3d_phy_read(base, USB3_SQUELCH_FFE);
150 val &= ~(USB3_SQUELCH_FFE_FFE_CAP_SEL_MASK
151 | USB3_SQUELCH_FFE_FFE_RES_SEL_MASK
152 | USB3_SQUELCH_FFE_SQ_THRESH_IN_MASK);
153 val |= ((0xD << USB3_SQUELCH_FFE_FFE_CAP_SEL_SHIFT)
154 | (0x7 << USB3_SQUELCH_FFE_FFE_RES_SEL_SHIFT)
155 | (0x8 << USB3_SQUELCH_FFE_SQ_THRESH_IN_SHIFT));
156 mv_u3d_phy_write(base, USB3_SQUELCH_FFE, val);
157 udelay(100);
158
159 val = mv_u3d_phy_read(base, USB3_GEN1_SET0);
160 val &= ~USB3_GEN1_SET0_G1_TX_SLEW_CTRL_EN_MASK;
161 val |= 1 << USB3_GEN1_SET0_G1_TX_EMPH_EN_SHIFT;
162 mv_u3d_phy_write(base, USB3_GEN1_SET0, val);
163 udelay(100);
164
165 val = mv_u3d_phy_read(base, USB3_GEN2_SET0);
166 val &= ~(USB3_GEN2_SET0_G2_TX_AMP_MASK
167 | USB3_GEN2_SET0_G2_TX_EMPH_AMP_MASK
168 | USB3_GEN2_SET0_G2_TX_SLEW_CTRL_EN_MASK);
169 val |= ((0x14 << USB3_GEN2_SET0_G2_TX_AMP_SHIFT)
170 | (1 << USB3_GEN2_SET0_G2_TX_AMP_ADJ_SHIFT)
171 | (0xA << USB3_GEN2_SET0_G2_TX_EMPH_AMP_SHIFT)
172 | (1 << USB3_GEN2_SET0_G2_TX_EMPH_EN_SHIFT));
173 mv_u3d_phy_write(base, USB3_GEN2_SET0, val);
174 udelay(100);
175
176 mv_u3d_phy_read(base, USB3_TX_EMPPH);
177 val &= ~(USB3_TX_EMPPH_AMP_MASK
178 | USB3_TX_EMPPH_EN_MASK
179 | USB3_TX_EMPPH_AMP_FORCE_MASK
180 | USB3_TX_EMPPH_PAR1_MASK
181 | USB3_TX_EMPPH_PAR2_MASK);
182 val |= ((0xB << USB3_TX_EMPPH_AMP_SHIFT)
183 | (1 << USB3_TX_EMPPH_EN_SHIFT)
184 | (1 << USB3_TX_EMPPH_AMP_FORCE_SHIFT)
185 | (0x1C << USB3_TX_EMPPH_PAR1_SHIFT)
186 | (1 << USB3_TX_EMPPH_PAR2_SHIFT));
187
188 mv_u3d_phy_write(base, USB3_TX_EMPPH, val);
189 udelay(100);
190
191 val = mv_u3d_phy_read(base, USB3_GEN2_SET1);
192 val &= ~(USB3_GEN2_SET1_G2_RX_SELMUPI_MASK
193 | USB3_GEN2_SET1_G2_RX_SELMUPF_MASK
194 | USB3_GEN2_SET1_G2_RX_SELMUFI_MASK
195 | USB3_GEN2_SET1_G2_RX_SELMUFF_MASK);
196 val |= ((1 << USB3_GEN2_SET1_G2_RX_SELMUPI_SHIFT)
197 | (1 << USB3_GEN2_SET1_G2_RX_SELMUPF_SHIFT)
198 | (1 << USB3_GEN2_SET1_G2_RX_SELMUFI_SHIFT)
199 | (1 << USB3_GEN2_SET1_G2_RX_SELMUFF_SHIFT));
200 mv_u3d_phy_write(base, USB3_GEN2_SET1, val);
201 udelay(100);
202
203 val = mv_u3d_phy_read(base, USB3_DIGITAL_LOOPBACK_EN);
204 val &= ~USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_MASK;
205 val |= 1 << USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_SHIFT;
206 mv_u3d_phy_write(base, USB3_DIGITAL_LOOPBACK_EN, val);
207 udelay(100);
208
209 val = mv_u3d_phy_read(base, USB3_IMPEDANCE_TX_SSC);
210 val &= ~USB3_IMPEDANCE_TX_SSC_SSC_AMP_MASK;
211 val |= 0xC << USB3_IMPEDANCE_TX_SSC_SSC_AMP_SHIFT;
212 mv_u3d_phy_write(base, USB3_IMPEDANCE_TX_SSC, val);
213 udelay(100);
214
215 val = mv_u3d_phy_read(base, USB3_IMPEDANCE_CALI_CTRL);
216 val &= ~USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_MASK;
217 val |= 0x4 << USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_SHIFT;
218 mv_u3d_phy_write(base, USB3_IMPEDANCE_CALI_CTRL, val);
219 udelay(100);
220
221 val = mv_u3d_phy_read(base, USB3_PHY_ISOLATION_MODE);
222 val &= ~(USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_MASK
223 | USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_MASK
224 | USB3_PHY_ISOLATION_MODE_TX_DRV_IDLE_MASK);
225 val |= ((1 << USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_SHIFT)
226 | (1 << USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_SHIFT));
227 mv_u3d_phy_write(base, USB3_PHY_ISOLATION_MODE, val);
228 udelay(100);
229
230 val = mv_u3d_phy_read(base, USB3_TXDETRX);
231 val &= ~(USB3_TXDETRX_VTHSEL_MASK);
232 val |= 0x1 << USB3_TXDETRX_VTHSEL_SHIFT;
233 mv_u3d_phy_write(base, USB3_TXDETRX, val);
234 udelay(100);
235
236 dev_dbg(mv_u3d_phy->dev, "start calibration\n");
237
238calstart:
239 /* Perform Manual Calibration */
240 mv_u3d_phy_set(base, USB3_KVCO_CALI_CONTROL,
241 1 << USB3_KVCO_CALI_CONTROL_CAL_START_SHIFT);
242
243 mdelay(1);
244
245 count = 0;
246 while (1) {
247 val = mv_u3d_phy_read(base, USB3_KVCO_CALI_CONTROL);
248 if (val & (1 << USB3_KVCO_CALI_CONTROL_CAL_DONE_SHIFT))
249 break;
250 else if (count > 50) {
251 dev_dbg(mv_u3d_phy->dev, "calibration failure, retry...\n");
252 goto calstart;
253 }
254 count++;
255 mdelay(1);
256 }
257
258 /* active PIPE interface */
259 mv_u3d_phy_write(base, USB3_PIPE_SM_CTRL,
260 1 << USB3_PIPE_SM_CTRL_PHY_INIT_DONE);
261
262 return 0;
263}
264
265static int mv_u3d_phy_probe(struct platform_device *pdev)
266{
267 struct mv_u3d_phy *mv_u3d_phy;
268 struct mv_usb_platform_data *pdata;
269 struct device *dev = &pdev->dev;
270 struct resource *res;
271 void __iomem *phy_base;
272 int ret;
273
274 pdata = dev_get_platdata(&pdev->dev);
275 if (!pdata) {
276 dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
277 return -EINVAL;
278 }
279
280 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
281 phy_base = devm_ioremap_resource(dev, res);
282 if (IS_ERR(phy_base))
283 return PTR_ERR(phy_base);
284
285 mv_u3d_phy = devm_kzalloc(dev, sizeof(*mv_u3d_phy), GFP_KERNEL);
286 if (!mv_u3d_phy)
287 return -ENOMEM;
288
289 mv_u3d_phy->dev = &pdev->dev;
290 mv_u3d_phy->plat = pdata;
291 mv_u3d_phy->base = phy_base;
292 mv_u3d_phy->phy.dev = mv_u3d_phy->dev;
293 mv_u3d_phy->phy.label = "mv-u3d-phy";
294 mv_u3d_phy->phy.init = mv_u3d_phy_init;
295 mv_u3d_phy->phy.shutdown = mv_u3d_phy_shutdown;
296
297 ret = usb_add_phy(&mv_u3d_phy->phy, USB_PHY_TYPE_USB3);
298 if (ret)
299 goto err;
300
301 if (!mv_u3d_phy->clk)
302 mv_u3d_phy->clk = clk_get(mv_u3d_phy->dev, "u3dphy");
303
304 platform_set_drvdata(pdev, mv_u3d_phy);
305
306 dev_info(&pdev->dev, "Initialized Marvell USB 3.0 PHY\n");
307err:
308 return ret;
309}
310
311static int mv_u3d_phy_remove(struct platform_device *pdev)
312{
313 struct mv_u3d_phy *mv_u3d_phy = platform_get_drvdata(pdev);
314
315 usb_remove_phy(&mv_u3d_phy->phy);
316
317 if (mv_u3d_phy->clk) {
318 clk_put(mv_u3d_phy->clk);
319 mv_u3d_phy->clk = NULL;
320 }
321
322 return 0;
323}
324
325static struct platform_driver mv_u3d_phy_driver = {
326 .probe = mv_u3d_phy_probe,
327 .remove = mv_u3d_phy_remove,
328 .driver = {
329 .name = "mv-u3d-phy",
330 .owner = THIS_MODULE,
331 },
332};
333
334module_platform_driver(mv_u3d_phy_driver);
335MODULE_DESCRIPTION("Marvell USB 3.0 PHY controller");
336MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>");
337MODULE_LICENSE("GPL");
338MODULE_ALIAS("platform:mv-u3d-phy");
diff --git a/drivers/usb/phy/phy-mv-u3d-usb.h b/drivers/usb/phy/phy-mv-u3d-usb.h
deleted file mode 100644
index 2a658cb9a527..000000000000
--- a/drivers/usb/phy/phy-mv-u3d-usb.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 */
8
9#ifndef __MV_U3D_PHY_H
10#define __MV_U3D_PHY_H
11
12#define USB3_POWER_PLL_CONTROL 0x1
13#define USB3_KVCO_CALI_CONTROL 0x2
14#define USB3_IMPEDANCE_CALI_CTRL 0x3
15#define USB3_IMPEDANCE_TX_SSC 0x4
16#define USB3_SQUELCH_FFE 0x6
17#define USB3_GEN1_SET0 0xD
18#define USB3_GEN2_SET0 0xF
19#define USB3_GEN2_SET1 0x10
20#define USB3_DIGITAL_LOOPBACK_EN 0x23
21#define USB3_PHY_ISOLATION_MODE 0x26
22#define USB3_TXDETRX 0x48
23#define USB3_TX_EMPPH 0x5E
24#define USB3_RESET_CONTROL 0x90
25#define USB3_PIPE_SM_CTRL 0x91
26
27#define USB3_RESET_CONTROL_RESET_PIPE 0x1
28#define USB3_RESET_CONTROL_RESET_PHY 0x2
29
30#define USB3_POWER_PLL_CONTROL_REF_FREF_SEL_MASK (0x1F << 0)
31#define USB3_POWER_PLL_CONTROL_REF_FREF_SEL_SHIFT 0
32#define USB3_PLL_25MHZ 0x2
33#define USB3_PLL_26MHZ 0x5
34#define USB3_POWER_PLL_CONTROL_PHY_MODE_MASK (0x7 << 5)
35#define USB3_POWER_PLL_CONTROL_PHY_MODE_SHIFT 5
36#define USB3_POWER_PLL_CONTROL_PU_MASK (0xF << 12)
37#define USB3_POWER_PLL_CONTROL_PU_SHIFT 12
38#define USB3_POWER_PLL_CONTROL_PU (0xF << 12)
39
40#define USB3_KVCO_CALI_CONTROL_USE_MAX_PLL_RATE_MASK (0x1 << 12)
41#define USB3_KVCO_CALI_CONTROL_USE_MAX_PLL_RATE_SHIFT 12
42#define USB3_KVCO_CALI_CONTROL_CAL_DONE_SHIFT 14
43#define USB3_KVCO_CALI_CONTROL_CAL_START_SHIFT 15
44
45#define USB3_SQUELCH_FFE_FFE_CAP_SEL_MASK 0xF
46#define USB3_SQUELCH_FFE_FFE_CAP_SEL_SHIFT 0
47#define USB3_SQUELCH_FFE_FFE_RES_SEL_MASK (0x7 << 4)
48#define USB3_SQUELCH_FFE_FFE_RES_SEL_SHIFT 4
49#define USB3_SQUELCH_FFE_SQ_THRESH_IN_MASK (0x1F << 8)
50#define USB3_SQUELCH_FFE_SQ_THRESH_IN_SHIFT 8
51
52#define USB3_GEN1_SET0_G1_TX_SLEW_CTRL_EN_MASK (0x1 << 15)
53#define USB3_GEN1_SET0_G1_TX_EMPH_EN_SHIFT 11
54
55#define USB3_GEN2_SET0_G2_TX_AMP_MASK (0x1F << 1)
56#define USB3_GEN2_SET0_G2_TX_AMP_SHIFT 1
57#define USB3_GEN2_SET0_G2_TX_AMP_ADJ_SHIFT 6
58#define USB3_GEN2_SET0_G2_TX_EMPH_AMP_MASK (0xF << 7)
59#define USB3_GEN2_SET0_G2_TX_EMPH_AMP_SHIFT 7
60#define USB3_GEN2_SET0_G2_TX_EMPH_EN_MASK (0x1 << 11)
61#define USB3_GEN2_SET0_G2_TX_EMPH_EN_SHIFT 11
62#define USB3_GEN2_SET0_G2_TX_SLEW_CTRL_EN_MASK (0x1 << 15)
63#define USB3_GEN2_SET0_G2_TX_SLEW_CTRL_EN_SHIFT 15
64
65#define USB3_GEN2_SET1_G2_RX_SELMUPI_MASK (0x7 << 0)
66#define USB3_GEN2_SET1_G2_RX_SELMUPI_SHIFT 0
67#define USB3_GEN2_SET1_G2_RX_SELMUPF_MASK (0x7 << 3)
68#define USB3_GEN2_SET1_G2_RX_SELMUPF_SHIFT 3
69#define USB3_GEN2_SET1_G2_RX_SELMUFI_MASK (0x3 << 6)
70#define USB3_GEN2_SET1_G2_RX_SELMUFI_SHIFT 6
71#define USB3_GEN2_SET1_G2_RX_SELMUFF_MASK (0x3 << 8)
72#define USB3_GEN2_SET1_G2_RX_SELMUFF_SHIFT 8
73
74#define USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_MASK (0x3 << 10)
75#define USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_SHIFT 10
76
77#define USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_MASK (0x7 << 12)
78#define USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_SHIFT 12
79
80#define USB3_IMPEDANCE_TX_SSC_SSC_AMP_MASK (0x3F << 0)
81#define USB3_IMPEDANCE_TX_SSC_SSC_AMP_SHIFT 0
82
83#define USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_MASK 0xF
84#define USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_SHIFT 0
85#define USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_MASK (0xF << 4)
86#define USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_SHIFT 4
87#define USB3_PHY_ISOLATION_MODE_TX_DRV_IDLE_MASK (0x1 << 8)
88
89#define USB3_TXDETRX_VTHSEL_MASK (0x3 << 4)
90#define USB3_TXDETRX_VTHSEL_SHIFT 4
91
92#define USB3_TX_EMPPH_AMP_MASK (0xF << 0)
93#define USB3_TX_EMPPH_AMP_SHIFT 0
94#define USB3_TX_EMPPH_EN_MASK (0x1 << 6)
95#define USB3_TX_EMPPH_EN_SHIFT 6
96#define USB3_TX_EMPPH_AMP_FORCE_MASK (0x1 << 7)
97#define USB3_TX_EMPPH_AMP_FORCE_SHIFT 7
98#define USB3_TX_EMPPH_PAR1_MASK (0x1F << 8)
99#define USB3_TX_EMPPH_PAR1_SHIFT 8
100#define USB3_TX_EMPPH_PAR2_MASK (0x1 << 13)
101#define USB3_TX_EMPPH_PAR2_SHIFT 13
102
103#define USB3_PIPE_SM_CTRL_PHY_INIT_DONE 15
104
105#endif /* __MV_U3D_PHY_H */
diff --git a/drivers/usb/phy/phy-ulpi.c b/drivers/usb/phy/phy-ulpi.c
index 17ea3f271bd8..4e3877c329f2 100644
--- a/drivers/usb/phy/phy-ulpi.c
+++ b/drivers/usb/phy/phy-ulpi.c
@@ -48,6 +48,7 @@ static struct ulpi_info ulpi_ids[] = {
48 ULPI_INFO(ULPI_ID(0x04cc, 0x1504), "NXP ISP1504"), 48 ULPI_INFO(ULPI_ID(0x04cc, 0x1504), "NXP ISP1504"),
49 ULPI_INFO(ULPI_ID(0x0424, 0x0006), "SMSC USB331x"), 49 ULPI_INFO(ULPI_ID(0x0424, 0x0006), "SMSC USB331x"),
50 ULPI_INFO(ULPI_ID(0x0424, 0x0007), "SMSC USB3320"), 50 ULPI_INFO(ULPI_ID(0x0424, 0x0007), "SMSC USB3320"),
51 ULPI_INFO(ULPI_ID(0x0424, 0x0009), "SMSC USB334x"),
51 ULPI_INFO(ULPI_ID(0x0451, 0x1507), "TI TUSB1210"), 52 ULPI_INFO(ULPI_ID(0x0451, 0x1507), "TI TUSB1210"),
52}; 53};
53 54
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 08:32:37 -0400