usb: phy: omap-usb3: fix dpll clock index

Correction of the omap_usb3_dpll_params array when the sys_clk_rate is
20MHz.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c
index efe6e1464f45..a2fb30bbb971 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/usb/phy/phy-omap-usb3.c
@@ -71,9 +71,9 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
         {1250, 5, 4, 20, 0},            /* 12 MHz */
         {3125, 20, 4, 20, 0},           /* 16.8 MHz */
         {1172, 8, 4, 20, 65537},        /* 19.2 MHz */
+        {1000, 7, 4, 10, 0},            /* 20 MHz */
         {1250, 12, 4, 20, 0},           /* 26 MHz */
         {3125, 47, 4, 20, 92843},       /* 38.4 MHz */
-        {1000, 7, 4, 10, 0},            /* 20 MHz */
 
 };