aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/usb/phy
diff options
context:
space:
mode:
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2013-06-08 16:34:36 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-06-11 03:11:16 -0400
commit54407f190c8d542572a9547ba5460d811810b6e4 (patch)
treea5551de41842e27e0e806418ad76990c09a52708 /drivers/usb/phy
parent7173e59e6b5f9cbde3ece66ae664454edcac6382 (diff)
phy-rcar-usb: add R8A7778 support
The driver currently only supports R8A7779 SoC. Compared to it, R8A7778 USB-PHY has extra register range containing two high-speed signal quality characteristic control registers which should be set up during USB-PHY startup depending on whether a ferrite bead is in use or not. So, we now handle an optional second memory range in the driver's probe method, add the 'ferrite_bead' field to the driver's platform data, and add an extra (optional) step to the USB-PHY startup routine which sets up the extended registers. Also mark in the driver's Kconfig section that R8A7778 is now supported and generally clarify that section, uppercasing the word "phy" and also changing the module name that got lost in the big driver rename, while at it... The patch has been tested on the Marzen and BOCK-W boards. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/usb/phy')
-rw-r--r--drivers/usb/phy/Kconfig10
-rw-r--r--drivers/usb/phy/phy-rcar-usb.c37
2 files changed, 36 insertions, 11 deletions
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 371d0e74e909..ac0b98f78c70 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -181,15 +181,15 @@ config USB_MXS_PHY
181 MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x. 181 MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
182 182
183config USB_RCAR_PHY 183config USB_RCAR_PHY
184 tristate "Renesas R-Car USB phy support" 184 tristate "Renesas R-Car USB PHY support"
185 depends on USB || USB_GADGET 185 depends on USB || USB_GADGET
186 help 186 help
187 Say Y here to add support for the Renesas R-Car USB phy driver. 187 Say Y here to add support for the Renesas R-Car USB common PHY driver.
188 This chip is typically used as USB phy for USB host, gadget. 188 This chip is typically used as USB PHY for USB host, gadget.
189 This driver supports: R8A7779 189 This driver supports R8A7778 and R8A7779.
190 190
191 To compile this driver as a module, choose M here: the 191 To compile this driver as a module, choose M here: the
192 module will be called rcar-phy. 192 module will be called phy-rcar-usb.
193 193
194config USB_ULPI 194config USB_ULPI
195 bool "Generic ULPI Transceiver Driver" 195 bool "Generic ULPI Transceiver Driver"
diff --git a/drivers/usb/phy/phy-rcar-usb.c b/drivers/usb/phy/phy-rcar-usb.c
index 823b2bb807d2..ae909408958d 100644
--- a/drivers/usb/phy/phy-rcar-usb.c
+++ b/drivers/usb/phy/phy-rcar-usb.c
@@ -26,15 +26,21 @@
26#define USBOH0 0x1C 26#define USBOH0 0x1C
27#define USBCTL0 0x58 27#define USBCTL0 0x58
28 28
29/* High-speed signal quality characteristic control registers (R8A7778 only) */
30#define HSQCTL1 0x24
31#define HSQCTL2 0x28
32
29/* USBPCTRL0 */ 33/* USBPCTRL0 */
30#define OVC2 (1 << 10) /* Switches the OVC input pin for port 2: */ 34#define OVC2 (1 << 10) /* (R8A7779 only) */
35 /* Switches the OVC input pin for port 2: */
31 /* 1: USB_OVC2, 0: OVC2 */ 36 /* 1: USB_OVC2, 0: OVC2 */
32#define OVC1_VBUS1 (1 << 9) /* Switches the OVC input pin for port 1: */ 37#define OVC1_VBUS1 (1 << 9) /* Switches the OVC input pin for port 1: */
33 /* 1: USB_OVC1, 0: OVC1/VBUS1 */ 38 /* 1: USB_OVC1, 0: OVC1/VBUS1 */
34 /* Function mode: set to 0 */ 39 /* Function mode: set to 0 */
35#define OVC0 (1 << 8) /* Switches the OVC input pin for port 0: */ 40#define OVC0 (1 << 8) /* Switches the OVC input pin for port 0: */
36 /* 1: USB_OVC0 pin, 0: OVC0 */ 41 /* 1: USB_OVC0 pin, 0: OVC0 */
37#define OVC2_ACT (1 << 6) /* Host mode: OVC2 polarity: */ 42#define OVC2_ACT (1 << 6) /* (R8A7779 only) */
43 /* Host mode: OVC2 polarity: */
38 /* 1: active-high, 0: active-low */ 44 /* 1: active-high, 0: active-low */
39#define PENC (1 << 4) /* Function mode: output level of PENC1 pin: */ 45#define PENC (1 << 4) /* Function mode: output level of PENC1 pin: */
40 /* 1: high, 0: low */ 46 /* 1: high, 0: low */
@@ -59,6 +65,7 @@ struct rcar_usb_phy_priv {
59 spinlock_t lock; 65 spinlock_t lock;
60 66
61 void __iomem *reg0; 67 void __iomem *reg0;
68 void __iomem *reg1;
62 int counter; 69 int counter;
63}; 70};
64 71
@@ -78,6 +85,7 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
78 struct device *dev = phy->dev; 85 struct device *dev = phy->dev;
79 struct rcar_phy_platform_data *pdata = dev->platform_data; 86 struct rcar_phy_platform_data *pdata = dev->platform_data;
80 void __iomem *reg0 = priv->reg0; 87 void __iomem *reg0 = priv->reg0;
88 void __iomem *reg1 = priv->reg1;
81 static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT }; 89 static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT };
82 int i; 90 int i;
83 u32 val; 91 u32 val;
@@ -96,7 +104,16 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
96 /* (2) start USB-PHY internal PLL */ 104 /* (2) start USB-PHY internal PLL */
97 iowrite32(PHY_ENB | PLL_ENB, (reg0 + USBPCTRL1)); 105 iowrite32(PHY_ENB | PLL_ENB, (reg0 + USBPCTRL1));
98 106
99 /* (3) USB module status check */ 107 /* (3) set USB-PHY in accord with the conditions of usage */
108 if (reg1) {
109 u32 hsqctl1 = pdata->ferrite_bead ? 0x41 : 0;
110 u32 hsqctl2 = pdata->ferrite_bead ? 0x0d : 7;
111
112 iowrite32(hsqctl1, reg1 + HSQCTL1);
113 iowrite32(hsqctl2, reg1 + HSQCTL2);
114 }
115
116 /* (4) USB module status check */
100 for (i = 0; i < 1024; i++) { 117 for (i = 0; i < 1024; i++) {
101 udelay(10); 118 udelay(10);
102 val = ioread32(reg0 + USBST); 119 val = ioread32(reg0 + USBST);
@@ -109,7 +126,7 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
109 goto phy_init_end; 126 goto phy_init_end;
110 } 127 }
111 128
112 /* (4) USB-PHY reset clear */ 129 /* (5) USB-PHY reset clear */
113 iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1)); 130 iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1));
114 131
115 /* Board specific port settings */ 132 /* Board specific port settings */
@@ -162,9 +179,9 @@ static void rcar_usb_phy_shutdown(struct usb_phy *phy)
162static int rcar_usb_phy_probe(struct platform_device *pdev) 179static int rcar_usb_phy_probe(struct platform_device *pdev)
163{ 180{
164 struct rcar_usb_phy_priv *priv; 181 struct rcar_usb_phy_priv *priv;
165 struct resource *res0; 182 struct resource *res0, *res1;
166 struct device *dev = &pdev->dev; 183 struct device *dev = &pdev->dev;
167 void __iomem *reg0; 184 void __iomem *reg0, *reg1 = NULL;
168 int ret; 185 int ret;
169 186
170 if (!pdev->dev.platform_data) { 187 if (!pdev->dev.platform_data) {
@@ -182,6 +199,13 @@ static int rcar_usb_phy_probe(struct platform_device *pdev)
182 if (IS_ERR(reg0)) 199 if (IS_ERR(reg0))
183 return PTR_ERR(reg0); 200 return PTR_ERR(reg0);
184 201
202 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
203 if (res1) {
204 reg1 = devm_ioremap_resource(dev, res1);
205 if (IS_ERR(reg1))
206 return PTR_ERR(reg1);
207 }
208
185 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 209 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
186 if (!priv) { 210 if (!priv) {
187 dev_err(dev, "priv data allocation error\n"); 211 dev_err(dev, "priv data allocation error\n");
@@ -189,6 +213,7 @@ static int rcar_usb_phy_probe(struct platform_device *pdev)
189 } 213 }
190 214
191 priv->reg0 = reg0; 215 priv->reg0 = reg0;
216 priv->reg1 = reg1;
192 priv->counter = 0; 217 priv->counter = 0;
193 priv->phy.dev = dev; 218 priv->phy.dev = dev;
194 priv->phy.label = dev_name(dev); 219 priv->phy.label = dev_name(dev);