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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/usb/musb
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/usb/musb')
-rw-r--r--drivers/usb/musb/Kconfig13
-rw-r--r--drivers/usb/musb/Makefile2
-rw-r--r--drivers/usb/musb/blackfin.c153
-rw-r--r--drivers/usb/musb/blackfin.h39
-rw-r--r--drivers/usb/musb/cppi_dma.c40
-rw-r--r--drivers/usb/musb/davinci.c7
-rw-r--r--drivers/usb/musb/musb_core.c672
-rw-r--r--drivers/usb/musb/musb_core.h68
-rw-r--r--drivers/usb/musb/musb_dma.h11
-rw-r--r--drivers/usb/musb/musb_gadget.c222
-rw-r--r--drivers/usb/musb/musb_gadget.h4
-rw-r--r--drivers/usb/musb/musb_gadget_ep0.c84
-rw-r--r--drivers/usb/musb/musb_host.c47
-rw-r--r--drivers/usb/musb/musb_regs.h135
-rw-r--r--drivers/usb/musb/musb_virthub.c1
-rw-r--r--drivers/usb/musb/musbhsdma.c38
-rw-r--r--drivers/usb/musb/musbhsdma.h17
-rw-r--r--drivers/usb/musb/omap2430.c54
-rw-r--r--drivers/usb/musb/omap2430.h34
-rw-r--r--drivers/usb/musb/tusb6010.c15
-rw-r--r--drivers/usb/musb/tusb6010_omap.c29
21 files changed, 1114 insertions, 571 deletions
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index b84abd8ee8a5..07fe490b44d8 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -9,10 +9,9 @@ comment "Enable Host or Gadget support to see Inventra options"
9# (M)HDRC = (Multipoint) Highspeed Dual-Role Controller 9# (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
10config USB_MUSB_HDRC 10config USB_MUSB_HDRC
11 depends on (USB || USB_GADGET) 11 depends on (USB || USB_GADGET)
12 depends on (ARM || BLACKFIN) 12 depends on (ARM || (BF54x && !BF544) || (BF52x && !BF522 && !BF523))
13 select NOP_USB_XCEIV if ARCH_DAVINCI 13 select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN)
14 select TWL4030_USB if MACH_OMAP_3430SDP 14 select TWL4030_USB if MACH_OMAP_3430SDP
15 select NOP_USB_XCEIV if MACH_OMAP3EVM
16 select USB_OTG_UTILS 15 select USB_OTG_UTILS
17 tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)' 16 tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
18 help 17 help
@@ -38,18 +37,18 @@ config USB_MUSB_SOC
38 depends on USB_MUSB_HDRC 37 depends on USB_MUSB_HDRC
39 default y if ARCH_DAVINCI 38 default y if ARCH_DAVINCI
40 default y if ARCH_OMAP2430 39 default y if ARCH_OMAP2430
41 default y if ARCH_OMAP34XX 40 default y if ARCH_OMAP3
42 default y if (BF54x && !BF544) 41 default y if (BF54x && !BF544)
43 default y if (BF52x && !BF522 && !BF523) 42 default y if (BF52x && !BF522 && !BF523)
44 43
45comment "DaVinci 35x and 644x USB support" 44comment "DaVinci 35x and 644x USB support"
46 depends on USB_MUSB_HDRC && ARCH_DAVINCI 45 depends on USB_MUSB_HDRC && ARCH_DAVINCI_DMx
47 46
48comment "OMAP 243x high speed USB support" 47comment "OMAP 243x high speed USB support"
49 depends on USB_MUSB_HDRC && ARCH_OMAP2430 48 depends on USB_MUSB_HDRC && ARCH_OMAP2430
50 49
51comment "OMAP 343x high speed USB support" 50comment "OMAP 343x high speed USB support"
52 depends on USB_MUSB_HDRC && ARCH_OMAP34XX 51 depends on USB_MUSB_HDRC && ARCH_OMAP3
53 52
54comment "Blackfin high speed USB Support" 53comment "Blackfin high speed USB Support"
55 depends on USB_MUSB_HDRC && ((BF54x && !BF544) || (BF52x && !BF522 && !BF523)) 54 depends on USB_MUSB_HDRC && ((BF54x && !BF544) || (BF52x && !BF522 && !BF523))
@@ -154,7 +153,7 @@ config MUSB_PIO_ONLY
154config USB_INVENTRA_DMA 153config USB_INVENTRA_DMA
155 bool 154 bool
156 depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY 155 depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
157 default ARCH_OMAP2430 || ARCH_OMAP34XX || BLACKFIN 156 default ARCH_OMAP2430 || ARCH_OMAP3 || BLACKFIN
158 help 157 help
159 Enable DMA transfers using Mentor's engine. 158 Enable DMA transfers using Mentor's engine.
160 159
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 85710ccc1887..3a485dabebbb 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -6,7 +6,7 @@ musb_hdrc-objs := musb_core.o
6 6
7obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o 7obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
8 8
9ifeq ($(CONFIG_ARCH_DAVINCI),y) 9ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
10 musb_hdrc-objs += davinci.o 10 musb_hdrc-objs += davinci.o
11endif 11endif
12 12
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
index fcec87ea709e..ec8d324237f6 100644
--- a/drivers/usb/musb/blackfin.c
+++ b/drivers/usb/musb/blackfin.c
@@ -11,7 +11,6 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/sched.h> 13#include <linux/sched.h>
14#include <linux/slab.h>
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/list.h> 15#include <linux/list.h>
17#include <linux/gpio.h> 16#include <linux/gpio.h>
@@ -29,6 +28,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
29{ 28{
30 void __iomem *fifo = hw_ep->fifo; 29 void __iomem *fifo = hw_ep->fifo;
31 void __iomem *epio = hw_ep->regs; 30 void __iomem *epio = hw_ep->regs;
31 u8 epnum = hw_ep->epnum;
32 32
33 prefetch((u8 *)src); 33 prefetch((u8 *)src);
34 34
@@ -39,14 +39,51 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
39 39
40 dump_fifo_data(src, len); 40 dump_fifo_data(src, len);
41 41
42 if (unlikely((unsigned long)src & 0x01)) 42 if (!ANOMALY_05000380 && epnum != 0) {
43 outsw_8((unsigned long)fifo, src, 43 u16 dma_reg;
44 len & 0x01 ? (len >> 1) + 1 : len >> 1); 44
45 else 45 flush_dcache_range((unsigned long)src,
46 outsw((unsigned long)fifo, src, 46 (unsigned long)(src + len));
47 len & 0x01 ? (len >> 1) + 1 : len >> 1); 47
48} 48 /* Setup DMA address register */
49 dma_reg = (u32)src;
50 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
51 SSYNC();
52
53 dma_reg = (u32)src >> 16;
54 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
55 SSYNC();
56
57 /* Setup DMA count register */
58 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
59 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
60 SSYNC();
61
62 /* Enable the DMA */
63 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
64 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
65 SSYNC();
66
67 /* Wait for compelete */
68 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
69 cpu_relax();
70
71 /* acknowledge dma interrupt */
72 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
73 SSYNC();
49 74
75 /* Reset DMA */
76 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
77 SSYNC();
78 } else {
79 SSYNC();
80
81 if (unlikely((unsigned long)src & 0x01))
82 outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
83 else
84 outsw((unsigned long)fifo, src, (len + 1) >> 1);
85 }
86}
50/* 87/*
51 * Unload an endpoint's FIFO 88 * Unload an endpoint's FIFO
52 */ 89 */
@@ -54,53 +91,62 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
54{ 91{
55 void __iomem *fifo = hw_ep->fifo; 92 void __iomem *fifo = hw_ep->fifo;
56 u8 epnum = hw_ep->epnum; 93 u8 epnum = hw_ep->epnum;
57 u16 dma_reg = 0;
58 94
59 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 95 if (ANOMALY_05000467 && epnum != 0) {
60 'R', hw_ep->epnum, fifo, len, dst); 96 u16 dma_reg;
61 97
62#ifdef CONFIG_BF52x 98 invalidate_dcache_range((unsigned long)dst,
63 invalidate_dcache_range((unsigned int)dst, 99 (unsigned long)(dst + len));
64 (unsigned int)(dst + len));
65 100
66 /* Setup DMA address register */ 101 /* Setup DMA address register */
67 dma_reg = (u16) ((u32) dst & 0xFFFF); 102 dma_reg = (u32)dst;
68 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); 103 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
69 SSYNC(); 104 SSYNC();
70 105
71 dma_reg = (u16) (((u32) dst >> 16) & 0xFFFF); 106 dma_reg = (u32)dst >> 16;
72 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg); 107 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
73 SSYNC(); 108 SSYNC();
74 109
75 /* Setup DMA count register */ 110 /* Setup DMA count register */
76 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len); 111 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
77 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0); 112 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
78 SSYNC(); 113 SSYNC();
79 114
80 /* Enable the DMA */ 115 /* Enable the DMA */
81 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA; 116 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
82 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg); 117 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
83 SSYNC(); 118 SSYNC();
84 119
85 /* Wait for compelete */ 120 /* Wait for compelete */
86 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum))) 121 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
87 cpu_relax(); 122 cpu_relax();
88 123
89 /* acknowledge dma interrupt */ 124 /* acknowledge dma interrupt */
90 bfin_write_USB_DMA_INTERRUPT(1 << epnum); 125 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
91 SSYNC(); 126 SSYNC();
92 127
93 /* Reset DMA */ 128 /* Reset DMA */
94 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0); 129 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
95 SSYNC(); 130 SSYNC();
96#else 131 } else {
97 if (unlikely((unsigned long)dst & 0x01)) 132 SSYNC();
98 insw_8((unsigned long)fifo, dst, 133 /* Read the last byte of packet with odd size from address fifo + 4
99 len & 0x01 ? (len >> 1) + 1 : len >> 1); 134 * to trigger 1 byte access to EP0 FIFO.
100 else 135 */
101 insw((unsigned long)fifo, dst, 136 if (len == 1)
102 len & 0x01 ? (len >> 1) + 1 : len >> 1); 137 *dst = (u8)inw((unsigned long)fifo + 4);
103#endif 138 else {
139 if (unlikely((unsigned long)dst & 0x01))
140 insw_8((unsigned long)fifo, dst, len >> 1);
141 else
142 insw((unsigned long)fifo, dst, len >> 1);
143
144 if (len & 0x01)
145 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
146 }
147 }
148 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
149 'R', hw_ep->epnum, fifo, len, dst);
104 150
105 dump_fifo_data(dst, len); 151 dump_fifo_data(dst, len);
106} 152}
@@ -126,13 +172,7 @@ static irqreturn_t blackfin_interrupt(int irq, void *__hci)
126 172
127 spin_unlock_irqrestore(&musb->lock, flags); 173 spin_unlock_irqrestore(&musb->lock, flags);
128 174
129 /* REVISIT we sometimes get spurious IRQs on g_ep0 175 return retval;
130 * not clear why... fall in BF54x too.
131 */
132 if (retval != IRQ_HANDLED)
133 DBG(5, "spurious?\n");
134
135 return IRQ_HANDLED;
136} 176}
137 177
138static void musb_conn_timer_handler(unsigned long _musb) 178static void musb_conn_timer_handler(unsigned long _musb)
@@ -225,8 +265,9 @@ int musb_platform_get_vbus_status(struct musb *musb)
225 return 0; 265 return 0;
226} 266}
227 267
228void musb_platform_set_mode(struct musb *musb, u8 musb_mode) 268int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
229{ 269{
270 return -EIO;
230} 271}
231 272
232int __init musb_platform_init(struct musb *musb) 273int __init musb_platform_init(struct musb *musb)
@@ -261,10 +302,6 @@ int __init musb_platform_init(struct musb *musb)
261 SSYNC(); 302 SSYNC();
262 } 303 }
263 304
264 /* TODO
265 * Set SIC-IVG register
266 */
267
268 /* Configure PLL oscillator register */ 305 /* Configure PLL oscillator register */
269 bfin_write_USB_PLLOSC_CTRL(0x30a8); 306 bfin_write_USB_PLLOSC_CTRL(0x30a8);
270 SSYNC(); 307 SSYNC();
diff --git a/drivers/usb/musb/blackfin.h b/drivers/usb/musb/blackfin.h
index a240c1e53d16..bd9352a2ef2a 100644
--- a/drivers/usb/musb/blackfin.h
+++ b/drivers/usb/musb/blackfin.h
@@ -14,6 +14,43 @@
14 * Blackfin specific definitions 14 * Blackfin specific definitions
15 */ 15 */
16 16
17/* Anomalies notes:
18 *
19 * 05000450 - USB DMA Mode 1 Short Packet Data Corruption:
20 * MUSB driver is designed to transfer buffer of N * maxpacket size
21 * in DMA mode 1 and leave the rest of the data to the next
22 * transfer in DMA mode 0, so we never transmit a short packet in
23 * DMA mode 1.
24 *
25 * 05000463 - This anomaly doesn't affect this driver since it
26 * never uses L1 or L2 memory as data destination.
27 *
28 * 05000464 - This anomaly doesn't affect this driver since it
29 * never uses L1 or L2 memory as data source.
30 *
31 * 05000465 - The anomaly can be seen when SCLK is over 100 MHz, and there is
32 * no way to workaround for bulk endpoints. Since the wMaxPackSize
33 * of bulk is less than or equal to 512, while the fifo size of
34 * endpoint 5, 6, 7 is 1024, the double buffer mode is enabled
35 * automatically when these endpoints are used for bulk OUT.
36 *
37 * 05000466 - This anomaly doesn't affect this driver since it never mixes
38 * concurrent DMA and core accesses to the TX endpoint FIFOs.
39 *
40 * 05000467 - The workaround for this anomaly will introduce another
41 * anomaly - 05000465.
42 */
43
44/* The Mentor USB DMA engine on BF52x (silicon v0.0 and v0.1) seems to be
45 * unstable in host mode. This may be caused by Anomaly 05000380. After
46 * digging out the root cause, we will change this number accordingly.
47 * So, need to either use silicon v0.2+ or disable DMA mode in MUSB.
48 */
49#if ANOMALY_05000380 && defined(CONFIG_BF52x) && \
50 defined(CONFIG_USB_MUSB_HDRC) && !defined(CONFIG_MUSB_PIO_ONLY)
51# error "Please use PIO mode in MUSB driver on bf52x chip v0.0 and v0.1"
52#endif
53
17#undef DUMP_FIFO_DATA 54#undef DUMP_FIFO_DATA
18#ifdef DUMP_FIFO_DATA 55#ifdef DUMP_FIFO_DATA
19static void dump_fifo_data(u8 *buf, u16 len) 56static void dump_fifo_data(u8 *buf, u16 len)
@@ -32,7 +69,6 @@ static void dump_fifo_data(u8 *buf, u16 len)
32#define dump_fifo_data(buf, len) do {} while (0) 69#define dump_fifo_data(buf, len) do {} while (0)
33#endif 70#endif
34 71
35#ifdef CONFIG_BF52x
36 72
37#define USB_DMA_BASE USB_DMA_INTERRUPT 73#define USB_DMA_BASE USB_DMA_INTERRUPT
38#define USB_DMAx_CTRL 0x04 74#define USB_DMAx_CTRL 0x04
@@ -42,7 +78,6 @@ static void dump_fifo_data(u8 *buf, u16 len)
42#define USB_DMAx_COUNT_HIGH 0x14 78#define USB_DMAx_COUNT_HIGH 0x14
43 79
44#define USB_DMA_REG(ep, reg) (USB_DMA_BASE + 0x20 * ep + reg) 80#define USB_DMA_REG(ep, reg) (USB_DMA_BASE + 0x20 * ep + reg)
45#endif
46 81
47/* Almost 1 second */ 82/* Almost 1 second */
48#define TIMER_DELAY (1 * HZ) 83#define TIMER_DELAY (1 * HZ)
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index ef2332a9941d..59dc3d351b60 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -7,6 +7,7 @@
7 */ 7 */
8 8
9#include <linux/platform_device.h> 9#include <linux/platform_device.h>
10#include <linux/slab.h>
10#include <linux/usb.h> 11#include <linux/usb.h>
11 12
12#include "musb_core.h" 13#include "musb_core.h"
@@ -1154,8 +1155,11 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1154 struct musb_hw_ep *hw_ep = NULL; 1155 struct musb_hw_ep *hw_ep = NULL;
1155 u32 rx, tx; 1156 u32 rx, tx;
1156 int i, index; 1157 int i, index;
1158 unsigned long flags;
1157 1159
1158 cppi = container_of(musb->dma_controller, struct cppi, controller); 1160 cppi = container_of(musb->dma_controller, struct cppi, controller);
1161 if (cppi->irq)
1162 spin_lock_irqsave(&musb->lock, flags);
1159 1163
1160 tibase = musb->ctrl_base; 1164 tibase = musb->ctrl_base;
1161 1165
@@ -1188,8 +1192,13 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1188 1192
1189 bd = tx_ch->head; 1193 bd = tx_ch->head;
1190 1194
1195 /*
1196 * If Head is null then this could mean that a abort interrupt
1197 * that needs to be acknowledged.
1198 */
1191 if (NULL == bd) { 1199 if (NULL == bd) {
1192 DBG(1, "null BD\n"); 1200 DBG(1, "null BD\n");
1201 tx_ram->tx_complete = 0;
1193 continue; 1202 continue;
1194 } 1203 }
1195 1204
@@ -1285,6 +1294,9 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1285 /* write to CPPI EOI register to re-enable interrupts */ 1294 /* write to CPPI EOI register to re-enable interrupts */
1286 musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0); 1295 musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
1287 1296
1297 if (cppi->irq)
1298 spin_unlock_irqrestore(&musb->lock, flags);
1299
1288 return IRQ_HANDLED; 1300 return IRQ_HANDLED;
1289} 1301}
1290 1302
@@ -1406,15 +1418,6 @@ static int cppi_channel_abort(struct dma_channel *channel)
1406 1418
1407 if (cppi_ch->transmit) { 1419 if (cppi_ch->transmit) {
1408 struct cppi_tx_stateram __iomem *tx_ram; 1420 struct cppi_tx_stateram __iomem *tx_ram;
1409 int enabled;
1410
1411 /* mask interrupts raised to signal teardown complete. */
1412 enabled = musb_readl(tibase, DAVINCI_TXCPPI_INTENAB_REG)
1413 & (1 << cppi_ch->index);
1414 if (enabled)
1415 musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,
1416 (1 << cppi_ch->index));
1417
1418 /* REVISIT put timeouts on these controller handshakes */ 1421 /* REVISIT put timeouts on these controller handshakes */
1419 1422
1420 cppi_dump_tx(6, cppi_ch, " (teardown)"); 1423 cppi_dump_tx(6, cppi_ch, " (teardown)");
@@ -1429,7 +1432,6 @@ static int cppi_channel_abort(struct dma_channel *channel)
1429 do { 1432 do {
1430 value = musb_readl(&tx_ram->tx_complete, 0); 1433 value = musb_readl(&tx_ram->tx_complete, 0);
1431 } while (0xFFFFFFFC != value); 1434 } while (0xFFFFFFFC != value);
1432 musb_writel(&tx_ram->tx_complete, 0, 0xFFFFFFFC);
1433 1435
1434 /* FIXME clean up the transfer state ... here? 1436 /* FIXME clean up the transfer state ... here?
1435 * the completion routine should get called with 1437 * the completion routine should get called with
@@ -1442,23 +1444,15 @@ static int cppi_channel_abort(struct dma_channel *channel)
1442 musb_writew(regs, MUSB_TXCSR, value); 1444 musb_writew(regs, MUSB_TXCSR, value);
1443 musb_writew(regs, MUSB_TXCSR, value); 1445 musb_writew(regs, MUSB_TXCSR, value);
1444 1446
1445 /* While we scrub the TX state RAM, ensure that we clean 1447 /*
1446 * up any interrupt that's currently asserted:
1447 * 1. Write to completion Ptr value 0x1(bit 0 set) 1448 * 1. Write to completion Ptr value 0x1(bit 0 set)
1448 * (write back mode) 1449 * (write back mode)
1449 * 2. Write to completion Ptr value 0x0(bit 0 cleared) 1450 * 2. Wait for abort interrupt and then put the channel in
1450 * (compare mode) 1451 * compare mode by writing 1 to the tx_complete register.
1451 * Value written is compared(for bits 31:2) and when
1452 * equal, interrupt is deasserted.
1453 */ 1452 */
1454 cppi_reset_tx(tx_ram, 1); 1453 cppi_reset_tx(tx_ram, 1);
1455 musb_writel(&tx_ram->tx_complete, 0, 0); 1454 cppi_ch->head = 0;
1456 1455 musb_writel(&tx_ram->tx_complete, 0, 1);
1457 /* re-enable interrupt */
1458 if (enabled)
1459 musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
1460 (1 << cppi_ch->index));
1461
1462 cppi_dump_tx(5, cppi_ch, " (done teardown)"); 1456 cppi_dump_tx(5, cppi_ch, " (done teardown)");
1463 1457
1464 /* REVISIT tx side _should_ clean up the same way 1458 /* REVISIT tx side _should_ clean up the same way
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index e16ff605c458..ce2e16fee0df 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -24,7 +24,6 @@
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/kernel.h> 25#include <linux/kernel.h>
26#include <linux/sched.h> 26#include <linux/sched.h>
27#include <linux/slab.h>
28#include <linux/init.h> 27#include <linux/init.h>
29#include <linux/list.h> 28#include <linux/list.h>
30#include <linux/delay.h> 29#include <linux/delay.h>
@@ -42,7 +41,7 @@
42#include "musb_core.h" 41#include "musb_core.h"
43 42
44#ifdef CONFIG_MACH_DAVINCI_EVM 43#ifdef CONFIG_MACH_DAVINCI_EVM
45#define GPIO_nVBUS_DRV 144 44#define GPIO_nVBUS_DRV 160
46#endif 45#endif
47 46
48#include "davinci.h" 47#include "davinci.h"
@@ -274,7 +273,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
274 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through 273 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
275 * the Mentor registers (except for setup), use the TI ones and EOI. 274 * the Mentor registers (except for setup), use the TI ones and EOI.
276 * 275 *
277 * Docs describe irq "vector" registers asociated with the CPPI and 276 * Docs describe irq "vector" registers associated with the CPPI and
278 * USB EOI registers. These hold a bitmask corresponding to the 277 * USB EOI registers. These hold a bitmask corresponding to the
279 * current IRQ, not an irq handler address. Would using those bits 278 * current IRQ, not an irq handler address. Would using those bits
280 * resolve some of the races observed in this dispatch code?? 279 * resolve some of the races observed in this dispatch code??
@@ -445,6 +444,8 @@ int __init musb_platform_init(struct musb *musb)
445 return 0; 444 return 0;
446 445
447fail: 446fail:
447 clk_disable(musb->clock);
448
448 usb_nop_xceiv_unregister(); 449 usb_nop_xceiv_unregister();
449 return -ENODEV; 450 return -ENODEV;
450} 451}
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 547e0e390726..705cc4ad8737 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -379,7 +379,6 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
379 u8 devctl, u8 power) 379 u8 devctl, u8 power)
380{ 380{
381 irqreturn_t handled = IRQ_NONE; 381 irqreturn_t handled = IRQ_NONE;
382 void __iomem *mbase = musb->mregs;
383 382
384 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 383 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
385 int_usb); 384 int_usb);
@@ -394,6 +393,8 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
394 393
395 if (devctl & MUSB_DEVCTL_HM) { 394 if (devctl & MUSB_DEVCTL_HM) {
396#ifdef CONFIG_USB_MUSB_HDRC_HCD 395#ifdef CONFIG_USB_MUSB_HDRC_HCD
396 void __iomem *mbase = musb->mregs;
397
397 switch (musb->xceiv->state) { 398 switch (musb->xceiv->state) {
398 case OTG_STATE_A_SUSPEND: 399 case OTG_STATE_A_SUSPEND:
399 /* remote wakeup? later, GetPortStatus 400 /* remote wakeup? later, GetPortStatus
@@ -471,6 +472,8 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
471#ifdef CONFIG_USB_MUSB_HDRC_HCD 472#ifdef CONFIG_USB_MUSB_HDRC_HCD
472 /* see manual for the order of the tests */ 473 /* see manual for the order of the tests */
473 if (int_usb & MUSB_INTR_SESSREQ) { 474 if (int_usb & MUSB_INTR_SESSREQ) {
475 void __iomem *mbase = musb->mregs;
476
474 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 477 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
475 478
476 /* IRQ arrives from ID pin sense or (later, if VBUS power 479 /* IRQ arrives from ID pin sense or (later, if VBUS power
@@ -519,6 +522,8 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
519 case OTG_STATE_A_WAIT_BCON: 522 case OTG_STATE_A_WAIT_BCON:
520 case OTG_STATE_A_WAIT_VRISE: 523 case OTG_STATE_A_WAIT_VRISE:
521 if (musb->vbuserr_retry) { 524 if (musb->vbuserr_retry) {
525 void __iomem *mbase = musb->mregs;
526
522 musb->vbuserr_retry--; 527 musb->vbuserr_retry--;
523 ignore = 1; 528 ignore = 1;
524 devctl |= MUSB_DEVCTL_SESSION; 529 devctl |= MUSB_DEVCTL_SESSION;
@@ -557,8 +562,72 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
557 handled = IRQ_HANDLED; 562 handled = IRQ_HANDLED;
558 } 563 }
559 564
565
566 if (int_usb & MUSB_INTR_SUSPEND) {
567 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
568 otg_state_string(musb), devctl, power);
569 handled = IRQ_HANDLED;
570
571 switch (musb->xceiv->state) {
572#ifdef CONFIG_USB_MUSB_OTG
573 case OTG_STATE_A_PERIPHERAL:
574 /* We also come here if the cable is removed, since
575 * this silicon doesn't report ID-no-longer-grounded.
576 *
577 * We depend on T(a_wait_bcon) to shut us down, and
578 * hope users don't do anything dicey during this
579 * undesired detour through A_WAIT_BCON.
580 */
581 musb_hnp_stop(musb);
582 usb_hcd_resume_root_hub(musb_to_hcd(musb));
583 musb_root_disconnect(musb);
584 musb_platform_try_idle(musb, jiffies
585 + msecs_to_jiffies(musb->a_wait_bcon
586 ? : OTG_TIME_A_WAIT_BCON));
587
588 break;
589#endif
590 case OTG_STATE_B_IDLE:
591 if (!musb->is_active)
592 break;
593 case OTG_STATE_B_PERIPHERAL:
594 musb_g_suspend(musb);
595 musb->is_active = is_otg_enabled(musb)
596 && musb->xceiv->gadget->b_hnp_enable;
597 if (musb->is_active) {
598#ifdef CONFIG_USB_MUSB_OTG
599 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
600 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
601 mod_timer(&musb->otg_timer, jiffies
602 + msecs_to_jiffies(
603 OTG_TIME_B_ASE0_BRST));
604#endif
605 }
606 break;
607 case OTG_STATE_A_WAIT_BCON:
608 if (musb->a_wait_bcon != 0)
609 musb_platform_try_idle(musb, jiffies
610 + msecs_to_jiffies(musb->a_wait_bcon));
611 break;
612 case OTG_STATE_A_HOST:
613 musb->xceiv->state = OTG_STATE_A_SUSPEND;
614 musb->is_active = is_otg_enabled(musb)
615 && musb->xceiv->host->b_hnp_enable;
616 break;
617 case OTG_STATE_B_HOST:
618 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
619 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
620 break;
621 default:
622 /* "should not happen" */
623 musb->is_active = 0;
624 break;
625 }
626 }
627
560 if (int_usb & MUSB_INTR_CONNECT) { 628 if (int_usb & MUSB_INTR_CONNECT) {
561 struct usb_hcd *hcd = musb_to_hcd(musb); 629 struct usb_hcd *hcd = musb_to_hcd(musb);
630 void __iomem *mbase = musb->mregs;
562 631
563 handled = IRQ_HANDLED; 632 handled = IRQ_HANDLED;
564 musb->is_active = 1; 633 musb->is_active = 1;
@@ -625,10 +694,61 @@ b_host:
625 } 694 }
626#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 695#endif /* CONFIG_USB_MUSB_HDRC_HCD */
627 696
697 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
698 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
699 otg_state_string(musb),
700 MUSB_MODE(musb), devctl);
701 handled = IRQ_HANDLED;
702
703 switch (musb->xceiv->state) {
704#ifdef CONFIG_USB_MUSB_HDRC_HCD
705 case OTG_STATE_A_HOST:
706 case OTG_STATE_A_SUSPEND:
707 usb_hcd_resume_root_hub(musb_to_hcd(musb));
708 musb_root_disconnect(musb);
709 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
710 musb_platform_try_idle(musb, jiffies
711 + msecs_to_jiffies(musb->a_wait_bcon));
712 break;
713#endif /* HOST */
714#ifdef CONFIG_USB_MUSB_OTG
715 case OTG_STATE_B_HOST:
716 /* REVISIT this behaves for "real disconnect"
717 * cases; make sure the other transitions from
718 * from B_HOST act right too. The B_HOST code
719 * in hnp_stop() is currently not used...
720 */
721 musb_root_disconnect(musb);
722 musb_to_hcd(musb)->self.is_b_host = 0;
723 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
724 MUSB_DEV_MODE(musb);
725 musb_g_disconnect(musb);
726 break;
727 case OTG_STATE_A_PERIPHERAL:
728 musb_hnp_stop(musb);
729 musb_root_disconnect(musb);
730 /* FALLTHROUGH */
731 case OTG_STATE_B_WAIT_ACON:
732 /* FALLTHROUGH */
733#endif /* OTG */
734#ifdef CONFIG_USB_GADGET_MUSB_HDRC
735 case OTG_STATE_B_PERIPHERAL:
736 case OTG_STATE_B_IDLE:
737 musb_g_disconnect(musb);
738 break;
739#endif /* GADGET */
740 default:
741 WARNING("unhandled DISCONNECT transition (%s)\n",
742 otg_state_string(musb));
743 break;
744 }
745 }
746
628 /* mentor saves a bit: bus reset and babble share the same irq. 747 /* mentor saves a bit: bus reset and babble share the same irq.
629 * only host sees babble; only peripheral sees bus reset. 748 * only host sees babble; only peripheral sees bus reset.
630 */ 749 */
631 if (int_usb & MUSB_INTR_RESET) { 750 if (int_usb & MUSB_INTR_RESET) {
751 handled = IRQ_HANDLED;
632 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 752 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
633 /* 753 /*
634 * Looks like non-HS BABBLE can be ignored, but 754 * Looks like non-HS BABBLE can be ignored, but
@@ -641,7 +761,7 @@ b_host:
641 DBG(1, "BABBLE devctl: %02x\n", devctl); 761 DBG(1, "BABBLE devctl: %02x\n", devctl);
642 else { 762 else {
643 ERR("Stopping host session -- babble\n"); 763 ERR("Stopping host session -- babble\n");
644 musb_writeb(mbase, MUSB_DEVCTL, 0); 764 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
645 } 765 }
646 } else if (is_peripheral_capable()) { 766 } else if (is_peripheral_capable()) {
647 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 767 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
@@ -686,29 +806,7 @@ b_host:
686 otg_state_string(musb)); 806 otg_state_string(musb));
687 } 807 }
688 } 808 }
689
690 handled = IRQ_HANDLED;
691 } 809 }
692 schedule_work(&musb->irq_work);
693
694 return handled;
695}
696
697/*
698 * Interrupt Service Routine to record USB "global" interrupts.
699 * Since these do not happen often and signify things of
700 * paramount importance, it seems OK to check them individually;
701 * the order of the tests is specified in the manual
702 *
703 * @param musb instance pointer
704 * @param int_usb register contents
705 * @param devctl
706 * @param power
707 */
708static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
709 u8 devctl, u8 power)
710{
711 irqreturn_t handled = IRQ_NONE;
712 810
713#if 0 811#if 0
714/* REVISIT ... this would be for multiplexing periodic endpoints, or 812/* REVISIT ... this would be for multiplexing periodic endpoints, or
@@ -755,117 +853,7 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
755 } 853 }
756#endif 854#endif
757 855
758 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 856 schedule_work(&musb->irq_work);
759 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
760 otg_state_string(musb),
761 MUSB_MODE(musb), devctl);
762 handled = IRQ_HANDLED;
763
764 switch (musb->xceiv->state) {
765#ifdef CONFIG_USB_MUSB_HDRC_HCD
766 case OTG_STATE_A_HOST:
767 case OTG_STATE_A_SUSPEND:
768 usb_hcd_resume_root_hub(musb_to_hcd(musb));
769 musb_root_disconnect(musb);
770 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
771 musb_platform_try_idle(musb, jiffies
772 + msecs_to_jiffies(musb->a_wait_bcon));
773 break;
774#endif /* HOST */
775#ifdef CONFIG_USB_MUSB_OTG
776 case OTG_STATE_B_HOST:
777 /* REVISIT this behaves for "real disconnect"
778 * cases; make sure the other transitions from
779 * from B_HOST act right too. The B_HOST code
780 * in hnp_stop() is currently not used...
781 */
782 musb_root_disconnect(musb);
783 musb_to_hcd(musb)->self.is_b_host = 0;
784 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
785 MUSB_DEV_MODE(musb);
786 musb_g_disconnect(musb);
787 break;
788 case OTG_STATE_A_PERIPHERAL:
789 musb_hnp_stop(musb);
790 musb_root_disconnect(musb);
791 /* FALLTHROUGH */
792 case OTG_STATE_B_WAIT_ACON:
793 /* FALLTHROUGH */
794#endif /* OTG */
795#ifdef CONFIG_USB_GADGET_MUSB_HDRC
796 case OTG_STATE_B_PERIPHERAL:
797 case OTG_STATE_B_IDLE:
798 musb_g_disconnect(musb);
799 break;
800#endif /* GADGET */
801 default:
802 WARNING("unhandled DISCONNECT transition (%s)\n",
803 otg_state_string(musb));
804 break;
805 }
806
807 schedule_work(&musb->irq_work);
808 }
809
810 if (int_usb & MUSB_INTR_SUSPEND) {
811 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
812 otg_state_string(musb), devctl, power);
813 handled = IRQ_HANDLED;
814
815 switch (musb->xceiv->state) {
816#ifdef CONFIG_USB_MUSB_OTG
817 case OTG_STATE_A_PERIPHERAL:
818 /* We also come here if the cable is removed, since
819 * this silicon doesn't report ID-no-longer-grounded.
820 *
821 * We depend on T(a_wait_bcon) to shut us down, and
822 * hope users don't do anything dicey during this
823 * undesired detour through A_WAIT_BCON.
824 */
825 musb_hnp_stop(musb);
826 usb_hcd_resume_root_hub(musb_to_hcd(musb));
827 musb_root_disconnect(musb);
828 musb_platform_try_idle(musb, jiffies
829 + msecs_to_jiffies(musb->a_wait_bcon
830 ? : OTG_TIME_A_WAIT_BCON));
831 break;
832#endif
833 case OTG_STATE_B_PERIPHERAL:
834 musb_g_suspend(musb);
835 musb->is_active = is_otg_enabled(musb)
836 && musb->xceiv->gadget->b_hnp_enable;
837 if (musb->is_active) {
838#ifdef CONFIG_USB_MUSB_OTG
839 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
840 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
841 mod_timer(&musb->otg_timer, jiffies
842 + msecs_to_jiffies(
843 OTG_TIME_B_ASE0_BRST));
844#endif
845 }
846 break;
847 case OTG_STATE_A_WAIT_BCON:
848 if (musb->a_wait_bcon != 0)
849 musb_platform_try_idle(musb, jiffies
850 + msecs_to_jiffies(musb->a_wait_bcon));
851 break;
852 case OTG_STATE_A_HOST:
853 musb->xceiv->state = OTG_STATE_A_SUSPEND;
854 musb->is_active = is_otg_enabled(musb)
855 && musb->xceiv->host->b_hnp_enable;
856 break;
857 case OTG_STATE_B_HOST:
858 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
859 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
860 break;
861 default:
862 /* "should not happen" */
863 musb->is_active = 0;
864 break;
865 }
866 schedule_work(&musb->irq_work);
867 }
868
869 857
870 return handled; 858 return handled;
871} 859}
@@ -977,10 +965,8 @@ static void musb_shutdown(struct platform_device *pdev)
977 spin_lock_irqsave(&musb->lock, flags); 965 spin_lock_irqsave(&musb->lock, flags);
978 musb_platform_disable(musb); 966 musb_platform_disable(musb);
979 musb_generic_disable(musb); 967 musb_generic_disable(musb);
980 if (musb->clock) { 968 if (musb->clock)
981 clk_put(musb->clock); 969 clk_put(musb->clock);
982 musb->clock = NULL;
983 }
984 spin_unlock_irqrestore(&musb->lock, flags); 970 spin_unlock_irqrestore(&musb->lock, flags);
985 971
986 /* FIXME power down */ 972 /* FIXME power down */
@@ -1000,7 +986,7 @@ static void musb_shutdown(struct platform_device *pdev)
1000 * more than selecting one of a bunch of predefined configurations. 986 * more than selecting one of a bunch of predefined configurations.
1001 */ 987 */
1002#if defined(CONFIG_USB_TUSB6010) || \ 988#if defined(CONFIG_USB_TUSB6010) || \
1003 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) 989 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
1004static ushort __initdata fifo_mode = 4; 990static ushort __initdata fifo_mode = 4;
1005#else 991#else
1006static ushort __initdata fifo_mode = 2; 992static ushort __initdata fifo_mode = 2;
@@ -1095,6 +1081,36 @@ static struct fifo_cfg __initdata mode_4_cfg[] = {
1095{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1081{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1096}; 1082};
1097 1083
1084/* mode 5 - fits in 8KB */
1085static struct fifo_cfg __initdata mode_5_cfg[] = {
1086{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1087{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1088{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1089{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1090{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1091{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1092{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1093{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1094{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1095{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1096{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1097{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1098{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1099{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1100{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1101{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1102{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1103{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1104{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1105{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1106{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1107{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1108{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1109{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1110{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1111{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1112{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1113};
1098 1114
1099/* 1115/*
1100 * configure a fifo; for non-shared endpoints, this may be called 1116 * configure a fifo; for non-shared endpoints, this may be called
@@ -1210,6 +1226,10 @@ static int __init ep_config_from_table(struct musb *musb)
1210 cfg = mode_4_cfg; 1226 cfg = mode_4_cfg;
1211 n = ARRAY_SIZE(mode_4_cfg); 1227 n = ARRAY_SIZE(mode_4_cfg);
1212 break; 1228 break;
1229 case 5:
1230 cfg = mode_5_cfg;
1231 n = ARRAY_SIZE(mode_5_cfg);
1232 break;
1213 } 1233 }
1214 1234
1215 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1235 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
@@ -1314,13 +1334,9 @@ enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1314 */ 1334 */
1315static int __init musb_core_init(u16 musb_type, struct musb *musb) 1335static int __init musb_core_init(u16 musb_type, struct musb *musb)
1316{ 1336{
1317#ifdef MUSB_AHB_ID
1318 u32 data;
1319#endif
1320 u8 reg; 1337 u8 reg;
1321 char *type; 1338 char *type;
1322 u16 hwvers, rev_major, rev_minor; 1339 char aInfo[90], aRevision[32], aDate[12];
1323 char aInfo[78], aRevision[32], aDate[12];
1324 void __iomem *mbase = musb->mregs; 1340 void __iomem *mbase = musb->mregs;
1325 int status = 0; 1341 int status = 0;
1326 int i; 1342 int i;
@@ -1329,23 +1345,17 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1329 reg = musb_read_configdata(mbase); 1345 reg = musb_read_configdata(mbase);
1330 1346
1331 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1347 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1332 if (reg & MUSB_CONFIGDATA_DYNFIFO) 1348 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1333 strcat(aInfo, ", dyn FIFOs"); 1349 strcat(aInfo, ", dyn FIFOs");
1350 musb->dyn_fifo = true;
1351 }
1334 if (reg & MUSB_CONFIGDATA_MPRXE) { 1352 if (reg & MUSB_CONFIGDATA_MPRXE) {
1335 strcat(aInfo, ", bulk combine"); 1353 strcat(aInfo, ", bulk combine");
1336#ifdef C_MP_RX
1337 musb->bulk_combine = true; 1354 musb->bulk_combine = true;
1338#else
1339 strcat(aInfo, " (X)"); /* no driver support */
1340#endif
1341 } 1355 }
1342 if (reg & MUSB_CONFIGDATA_MPTXE) { 1356 if (reg & MUSB_CONFIGDATA_MPTXE) {
1343 strcat(aInfo, ", bulk split"); 1357 strcat(aInfo, ", bulk split");
1344#ifdef C_MP_TX
1345 musb->bulk_split = true; 1358 musb->bulk_split = true;
1346#else
1347 strcat(aInfo, " (X)"); /* no driver support */
1348#endif
1349 } 1359 }
1350 if (reg & MUSB_CONFIGDATA_HBRXE) { 1360 if (reg & MUSB_CONFIGDATA_HBRXE) {
1351 strcat(aInfo, ", HB-ISO Rx"); 1361 strcat(aInfo, ", HB-ISO Rx");
@@ -1361,20 +1371,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1361 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1371 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1362 musb_driver_name, reg, aInfo); 1372 musb_driver_name, reg, aInfo);
1363 1373
1364#ifdef MUSB_AHB_ID
1365 data = musb_readl(mbase, 0x404);
1366 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1367 (data >> 16) & 0xff, (data >> 24) & 0xff);
1368 /* FIXME ID2 and ID3 are unused */
1369 data = musb_readl(mbase, 0x408);
1370 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1371 data = musb_readl(mbase, 0x40c);
1372 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1373 reg = musb_readb(mbase, 0x400);
1374 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1375#else
1376 aDate[0] = 0; 1374 aDate[0] = 0;
1377#endif
1378 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1375 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1379 musb->is_multipoint = 1; 1376 musb->is_multipoint = 1;
1380 type = "M"; 1377 type = "M";
@@ -1391,11 +1388,10 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1391 } 1388 }
1392 1389
1393 /* log release info */ 1390 /* log release info */
1394 hwvers = musb_read_hwvers(mbase); 1391 musb->hwvers = musb_read_hwvers(mbase);
1395 rev_major = (hwvers >> 10) & 0x1f; 1392 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1396 rev_minor = hwvers & 0x3ff; 1393 MUSB_HWVERS_MINOR(musb->hwvers),
1397 snprintf(aRevision, 32, "%d.%d%s", rev_major, 1394 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1398 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1399 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1395 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1400 musb_driver_name, type, aRevision, aDate); 1396 musb_driver_name, type, aRevision, aDate);
1401 1397
@@ -1406,21 +1402,10 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1406 musb->nr_endpoints = 1; 1402 musb->nr_endpoints = 1;
1407 musb->epmask = 1; 1403 musb->epmask = 1;
1408 1404
1409 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1405 if (musb->dyn_fifo)
1410 if (musb->config->dyn_fifo) 1406 status = ep_config_from_table(musb);
1411 status = ep_config_from_table(musb); 1407 else
1412 else { 1408 status = ep_config_from_hw(musb);
1413 ERR("reconfigure software for Dynamic FIFOs\n");
1414 status = -ENODEV;
1415 }
1416 } else {
1417 if (!musb->config->dyn_fifo)
1418 status = ep_config_from_hw(musb);
1419 else {
1420 ERR("reconfigure software for static FIFOs\n");
1421 return -ENODEV;
1422 }
1423 }
1424 1409
1425 if (status < 0) 1410 if (status < 0)
1426 return status; 1411 return status;
@@ -1523,6 +1508,14 @@ irqreturn_t musb_interrupt(struct musb *musb)
1523 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1508 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1524 musb->int_usb, musb->int_tx, musb->int_rx); 1509 musb->int_usb, musb->int_tx, musb->int_rx);
1525 1510
1511#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1512 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1513 if (!musb->gadget_driver) {
1514 DBG(5, "No gadget driver loaded\n");
1515 return IRQ_HANDLED;
1516 }
1517#endif
1518
1526 /* the core can interrupt us for multiple reasons; docs have 1519 /* the core can interrupt us for multiple reasons; docs have
1527 * a generic interrupt flowchart to follow 1520 * a generic interrupt flowchart to follow
1528 */ 1521 */
@@ -1581,11 +1574,6 @@ irqreturn_t musb_interrupt(struct musb *musb)
1581 ep_num++; 1574 ep_num++;
1582 } 1575 }
1583 1576
1584 /* finish handling "global" interrupts after handling fifos */
1585 if (musb->int_usb)
1586 retval |= musb_stage2_irq(musb,
1587 musb->int_usb, devctl, power);
1588
1589 return retval; 1577 return retval;
1590} 1578}
1591 1579
@@ -1690,7 +1678,7 @@ musb_vbus_store(struct device *dev, struct device_attribute *attr,
1690 unsigned long val; 1678 unsigned long val;
1691 1679
1692 if (sscanf(buf, "%lu", &val) < 1) { 1680 if (sscanf(buf, "%lu", &val) < 1) {
1693 printk(KERN_ERR "Invalid VBUS timeout ms value\n"); 1681 dev_err(dev, "Invalid VBUS timeout ms value\n");
1694 return -EINVAL; 1682 return -EINVAL;
1695 } 1683 }
1696 1684
@@ -1740,7 +1728,7 @@ musb_srp_store(struct device *dev, struct device_attribute *attr,
1740 1728
1741 if (sscanf(buf, "%hu", &srp) != 1 1729 if (sscanf(buf, "%hu", &srp) != 1
1742 || (srp != 1)) { 1730 || (srp != 1)) {
1743 printk(KERN_ERR "SRP: Value must be 1\n"); 1731 dev_err(dev, "SRP: Value must be 1\n");
1744 return -EINVAL; 1732 return -EINVAL;
1745 } 1733 }
1746 1734
@@ -1753,6 +1741,19 @@ static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1753 1741
1754#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1742#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1755 1743
1744static struct attribute *musb_attributes[] = {
1745 &dev_attr_mode.attr,
1746 &dev_attr_vbus.attr,
1747#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1748 &dev_attr_srp.attr,
1749#endif
1750 NULL
1751};
1752
1753static const struct attribute_group musb_attr_group = {
1754 .attrs = musb_attributes,
1755};
1756
1756#endif /* sysfs */ 1757#endif /* sysfs */
1757 1758
1758/* Only used to provide driver mode change events */ 1759/* Only used to provide driver mode change events */
@@ -1827,11 +1828,7 @@ static void musb_free(struct musb *musb)
1827 */ 1828 */
1828 1829
1829#ifdef CONFIG_SYSFS 1830#ifdef CONFIG_SYSFS
1830 device_remove_file(musb->controller, &dev_attr_mode); 1831 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1831 device_remove_file(musb->controller, &dev_attr_vbus);
1832#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1833 device_remove_file(musb->controller, &dev_attr_srp);
1834#endif
1835#endif 1832#endif
1836 1833
1837#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1834#ifdef CONFIG_USB_GADGET_MUSB_HDRC
@@ -1854,15 +1851,6 @@ static void musb_free(struct musb *musb)
1854 put_device(musb->xceiv->dev); 1851 put_device(musb->xceiv->dev);
1855#endif 1852#endif
1856 1853
1857 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1858 musb_platform_exit(musb);
1859 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1860
1861 if (musb->clock) {
1862 clk_disable(musb->clock);
1863 clk_put(musb->clock);
1864 }
1865
1866#ifdef CONFIG_USB_MUSB_HDRC_HCD 1854#ifdef CONFIG_USB_MUSB_HDRC_HCD
1867 usb_put_hcd(musb_to_hcd(musb)); 1855 usb_put_hcd(musb_to_hcd(musb));
1868#else 1856#else
@@ -1890,8 +1878,10 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1890 */ 1878 */
1891 if (!plat) { 1879 if (!plat) {
1892 dev_dbg(dev, "no platform_data?\n"); 1880 dev_dbg(dev, "no platform_data?\n");
1893 return -ENODEV; 1881 status = -ENODEV;
1882 goto fail0;
1894 } 1883 }
1884
1895 switch (plat->mode) { 1885 switch (plat->mode) {
1896 case MUSB_HOST: 1886 case MUSB_HOST:
1897#ifdef CONFIG_USB_MUSB_HDRC_HCD 1887#ifdef CONFIG_USB_MUSB_HDRC_HCD
@@ -1913,13 +1903,16 @@ bad_config:
1913#endif 1903#endif
1914 default: 1904 default:
1915 dev_err(dev, "incompatible Kconfig role setting\n"); 1905 dev_err(dev, "incompatible Kconfig role setting\n");
1916 return -EINVAL; 1906 status = -EINVAL;
1907 goto fail0;
1917 } 1908 }
1918 1909
1919 /* allocate */ 1910 /* allocate */
1920 musb = allocate_instance(dev, plat->config, ctrl); 1911 musb = allocate_instance(dev, plat->config, ctrl);
1921 if (!musb) 1912 if (!musb) {
1922 return -ENOMEM; 1913 status = -ENOMEM;
1914 goto fail0;
1915 }
1923 1916
1924 spin_lock_init(&musb->lock); 1917 spin_lock_init(&musb->lock);
1925 musb->board_mode = plat->mode; 1918 musb->board_mode = plat->mode;
@@ -1937,7 +1930,7 @@ bad_config:
1937 if (IS_ERR(musb->clock)) { 1930 if (IS_ERR(musb->clock)) {
1938 status = PTR_ERR(musb->clock); 1931 status = PTR_ERR(musb->clock);
1939 musb->clock = NULL; 1932 musb->clock = NULL;
1940 goto fail; 1933 goto fail1;
1941 } 1934 }
1942 } 1935 }
1943 1936
@@ -1956,12 +1949,12 @@ bad_config:
1956 */ 1949 */
1957 musb->isr = generic_interrupt; 1950 musb->isr = generic_interrupt;
1958 status = musb_platform_init(musb); 1951 status = musb_platform_init(musb);
1959
1960 if (status < 0) 1952 if (status < 0)
1961 goto fail; 1953 goto fail2;
1954
1962 if (!musb->isr) { 1955 if (!musb->isr) {
1963 status = -ENODEV; 1956 status = -ENODEV;
1964 goto fail2; 1957 goto fail3;
1965 } 1958 }
1966 1959
1967#ifndef CONFIG_MUSB_PIO_ONLY 1960#ifndef CONFIG_MUSB_PIO_ONLY
@@ -1987,7 +1980,7 @@ bad_config:
1987 ? MUSB_CONTROLLER_MHDRC 1980 ? MUSB_CONTROLLER_MHDRC
1988 : MUSB_CONTROLLER_HDRC, musb); 1981 : MUSB_CONTROLLER_HDRC, musb);
1989 if (status < 0) 1982 if (status < 0)
1990 goto fail2; 1983 goto fail3;
1991 1984
1992#ifdef CONFIG_USB_MUSB_OTG 1985#ifdef CONFIG_USB_MUSB_OTG
1993 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1986 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
@@ -2000,7 +1993,7 @@ bad_config:
2000 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1993 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2001 dev_err(dev, "request_irq %d failed!\n", nIrq); 1994 dev_err(dev, "request_irq %d failed!\n", nIrq);
2002 status = -ENODEV; 1995 status = -ENODEV;
2003 goto fail2; 1996 goto fail3;
2004 } 1997 }
2005 musb->nIrq = nIrq; 1998 musb->nIrq = nIrq;
2006/* FIXME this handles wakeup irqs wrong */ 1999/* FIXME this handles wakeup irqs wrong */
@@ -2011,19 +2004,6 @@ bad_config:
2011 musb->irq_wake = 0; 2004 musb->irq_wake = 0;
2012 } 2005 }
2013 2006
2014 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2015 musb_driver_name,
2016 ({char *s;
2017 switch (musb->board_mode) {
2018 case MUSB_HOST: s = "Host"; break;
2019 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2020 default: s = "OTG"; break;
2021 }; s; }),
2022 ctrl,
2023 (is_dma_capable() && musb->dma_controller)
2024 ? "DMA" : "PIO",
2025 musb->nIrq);
2026
2027 /* host side needs more setup */ 2007 /* host side needs more setup */
2028 if (is_host_enabled(musb)) { 2008 if (is_host_enabled(musb)) {
2029 struct usb_hcd *hcd = musb_to_hcd(musb); 2009 struct usb_hcd *hcd = musb_to_hcd(musb);
@@ -2034,6 +2014,13 @@ bad_config:
2034 hcd->self.otg_port = 1; 2014 hcd->self.otg_port = 1;
2035 musb->xceiv->host = &hcd->self; 2015 musb->xceiv->host = &hcd->self;
2036 hcd->power_budget = 2 * (plat->power ? : 250); 2016 hcd->power_budget = 2 * (plat->power ? : 250);
2017
2018 /* program PHY to use external vBus if required */
2019 if (plat->extvbus) {
2020 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2021 busctl |= MUSB_ULPI_USE_EXTVBUS;
2022 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2023 }
2037 } 2024 }
2038 2025
2039 /* For the host-only role, we can activate right away. 2026 /* For the host-only role, we can activate right away.
@@ -2046,8 +2033,6 @@ bad_config:
2046 musb->xceiv->state = OTG_STATE_A_IDLE; 2033 musb->xceiv->state = OTG_STATE_A_IDLE;
2047 2034
2048 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2035 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2049 if (status)
2050 goto fail;
2051 2036
2052 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2037 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2053 "HOST", status, 2038 "HOST", status,
@@ -2062,8 +2047,6 @@ bad_config:
2062 musb->xceiv->state = OTG_STATE_B_IDLE; 2047 musb->xceiv->state = OTG_STATE_B_IDLE;
2063 2048
2064 status = musb_gadget_setup(musb); 2049 status = musb_gadget_setup(musb);
2065 if (status)
2066 goto fail;
2067 2050
2068 DBG(1, "%s mode, status %d, dev%02x\n", 2051 DBG(1, "%s mode, status %d, dev%02x\n",
2069 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2052 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
@@ -2071,38 +2054,52 @@ bad_config:
2071 musb_readb(musb->mregs, MUSB_DEVCTL)); 2054 musb_readb(musb->mregs, MUSB_DEVCTL));
2072 2055
2073 } 2056 }
2057 if (status < 0)
2058 goto fail3;
2074 2059
2075#ifdef CONFIG_SYSFS 2060#ifdef CONFIG_SYSFS
2076 status = device_create_file(dev, &dev_attr_mode); 2061 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2077 status = device_create_file(dev, &dev_attr_vbus);
2078#ifdef CONFIG_USB_GADGET_MUSB_HDRC
2079 status = device_create_file(dev, &dev_attr_srp);
2080#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2081 status = 0;
2082#endif
2083 if (status) 2062 if (status)
2084 goto fail2; 2063 goto fail4;
2064#endif
2065
2066 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2067 ({char *s;
2068 switch (musb->board_mode) {
2069 case MUSB_HOST: s = "Host"; break;
2070 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2071 default: s = "OTG"; break;
2072 }; s; }),
2073 ctrl,
2074 (is_dma_capable() && musb->dma_controller)
2075 ? "DMA" : "PIO",
2076 musb->nIrq);
2085 2077
2086 return 0; 2078 return 0;
2087 2079
2088fail2: 2080fail4:
2089#ifdef CONFIG_SYSFS 2081 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2090 device_remove_file(musb->controller, &dev_attr_mode); 2082 usb_remove_hcd(musb_to_hcd(musb));
2091 device_remove_file(musb->controller, &dev_attr_vbus); 2083 else
2092#ifdef CONFIG_USB_GADGET_MUSB_HDRC 2084 musb_gadget_cleanup(musb);
2093 device_remove_file(musb->controller, &dev_attr_srp); 2085
2094#endif 2086fail3:
2095#endif 2087 if (musb->irq_wake)
2088 device_init_wakeup(dev, 0);
2096 musb_platform_exit(musb); 2089 musb_platform_exit(musb);
2097fail:
2098 dev_err(musb->controller,
2099 "musb_init_controller failed with status %d\n", status);
2100 2090
2091fail2:
2101 if (musb->clock) 2092 if (musb->clock)
2102 clk_put(musb->clock); 2093 clk_put(musb->clock);
2103 device_init_wakeup(dev, 0); 2094
2095fail1:
2096 dev_err(musb->controller,
2097 "musb_init_controller failed with status %d\n", status);
2098
2104 musb_free(musb); 2099 musb_free(musb);
2105 2100
2101fail0:
2102
2106 return status; 2103 return status;
2107 2104
2108} 2105}
@@ -2121,6 +2118,7 @@ static int __init musb_probe(struct platform_device *pdev)
2121{ 2118{
2122 struct device *dev = &pdev->dev; 2119 struct device *dev = &pdev->dev;
2123 int irq = platform_get_irq(pdev, 0); 2120 int irq = platform_get_irq(pdev, 0);
2121 int status;
2124 struct resource *iomem; 2122 struct resource *iomem;
2125 void __iomem *base; 2123 void __iomem *base;
2126 2124
@@ -2128,7 +2126,7 @@ static int __init musb_probe(struct platform_device *pdev)
2128 if (!iomem || irq == 0) 2126 if (!iomem || irq == 0)
2129 return -ENODEV; 2127 return -ENODEV;
2130 2128
2131 base = ioremap(iomem->start, iomem->end - iomem->start + 1); 2129 base = ioremap(iomem->start, resource_size(iomem));
2132 if (!base) { 2130 if (!base) {
2133 dev_err(dev, "ioremap failed\n"); 2131 dev_err(dev, "ioremap failed\n");
2134 return -ENOMEM; 2132 return -ENOMEM;
@@ -2138,10 +2136,14 @@ static int __init musb_probe(struct platform_device *pdev)
2138 /* clobbered by use_dma=n */ 2136 /* clobbered by use_dma=n */
2139 orig_dma_mask = dev->dma_mask; 2137 orig_dma_mask = dev->dma_mask;
2140#endif 2138#endif
2141 return musb_init_controller(dev, irq, base); 2139 status = musb_init_controller(dev, irq, base);
2140 if (status < 0)
2141 iounmap(base);
2142
2143 return status;
2142} 2144}
2143 2145
2144static int __devexit musb_remove(struct platform_device *pdev) 2146static int __exit musb_remove(struct platform_device *pdev)
2145{ 2147{
2146 struct musb *musb = dev_to_musb(&pdev->dev); 2148 struct musb *musb = dev_to_musb(&pdev->dev);
2147 void __iomem *ctrl_base = musb->ctrl_base; 2149 void __iomem *ctrl_base = musb->ctrl_base;
@@ -2156,6 +2158,10 @@ static int __devexit musb_remove(struct platform_device *pdev)
2156 if (musb->board_mode == MUSB_HOST) 2158 if (musb->board_mode == MUSB_HOST)
2157 usb_remove_hcd(musb_to_hcd(musb)); 2159 usb_remove_hcd(musb_to_hcd(musb));
2158#endif 2160#endif
2161 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2162 musb_platform_exit(musb);
2163 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2164
2159 musb_free(musb); 2165 musb_free(musb);
2160 iounmap(ctrl_base); 2166 iounmap(ctrl_base);
2161 device_init_wakeup(&pdev->dev, 0); 2167 device_init_wakeup(&pdev->dev, 0);
@@ -2167,6 +2173,150 @@ static int __devexit musb_remove(struct platform_device *pdev)
2167 2173
2168#ifdef CONFIG_PM 2174#ifdef CONFIG_PM
2169 2175
2176static struct musb_context_registers musb_context;
2177
2178void musb_save_context(struct musb *musb)
2179{
2180 int i;
2181 void __iomem *musb_base = musb->mregs;
2182
2183 if (is_host_enabled(musb)) {
2184 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2185 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2186 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2187 }
2188 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2189 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2190 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2191 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2192 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2193 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2194
2195 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2196 musb_writeb(musb_base, MUSB_INDEX, i);
2197 musb_context.index_regs[i].txmaxp =
2198 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2199 musb_context.index_regs[i].txcsr =
2200 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2201 musb_context.index_regs[i].rxmaxp =
2202 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2203 musb_context.index_regs[i].rxcsr =
2204 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2205
2206 if (musb->dyn_fifo) {
2207 musb_context.index_regs[i].txfifoadd =
2208 musb_read_txfifoadd(musb_base);
2209 musb_context.index_regs[i].rxfifoadd =
2210 musb_read_rxfifoadd(musb_base);
2211 musb_context.index_regs[i].txfifosz =
2212 musb_read_txfifosz(musb_base);
2213 musb_context.index_regs[i].rxfifosz =
2214 musb_read_rxfifosz(musb_base);
2215 }
2216 if (is_host_enabled(musb)) {
2217 musb_context.index_regs[i].txtype =
2218 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2219 musb_context.index_regs[i].txinterval =
2220 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2221 musb_context.index_regs[i].rxtype =
2222 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2223 musb_context.index_regs[i].rxinterval =
2224 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2225
2226 musb_context.index_regs[i].txfunaddr =
2227 musb_read_txfunaddr(musb_base, i);
2228 musb_context.index_regs[i].txhubaddr =
2229 musb_read_txhubaddr(musb_base, i);
2230 musb_context.index_regs[i].txhubport =
2231 musb_read_txhubport(musb_base, i);
2232
2233 musb_context.index_regs[i].rxfunaddr =
2234 musb_read_rxfunaddr(musb_base, i);
2235 musb_context.index_regs[i].rxhubaddr =
2236 musb_read_rxhubaddr(musb_base, i);
2237 musb_context.index_regs[i].rxhubport =
2238 musb_read_rxhubport(musb_base, i);
2239 }
2240 }
2241
2242 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2243
2244 musb_platform_save_context(musb, &musb_context);
2245}
2246
2247void musb_restore_context(struct musb *musb)
2248{
2249 int i;
2250 void __iomem *musb_base = musb->mregs;
2251 void __iomem *ep_target_regs;
2252
2253 musb_platform_restore_context(musb, &musb_context);
2254
2255 if (is_host_enabled(musb)) {
2256 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2257 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2258 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2259 }
2260 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2261 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2262 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2263 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2264 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2265
2266 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2267 musb_writeb(musb_base, MUSB_INDEX, i);
2268 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2269 musb_context.index_regs[i].txmaxp);
2270 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2271 musb_context.index_regs[i].txcsr);
2272 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2273 musb_context.index_regs[i].rxmaxp);
2274 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2275 musb_context.index_regs[i].rxcsr);
2276
2277 if (musb->dyn_fifo) {
2278 musb_write_txfifosz(musb_base,
2279 musb_context.index_regs[i].txfifosz);
2280 musb_write_rxfifosz(musb_base,
2281 musb_context.index_regs[i].rxfifosz);
2282 musb_write_txfifoadd(musb_base,
2283 musb_context.index_regs[i].txfifoadd);
2284 musb_write_rxfifoadd(musb_base,
2285 musb_context.index_regs[i].rxfifoadd);
2286 }
2287
2288 if (is_host_enabled(musb)) {
2289 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2290 musb_context.index_regs[i].txtype);
2291 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2292 musb_context.index_regs[i].txinterval);
2293 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2294 musb_context.index_regs[i].rxtype);
2295 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2296
2297 musb_context.index_regs[i].rxinterval);
2298 musb_write_txfunaddr(musb_base, i,
2299 musb_context.index_regs[i].txfunaddr);
2300 musb_write_txhubaddr(musb_base, i,
2301 musb_context.index_regs[i].txhubaddr);
2302 musb_write_txhubport(musb_base, i,
2303 musb_context.index_regs[i].txhubport);
2304
2305 ep_target_regs =
2306 musb_read_target_reg_base(i, musb_base);
2307
2308 musb_write_rxfunaddr(ep_target_regs,
2309 musb_context.index_regs[i].rxfunaddr);
2310 musb_write_rxhubaddr(ep_target_regs,
2311 musb_context.index_regs[i].rxhubaddr);
2312 musb_write_rxhubport(ep_target_regs,
2313 musb_context.index_regs[i].rxhubport);
2314 }
2315 }
2316
2317 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2318}
2319
2170static int musb_suspend(struct device *dev) 2320static int musb_suspend(struct device *dev)
2171{ 2321{
2172 struct platform_device *pdev = to_platform_device(dev); 2322 struct platform_device *pdev = to_platform_device(dev);
@@ -2188,6 +2338,8 @@ static int musb_suspend(struct device *dev)
2188 */ 2338 */
2189 } 2339 }
2190 2340
2341 musb_save_context(musb);
2342
2191 if (musb->set_clock) 2343 if (musb->set_clock)
2192 musb->set_clock(musb->clock, 0); 2344 musb->set_clock(musb->clock, 0);
2193 else 2345 else
@@ -2209,6 +2361,8 @@ static int musb_resume_noirq(struct device *dev)
2209 else 2361 else
2210 clk_enable(musb->clock); 2362 clk_enable(musb->clock);
2211 2363
2364 musb_restore_context(musb);
2365
2212 /* for static cmos like DaVinci, register values were preserved 2366 /* for static cmos like DaVinci, register values were preserved
2213 * unless for some reason the whole soc powered down or the USB 2367 * unless for some reason the whole soc powered down or the USB
2214 * module got reset through the PSC (vs just being disabled). 2368 * module got reset through the PSC (vs just being disabled).
@@ -2216,7 +2370,7 @@ static int musb_resume_noirq(struct device *dev)
2216 return 0; 2370 return 0;
2217} 2371}
2218 2372
2219static struct dev_pm_ops musb_dev_pm_ops = { 2373static const struct dev_pm_ops musb_dev_pm_ops = {
2220 .suspend = musb_suspend, 2374 .suspend = musb_suspend,
2221 .resume_noirq = musb_resume_noirq, 2375 .resume_noirq = musb_resume_noirq,
2222}; 2376};
@@ -2233,7 +2387,7 @@ static struct platform_driver musb_driver = {
2233 .owner = THIS_MODULE, 2387 .owner = THIS_MODULE,
2234 .pm = MUSB_DEV_PM_OPS, 2388 .pm = MUSB_DEV_PM_OPS,
2235 }, 2389 },
2236 .remove = __devexit_p(musb_remove), 2390 .remove = __exit_p(musb_remove),
2237 .shutdown = musb_shutdown, 2391 .shutdown = musb_shutdown,
2238}; 2392};
2239 2393
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 6aa5f22e5274..ac17b004909b 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -52,6 +52,15 @@ struct musb;
52struct musb_hw_ep; 52struct musb_hw_ep;
53struct musb_ep; 53struct musb_ep;
54 54
55/* Helper defines for struct musb->hwvers */
56#define MUSB_HWVERS_MAJOR(x) ((x >> 10) & 0x1f)
57#define MUSB_HWVERS_MINOR(x) (x & 0x3ff)
58#define MUSB_HWVERS_RC 0x8000
59#define MUSB_HWVERS_1300 0x52C
60#define MUSB_HWVERS_1400 0x590
61#define MUSB_HWVERS_1800 0x720
62#define MUSB_HWVERS_1900 0x784
63#define MUSB_HWVERS_2000 0x800
55 64
56#include "musb_debug.h" 65#include "musb_debug.h"
57#include "musb_dma.h" 66#include "musb_dma.h"
@@ -322,6 +331,7 @@ struct musb {
322 struct clk *clock; 331 struct clk *clock;
323 irqreturn_t (*isr)(int, void *); 332 irqreturn_t (*isr)(int, void *);
324 struct work_struct irq_work; 333 struct work_struct irq_work;
334 u16 hwvers;
325 335
326/* this hub status bit is reserved by USB 2.0 and not seen by usbcore */ 336/* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
327#define MUSB_PORT_STAT_RESUME (1 << 31) 337#define MUSB_PORT_STAT_RESUME (1 << 31)
@@ -403,22 +413,15 @@ struct musb {
403 413
404 unsigned hb_iso_rx:1; /* high bandwidth iso rx? */ 414 unsigned hb_iso_rx:1; /* high bandwidth iso rx? */
405 unsigned hb_iso_tx:1; /* high bandwidth iso tx? */ 415 unsigned hb_iso_tx:1; /* high bandwidth iso tx? */
416 unsigned dyn_fifo:1; /* dynamic FIFO supported? */
406 417
407#ifdef C_MP_TX 418 unsigned bulk_split:1;
408 unsigned bulk_split:1;
409#define can_bulk_split(musb,type) \ 419#define can_bulk_split(musb,type) \
410 (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split) 420 (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split)
411#else
412#define can_bulk_split(musb, type) 0
413#endif
414 421
415#ifdef C_MP_RX 422 unsigned bulk_combine:1;
416 unsigned bulk_combine:1;
417#define can_bulk_combine(musb,type) \ 423#define can_bulk_combine(musb,type) \
418 (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine) 424 (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine)
419#else
420#define can_bulk_combine(musb, type) 0
421#endif
422 425
423#ifdef CONFIG_USB_GADGET_MUSB_HDRC 426#ifdef CONFIG_USB_GADGET_MUSB_HDRC
424 /* is_suspended means USB B_PERIPHERAL suspend */ 427 /* is_suspended means USB B_PERIPHERAL suspend */
@@ -453,6 +456,45 @@ struct musb {
453#endif 456#endif
454}; 457};
455 458
459#ifdef CONFIG_PM
460struct musb_csr_regs {
461 /* FIFO registers */
462 u16 txmaxp, txcsr, rxmaxp, rxcsr;
463 u16 rxfifoadd, txfifoadd;
464 u8 txtype, txinterval, rxtype, rxinterval;
465 u8 rxfifosz, txfifosz;
466 u8 txfunaddr, txhubaddr, txhubport;
467 u8 rxfunaddr, rxhubaddr, rxhubport;
468};
469
470struct musb_context_registers {
471
472#ifdef CONFIG_PM
473 u32 otg_sysconfig, otg_forcestandby;
474#endif
475 u8 power;
476 u16 intrtxe, intrrxe;
477 u8 intrusbe;
478 u16 frame;
479 u8 index, testmode;
480
481 u8 devctl, busctl, misc;
482
483 struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
484};
485
486#ifdef CONFIG_PM
487extern void musb_platform_save_context(struct musb *musb,
488 struct musb_context_registers *musb_context);
489extern void musb_platform_restore_context(struct musb *musb,
490 struct musb_context_registers *musb_context);
491#else
492#define musb_platform_save_context(m, x) do {} while (0)
493#define musb_platform_restore_context(m, x) do {} while (0)
494#endif
495
496#endif
497
456static inline void musb_set_vbus(struct musb *musb, int is_on) 498static inline void musb_set_vbus(struct musb *musb, int is_on)
457{ 499{
458 musb->board_set_vbus(musb, is_on); 500 musb->board_set_vbus(musb, is_on);
@@ -554,7 +596,7 @@ extern void musb_hnp_stop(struct musb *musb);
554extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode); 596extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode);
555 597
556#if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \ 598#if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \
557 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) 599 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
558extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout); 600extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
559#else 601#else
560#define musb_platform_try_idle(x, y) do {} while (0) 602#define musb_platform_try_idle(x, y) do {} while (0)
diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h
index 0a2c4e3602c1..916065ba9e70 100644
--- a/drivers/usb/musb/musb_dma.h
+++ b/drivers/usb/musb/musb_dma.h
@@ -80,6 +80,17 @@ struct musb_hw_ep;
80#define tusb_dma_omap() 0 80#define tusb_dma_omap() 0
81#endif 81#endif
82 82
83/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
84 * Only allow DMA mode 1 to be used when the USB will actually generate the
85 * interrupts we expect.
86 */
87#ifdef CONFIG_BLACKFIN
88# undef USE_MODE1
89# if !ANOMALY_05000456
90# define USE_MODE1
91# endif
92#endif
93
83/* 94/*
84 * DMA channel status ... updated by the dma controller driver whenever that 95 * DMA channel status ... updated by the dma controller driver whenever that
85 * status changes, and protected by the overall controller spinlock. 96 * status changes, and protected by the overall controller spinlock.
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 74073f9a43f0..6fca870e957e 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -43,6 +43,7 @@
43#include <linux/moduleparam.h> 43#include <linux/moduleparam.h>
44#include <linux/stat.h> 44#include <linux/stat.h>
45#include <linux/dma-mapping.h> 45#include <linux/dma-mapping.h>
46#include <linux/slab.h>
46 47
47#include "musb_core.h" 48#include "musb_core.h"
48 49
@@ -309,7 +310,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
309 size_t request_size; 310 size_t request_size;
310 311
311 /* setup DMA, then program endpoint CSR */ 312 /* setup DMA, then program endpoint CSR */
312 request_size = min(request->length, 313 request_size = min_t(size_t, request->length,
313 musb_ep->dma->max_len); 314 musb_ep->dma->max_len);
314 if (request_size < musb_ep->packet_sz) 315 if (request_size < musb_ep->packet_sz)
315 musb_ep->dma->desired_mode = 0; 316 musb_ep->dma->desired_mode = 0;
@@ -319,7 +320,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
319 use_dma = use_dma && c->channel_program( 320 use_dma = use_dma && c->channel_program(
320 musb_ep->dma, musb_ep->packet_sz, 321 musb_ep->dma, musb_ep->packet_sz,
321 musb_ep->dma->desired_mode, 322 musb_ep->dma->desired_mode,
322 request->dma, request_size); 323 request->dma + request->actual, request_size);
323 if (use_dma) { 324 if (use_dma) {
324 if (musb_ep->dma->desired_mode == 0) { 325 if (musb_ep->dma->desired_mode == 0) {
325 /* 326 /*
@@ -429,112 +430,102 @@ void musb_g_tx(struct musb *musb, u8 epnum)
429 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); 430 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
430 431
431 dma = is_dma_capable() ? musb_ep->dma : NULL; 432 dma = is_dma_capable() ? musb_ep->dma : NULL;
432 do { 433
433 /* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX 434 /*
434 * probably rates reporting as a host error 435 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
436 * probably rates reporting as a host error.
437 */
438 if (csr & MUSB_TXCSR_P_SENTSTALL) {
439 csr |= MUSB_TXCSR_P_WZC_BITS;
440 csr &= ~MUSB_TXCSR_P_SENTSTALL;
441 musb_writew(epio, MUSB_TXCSR, csr);
442 return;
443 }
444
445 if (csr & MUSB_TXCSR_P_UNDERRUN) {
446 /* We NAKed, no big deal... little reason to care. */
447 csr |= MUSB_TXCSR_P_WZC_BITS;
448 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
449 musb_writew(epio, MUSB_TXCSR, csr);
450 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
451 }
452
453 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
454 /*
455 * SHOULD NOT HAPPEN... has with CPPI though, after
456 * changing SENDSTALL (and other cases); harmless?
435 */ 457 */
436 if (csr & MUSB_TXCSR_P_SENTSTALL) { 458 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
437 csr |= MUSB_TXCSR_P_WZC_BITS; 459 return;
438 csr &= ~MUSB_TXCSR_P_SENTSTALL; 460 }
439 musb_writew(epio, MUSB_TXCSR, csr); 461
440 break; 462 if (request) {
441 } 463 u8 is_dma = 0;
442 464
443 if (csr & MUSB_TXCSR_P_UNDERRUN) { 465 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
444 /* we NAKed, no big deal ... little reason to care */ 466 is_dma = 1;
445 csr |= MUSB_TXCSR_P_WZC_BITS; 467 csr |= MUSB_TXCSR_P_WZC_BITS;
446 csr &= ~(MUSB_TXCSR_P_UNDERRUN 468 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
447 | MUSB_TXCSR_TXPKTRDY); 469 MUSB_TXCSR_TXPKTRDY);
448 musb_writew(epio, MUSB_TXCSR, csr); 470 musb_writew(epio, MUSB_TXCSR, csr);
449 DBG(20, "underrun on ep%d, req %p\n", epnum, request); 471 /* Ensure writebuffer is empty. */
472 csr = musb_readw(epio, MUSB_TXCSR);
473 request->actual += musb_ep->dma->actual_len;
474 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
475 epnum, csr, musb_ep->dma->actual_len, request);
450 } 476 }
451 477
452 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 478 if (is_dma || request->actual == request->length) {
453 /* SHOULD NOT HAPPEN ... has with cppi though, after 479 /*
454 * changing SENDSTALL (and other cases); harmless? 480 * First, maybe a terminating short packet. Some DMA
481 * engines might handle this by themselves.
455 */ 482 */
456 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); 483 if ((request->zero && request->length
457 break; 484 && request->length % musb_ep->packet_sz == 0)
458 } 485#ifdef CONFIG_USB_INVENTRA_DMA
459 486 || (is_dma && (!dma->desired_mode ||
460 if (request) { 487 (request->actual &
461 u8 is_dma = 0; 488 (musb_ep->packet_sz - 1))))
489#endif
490 ) {
491 /*
492 * On DMA completion, FIFO may not be
493 * available yet...
494 */
495 if (csr & MUSB_TXCSR_TXPKTRDY)
496 return;
462 497
463 if (dma && (csr & MUSB_TXCSR_DMAENAB)) { 498 DBG(4, "sending zero pkt\n");
464 is_dma = 1; 499 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
465 csr |= MUSB_TXCSR_P_WZC_BITS;
466 csr &= ~(MUSB_TXCSR_DMAENAB
467 | MUSB_TXCSR_P_UNDERRUN
468 | MUSB_TXCSR_TXPKTRDY); 500 | MUSB_TXCSR_TXPKTRDY);
469 musb_writew(epio, MUSB_TXCSR, csr); 501 request->zero = 0;
470 /* ensure writebuffer is empty */
471 csr = musb_readw(epio, MUSB_TXCSR);
472 request->actual += musb_ep->dma->actual_len;
473 DBG(4, "TXCSR%d %04x, dma off, "
474 "len %zu, req %p\n",
475 epnum, csr,
476 musb_ep->dma->actual_len,
477 request);
478 } 502 }
479 503
480 if (is_dma || request->actual == request->length) { 504 /* ... or if not, then complete it. */
481 505 musb_g_giveback(musb_ep, request, 0);
482 /* First, maybe a terminating short packet.
483 * Some DMA engines might handle this by
484 * themselves.
485 */
486 if ((request->zero
487 && request->length
488 && (request->length
489 % musb_ep->packet_sz)
490 == 0)
491#ifdef CONFIG_USB_INVENTRA_DMA
492 || (is_dma &&
493 ((!dma->desired_mode) ||
494 (request->actual &
495 (musb_ep->packet_sz - 1))))
496#endif
497 ) {
498 /* on dma completion, fifo may not
499 * be available yet ...
500 */
501 if (csr & MUSB_TXCSR_TXPKTRDY)
502 break;
503
504 DBG(4, "sending zero pkt\n");
505 musb_writew(epio, MUSB_TXCSR,
506 MUSB_TXCSR_MODE
507 | MUSB_TXCSR_TXPKTRDY);
508 request->zero = 0;
509 }
510
511 /* ... or if not, then complete it */
512 musb_g_giveback(musb_ep, request, 0);
513 506
514 /* kickstart next transfer if appropriate; 507 /*
515 * the packet that just completed might not 508 * Kickstart next transfer if appropriate;
516 * be transmitted for hours or days. 509 * the packet that just completed might not
517 * REVISIT for double buffering... 510 * be transmitted for hours or days.
518 * FIXME revisit for stalls too... 511 * REVISIT for double buffering...
519 */ 512 * FIXME revisit for stalls too...
520 musb_ep_select(mbase, epnum); 513 */
521 csr = musb_readw(epio, MUSB_TXCSR); 514 musb_ep_select(mbase, epnum);
522 if (csr & MUSB_TXCSR_FIFONOTEMPTY) 515 csr = musb_readw(epio, MUSB_TXCSR);
523 break; 516 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
524 request = musb_ep->desc 517 return;
525 ? next_request(musb_ep) 518
526 : NULL; 519 request = musb_ep->desc ? next_request(musb_ep) : NULL;
527 if (!request) { 520 if (!request) {
528 DBG(4, "%s idle now\n", 521 DBG(4, "%s idle now\n",
529 musb_ep->end_point.name); 522 musb_ep->end_point.name);
530 break; 523 return;
531 }
532 } 524 }
533
534 txstate(musb, to_musb_request(request));
535 } 525 }
536 526
537 } while (0); 527 txstate(musb, to_musb_request(request));
528 }
538} 529}
539 530
540/* ------------------------------------------------------------ */ 531/* ------------------------------------------------------------ */
@@ -756,6 +747,8 @@ void musb_g_rx(struct musb *musb, u8 epnum)
756 musb_ep_select(mbase, epnum); 747 musb_ep_select(mbase, epnum);
757 748
758 request = next_request(musb_ep); 749 request = next_request(musb_ep);
750 if (!request)
751 return;
759 752
760 csr = musb_readw(epio, MUSB_RXCSR); 753 csr = musb_readw(epio, MUSB_RXCSR);
761 dma = is_dma_capable() ? musb_ep->dma : NULL; 754 dma = is_dma_capable() ? musb_ep->dma : NULL;
@@ -903,7 +896,14 @@ static int musb_gadget_enable(struct usb_ep *ep,
903 /* REVISIT if can_bulk_split(), use by updating "tmp"; 896 /* REVISIT if can_bulk_split(), use by updating "tmp";
904 * likewise high bandwidth periodic tx 897 * likewise high bandwidth periodic tx
905 */ 898 */
906 musb_writew(regs, MUSB_TXMAXP, tmp); 899 /* Set TXMAXP with the FIFO size of the endpoint
900 * to disable double buffering mode. Currently, It seems that double
901 * buffering has problem if musb RTL revision number < 2.0.
902 */
903 if (musb->hwvers < MUSB_HWVERS_2000)
904 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
905 else
906 musb_writew(regs, MUSB_TXMAXP, tmp);
907 907
908 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; 908 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
909 if (musb_readw(regs, MUSB_TXCSR) 909 if (musb_readw(regs, MUSB_TXCSR)
@@ -933,7 +933,13 @@ static int musb_gadget_enable(struct usb_ep *ep,
933 /* REVISIT if can_bulk_combine() use by updating "tmp" 933 /* REVISIT if can_bulk_combine() use by updating "tmp"
934 * likewise high bandwidth periodic rx 934 * likewise high bandwidth periodic rx
935 */ 935 */
936 musb_writew(regs, MUSB_RXMAXP, tmp); 936 /* Set RXMAXP with the FIFO size of the endpoint
937 * to disable double buffering mode.
938 */
939 if (musb->hwvers < MUSB_HWVERS_2000)
940 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_rx);
941 else
942 musb_writew(regs, MUSB_RXMAXP, tmp);
937 943
938 /* force shared fifo to OUT-only mode */ 944 /* force shared fifo to OUT-only mode */
939 if (hw_ep->is_shared_fifo) { 945 if (hw_ep->is_shared_fifo) {
@@ -966,6 +972,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
966 972
967 musb_ep->desc = desc; 973 musb_ep->desc = desc;
968 musb_ep->busy = 0; 974 musb_ep->busy = 0;
975 musb_ep->wedged = 0;
969 status = 0; 976 status = 0;
970 977
971 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", 978 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
@@ -1220,7 +1227,7 @@ done:
1220 * 1227 *
1221 * exported to ep0 code 1228 * exported to ep0 code
1222 */ 1229 */
1223int musb_gadget_set_halt(struct usb_ep *ep, int value) 1230static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1224{ 1231{
1225 struct musb_ep *musb_ep = to_musb_ep(ep); 1232 struct musb_ep *musb_ep = to_musb_ep(ep);
1226 u8 epnum = musb_ep->current_epnum; 1233 u8 epnum = musb_ep->current_epnum;
@@ -1262,7 +1269,8 @@ int musb_gadget_set_halt(struct usb_ep *ep, int value)
1262 goto done; 1269 goto done;
1263 } 1270 }
1264 } 1271 }
1265 } 1272 } else
1273 musb_ep->wedged = 0;
1266 1274
1267 /* set/clear the stall and toggle bits */ 1275 /* set/clear the stall and toggle bits */
1268 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); 1276 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
@@ -1301,6 +1309,21 @@ done:
1301 return status; 1309 return status;
1302} 1310}
1303 1311
1312/*
1313 * Sets the halt feature with the clear requests ignored
1314 */
1315static int musb_gadget_set_wedge(struct usb_ep *ep)
1316{
1317 struct musb_ep *musb_ep = to_musb_ep(ep);
1318
1319 if (!ep)
1320 return -EINVAL;
1321
1322 musb_ep->wedged = 1;
1323
1324 return usb_ep_set_halt(ep);
1325}
1326
1304static int musb_gadget_fifo_status(struct usb_ep *ep) 1327static int musb_gadget_fifo_status(struct usb_ep *ep)
1305{ 1328{
1306 struct musb_ep *musb_ep = to_musb_ep(ep); 1329 struct musb_ep *musb_ep = to_musb_ep(ep);
@@ -1371,6 +1394,7 @@ static const struct usb_ep_ops musb_ep_ops = {
1371 .queue = musb_gadget_queue, 1394 .queue = musb_gadget_queue,
1372 .dequeue = musb_gadget_dequeue, 1395 .dequeue = musb_gadget_dequeue,
1373 .set_halt = musb_gadget_set_halt, 1396 .set_halt = musb_gadget_set_halt,
1397 .set_wedge = musb_gadget_set_wedge,
1374 .fifo_status = musb_gadget_fifo_status, 1398 .fifo_status = musb_gadget_fifo_status,
1375 .fifo_flush = musb_gadget_fifo_flush 1399 .fifo_flush = musb_gadget_fifo_flush
1376}; 1400};
@@ -1687,8 +1711,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1687 return -EINVAL; 1711 return -EINVAL;
1688 1712
1689 /* driver must be initialized to support peripheral mode */ 1713 /* driver must be initialized to support peripheral mode */
1690 if (!musb || !(musb->board_mode == MUSB_OTG 1714 if (!musb) {
1691 || musb->board_mode != MUSB_OTG)) {
1692 DBG(1, "%s, no dev??\n", __func__); 1715 DBG(1, "%s, no dev??\n", __func__);
1693 return -ENODEV; 1716 return -ENODEV;
1694 } 1717 }
@@ -1723,6 +1746,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1723 spin_lock_irqsave(&musb->lock, flags); 1746 spin_lock_irqsave(&musb->lock, flags);
1724 1747
1725 otg_set_peripheral(musb->xceiv, &musb->g); 1748 otg_set_peripheral(musb->xceiv, &musb->g);
1749 musb->xceiv->state = OTG_STATE_B_IDLE;
1726 musb->is_active = 1; 1750 musb->is_active = 1;
1727 1751
1728 /* FIXME this ignores the softconnect flag. Drivers are 1752 /* FIXME this ignores the softconnect flag. Drivers are
diff --git a/drivers/usb/musb/musb_gadget.h b/drivers/usb/musb/musb_gadget.h
index 59502da9f739..c8b140325d82 100644
--- a/drivers/usb/musb/musb_gadget.h
+++ b/drivers/usb/musb/musb_gadget.h
@@ -75,6 +75,8 @@ struct musb_ep {
75 /* later things are modified based on usage */ 75 /* later things are modified based on usage */
76 struct list_head req_list; 76 struct list_head req_list;
77 77
78 u8 wedged;
79
78 /* true if lock must be dropped but req_list may not be advanced */ 80 /* true if lock must be dropped but req_list may not be advanced */
79 u8 busy; 81 u8 busy;
80}; 82};
@@ -103,6 +105,4 @@ extern void musb_gadget_cleanup(struct musb *);
103 105
104extern void musb_g_giveback(struct musb_ep *, struct usb_request *, int); 106extern void musb_g_giveback(struct musb_ep *, struct usb_request *, int);
105 107
106extern int musb_gadget_set_halt(struct usb_ep *ep, int value);
107
108#endif /* __MUSB_GADGET_H */ 108#endif /* __MUSB_GADGET_H */
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index 522efb31b56b..53d06451f820 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -199,7 +199,6 @@ service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
199static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req) 199static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
200{ 200{
201 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0); 201 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
202 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
203} 202}
204 203
205/* 204/*
@@ -258,30 +257,53 @@ __acquires(musb->lock)
258 case USB_RECIP_INTERFACE: 257 case USB_RECIP_INTERFACE:
259 break; 258 break;
260 case USB_RECIP_ENDPOINT:{ 259 case USB_RECIP_ENDPOINT:{
261 const u8 num = ctrlrequest->wIndex & 0x0f; 260 const u8 epnum =
262 struct musb_ep *musb_ep; 261 ctrlrequest->wIndex & 0x0f;
262 struct musb_ep *musb_ep;
263 struct musb_hw_ep *ep;
264 void __iomem *regs;
265 int is_in;
266 u16 csr;
263 267
264 if (num == 0 268 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
265 || num >= MUSB_C_NUM_EPS 269 ctrlrequest->wValue != USB_ENDPOINT_HALT)
266 || ctrlrequest->wValue
267 != USB_ENDPOINT_HALT)
268 break; 270 break;
269 271
270 if (ctrlrequest->wIndex & USB_DIR_IN) 272 ep = musb->endpoints + epnum;
271 musb_ep = &musb->endpoints[num].ep_in; 273 regs = ep->regs;
274 is_in = ctrlrequest->wIndex & USB_DIR_IN;
275 if (is_in)
276 musb_ep = &ep->ep_in;
272 else 277 else
273 musb_ep = &musb->endpoints[num].ep_out; 278 musb_ep = &ep->ep_out;
274 if (!musb_ep->desc) 279 if (!musb_ep->desc)
275 break; 280 break;
276 281
277 /* REVISIT do it directly, no locking games */ 282 handled = 1;
278 spin_unlock(&musb->lock); 283 /* Ignore request if endpoint is wedged */
279 musb_gadget_set_halt(&musb_ep->end_point, 0); 284 if (musb_ep->wedged)
280 spin_lock(&musb->lock); 285 break;
286
287 musb_ep_select(mbase, epnum);
288 if (is_in) {
289 csr = musb_readw(regs, MUSB_TXCSR);
290 csr |= MUSB_TXCSR_CLRDATATOG |
291 MUSB_TXCSR_P_WZC_BITS;
292 csr &= ~(MUSB_TXCSR_P_SENDSTALL |
293 MUSB_TXCSR_P_SENTSTALL |
294 MUSB_TXCSR_TXPKTRDY);
295 musb_writew(regs, MUSB_TXCSR, csr);
296 } else {
297 csr = musb_readw(regs, MUSB_RXCSR);
298 csr |= MUSB_RXCSR_CLRDATATOG |
299 MUSB_RXCSR_P_WZC_BITS;
300 csr &= ~(MUSB_RXCSR_P_SENDSTALL |
301 MUSB_RXCSR_P_SENTSTALL);
302 musb_writew(regs, MUSB_RXCSR, csr);
303 }
281 304
282 /* select ep0 again */ 305 /* select ep0 again */
283 musb_ep_select(mbase, 0); 306 musb_ep_select(mbase, 0);
284 handled = 1;
285 } break; 307 } break;
286 default: 308 default:
287 /* class, vendor, etc ... delegate */ 309 /* class, vendor, etc ... delegate */
@@ -374,10 +396,8 @@ stall:
374 int is_in; 396 int is_in;
375 u16 csr; 397 u16 csr;
376 398
377 if (epnum == 0 399 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
378 || epnum >= MUSB_C_NUM_EPS 400 ctrlrequest->wValue != USB_ENDPOINT_HALT)
379 || ctrlrequest->wValue
380 != USB_ENDPOINT_HALT)
381 break; 401 break;
382 402
383 ep = musb->endpoints + epnum; 403 ep = musb->endpoints + epnum;
@@ -392,24 +412,20 @@ stall:
392 412
393 musb_ep_select(mbase, epnum); 413 musb_ep_select(mbase, epnum);
394 if (is_in) { 414 if (is_in) {
395 csr = musb_readw(regs, 415 csr = musb_readw(regs, MUSB_TXCSR);
396 MUSB_TXCSR);
397 if (csr & MUSB_TXCSR_FIFONOTEMPTY) 416 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
398 csr |= MUSB_TXCSR_FLUSHFIFO; 417 csr |= MUSB_TXCSR_FLUSHFIFO;
399 csr |= MUSB_TXCSR_P_SENDSTALL 418 csr |= MUSB_TXCSR_P_SENDSTALL
400 | MUSB_TXCSR_CLRDATATOG 419 | MUSB_TXCSR_CLRDATATOG
401 | MUSB_TXCSR_P_WZC_BITS; 420 | MUSB_TXCSR_P_WZC_BITS;
402 musb_writew(regs, MUSB_TXCSR, 421 musb_writew(regs, MUSB_TXCSR, csr);
403 csr);
404 } else { 422 } else {
405 csr = musb_readw(regs, 423 csr = musb_readw(regs, MUSB_RXCSR);
406 MUSB_RXCSR);
407 csr |= MUSB_RXCSR_P_SENDSTALL 424 csr |= MUSB_RXCSR_P_SENDSTALL
408 | MUSB_RXCSR_FLUSHFIFO 425 | MUSB_RXCSR_FLUSHFIFO
409 | MUSB_RXCSR_CLRDATATOG 426 | MUSB_RXCSR_CLRDATATOG
410 | MUSB_RXCSR_P_WZC_BITS; 427 | MUSB_RXCSR_P_WZC_BITS;
411 musb_writew(regs, MUSB_RXCSR, 428 musb_writew(regs, MUSB_RXCSR, csr);
412 csr);
413 } 429 }
414 430
415 /* select ep0 again */ 431 /* select ep0 again */
@@ -648,7 +664,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
648 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN; 664 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
649 break; 665 break;
650 default: 666 default:
651 ERR("SetupEnd came in a wrong ep0stage %s", 667 ERR("SetupEnd came in a wrong ep0stage %s\n",
652 decode_ep0stage(musb->ep0_state)); 668 decode_ep0stage(musb->ep0_state));
653 } 669 }
654 csr = musb_readw(regs, MUSB_CSR0); 670 csr = musb_readw(regs, MUSB_CSR0);
@@ -771,12 +787,18 @@ setup:
771 handled = service_zero_data_request( 787 handled = service_zero_data_request(
772 musb, &setup); 788 musb, &setup);
773 789
790 /*
791 * We're expecting no data in any case, so
792 * always set the DATAEND bit -- doing this
793 * here helps avoid SetupEnd interrupt coming
794 * in the idle stage when we're stalling...
795 */
796 musb->ackpend |= MUSB_CSR0_P_DATAEND;
797
774 /* status stage might be immediate */ 798 /* status stage might be immediate */
775 if (handled > 0) { 799 if (handled > 0)
776 musb->ackpend |= MUSB_CSR0_P_DATAEND;
777 musb->ep0_state = 800 musb->ep0_state =
778 MUSB_EP0_STAGE_STATUSIN; 801 MUSB_EP0_STAGE_STATUSIN;
779 }
780 break; 802 break;
781 803
782 /* sequence #1 (IN to host), includes GET_STATUS 804 /* sequence #1 (IN to host), includes GET_STATUS
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index e3ab40a966eb..877d20b1dff9 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -605,8 +605,14 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
607 /* NOTE: bulk combining rewrites high bits of maxpacket */ 607 /* NOTE: bulk combining rewrites high bits of maxpacket */
608 musb_writew(ep->regs, MUSB_RXMAXP, 608 /* Set RXMAXP with the FIFO size of the endpoint
609 qh->maxpacket | ((qh->hb_mult - 1) << 11)); 609 * to disable double buffer mode.
610 */
611 if (musb->hwvers < MUSB_HWVERS_2000)
612 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
613 else
614 musb_writew(ep->regs, MUSB_RXMAXP,
615 qh->maxpacket | ((qh->hb_mult - 1) << 11));
610 616
611 ep->rx_reinit = 0; 617 ep->rx_reinit = 0;
612} 618}
@@ -1642,18 +1648,18 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1642 c = musb->dma_controller; 1648 c = musb->dma_controller;
1643 1649
1644 if (usb_pipeisoc(pipe)) { 1650 if (usb_pipeisoc(pipe)) {
1645 int status = 0; 1651 int d_status = 0;
1646 struct usb_iso_packet_descriptor *d; 1652 struct usb_iso_packet_descriptor *d;
1647 1653
1648 d = urb->iso_frame_desc + qh->iso_idx; 1654 d = urb->iso_frame_desc + qh->iso_idx;
1649 1655
1650 if (iso_err) { 1656 if (iso_err) {
1651 status = -EILSEQ; 1657 d_status = -EILSEQ;
1652 urb->error_count++; 1658 urb->error_count++;
1653 } 1659 }
1654 if (rx_count > d->length) { 1660 if (rx_count > d->length) {
1655 if (status == 0) { 1661 if (d_status == 0) {
1656 status = -EOVERFLOW; 1662 d_status = -EOVERFLOW;
1657 urb->error_count++; 1663 urb->error_count++;
1658 } 1664 }
1659 DBG(2, "** OVERFLOW %d into %d\n",\ 1665 DBG(2, "** OVERFLOW %d into %d\n",\
@@ -1662,7 +1668,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1662 length = d->length; 1668 length = d->length;
1663 } else 1669 } else
1664 length = rx_count; 1670 length = rx_count;
1665 d->status = status; 1671 d->status = d_status;
1666 buf = urb->transfer_dma + d->offset; 1672 buf = urb->transfer_dma + d->offset;
1667 } else { 1673 } else {
1668 length = rx_count; 1674 length = rx_count;
@@ -1683,7 +1689,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1683 dma->desired_mode = 1; 1689 dma->desired_mode = 1;
1684 if (rx_count < hw_ep->max_packet_sz_rx) { 1690 if (rx_count < hw_ep->max_packet_sz_rx) {
1685 length = rx_count; 1691 length = rx_count;
1686 dma->bDesiredMode = 0; 1692 dma->desired_mode = 0;
1687 } else { 1693 } else {
1688 length = urb->transfer_buffer_length; 1694 length = urb->transfer_buffer_length;
1689 } 1695 }
@@ -1771,6 +1777,9 @@ static int musb_schedule(
1771 int best_end, epnum; 1777 int best_end, epnum;
1772 struct musb_hw_ep *hw_ep = NULL; 1778 struct musb_hw_ep *hw_ep = NULL;
1773 struct list_head *head = NULL; 1779 struct list_head *head = NULL;
1780 u8 toggle;
1781 u8 txtype;
1782 struct urb *urb = next_urb(qh);
1774 1783
1775 /* use fixed hardware for control and bulk */ 1784 /* use fixed hardware for control and bulk */
1776 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 1785 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
@@ -1809,6 +1818,27 @@ static int musb_schedule(
1809 diff -= (qh->maxpacket * qh->hb_mult); 1818 diff -= (qh->maxpacket * qh->hb_mult);
1810 1819
1811 if (diff >= 0 && best_diff > diff) { 1820 if (diff >= 0 && best_diff > diff) {
1821
1822 /*
1823 * Mentor controller has a bug in that if we schedule
1824 * a BULK Tx transfer on an endpoint that had earlier
1825 * handled ISOC then the BULK transfer has to start on
1826 * a zero toggle. If the BULK transfer starts on a 1
1827 * toggle then this transfer will fail as the mentor
1828 * controller starts the Bulk transfer on a 0 toggle
1829 * irrespective of the programming of the toggle bits
1830 * in the TXCSR register. Check for this condition
1831 * while allocating the EP for a Tx Bulk transfer. If
1832 * so skip this EP.
1833 */
1834 hw_ep = musb->endpoints + epnum;
1835 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
1836 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
1837 >> 4) & 0x3;
1838 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
1839 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
1840 continue;
1841
1812 best_diff = diff; 1842 best_diff = diff;
1813 best_end = epnum; 1843 best_end = epnum;
1814 } 1844 }
@@ -2012,6 +2042,7 @@ static int musb_urb_enqueue(
2012 * odd, rare, error prone, but legal. 2042 * odd, rare, error prone, but legal.
2013 */ 2043 */
2014 kfree(qh); 2044 kfree(qh);
2045 qh = NULL;
2015 ret = 0; 2046 ret = 0;
2016 } else 2047 } else
2017 ret = musb_schedule(musb, qh, 2048 ret = musb_schedule(musb, qh,
diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
index cc1d71b57d3c..fa55aacc385d 100644
--- a/drivers/usb/musb/musb_regs.h
+++ b/drivers/usb/musb/musb_regs.h
@@ -72,6 +72,10 @@
72#define MUSB_DEVCTL_HR 0x02 72#define MUSB_DEVCTL_HR 0x02
73#define MUSB_DEVCTL_SESSION 0x01 73#define MUSB_DEVCTL_SESSION 0x01
74 74
75/* MUSB ULPI VBUSCONTROL */
76#define MUSB_ULPI_USE_EXTVBUS 0x01
77#define MUSB_ULPI_USE_EXTVBUSIND 0x02
78
75/* TESTMODE */ 79/* TESTMODE */
76#define MUSB_TEST_FORCE_HOST 0x80 80#define MUSB_TEST_FORCE_HOST 0x80
77#define MUSB_TEST_FIFO_ACCESS 0x40 81#define MUSB_TEST_FIFO_ACCESS 0x40
@@ -246,6 +250,7 @@
246 250
247/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */ 251/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
248#define MUSB_HWVERS 0x6C /* 8 bit */ 252#define MUSB_HWVERS 0x6C /* 8 bit */
253#define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
249 254
250#define MUSB_EPINFO 0x78 /* 8 bit */ 255#define MUSB_EPINFO 0x78 /* 8 bit */
251#define MUSB_RAMINFO 0x79 /* 8 bit */ 256#define MUSB_RAMINFO 0x79 /* 8 bit */
@@ -321,6 +326,36 @@ static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
321 musb_writew(mbase, MUSB_RXFIFOADD, c_off); 326 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
322} 327}
323 328
329static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
330{
331 musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
332}
333
334static inline u8 musb_read_txfifosz(void __iomem *mbase)
335{
336 return musb_readb(mbase, MUSB_TXFIFOSZ);
337}
338
339static inline u16 musb_read_txfifoadd(void __iomem *mbase)
340{
341 return musb_readw(mbase, MUSB_TXFIFOADD);
342}
343
344static inline u8 musb_read_rxfifosz(void __iomem *mbase)
345{
346 return musb_readb(mbase, MUSB_RXFIFOSZ);
347}
348
349static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
350{
351 return musb_readw(mbase, MUSB_RXFIFOADD);
352}
353
354static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
355{
356 return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
357}
358
324static inline u8 musb_read_configdata(void __iomem *mbase) 359static inline u8 musb_read_configdata(void __iomem *mbase)
325{ 360{
326 musb_writeb(mbase, MUSB_INDEX, 0); 361 musb_writeb(mbase, MUSB_INDEX, 0);
@@ -376,6 +411,36 @@ static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
376 qh_h_port_reg); 411 qh_h_port_reg);
377} 412}
378 413
414static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
415{
416 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
417}
418
419static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
420{
421 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
422}
423
424static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
425{
426 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
427}
428
429static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
430{
431 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
432}
433
434static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
435{
436 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
437}
438
439static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
440{
441 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
442}
443
379#else /* CONFIG_BLACKFIN */ 444#else /* CONFIG_BLACKFIN */
380 445
381#define USB_BASE USB_FADDR 446#define USB_BASE USB_FADDR
@@ -436,7 +501,7 @@ static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
436#define MUSB_FLAT_OFFSET(_epnum, _offset) \ 501#define MUSB_FLAT_OFFSET(_epnum, _offset) \
437 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset)) 502 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
438 503
439/* Not implemented - HW has seperate Tx/Rx FIFO */ 504/* Not implemented - HW has separate Tx/Rx FIFO */
440#define MUSB_TXCSR_MODE 0x0000 505#define MUSB_TXCSR_MODE 0x0000
441 506
442static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size) 507static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
@@ -455,21 +520,54 @@ static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
455{ 520{
456} 521}
457 522
458static inline u8 musb_read_configdata(void __iomem *mbase) 523static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
524{
525}
526
527static inline u8 musb_read_txfifosz(void __iomem *mbase)
459{ 528{
460 return 0; 529 return 0;
461} 530}
462 531
463static inline u16 musb_read_hwvers(void __iomem *mbase) 532static inline u16 musb_read_txfifoadd(void __iomem *mbase)
533{
534 return 0;
535}
536
537static inline u8 musb_read_rxfifosz(void __iomem *mbase)
538{
539 return 0;
540}
541
542static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
543{
544 return 0;
545}
546
547static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
464{ 548{
465 return 0; 549 return 0;
466} 550}
467 551
468static inline u16 musb_read_target_reg_base(u8 i, void __iomem *mbase) 552static inline u8 musb_read_configdata(void __iomem *mbase)
469{ 553{
470 return 0; 554 return 0;
471} 555}
472 556
557static inline u16 musb_read_hwvers(void __iomem *mbase)
558{
559 /*
560 * This register is invisible on Blackfin, actually the MUSB
561 * RTL version of Blackfin is 1.9, so just harcode its value.
562 */
563 return MUSB_HWVERS_1900;
564}
565
566static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
567{
568 return NULL;
569}
570
473static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs, 571static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
474 u8 qh_addr_req) 572 u8 qh_addr_req)
475{ 573{
@@ -500,6 +598,35 @@ static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
500{ 598{
501} 599}
502 600
601static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
602{
603 return 0;
604}
605
606static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
607{
608 return 0;
609}
610
611static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
612{
613 return 0;
614}
615
616static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
617{
618 return 0;
619}
620
621static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
622{
623 return 0;
624}
625
626static inline void musb_read_txhubport(void __iomem *mbase, u8 epnum)
627{
628}
629
503#endif /* CONFIG_BLACKFIN */ 630#endif /* CONFIG_BLACKFIN */
504 631
505#endif /* __MUSB_REGS_H__ */ 632#endif /* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index bfe5fe4ebfee..7775e1c0a215 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -35,7 +35,6 @@
35#include <linux/module.h> 35#include <linux/module.h>
36#include <linux/kernel.h> 36#include <linux/kernel.h>
37#include <linux/sched.h> 37#include <linux/sched.h>
38#include <linux/slab.h>
39#include <linux/errno.h> 38#include <linux/errno.h>
40#include <linux/init.h> 39#include <linux/init.h>
41#include <linux/time.h> 40#include <linux/time.h>
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 5e83f96d6b77..1008044a3bbc 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -33,6 +33,7 @@
33#include <linux/device.h> 33#include <linux/device.h>
34#include <linux/interrupt.h> 34#include <linux/interrupt.h>
35#include <linux/platform_device.h> 35#include <linux/platform_device.h>
36#include <linux/slab.h>
36#include "musb_core.h" 37#include "musb_core.h"
37#include "musbhsdma.h" 38#include "musbhsdma.h"
38 39
@@ -250,14 +251,38 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
250 u8 bchannel; 251 u8 bchannel;
251 u8 int_hsdma; 252 u8 int_hsdma;
252 253
253 u32 addr; 254 u32 addr, count;
254 u16 csr; 255 u16 csr;
255 256
256 spin_lock_irqsave(&musb->lock, flags); 257 spin_lock_irqsave(&musb->lock, flags);
257 258
258 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 259 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
259 if (!int_hsdma) 260
260 goto done; 261#ifdef CONFIG_BLACKFIN
262 /* Clear DMA interrupt flags */
263 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
264#endif
265
266 if (!int_hsdma) {
267 DBG(2, "spurious DMA irq\n");
268
269 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
270 musb_channel = (struct musb_dma_channel *)
271 &(controller->channel[bchannel]);
272 channel = &musb_channel->channel;
273 if (channel->status == MUSB_DMA_STATUS_BUSY) {
274 count = musb_read_hsdma_count(mbase, bchannel);
275
276 if (count == 0)
277 int_hsdma |= (1 << bchannel);
278 }
279 }
280
281 DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
282
283 if (!int_hsdma)
284 goto done;
285 }
261 286
262 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 287 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
263 if (int_hsdma & (1 << bchannel)) { 288 if (int_hsdma & (1 << bchannel)) {
@@ -280,7 +305,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
280 channel->actual_len = addr 305 channel->actual_len = addr
281 - musb_channel->start_addr; 306 - musb_channel->start_addr;
282 307
283 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n", 308 DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
284 channel, musb_channel->start_addr, 309 channel, musb_channel->start_addr,
285 addr, channel->actual_len, 310 addr, channel->actual_len,
286 musb_channel->len, 311 musb_channel->len,
@@ -324,11 +349,6 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
324 } 349 }
325 } 350 }
326 351
327#ifdef CONFIG_BLACKFIN
328 /* Clear DMA interrup flags */
329 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
330#endif
331
332 retval = IRQ_HANDLED; 352 retval = IRQ_HANDLED;
333done: 353done:
334 spin_unlock_irqrestore(&musb->lock, flags); 354 spin_unlock_irqrestore(&musb->lock, flags);
diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
index 1299d92dc83f..613f95a058f7 100644
--- a/drivers/usb/musb/musbhsdma.h
+++ b/drivers/usb/musb/musbhsdma.h
@@ -55,6 +55,10 @@
55 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \ 55 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
56 addr) 56 addr)
57 57
58#define musb_read_hsdma_count(mbase, bchannel) \
59 musb_readl(mbase, \
60 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
61
58#define musb_write_hsdma_count(mbase, bchannel, len) \ 62#define musb_write_hsdma_count(mbase, bchannel, len) \
59 musb_writel(mbase, \ 63 musb_writel(mbase, \
60 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \ 64 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
@@ -96,6 +100,19 @@ static inline void musb_write_hsdma_addr(void __iomem *mbase,
96 ((u16)(((u32) dma_addr >> 16) & 0xFFFF))); 100 ((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
97} 101}
98 102
103static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
104{
105 u32 count = musb_readw(mbase,
106 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
107
108 count = count << 16;
109
110 count |= musb_readw(mbase,
111 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW));
112
113 return count;
114}
115
99static inline void musb_write_hsdma_count(void __iomem *mbase, 116static inline void musb_write_hsdma_count(void __iomem *mbase,
100 u8 bchannel, u32 len) 117 u8 bchannel, u32 len)
101{ 118{
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 34875201ee04..82592633502f 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -27,7 +27,6 @@
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/sched.h> 29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/init.h> 30#include <linux/init.h>
32#include <linux/list.h> 31#include <linux/list.h>
33#include <linux/clk.h> 32#include <linux/clk.h>
@@ -35,7 +34,7 @@
35 34
36#include <asm/mach-types.h> 35#include <asm/mach-types.h>
37#include <mach/hardware.h> 36#include <mach/hardware.h>
38#include <mach/mux.h> 37#include <plat/mux.h>
39 38
40#include "musb_core.h" 39#include "musb_core.h"
41#include "omap2430.h" 40#include "omap2430.h"
@@ -220,7 +219,7 @@ int __init musb_platform_init(struct musb *musb)
220 219
221 musb_platform_resume(musb); 220 musb_platform_resume(musb);
222 221
223 l = omap_readl(OTG_SYSCONFIG); 222 l = musb_readl(musb->mregs, OTG_SYSCONFIG);
224 l &= ~ENABLEWAKEUP; /* disable wakeup */ 223 l &= ~ENABLEWAKEUP; /* disable wakeup */
225 l &= ~NOSTDBY; /* remove possible nostdby */ 224 l &= ~NOSTDBY; /* remove possible nostdby */
226 l |= SMARTSTDBY; /* enable smart standby */ 225 l |= SMARTSTDBY; /* enable smart standby */
@@ -233,17 +232,19 @@ int __init musb_platform_init(struct musb *musb)
233 */ 232 */
234 if (!cpu_is_omap3430()) 233 if (!cpu_is_omap3430())
235 l |= AUTOIDLE; /* enable auto idle */ 234 l |= AUTOIDLE; /* enable auto idle */
236 omap_writel(l, OTG_SYSCONFIG); 235 musb_writel(musb->mregs, OTG_SYSCONFIG, l);
237 236
238 l = omap_readl(OTG_INTERFSEL); 237 l = musb_readl(musb->mregs, OTG_INTERFSEL);
239 l |= ULPI_12PIN; 238 l |= ULPI_12PIN;
240 omap_writel(l, OTG_INTERFSEL); 239 musb_writel(musb->mregs, OTG_INTERFSEL, l);
241 240
242 pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, " 241 pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
243 "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", 242 "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
244 omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG), 243 musb_readl(musb->mregs, OTG_REVISION),
245 omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL), 244 musb_readl(musb->mregs, OTG_SYSCONFIG),
246 omap_readl(OTG_SIMENABLE)); 245 musb_readl(musb->mregs, OTG_SYSSTATUS),
246 musb_readl(musb->mregs, OTG_INTERFSEL),
247 musb_readl(musb->mregs, OTG_SIMENABLE));
247 248
248 omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1); 249 omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
249 250
@@ -255,6 +256,22 @@ int __init musb_platform_init(struct musb *musb)
255 return 0; 256 return 0;
256} 257}
257 258
259#ifdef CONFIG_PM
260void musb_platform_save_context(struct musb *musb,
261 struct musb_context_registers *musb_context)
262{
263 musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG);
264 musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY);
265}
266
267void musb_platform_restore_context(struct musb *musb,
268 struct musb_context_registers *musb_context)
269{
270 musb_writel(musb->mregs, OTG_SYSCONFIG, musb_context->otg_sysconfig);
271 musb_writel(musb->mregs, OTG_FORCESTDBY, musb_context->otg_forcestandby);
272}
273#endif
274
258int musb_platform_suspend(struct musb *musb) 275int musb_platform_suspend(struct musb *musb)
259{ 276{
260 u32 l; 277 u32 l;
@@ -263,13 +280,13 @@ int musb_platform_suspend(struct musb *musb)
263 return 0; 280 return 0;
264 281
265 /* in any role */ 282 /* in any role */
266 l = omap_readl(OTG_FORCESTDBY); 283 l = musb_readl(musb->mregs, OTG_FORCESTDBY);
267 l |= ENABLEFORCE; /* enable MSTANDBY */ 284 l |= ENABLEFORCE; /* enable MSTANDBY */
268 omap_writel(l, OTG_FORCESTDBY); 285 musb_writel(musb->mregs, OTG_FORCESTDBY, l);
269 286
270 l = omap_readl(OTG_SYSCONFIG); 287 l = musb_readl(musb->mregs, OTG_SYSCONFIG);
271 l |= ENABLEWAKEUP; /* enable wakeup */ 288 l |= ENABLEWAKEUP; /* enable wakeup */
272 omap_writel(l, OTG_SYSCONFIG); 289 musb_writel(musb->mregs, OTG_SYSCONFIG, l);
273 290
274 otg_set_suspend(musb->xceiv, 1); 291 otg_set_suspend(musb->xceiv, 1);
275 292
@@ -295,13 +312,13 @@ static int musb_platform_resume(struct musb *musb)
295 else 312 else
296 clk_enable(musb->clock); 313 clk_enable(musb->clock);
297 314
298 l = omap_readl(OTG_SYSCONFIG); 315 l = musb_readl(musb->mregs, OTG_SYSCONFIG);
299 l &= ~ENABLEWAKEUP; /* disable wakeup */ 316 l &= ~ENABLEWAKEUP; /* disable wakeup */
300 omap_writel(l, OTG_SYSCONFIG); 317 musb_writel(musb->mregs, OTG_SYSCONFIG, l);
301 318
302 l = omap_readl(OTG_FORCESTDBY); 319 l = musb_readl(musb->mregs, OTG_FORCESTDBY);
303 l &= ~ENABLEFORCE; /* disable MSTANDBY */ 320 l &= ~ENABLEFORCE; /* disable MSTANDBY */
304 omap_writel(l, OTG_FORCESTDBY); 321 musb_writel(musb->mregs, OTG_FORCESTDBY, l);
305 322
306 return 0; 323 return 0;
307} 324}
@@ -314,8 +331,5 @@ int musb_platform_exit(struct musb *musb)
314 331
315 musb_platform_suspend(musb); 332 musb_platform_suspend(musb);
316 333
317 clk_put(musb->clock);
318 musb->clock = 0;
319
320 return 0; 334 return 0;
321} 335}
diff --git a/drivers/usb/musb/omap2430.h b/drivers/usb/musb/omap2430.h
index dc7670718cd2..40b3c02ae9f0 100644
--- a/drivers/usb/musb/omap2430.h
+++ b/drivers/usb/musb/omap2430.h
@@ -10,47 +10,43 @@
10#ifndef __MUSB_OMAP243X_H__ 10#ifndef __MUSB_OMAP243X_H__
11#define __MUSB_OMAP243X_H__ 11#define __MUSB_OMAP243X_H__
12 12
13#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 13#include <plat/usb.h>
14#include <mach/hardware.h>
15#include <mach/usb.h>
16 14
17/* 15/*
18 * OMAP2430-specific definitions 16 * OMAP2430-specific definitions
19 */ 17 */
20 18
21#define MENTOR_BASE_OFFSET 0 19#define OTG_REVISION 0x400
22#if defined(CONFIG_ARCH_OMAP2430) 20
23#define OMAP_HSOTG_BASE (OMAP243X_HS_BASE) 21#define OTG_SYSCONFIG 0x404
24#elif defined(CONFIG_ARCH_OMAP3430)
25#define OMAP_HSOTG_BASE (OMAP34XX_HSUSB_OTG_BASE)
26#endif
27#define OMAP_HSOTG(offset) (OMAP_HSOTG_BASE + 0x400 + (offset))
28#define OTG_REVISION OMAP_HSOTG(0x0)
29#define OTG_SYSCONFIG OMAP_HSOTG(0x4)
30# define MIDLEMODE 12 /* bit position */ 22# define MIDLEMODE 12 /* bit position */
31# define FORCESTDBY (0 << MIDLEMODE) 23# define FORCESTDBY (0 << MIDLEMODE)
32# define NOSTDBY (1 << MIDLEMODE) 24# define NOSTDBY (1 << MIDLEMODE)
33# define SMARTSTDBY (2 << MIDLEMODE) 25# define SMARTSTDBY (2 << MIDLEMODE)
26
34# define SIDLEMODE 3 /* bit position */ 27# define SIDLEMODE 3 /* bit position */
35# define FORCEIDLE (0 << SIDLEMODE) 28# define FORCEIDLE (0 << SIDLEMODE)
36# define NOIDLE (1 << SIDLEMODE) 29# define NOIDLE (1 << SIDLEMODE)
37# define SMARTIDLE (2 << SIDLEMODE) 30# define SMARTIDLE (2 << SIDLEMODE)
31
38# define ENABLEWAKEUP (1 << 2) 32# define ENABLEWAKEUP (1 << 2)
39# define SOFTRST (1 << 1) 33# define SOFTRST (1 << 1)
40# define AUTOIDLE (1 << 0) 34# define AUTOIDLE (1 << 0)
41#define OTG_SYSSTATUS OMAP_HSOTG(0x8) 35
36#define OTG_SYSSTATUS 0x408
42# define RESETDONE (1 << 0) 37# define RESETDONE (1 << 0)
43#define OTG_INTERFSEL OMAP_HSOTG(0xc) 38
39#define OTG_INTERFSEL 0x40c
44# define EXTCP (1 << 2) 40# define EXTCP (1 << 2)
45# define PHYSEL 0 /* bit position */ 41# define PHYSEL 0 /* bit position */
46# define UTMI_8BIT (0 << PHYSEL) 42# define UTMI_8BIT (0 << PHYSEL)
47# define ULPI_12PIN (1 << PHYSEL) 43# define ULPI_12PIN (1 << PHYSEL)
48# define ULPI_8PIN (2 << PHYSEL) 44# define ULPI_8PIN (2 << PHYSEL)
49#define OTG_SIMENABLE OMAP_HSOTG(0x10) 45
46#define OTG_SIMENABLE 0x410
50# define TM1 (1 << 0) 47# define TM1 (1 << 0)
51#define OTG_FORCESTDBY OMAP_HSOTG(0x14)
52# define ENABLEFORCE (1 << 0)
53 48
54#endif /* CONFIG_ARCH_OMAP2430 */ 49#define OTG_FORCESTDBY 0x414
50# define ENABLEFORCE (1 << 0)
55 51
56#endif /* __MUSB_OMAP243X_H__ */ 52#endif /* __MUSB_OMAP243X_H__ */
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index 88b587c703e9..60d3938cafcf 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -29,6 +29,19 @@ static void tusb_source_power(struct musb *musb, int is_on);
29#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 29#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
30#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 30#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
31 31
32#ifdef CONFIG_PM
33/* REVISIT: These should be only needed if somebody implements off idle */
34void musb_platform_save_context(struct musb *musb,
35 struct musb_context_registers *musb_context)
36{
37}
38
39void musb_platform_restore_context(struct musb *musb,
40 struct musb_context_registers *musb_context)
41{
42}
43#endif
44
32/* 45/*
33 * Checks the revision. We need to use the DMA register as 3.0 does not 46 * Checks the revision. We need to use the DMA register as 3.0 does not
34 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 47 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
@@ -1118,7 +1131,7 @@ int __init musb_platform_init(struct musb *musb)
1118 } 1131 }
1119 musb->sync = mem->start; 1132 musb->sync = mem->start;
1120 1133
1121 sync = ioremap(mem->start, mem->end - mem->start + 1); 1134 sync = ioremap(mem->start, resource_size(mem));
1122 if (!sync) { 1135 if (!sync) {
1123 pr_debug("ioremap for sync failed\n"); 1136 pr_debug("ioremap for sync failed\n");
1124 ret = -ENOMEM; 1137 ret = -ENOMEM;
diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
index 7e073a0d7ac9..c061a88f2b0f 100644
--- a/drivers/usb/musb/tusb6010_omap.c
+++ b/drivers/usb/musb/tusb6010_omap.c
@@ -15,8 +15,9 @@
15#include <linux/usb.h> 15#include <linux/usb.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
18#include <mach/dma.h> 18#include <linux/slab.h>
19#include <mach/mux.h> 19#include <plat/dma.h>
20#include <plat/mux.h>
20 21
21#include "musb_core.h" 22#include "musb_core.h"
22 23
@@ -38,7 +39,7 @@ struct tusb_omap_dma_ch {
38 39
39 struct tusb_omap_dma *tusb_dma; 40 struct tusb_omap_dma *tusb_dma;
40 41
41 void __iomem *dma_addr; 42 dma_addr_t dma_addr;
42 43
43 u32 len; 44 u32 len;
44 u16 packet_sz; 45 u16 packet_sz;
@@ -125,6 +126,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
125 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 126 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
126 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 127 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
127 struct musb *musb = chdat->musb; 128 struct musb *musb = chdat->musb;
129 struct device *dev = musb->controller;
128 struct musb_hw_ep *hw_ep = chdat->hw_ep; 130 struct musb_hw_ep *hw_ep = chdat->hw_ep;
129 void __iomem *ep_conf = hw_ep->conf; 131 void __iomem *ep_conf = hw_ep->conf;
130 void __iomem *mbase = musb->mregs; 132 void __iomem *mbase = musb->mregs;
@@ -172,13 +174,15 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
172 DBG(3, "Using PIO for remaining %lu bytes\n", pio); 174 DBG(3, "Using PIO for remaining %lu bytes\n", pio);
173 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 175 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
174 if (chdat->tx) { 176 if (chdat->tx) {
175 dma_cache_maint(phys_to_virt((u32)chdat->dma_addr), 177 dma_unmap_single(dev, chdat->dma_addr,
176 chdat->transfer_len, DMA_TO_DEVICE); 178 chdat->transfer_len,
179 DMA_TO_DEVICE);
177 musb_write_fifo(hw_ep, pio, buf); 180 musb_write_fifo(hw_ep, pio, buf);
178 } else { 181 } else {
182 dma_unmap_single(dev, chdat->dma_addr,
183 chdat->transfer_len,
184 DMA_FROM_DEVICE);
179 musb_read_fifo(hw_ep, pio, buf); 185 musb_read_fifo(hw_ep, pio, buf);
180 dma_cache_maint(phys_to_virt((u32)chdat->dma_addr),
181 chdat->transfer_len, DMA_FROM_DEVICE);
182 } 186 }
183 channel->actual_len += pio; 187 channel->actual_len += pio;
184 } 188 }
@@ -223,6 +227,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
223 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 227 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
224 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 228 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
225 struct musb *musb = chdat->musb; 229 struct musb *musb = chdat->musb;
230 struct device *dev = musb->controller;
226 struct musb_hw_ep *hw_ep = chdat->hw_ep; 231 struct musb_hw_ep *hw_ep = chdat->hw_ep;
227 void __iomem *mbase = musb->mregs; 232 void __iomem *mbase = musb->mregs;
228 void __iomem *ep_conf = hw_ep->conf; 233 void __iomem *ep_conf = hw_ep->conf;
@@ -298,14 +303,16 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
298 chdat->packet_sz = packet_sz; 303 chdat->packet_sz = packet_sz;
299 chdat->len = len; 304 chdat->len = len;
300 channel->actual_len = 0; 305 channel->actual_len = 0;
301 chdat->dma_addr = (void __iomem *)dma_addr; 306 chdat->dma_addr = dma_addr;
302 channel->status = MUSB_DMA_STATUS_BUSY; 307 channel->status = MUSB_DMA_STATUS_BUSY;
303 308
304 /* Since we're recycling dma areas, we need to clean or invalidate */ 309 /* Since we're recycling dma areas, we need to clean or invalidate */
305 if (chdat->tx) 310 if (chdat->tx)
306 dma_cache_maint(phys_to_virt(dma_addr), len, DMA_TO_DEVICE); 311 dma_map_single(dev, phys_to_virt(dma_addr), len,
312 DMA_TO_DEVICE);
307 else 313 else
308 dma_cache_maint(phys_to_virt(dma_addr), len, DMA_FROM_DEVICE); 314 dma_map_single(dev, phys_to_virt(dma_addr), len,
315 DMA_FROM_DEVICE);
309 316
310 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ 317 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
311 if ((dma_addr & 0x3) == 0) { 318 if ((dma_addr & 0x3) == 0) {
@@ -648,7 +655,7 @@ void dma_controller_destroy(struct dma_controller *c)
648 } 655 }
649 } 656 }
650 657
651 if (!tusb_dma->multichannel && tusb_dma && tusb_dma->ch >= 0) 658 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0)
652 omap_free_dma(tusb_dma->ch); 659 omap_free_dma(tusb_dma->ch);
653 660
654 kfree(tusb_dma); 661 kfree(tusb_dma);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-07 09:29:24 -0400