Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

1 files changed, 85 insertions, 96 deletions

diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 9e65c47cc98b..8b2473fa0f47 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -41,6 +41,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/list.h>
+#include <linux/dma-mapping.h>
 
 #include "musb_core.h"
 #include "musb_host.h"
@@ -105,6 +106,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
  */
 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
 {
+        struct musb     *musb = ep->musb;
         void __iomem    *epio = ep->regs;
         u16             csr;
         u16             lastcsr = 0;
@@ -113,7 +115,7 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
         csr = musb_readw(epio, MUSB_TXCSR);
         while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
                 if (csr != lastcsr)
-                        DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
+                        dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
                 lastcsr = csr;
                 csr |= MUSB_TXCSR_FLUSHFIFO;
                 musb_writew(epio, MUSB_TXCSR, csr);
@@ -239,7 +241,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
                 len = urb->transfer_buffer_length - urb->actual_length;
         }
 
-        DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
+        dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
                         qh, urb, address, qh->epnum,
                         is_in ? "in" : "out",
                         ({char *s; switch (qh->type) {
@@ -262,7 +264,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
         switch (qh->type) {
         case USB_ENDPOINT_XFER_ISOC:
         case USB_ENDPOINT_XFER_INT:
-                DBG(3, "check whether there's still time for periodic Tx\n");
+                dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
                 frame = musb_readw(mbase, MUSB_FRAME);
                 /* FIXME this doesn't implement that scheduling policy ...
                  * or handle framecounter wrapping
@@ -277,7 +279,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
                 } else {
                         qh->frame = urb->start_frame;
                         /* enable SOF interrupt so we can count down */
-                        DBG(1, "SOF for %d\n", epnum);
+                        dev_dbg(musb->controller, "SOF for %d\n", epnum);
 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
                         musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
 #endif
@@ -285,7 +287,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
                 break;
         default:
 start:
-                DBG(4, "Start TX%d %s\n", epnum,
+                dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
                         hw_ep->tx_channel ? "dma" : "pio");
 
                 if (!hw_ep->tx_channel)
@@ -300,21 +302,7 @@ static void musb_giveback(struct musb *musb, struct urb *urb, int status)
 __releases(musb->lock)
 __acquires(musb->lock)
 {
-        DBG(({ int level; switch (status) {
-                                case 0:
-                                        level = 4;
-                                        break;
-                                /* common/boring faults */
-                                case -EREMOTEIO:
-                                case -ESHUTDOWN:
-                                case -ECONNRESET:
-                                case -EPIPE:
-                                        level = 3;
-                                        break;
-                                default:
-                                        level = 2;
-                                        break;
-                                }; level; }),
+        dev_dbg(musb->controller,
                         "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
                         urb, urb->complete, status,
                         usb_pipedevice(urb->pipe),
@@ -425,7 +413,7 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
         }
 
         if (qh != NULL && qh->is_ready) {
-                DBG(4, "... next ep%d %cX urb %p\n",
+                dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
                     hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
                 musb_start_urb(musb, is_in, qh);
         }
@@ -470,7 +458,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
 
         /* musb_ep_select(mbase, epnum); */
         rx_count = musb_readw(epio, MUSB_RXCOUNT);
-        DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
+        dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
                         urb->transfer_buffer, qh->offset,
                         urb->transfer_buffer_length);
 
@@ -492,7 +480,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
                                 status = -EOVERFLOW;
                                 urb->error_count++;
                         }
-                        DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
+                        dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
                         do_flush = 1;
                 } else
                         length = rx_count;
@@ -510,7 +498,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
                 if (rx_count > length) {
                         if (urb->status == -EINPROGRESS)
                                 urb->status = -EOVERFLOW;
-                        DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
+                        dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
                         do_flush = 1;
                 } else
                         length = rx_count;
@@ -608,7 +596,7 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
         /* Set RXMAXP with the FIFO size of the endpoint
          * to disable double buffer mode.
          */
-        if (musb->hwvers < MUSB_HWVERS_2000)
+        if (musb->double_buffer_not_ok)
                 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
         else
                 musb_writew(ep->regs, MUSB_RXMAXP,
@@ -696,7 +684,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
         struct musb_qh          *qh = musb_ep_get_qh(hw_ep, !is_out);
         u16                     packet_sz = qh->maxpacket;
 
-        DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
+        dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
                                 "h_addr%02x h_port%02x bytes %d\n",
                         is_out ? "-->" : "<--",
                         epnum, urb, urb->dev->speed,
@@ -783,14 +771,13 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
                 /* protocol/endpoint/interval/NAKlimit */
                 if (epnum) {
                         musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
-                        if (can_bulk_split(musb, qh->type))
+                        if (musb->double_buffer_not_ok)
                                 musb_writew(epio, MUSB_TXMAXP,
-                                        packet_sz
-                                        | ((hw_ep->max_packet_sz_tx /
-                                                packet_sz) - 1) << 11);
+                                                hw_ep->max_packet_sz_tx);
                         else
                                 musb_writew(epio, MUSB_TXMAXP,
-                                        packet_sz);
+                                                qh->maxpacket |
+                                                ((qh->hb_mult - 1) << 11));
                         musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
                 } else {
                         musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
@@ -850,37 +837,32 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
                 /* kick things off */
 
                 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
-                        /* candidate for DMA */
-                        if (dma_channel) {
-                                dma_channel->actual_len = 0L;
-                                qh->segsize = len;
-
-                                /* AUTOREQ is in a DMA register */
-                                musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
-                                csr = musb_readw(hw_ep->regs,
-                                                MUSB_RXCSR);
-
-                                /* unless caller treats short rx transfers as
-                                 * errors, we dare not queue multiple transfers.
-                                 */
-                                dma_ok = dma_controller->channel_program(
-                                                dma_channel, packet_sz,
-                                                !(urb->transfer_flags
-                                                        & URB_SHORT_NOT_OK),
-                                                urb->transfer_dma + offset,
-                                                qh->segsize);
-                                if (!dma_ok) {
-                                        dma_controller->channel_release(
-                                                        dma_channel);
-                                        hw_ep->rx_channel = NULL;
-                                        dma_channel = NULL;
-                                } else
-                                        csr |= MUSB_RXCSR_DMAENAB;
-                        }
+                        /* Candidate for DMA */
+                        dma_channel->actual_len = 0L;
+                        qh->segsize = len;
+
+                        /* AUTOREQ is in a DMA register */
+                        musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
+                        csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
+
+                        /*
+                         * Unless caller treats short RX transfers as
+                         * errors, we dare not queue multiple transfers.
+                         */
+                        dma_ok = dma_controller->channel_program(dma_channel,
+                                        packet_sz, !(urb->transfer_flags &
+                                                     URB_SHORT_NOT_OK),
+                                        urb->transfer_dma + offset,
+                                        qh->segsize);
+                        if (!dma_ok) {
+                                dma_controller->channel_release(dma_channel);
+                                hw_ep->rx_channel = dma_channel = NULL;
+                        } else
+                                csr |= MUSB_RXCSR_DMAENAB;
                 }
 
                 csr |= MUSB_RXCSR_H_REQPKT;
-                DBG(7, "RXCSR%d := %04x\n", epnum, csr);
+                dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
                 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
                 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
         }
@@ -923,15 +905,15 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
                 request = (struct usb_ctrlrequest *) urb->setup_packet;
 
                 if (!request->wLength) {
-                        DBG(4, "start no-DATA\n");
+                        dev_dbg(musb->controller, "start no-DATA\n");
                         break;
                 } else if (request->bRequestType & USB_DIR_IN) {
-                        DBG(4, "start IN-DATA\n");
+                        dev_dbg(musb->controller, "start IN-DATA\n");
                         musb->ep0_stage = MUSB_EP0_IN;
                         more = true;
                         break;
                 } else {
-                        DBG(4, "start OUT-DATA\n");
+                        dev_dbg(musb->controller, "start OUT-DATA\n");
                         musb->ep0_stage = MUSB_EP0_OUT;
                         more = true;
                 }
@@ -943,7 +925,7 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
                 if (fifo_count) {
                         fifo_dest = (u8 *) (urb->transfer_buffer
                                         + urb->actual_length);
-                        DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
+                        dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
                                         fifo_count,
                                         (fifo_count == 1) ? "" : "s",
                                         fifo_dest);
@@ -988,7 +970,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
                         ? musb_readb(epio, MUSB_COUNT0)
                         : 0;
 
-        DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
+        dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
                 csr, qh, len, urb, musb->ep0_stage);
 
         /* if we just did status stage, we are done */
@@ -999,15 +981,15 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
 
         /* prepare status */
         if (csr & MUSB_CSR0_H_RXSTALL) {
-                DBG(6, "STALLING ENDPOINT\n");
+                dev_dbg(musb->controller, "STALLING ENDPOINT\n");
                 status = -EPIPE;
 
         } else if (csr & MUSB_CSR0_H_ERROR) {
-                DBG(2, "no response, csr0 %04x\n", csr);
+                dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
                 status = -EPROTO;
 
         } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
-                DBG(2, "control NAK timeout\n");
+                dev_dbg(musb->controller, "control NAK timeout\n");
 
                 /* NOTE:  this code path would be a good place to PAUSE a
                  * control transfer, if another one is queued, so that
@@ -1022,7 +1004,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
         }
 
         if (status) {
-                DBG(6, "aborting\n");
+                dev_dbg(musb->controller, "aborting\n");
                 retval = IRQ_HANDLED;
                 if (urb)
                         urb->status = status;
@@ -1072,7 +1054,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
                         /* flag status stage */
                         musb->ep0_stage = MUSB_EP0_STATUS;
 
-                        DBG(5, "ep0 STATUS, csr %04x\n", csr);
+                        dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
 
                 }
                 musb_writew(epio, MUSB_CSR0, csr);
@@ -1119,37 +1101,38 @@ void musb_host_tx(struct musb *musb, u8 epnum)
         u32                     status = 0;
         void __iomem            *mbase = musb->mregs;
         struct dma_channel      *dma;
+        bool                    transfer_pending = false;
 
         musb_ep_select(mbase, epnum);
         tx_csr = musb_readw(epio, MUSB_TXCSR);
 
         /* with CPPI, DMA sometimes triggers "extra" irqs */
         if (!urb) {
-                DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
+                dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
                 return;
         }
 
         pipe = urb->pipe;
         dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
-        DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
+        dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
                         dma ? ", dma" : "");
 
         /* check for errors */
         if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
                 /* dma was disabled, fifo flushed */
-                DBG(3, "TX end %d stall\n", epnum);
+                dev_dbg(musb->controller, "TX end %d stall\n", epnum);
 
                 /* stall; record URB status */
                 status = -EPIPE;
 
         } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
                 /* (NON-ISO) dma was disabled, fifo flushed */
-                DBG(3, "TX 3strikes on ep=%d\n", epnum);
+                dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
 
                 status = -ETIMEDOUT;
 
         } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
-                DBG(6, "TX end=%d device not responding\n", epnum);
+                dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
 
                 /* NOTE:  this code path would be a good place to PAUSE a
                  * transfer, if there's some other (nonperiodic) tx urb
@@ -1194,7 +1177,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
 
         /* second cppi case */
         if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
-                DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
+                dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
                 return;
         }
 
@@ -1253,7 +1236,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
                  * FIFO mode too...
                  */
                 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
-                        DBG(2, "DMA complete but packet still in FIFO, "
+                        dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
                             "CSR %04x\n", tx_csr);
                         return;
                 }
@@ -1279,7 +1262,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
                                 offset = d->offset;
                                 length = d->length;
                         }
-                } else if (dma) {
+                } else if (dma && urb->transfer_buffer_length == qh->offset) {
                         done = true;
                 } else {
                         /* see if we need to send more data, or ZLP */
@@ -1292,6 +1275,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
                         if (!done) {
                                 offset = qh->offset;
                                 length = urb->transfer_buffer_length - offset;
+                                transfer_pending = true;
                         }
                 }
         }
@@ -1311,7 +1295,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
                 urb->actual_length = qh->offset;
                 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
                 return;
-        } else  if (usb_pipeisoc(pipe) && dma) {
+        } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
                 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
                                 offset, length)) {
                         if (is_cppi_enabled() || tusb_dma_omap())
@@ -1319,7 +1303,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
                         return;
                 }
         } else  if (tx_csr & MUSB_TXCSR_DMAENAB) {
-                DBG(1, "not complete, but DMA enabled?\n");
+                dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
                 return;
         }
 
@@ -1332,6 +1316,8 @@ void musb_host_tx(struct musb *musb, u8 epnum)
          */
         if (length > qh->maxpacket)
                 length = qh->maxpacket;
+        /* Unmap the buffer so that CPU can use it */
+        usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
         musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
         qh->segsize = length;
 
@@ -1458,7 +1444,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                  * usbtest #11 (unlinks) triggers it regularly, sometimes
                  * with fifo full.  (Only with DMA??)
                  */
-                DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
+                dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
                         musb_readw(epio, MUSB_RXCOUNT));
                 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
                 return;
@@ -1466,20 +1452,20 @@ void musb_host_rx(struct musb *musb, u8 epnum)
 
         pipe = urb->pipe;
 
-        DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
+        dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
                 epnum, rx_csr, urb->actual_length,
                 dma ? dma->actual_len : 0);
 
         /* check for errors, concurrent stall & unlink is not really
          * handled yet! */
         if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
-                DBG(3, "RX end %d STALL\n", epnum);
+                dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
 
                 /* stall; record URB status */
                 status = -EPIPE;
 
         } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
-                DBG(3, "end %d RX proto error\n", epnum);
+                dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
 
                 status = -EPROTO;
                 musb_writeb(epio, MUSB_RXINTERVAL, 0);
@@ -1487,7 +1473,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
         } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
 
                 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
-                        DBG(6, "RX end %d NAK timeout\n", epnum);
+                        dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
 
                         /* NOTE: NAKing is *NOT* an error, so we want to
                          * continue.  Except ... if there's a request for
@@ -1510,12 +1496,12 @@ void musb_host_rx(struct musb *musb, u8 epnum)
 
                         goto finish;
                 } else {
-                        DBG(4, "RX end %d ISO data error\n", epnum);
+                        dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
                         /* packet error reported later */
                         iso_err = true;
                 }
         } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
-                DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
+                dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
                                 epnum);
                 status = -EPROTO;
         }
@@ -1561,7 +1547,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                         done = true;
                 }
 
-                DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
+                dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
                                 xfer_len, dma ? ", dma" : "");
                 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
 
@@ -1589,7 +1575,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                         /* even if there was an error, we did the dma
                          * for iso_frame_desc->length
                          */
-                        if (d->status != EILSEQ && d->status != -EOVERFLOW)
+                        if (d->status != -EILSEQ && d->status != -EOVERFLOW)
                                 d->status = 0;
 
                         if (++qh->iso_idx >= urb->number_of_packets)
@@ -1611,7 +1597,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                                 MUSB_RXCSR_H_WZC_BITS | val);
                 }
 
-                DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
+                dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
                         done ? "off" : "reset",
                         musb_readw(epio, MUSB_RXCSR),
                         musb_readw(epio, MUSB_RXCOUNT));
@@ -1644,7 +1630,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
 
                         rx_count = musb_readw(epio, MUSB_RXCOUNT);
 
-                        DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
+                        dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
                                         epnum, rx_count,
                                         urb->transfer_dma
                                                 + urb->actual_length,
@@ -1668,7 +1654,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                                                 d_status = -EOVERFLOW;
                                                 urb->error_count++;
                                         }
-                                        DBG(2, "** OVERFLOW %d into %d\n",\
+                                        dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
                                             rx_count, d->length);
 
                                         length = d->length;
@@ -1752,9 +1738,11 @@ void musb_host_rx(struct musb *musb, u8 epnum)
 #endif  /* Mentor DMA */
 
                 if (!dma) {
+                        /* Unmap the buffer so that CPU can use it */
+                        usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
                         done = musb_host_packet_rx(musb, urb,
                                         epnum, iso_err);
-                        DBG(6, "read %spacket\n", done ? "last " : "");
+                        dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
                 }
         }
 
@@ -1875,7 +1863,7 @@ static int musb_schedule(
         idle = 1;
         qh->mux = 0;
         hw_ep = musb->endpoints + best_end;
-        DBG(4, "qh %p periodic slot %d\n", qh, best_end);
+        dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
 success:
         if (head) {
                 idle = list_empty(head);
@@ -2081,6 +2069,7 @@ done:
 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
 {
         struct musb_hw_ep       *ep = qh->hw_ep;
+        struct musb             *musb = ep->musb;
         void __iomem            *epio = ep->regs;
         unsigned                hw_end = ep->epnum;
         void __iomem            *regs = ep->musb->mregs;
@@ -2096,7 +2085,7 @@ static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
                 dma = is_in ? ep->rx_channel : ep->tx_channel;
                 if (dma) {
                         status = ep->musb->dma_controller->channel_abort(dma);
-                        DBG(status ? 1 : 3,
+                        dev_dbg(musb->controller,
                                 "abort %cX%d DMA for urb %p --> %d\n",
                                 is_in ? 'R' : 'T', ep->epnum,
                                 urb, status);
@@ -2143,7 +2132,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
         int                     is_in  = usb_pipein(urb->pipe);
         int                     ret;
 
-        DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
+        dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
                         usb_pipedevice(urb->pipe),
                         usb_pipeendpoint(urb->pipe),
                         is_in ? "in" : "out");
@@ -2298,7 +2287,7 @@ static int musb_bus_suspend(struct usb_hcd *hcd)
 
         if (musb->is_active) {
                 WARNING("trying to suspend as %s while active\n",
-                                otg_state_string(musb));
+                                otg_state_string(musb->xceiv->state));
                 return -EBUSY;
         } else
                 return 0;