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authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>2015-01-20 17:56:02 -0500
committerFelipe Balbi <balbi@ti.com>2015-01-27 10:39:38 -0500
commit7ef077a8ad3557f030d0407c4f56c5a0cf1e418a (patch)
treed9096193b4cb402d2b4c381ba5376449d52db18f /drivers/usb/host
parent0316ca6319b98e485325be98a47d08fed07ead43 (diff)
usb: isp1760: Move driver from drivers/usb/host/ to drivers/usb/isp1760/
Now that this is DRD, it doesn't make sense to keep it under drivers/usb/host. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/host')
-rw-r--r--drivers/usb/host/Kconfig14
-rw-r--r--drivers/usb/host/Makefile4
-rw-r--r--drivers/usb/host/isp1760-core.c171
-rw-r--r--drivers/usb/host/isp1760-core.h68
-rw-r--r--drivers/usb/host/isp1760-hcd.c2231
-rw-r--r--drivers/usb/host/isp1760-hcd.h77
-rw-r--r--drivers/usb/host/isp1760-if.c312
-rw-r--r--drivers/usb/host/isp1760-regs.h230
-rw-r--r--drivers/usb/host/isp1760-udc.c1495
-rw-r--r--drivers/usb/host/isp1760-udc.h106
10 files changed, 0 insertions, 4708 deletions
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index fafc628480e0..3de291b6ac04 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -331,20 +331,6 @@ config USB_ISP116X_HCD
331 To compile this driver as a module, choose M here: the 331 To compile this driver as a module, choose M here: the
332 module will be called isp116x-hcd. 332 module will be called isp116x-hcd.
333 333
334config USB_ISP1760_HCD
335 tristate "ISP 1760 HCD support"
336 ---help---
337 The ISP1760 chip is a USB 2.0 host controller.
338
339 This driver does not support isochronous transfers or OTG.
340 This USB controller is usually attached to a non-DMA-Master
341 capable bus. NXP's eval kit brings this chip on PCI card
342 where the chip itself is behind a PLB to simulate such
343 a bus.
344
345 To compile this driver as a module, choose M here: the
346 module will be called isp1760.
347
348config USB_ISP1362_HCD 334config USB_ISP1362_HCD
349 tristate "ISP1362 HCD support" 335 tristate "ISP1362 HCD support"
350 ---help--- 336 ---help---
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 67d3f1843857..65b0b6a58599 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -5,9 +5,6 @@
5# tell define_trace.h where to find the xhci trace header 5# tell define_trace.h where to find the xhci trace header
6CFLAGS_xhci-trace.o := -I$(src) 6CFLAGS_xhci-trace.o := -I$(src)
7 7
8isp1760-y := isp1760-core.o isp1760-hcd.o isp1760-if.o
9isp1760-$(CONFIG_USB_ISP1761_UDC) += isp1760-udc.o
10
11fhci-y := fhci-hcd.o fhci-hub.o fhci-q.o 8fhci-y := fhci-hcd.o fhci-hub.o fhci-q.o
12fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o 9fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o
13 10
@@ -70,7 +67,6 @@ obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o
70obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o 67obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
71obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o 68obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
72obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o 69obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
73obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o
74obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o 70obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
75obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o 71obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
76obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o 72obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
diff --git a/drivers/usb/host/isp1760-core.c b/drivers/usb/host/isp1760-core.c
deleted file mode 100644
index 727e90ad15bd..000000000000
--- a/drivers/usb/host/isp1760-core.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * Driver for the NXP ISP1760 chip
3 *
4 * Copyright 2014 Laurent Pinchart
5 * Copyright 2007 Sebastian Siewior
6 *
7 * Contacts:
8 * Sebastian Siewior <bigeasy@linutronix.de>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 */
15
16#include <linux/delay.h>
17#include <linux/gpio/consumer.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/usb.h>
23
24#include "isp1760-core.h"
25#include "isp1760-hcd.h"
26#include "isp1760-regs.h"
27#include "isp1760-udc.h"
28
29static void isp1760_init_core(struct isp1760_device *isp)
30{
31 u32 otgctrl;
32 u32 hwmode;
33
34 /* Low-level chip reset */
35 if (isp->rst_gpio) {
36 gpiod_set_value_cansleep(isp->rst_gpio, 1);
37 mdelay(50);
38 gpiod_set_value_cansleep(isp->rst_gpio, 0);
39 }
40
41 /*
42 * Reset the host controller, including the CPU interface
43 * configuration.
44 */
45 isp1760_write32(isp->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
46 msleep(100);
47
48 /* Setup HW Mode Control: This assumes a level active-low interrupt */
49 hwmode = HW_DATA_BUS_32BIT;
50
51 if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_16)
52 hwmode &= ~HW_DATA_BUS_32BIT;
53 if (isp->devflags & ISP1760_FLAG_ANALOG_OC)
54 hwmode |= HW_ANA_DIGI_OC;
55 if (isp->devflags & ISP1760_FLAG_DACK_POL_HIGH)
56 hwmode |= HW_DACK_POL_HIGH;
57 if (isp->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
58 hwmode |= HW_DREQ_POL_HIGH;
59 if (isp->devflags & ISP1760_FLAG_INTR_POL_HIGH)
60 hwmode |= HW_INTR_HIGH_ACT;
61 if (isp->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
62 hwmode |= HW_INTR_EDGE_TRIG;
63
64 /*
65 * The ISP1761 has a dedicated DC IRQ line but supports sharing the HC
66 * IRQ line for both the host and device controllers. Hardcode IRQ
67 * sharing for now and disable the DC interrupts globally to avoid
68 * spurious interrupts during HCD registration.
69 */
70 if (isp->devflags & ISP1760_FLAG_ISP1761) {
71 isp1760_write32(isp->regs, DC_MODE, 0);
72 hwmode |= HW_COMN_IRQ;
73 }
74
75 /*
76 * We have to set this first in case we're in 16-bit mode.
77 * Write it twice to ensure correct upper bits if switching
78 * to 16-bit mode.
79 */
80 isp1760_write32(isp->regs, HC_HW_MODE_CTRL, hwmode);
81 isp1760_write32(isp->regs, HC_HW_MODE_CTRL, hwmode);
82
83 /*
84 * PORT 1 Control register of the ISP1760 is the OTG control register
85 * on ISP1761.
86 *
87 * TODO: Really support OTG. For now we configure port 1 in device mode
88 * when OTG is requested.
89 */
90 if ((isp->devflags & ISP1760_FLAG_ISP1761) &&
91 (isp->devflags & ISP1760_FLAG_OTG_EN))
92 otgctrl = ((HW_DM_PULLDOWN | HW_DP_PULLDOWN) << 16)
93 | HW_OTG_DISABLE;
94 else
95 otgctrl = (HW_SW_SEL_HC_DC << 16)
96 | (HW_VBUS_DRV | HW_SEL_CP_EXT);
97
98 isp1760_write32(isp->regs, HC_PORT1_CTRL, otgctrl);
99
100 dev_info(isp->dev, "bus width: %u, oc: %s\n",
101 isp->devflags & ISP1760_FLAG_BUS_WIDTH_16 ? 16 : 32,
102 isp->devflags & ISP1760_FLAG_ANALOG_OC ? "analog" : "digital");
103}
104
105void isp1760_set_pullup(struct isp1760_device *isp, bool enable)
106{
107 isp1760_write32(isp->regs, HW_OTG_CTRL_SET,
108 enable ? HW_DP_PULLUP : HW_DP_PULLUP << 16);
109}
110
111int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
112 struct device *dev, unsigned int devflags)
113{
114 struct isp1760_device *isp;
115 int ret;
116
117 if (usb_disabled())
118 return -ENODEV;
119
120 /* prevent usb-core allocating DMA pages */
121 dev->dma_mask = NULL;
122
123 isp = devm_kzalloc(dev, sizeof(*isp), GFP_KERNEL);
124 if (!isp)
125 return -ENOMEM;
126
127 isp->dev = dev;
128 isp->devflags = devflags;
129
130 isp->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
131 if (IS_ERR(isp->rst_gpio))
132 return PTR_ERR(isp->rst_gpio);
133
134 isp->regs = devm_ioremap_resource(dev, mem);
135 if (IS_ERR(isp->regs))
136 return PTR_ERR(isp->regs);
137
138 isp1760_init_core(isp);
139
140 ret = isp1760_hcd_register(&isp->hcd, isp->regs, mem, irq,
141 irqflags | IRQF_SHARED, dev);
142 if (ret < 0)
143 return ret;
144
145 if (devflags & ISP1760_FLAG_ISP1761) {
146 ret = isp1760_udc_register(isp, irq, irqflags | IRQF_SHARED |
147 IRQF_DISABLED);
148 if (ret < 0) {
149 isp1760_hcd_unregister(&isp->hcd);
150 return ret;
151 }
152 }
153
154 dev_set_drvdata(dev, isp);
155
156 return 0;
157}
158
159void isp1760_unregister(struct device *dev)
160{
161 struct isp1760_device *isp = dev_get_drvdata(dev);
162
163 if (isp->devflags & ISP1760_FLAG_ISP1761)
164 isp1760_udc_unregister(isp);
165
166 isp1760_hcd_unregister(&isp->hcd);
167}
168
169MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
170MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
171MODULE_LICENSE("GPL v2");
diff --git a/drivers/usb/host/isp1760-core.h b/drivers/usb/host/isp1760-core.h
deleted file mode 100644
index c70f8368a794..000000000000
--- a/drivers/usb/host/isp1760-core.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Driver for the NXP ISP1760 chip
3 *
4 * Copyright 2014 Laurent Pinchart
5 * Copyright 2007 Sebastian Siewior
6 *
7 * Contacts:
8 * Sebastian Siewior <bigeasy@linutronix.de>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 */
15
16#ifndef _ISP1760_CORE_H_
17#define _ISP1760_CORE_H_
18
19#include <linux/ioport.h>
20
21#include "isp1760-hcd.h"
22#include "isp1760-udc.h"
23
24struct device;
25struct gpio_desc;
26
27/*
28 * Device flags that can vary from board to board. All of these
29 * indicate the most "atypical" case, so that a devflags of 0 is
30 * a sane default configuration.
31 */
32#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
33#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
34#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
35#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
36#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
37#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
38#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
39#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
40
41struct isp1760_device {
42 struct device *dev;
43
44 void __iomem *regs;
45 unsigned int devflags;
46 struct gpio_desc *rst_gpio;
47
48 struct isp1760_hcd hcd;
49 struct isp1760_udc udc;
50};
51
52int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
53 struct device *dev, unsigned int devflags);
54void isp1760_unregister(struct device *dev);
55
56void isp1760_set_pullup(struct isp1760_device *isp, bool enable);
57
58static inline u32 isp1760_read32(void __iomem *base, u32 reg)
59{
60 return readl(base + reg);
61}
62
63static inline void isp1760_write32(void __iomem *base, u32 reg, u32 val)
64{
65 writel(val, base + reg);
66}
67
68#endif
diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c
deleted file mode 100644
index 568446c9ce8d..000000000000
--- a/drivers/usb/host/isp1760-hcd.c
+++ /dev/null
@@ -1,2231 +0,0 @@
1/*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
12 *
13 */
14#include <linux/gpio/consumer.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/list.h>
19#include <linux/usb.h>
20#include <linux/usb/hcd.h>
21#include <linux/debugfs.h>
22#include <linux/uaccess.h>
23#include <linux/io.h>
24#include <linux/mm.h>
25#include <linux/timer.h>
26#include <asm/unaligned.h>
27#include <asm/cacheflush.h>
28
29#include "isp1760-core.h"
30#include "isp1760-hcd.h"
31#include "isp1760-regs.h"
32
33static struct kmem_cache *qtd_cachep;
34static struct kmem_cache *qh_cachep;
35static struct kmem_cache *urb_listitem_cachep;
36
37typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
38 struct isp1760_qtd *qtd);
39
40static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
41{
42 return *(struct isp1760_hcd **)hcd->hcd_priv;
43}
44
45/* urb state*/
46#define DELETE_URB (0x0008)
47#define NO_TRANSFER_ACTIVE (0xffffffff)
48
49/* Philips Proprietary Transfer Descriptor (PTD) */
50typedef __u32 __bitwise __dw;
51struct ptd {
52 __dw dw0;
53 __dw dw1;
54 __dw dw2;
55 __dw dw3;
56 __dw dw4;
57 __dw dw5;
58 __dw dw6;
59 __dw dw7;
60};
61#define PTD_OFFSET 0x0400
62#define ISO_PTD_OFFSET 0x0400
63#define INT_PTD_OFFSET 0x0800
64#define ATL_PTD_OFFSET 0x0c00
65#define PAYLOAD_OFFSET 0x1000
66
67
68/* ATL */
69/* DW0 */
70#define DW0_VALID_BIT 1
71#define FROM_DW0_VALID(x) ((x) & 0x01)
72#define TO_DW0_LENGTH(x) (((u32) x) << 3)
73#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
74#define TO_DW0_MULTI(x) (((u32) x) << 29)
75#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
76/* DW1 */
77#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
78#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
79#define DW1_TRANS_BULK ((u32) 2 << 12)
80#define DW1_TRANS_INT ((u32) 3 << 12)
81#define DW1_TRANS_SPLIT ((u32) 1 << 14)
82#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
83#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
84#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
85/* DW2 */
86#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
87#define TO_DW2_RL(x) ((x) << 25)
88#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
89/* DW3 */
90#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
91#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
92#define TO_DW3_NAKCOUNT(x) ((x) << 19)
93#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
94#define TO_DW3_CERR(x) ((x) << 23)
95#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
96#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
97#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
98#define TO_DW3_PING(x) ((x) << 26)
99#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
100#define DW3_ERROR_BIT (1 << 28)
101#define DW3_BABBLE_BIT (1 << 29)
102#define DW3_HALT_BIT (1 << 30)
103#define DW3_ACTIVE_BIT (1 << 31)
104#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
105
106#define INT_UNDERRUN (1 << 2)
107#define INT_BABBLE (1 << 1)
108#define INT_EXACT (1 << 0)
109
110#define SETUP_PID (2)
111#define IN_PID (1)
112#define OUT_PID (0)
113
114/* Errata 1 */
115#define RL_COUNTER (0)
116#define NAK_COUNTER (0)
117#define ERR_COUNTER (2)
118
119struct isp1760_qtd {
120 u8 packet_type;
121 void *data_buffer;
122 u32 payload_addr;
123
124 /* the rest is HCD-private */
125 struct list_head qtd_list;
126 struct urb *urb;
127 size_t length;
128 size_t actual_length;
129
130 /* QTD_ENQUEUED: waiting for transfer (inactive) */
131 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
132 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
133 interrupt handler may touch this qtd! */
134 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
135 /* QTD_RETIRE: transfer error/abort qtd */
136#define QTD_ENQUEUED 0
137#define QTD_PAYLOAD_ALLOC 1
138#define QTD_XFER_STARTED 2
139#define QTD_XFER_COMPLETE 3
140#define QTD_RETIRE 4
141 u32 status;
142};
143
144/* Queue head, one for each active endpoint */
145struct isp1760_qh {
146 struct list_head qh_list;
147 struct list_head qtd_list;
148 u32 toggle;
149 u32 ping;
150 int slot;
151 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
152};
153
154struct urb_listitem {
155 struct list_head urb_list;
156 struct urb *urb;
157};
158
159/*
160 * Access functions for isp176x registers (addresses 0..0x03FF).
161 */
162static u32 reg_read32(void __iomem *base, u32 reg)
163{
164 return isp1760_read32(base, reg);
165}
166
167static void reg_write32(void __iomem *base, u32 reg, u32 val)
168{
169 isp1760_write32(base, reg, val);
170}
171
172/*
173 * Access functions for isp176x memory (offset >= 0x0400).
174 *
175 * bank_reads8() reads memory locations prefetched by an earlier write to
176 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
177 * bank optimizations, you should use the more generic mem_reads8() below.
178 *
179 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
180 * below.
181 *
182 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
183 * doesn't quite work because some people have to enforce 32-bit access
184 */
185static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
186 __u32 *dst, u32 bytes)
187{
188 __u32 __iomem *src;
189 u32 val;
190 __u8 *src_byteptr;
191 __u8 *dst_byteptr;
192
193 src = src_base + (bank_addr | src_offset);
194
195 if (src_offset < PAYLOAD_OFFSET) {
196 while (bytes >= 4) {
197 *dst = le32_to_cpu(__raw_readl(src));
198 bytes -= 4;
199 src++;
200 dst++;
201 }
202 } else {
203 while (bytes >= 4) {
204 *dst = __raw_readl(src);
205 bytes -= 4;
206 src++;
207 dst++;
208 }
209 }
210
211 if (!bytes)
212 return;
213
214 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
215 * allocated.
216 */
217 if (src_offset < PAYLOAD_OFFSET)
218 val = le32_to_cpu(__raw_readl(src));
219 else
220 val = __raw_readl(src);
221
222 dst_byteptr = (void *) dst;
223 src_byteptr = (void *) &val;
224 while (bytes > 0) {
225 *dst_byteptr = *src_byteptr;
226 dst_byteptr++;
227 src_byteptr++;
228 bytes--;
229 }
230}
231
232static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
233 u32 bytes)
234{
235 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
236 ndelay(90);
237 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
238}
239
240static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
241 __u32 const *src, u32 bytes)
242{
243 __u32 __iomem *dst;
244
245 dst = dst_base + dst_offset;
246
247 if (dst_offset < PAYLOAD_OFFSET) {
248 while (bytes >= 4) {
249 __raw_writel(cpu_to_le32(*src), dst);
250 bytes -= 4;
251 src++;
252 dst++;
253 }
254 } else {
255 while (bytes >= 4) {
256 __raw_writel(*src, dst);
257 bytes -= 4;
258 src++;
259 dst++;
260 }
261 }
262
263 if (!bytes)
264 return;
265 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
266 * extra bytes should not be read by the HW.
267 */
268
269 if (dst_offset < PAYLOAD_OFFSET)
270 __raw_writel(cpu_to_le32(*src), dst);
271 else
272 __raw_writel(*src, dst);
273}
274
275/*
276 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
277 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
278 */
279static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
280 struct ptd *ptd)
281{
282 reg_write32(base, HC_MEMORY_REG,
283 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
284 ndelay(90);
285 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
286 (void *) ptd, sizeof(*ptd));
287}
288
289static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
290 struct ptd *ptd)
291{
292 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
293 &ptd->dw1, 7*sizeof(ptd->dw1));
294 /* Make sure dw0 gets written last (after other dw's and after payload)
295 since it contains the enable bit */
296 wmb();
297 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
298 sizeof(ptd->dw0));
299}
300
301
302/* memory management of the 60kb on the chip from 0x1000 to 0xffff */
303static void init_memory(struct isp1760_hcd *priv)
304{
305 int i, curr;
306 u32 payload_addr;
307
308 payload_addr = PAYLOAD_OFFSET;
309 for (i = 0; i < BLOCK_1_NUM; i++) {
310 priv->memory_pool[i].start = payload_addr;
311 priv->memory_pool[i].size = BLOCK_1_SIZE;
312 priv->memory_pool[i].free = 1;
313 payload_addr += priv->memory_pool[i].size;
314 }
315
316 curr = i;
317 for (i = 0; i < BLOCK_2_NUM; i++) {
318 priv->memory_pool[curr + i].start = payload_addr;
319 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
320 priv->memory_pool[curr + i].free = 1;
321 payload_addr += priv->memory_pool[curr + i].size;
322 }
323
324 curr = i;
325 for (i = 0; i < BLOCK_3_NUM; i++) {
326 priv->memory_pool[curr + i].start = payload_addr;
327 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
328 priv->memory_pool[curr + i].free = 1;
329 payload_addr += priv->memory_pool[curr + i].size;
330 }
331
332 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
333}
334
335static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
336{
337 struct isp1760_hcd *priv = hcd_to_priv(hcd);
338 int i;
339
340 WARN_ON(qtd->payload_addr);
341
342 if (!qtd->length)
343 return;
344
345 for (i = 0; i < BLOCKS; i++) {
346 if (priv->memory_pool[i].size >= qtd->length &&
347 priv->memory_pool[i].free) {
348 priv->memory_pool[i].free = 0;
349 qtd->payload_addr = priv->memory_pool[i].start;
350 return;
351 }
352 }
353}
354
355static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
356{
357 struct isp1760_hcd *priv = hcd_to_priv(hcd);
358 int i;
359
360 if (!qtd->payload_addr)
361 return;
362
363 for (i = 0; i < BLOCKS; i++) {
364 if (priv->memory_pool[i].start == qtd->payload_addr) {
365 WARN_ON(priv->memory_pool[i].free);
366 priv->memory_pool[i].free = 1;
367 qtd->payload_addr = 0;
368 return;
369 }
370 }
371
372 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
373 __func__, qtd->payload_addr);
374 WARN_ON(1);
375 qtd->payload_addr = 0;
376}
377
378static int handshake(struct usb_hcd *hcd, u32 reg,
379 u32 mask, u32 done, int usec)
380{
381 u32 result;
382
383 do {
384 result = reg_read32(hcd->regs, reg);
385 if (result == ~0)
386 return -ENODEV;
387 result &= mask;
388 if (result == done)
389 return 0;
390 udelay(1);
391 usec--;
392 } while (usec > 0);
393 return -ETIMEDOUT;
394}
395
396/* reset a non-running (STS_HALT == 1) controller */
397static int ehci_reset(struct usb_hcd *hcd)
398{
399 int retval;
400 struct isp1760_hcd *priv = hcd_to_priv(hcd);
401
402 u32 command = reg_read32(hcd->regs, HC_USBCMD);
403
404 command |= CMD_RESET;
405 reg_write32(hcd->regs, HC_USBCMD, command);
406 hcd->state = HC_STATE_HALT;
407 priv->next_statechange = jiffies;
408 retval = handshake(hcd, HC_USBCMD,
409 CMD_RESET, 0, 250 * 1000);
410 return retval;
411}
412
413static struct isp1760_qh *qh_alloc(gfp_t flags)
414{
415 struct isp1760_qh *qh;
416
417 qh = kmem_cache_zalloc(qh_cachep, flags);
418 if (!qh)
419 return NULL;
420
421 INIT_LIST_HEAD(&qh->qh_list);
422 INIT_LIST_HEAD(&qh->qtd_list);
423 qh->slot = -1;
424
425 return qh;
426}
427
428static void qh_free(struct isp1760_qh *qh)
429{
430 WARN_ON(!list_empty(&qh->qtd_list));
431 WARN_ON(qh->slot > -1);
432 kmem_cache_free(qh_cachep, qh);
433}
434
435/* one-time init, only for memory state */
436static int priv_init(struct usb_hcd *hcd)
437{
438 struct isp1760_hcd *priv = hcd_to_priv(hcd);
439 u32 hcc_params;
440 int i;
441
442 spin_lock_init(&priv->lock);
443
444 for (i = 0; i < QH_END; i++)
445 INIT_LIST_HEAD(&priv->qh_list[i]);
446
447 /*
448 * hw default: 1K periodic list heads, one per frame.
449 * periodic_size can shrink by USBCMD update if hcc_params allows.
450 */
451 priv->periodic_size = DEFAULT_I_TDPS;
452
453 /* controllers may cache some of the periodic schedule ... */
454 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
455 /* full frame cache */
456 if (HCC_ISOC_CACHE(hcc_params))
457 priv->i_thresh = 8;
458 else /* N microframes cached */
459 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
460
461 return 0;
462}
463
464static int isp1760_hc_setup(struct usb_hcd *hcd)
465{
466 struct isp1760_hcd *priv = hcd_to_priv(hcd);
467 int result;
468 u32 scratch, hwmode;
469
470 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
471 /* Change bus pattern */
472 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
473 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
474 if (scratch != 0xdeadbabe) {
475 dev_err(hcd->self.controller, "Scratch test failed.\n");
476 return -ENODEV;
477 }
478
479 /*
480 * The RESET_HC bit in the SW_RESET register is supposed to reset the
481 * host controller without touching the CPU interface registers, but at
482 * least on the ISP1761 it seems to behave as the RESET_ALL bit and
483 * reset the whole device. We thus can't use it here, so let's reset
484 * the host controller through the EHCI USB Command register. The device
485 * has been reset in core code anyway, so this shouldn't matter.
486 */
487 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
488 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
489 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
490 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
491
492 result = ehci_reset(hcd);
493 if (result)
494 return result;
495
496 /* Step 11 passed */
497
498 /* ATL reset */
499 hwmode = reg_read32(hcd->regs, HC_HW_MODE_CTRL) & ~ALL_ATX_RESET;
500 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
501 mdelay(10);
502 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
503
504 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
505
506 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
507
508 return priv_init(hcd);
509}
510
511static u32 base_to_chip(u32 base)
512{
513 return ((base - 0x400) >> 3);
514}
515
516static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
517{
518 struct urb *urb;
519
520 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
521 return 1;
522
523 urb = qtd->urb;
524 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
525 return (qtd->urb != urb);
526}
527
528/* magic numbers that can affect system performance */
529#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
530#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
531#define EHCI_TUNE_RL_TT 0
532#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
533#define EHCI_TUNE_MULT_TT 1
534#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
535
536static void create_ptd_atl(struct isp1760_qh *qh,
537 struct isp1760_qtd *qtd, struct ptd *ptd)
538{
539 u32 maxpacket;
540 u32 multi;
541 u32 rl = RL_COUNTER;
542 u32 nak = NAK_COUNTER;
543
544 memset(ptd, 0, sizeof(*ptd));
545
546 /* according to 3.6.2, max packet len can not be > 0x400 */
547 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
548 usb_pipeout(qtd->urb->pipe));
549 multi = 1 + ((maxpacket >> 11) & 0x3);
550 maxpacket &= 0x7ff;
551
552 /* DW0 */
553 ptd->dw0 = DW0_VALID_BIT;
554 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
555 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
556 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
557
558 /* DW1 */
559 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
560 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
561 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
562
563 if (usb_pipebulk(qtd->urb->pipe))
564 ptd->dw1 |= DW1_TRANS_BULK;
565 else if (usb_pipeint(qtd->urb->pipe))
566 ptd->dw1 |= DW1_TRANS_INT;
567
568 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
569 /* split transaction */
570
571 ptd->dw1 |= DW1_TRANS_SPLIT;
572 if (qtd->urb->dev->speed == USB_SPEED_LOW)
573 ptd->dw1 |= DW1_SE_USB_LOSPEED;
574
575 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
576 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
577
578 /* SE bit for Split INT transfers */
579 if (usb_pipeint(qtd->urb->pipe) &&
580 (qtd->urb->dev->speed == USB_SPEED_LOW))
581 ptd->dw1 |= 2 << 16;
582
583 rl = 0;
584 nak = 0;
585 } else {
586 ptd->dw0 |= TO_DW0_MULTI(multi);
587 if (usb_pipecontrol(qtd->urb->pipe) ||
588 usb_pipebulk(qtd->urb->pipe))
589 ptd->dw3 |= TO_DW3_PING(qh->ping);
590 }
591 /* DW2 */
592 ptd->dw2 = 0;
593 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
594 ptd->dw2 |= TO_DW2_RL(rl);
595
596 /* DW3 */
597 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
598 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
599 if (usb_pipecontrol(qtd->urb->pipe)) {
600 if (qtd->data_buffer == qtd->urb->setup_packet)
601 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
602 else if (last_qtd_of_urb(qtd, qh))
603 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
604 }
605
606 ptd->dw3 |= DW3_ACTIVE_BIT;
607 /* Cerr */
608 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
609}
610
611static void transform_add_int(struct isp1760_qh *qh,
612 struct isp1760_qtd *qtd, struct ptd *ptd)
613{
614 u32 usof;
615 u32 period;
616
617 /*
618 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
619 * the algorithm from the original Philips driver code, which was
620 * pretty much used in this driver before as well, is quite horrendous
621 * and, i believe, incorrect. The code below follows the datasheet and
622 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
623 * more reliable this way (fingers crossed...).
624 */
625
626 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
627 /* urb->interval is in units of microframes (1/8 ms) */
628 period = qtd->urb->interval >> 3;
629
630 if (qtd->urb->interval > 4)
631 usof = 0x01; /* One bit set =>
632 interval 1 ms * uFrame-match */
633 else if (qtd->urb->interval > 2)
634 usof = 0x22; /* Two bits set => interval 1/2 ms */
635 else if (qtd->urb->interval > 1)
636 usof = 0x55; /* Four bits set => interval 1/4 ms */
637 else
638 usof = 0xff; /* All bits set => interval 1/8 ms */
639 } else {
640 /* urb->interval is in units of frames (1 ms) */
641 period = qtd->urb->interval;
642 usof = 0x0f; /* Execute Start Split on any of the
643 four first uFrames */
644
645 /*
646 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
647 * complete split needs to be sent. Valid only for IN." Also,
648 * "All bits can be set to one for every transfer." (p 82,
649 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
650 * that number come from? 0xff seems to work fine...
651 */
652 /* ptd->dw5 = 0x1c; */
653 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
654 }
655
656 period = period >> 1;/* Ensure equal or shorter period than requested */
657 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
658
659 ptd->dw2 |= period;
660 ptd->dw4 = usof;
661}
662
663static void create_ptd_int(struct isp1760_qh *qh,
664 struct isp1760_qtd *qtd, struct ptd *ptd)
665{
666 create_ptd_atl(qh, qtd, ptd);
667 transform_add_int(qh, qtd, ptd);
668}
669
670static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
671__releases(priv->lock)
672__acquires(priv->lock)
673{
674 struct isp1760_hcd *priv = hcd_to_priv(hcd);
675
676 if (!urb->unlinked) {
677 if (urb->status == -EINPROGRESS)
678 urb->status = 0;
679 }
680
681 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
682 void *ptr;
683 for (ptr = urb->transfer_buffer;
684 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
685 ptr += PAGE_SIZE)
686 flush_dcache_page(virt_to_page(ptr));
687 }
688
689 /* complete() can reenter this HCD */
690 usb_hcd_unlink_urb_from_ep(hcd, urb);
691 spin_unlock(&priv->lock);
692 usb_hcd_giveback_urb(hcd, urb, urb->status);
693 spin_lock(&priv->lock);
694}
695
696static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
697 u8 packet_type)
698{
699 struct isp1760_qtd *qtd;
700
701 qtd = kmem_cache_zalloc(qtd_cachep, flags);
702 if (!qtd)
703 return NULL;
704
705 INIT_LIST_HEAD(&qtd->qtd_list);
706 qtd->urb = urb;
707 qtd->packet_type = packet_type;
708 qtd->status = QTD_ENQUEUED;
709 qtd->actual_length = 0;
710
711 return qtd;
712}
713
714static void qtd_free(struct isp1760_qtd *qtd)
715{
716 WARN_ON(qtd->payload_addr);
717 kmem_cache_free(qtd_cachep, qtd);
718}
719
720static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
721 struct isp1760_slotinfo *slots,
722 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
723 struct ptd *ptd)
724{
725 struct isp1760_hcd *priv = hcd_to_priv(hcd);
726 int skip_map;
727
728 WARN_ON((slot < 0) || (slot > 31));
729 WARN_ON(qtd->length && !qtd->payload_addr);
730 WARN_ON(slots[slot].qtd);
731 WARN_ON(slots[slot].qh);
732 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
733
734 /* Make sure done map has not triggered from some unlinked transfer */
735 if (ptd_offset == ATL_PTD_OFFSET) {
736 priv->atl_done_map |= reg_read32(hcd->regs,
737 HC_ATL_PTD_DONEMAP_REG);
738 priv->atl_done_map &= ~(1 << slot);
739 } else {
740 priv->int_done_map |= reg_read32(hcd->regs,
741 HC_INT_PTD_DONEMAP_REG);
742 priv->int_done_map &= ~(1 << slot);
743 }
744
745 qh->slot = slot;
746 qtd->status = QTD_XFER_STARTED;
747 slots[slot].timestamp = jiffies;
748 slots[slot].qtd = qtd;
749 slots[slot].qh = qh;
750 ptd_write(hcd->regs, ptd_offset, slot, ptd);
751
752 if (ptd_offset == ATL_PTD_OFFSET) {
753 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
754 skip_map &= ~(1 << qh->slot);
755 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
756 } else {
757 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
758 skip_map &= ~(1 << qh->slot);
759 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
760 }
761}
762
763static int is_short_bulk(struct isp1760_qtd *qtd)
764{
765 return (usb_pipebulk(qtd->urb->pipe) &&
766 (qtd->actual_length < qtd->length));
767}
768
769static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
770 struct list_head *urb_list)
771{
772 int last_qtd;
773 struct isp1760_qtd *qtd, *qtd_next;
774 struct urb_listitem *urb_listitem;
775
776 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
777 if (qtd->status < QTD_XFER_COMPLETE)
778 break;
779
780 last_qtd = last_qtd_of_urb(qtd, qh);
781
782 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
783 qtd_next->status = QTD_RETIRE;
784
785 if (qtd->status == QTD_XFER_COMPLETE) {
786 if (qtd->actual_length) {
787 switch (qtd->packet_type) {
788 case IN_PID:
789 mem_reads8(hcd->regs, qtd->payload_addr,
790 qtd->data_buffer,
791 qtd->actual_length);
792 /* Fall through (?) */
793 case OUT_PID:
794 qtd->urb->actual_length +=
795 qtd->actual_length;
796 /* Fall through ... */
797 case SETUP_PID:
798 break;
799 }
800 }
801
802 if (is_short_bulk(qtd)) {
803 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
804 qtd->urb->status = -EREMOTEIO;
805 if (!last_qtd)
806 qtd_next->status = QTD_RETIRE;
807 }
808 }
809
810 if (qtd->payload_addr)
811 free_mem(hcd, qtd);
812
813 if (last_qtd) {
814 if ((qtd->status == QTD_RETIRE) &&
815 (qtd->urb->status == -EINPROGRESS))
816 qtd->urb->status = -EPIPE;
817 /* Defer calling of urb_done() since it releases lock */
818 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
819 GFP_ATOMIC);
820 if (unlikely(!urb_listitem))
821 break; /* Try again on next call */
822 urb_listitem->urb = qtd->urb;
823 list_add_tail(&urb_listitem->urb_list, urb_list);
824 }
825
826 list_del(&qtd->qtd_list);
827 qtd_free(qtd);
828 }
829}
830
831#define ENQUEUE_DEPTH 2
832static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
833{
834 struct isp1760_hcd *priv = hcd_to_priv(hcd);
835 int ptd_offset;
836 struct isp1760_slotinfo *slots;
837 int curr_slot, free_slot;
838 int n;
839 struct ptd ptd;
840 struct isp1760_qtd *qtd;
841
842 if (unlikely(list_empty(&qh->qtd_list))) {
843 WARN_ON(1);
844 return;
845 }
846
847 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
848 if (qh->tt_buffer_dirty)
849 return;
850
851 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
852 qtd_list)->urb->pipe)) {
853 ptd_offset = INT_PTD_OFFSET;
854 slots = priv->int_slots;
855 } else {
856 ptd_offset = ATL_PTD_OFFSET;
857 slots = priv->atl_slots;
858 }
859
860 free_slot = -1;
861 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
862 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
863 free_slot = curr_slot;
864 if (slots[curr_slot].qh == qh)
865 break;
866 }
867
868 n = 0;
869 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
870 if (qtd->status == QTD_ENQUEUED) {
871 WARN_ON(qtd->payload_addr);
872 alloc_mem(hcd, qtd);
873 if ((qtd->length) && (!qtd->payload_addr))
874 break;
875
876 if ((qtd->length) &&
877 ((qtd->packet_type == SETUP_PID) ||
878 (qtd->packet_type == OUT_PID))) {
879 mem_writes8(hcd->regs, qtd->payload_addr,
880 qtd->data_buffer, qtd->length);
881 }
882
883 qtd->status = QTD_PAYLOAD_ALLOC;
884 }
885
886 if (qtd->status == QTD_PAYLOAD_ALLOC) {
887/*
888 if ((curr_slot > 31) && (free_slot == -1))
889 dev_dbg(hcd->self.controller, "%s: No slot "
890 "available for transfer\n", __func__);
891*/
892 /* Start xfer for this endpoint if not already done */
893 if ((curr_slot > 31) && (free_slot > -1)) {
894 if (usb_pipeint(qtd->urb->pipe))
895 create_ptd_int(qh, qtd, &ptd);
896 else
897 create_ptd_atl(qh, qtd, &ptd);
898
899 start_bus_transfer(hcd, ptd_offset, free_slot,
900 slots, qtd, qh, &ptd);
901 curr_slot = free_slot;
902 }
903
904 n++;
905 if (n >= ENQUEUE_DEPTH)
906 break;
907 }
908 }
909}
910
911static void schedule_ptds(struct usb_hcd *hcd)
912{
913 struct isp1760_hcd *priv;
914 struct isp1760_qh *qh, *qh_next;
915 struct list_head *ep_queue;
916 LIST_HEAD(urb_list);
917 struct urb_listitem *urb_listitem, *urb_listitem_next;
918 int i;
919
920 if (!hcd) {
921 WARN_ON(1);
922 return;
923 }
924
925 priv = hcd_to_priv(hcd);
926
927 /*
928 * check finished/retired xfers, transfer payloads, call urb_done()
929 */
930 for (i = 0; i < QH_END; i++) {
931 ep_queue = &priv->qh_list[i];
932 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
933 collect_qtds(hcd, qh, &urb_list);
934 if (list_empty(&qh->qtd_list))
935 list_del(&qh->qh_list);
936 }
937 }
938
939 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
940 urb_list) {
941 isp1760_urb_done(hcd, urb_listitem->urb);
942 kmem_cache_free(urb_listitem_cachep, urb_listitem);
943 }
944
945 /*
946 * Schedule packets for transfer.
947 *
948 * According to USB2.0 specification:
949 *
950 * 1st prio: interrupt xfers, up to 80 % of bandwidth
951 * 2nd prio: control xfers
952 * 3rd prio: bulk xfers
953 *
954 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
955 * is very unclear on how to prioritize traffic):
956 *
957 * 1) Enqueue any queued control transfers, as long as payload chip mem
958 * and PTD ATL slots are available.
959 * 2) Enqueue any queued INT transfers, as long as payload chip mem
960 * and PTD INT slots are available.
961 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
962 * and PTD ATL slots are available.
963 *
964 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
965 * conservation of chip mem and performance.
966 *
967 * I'm sure this scheme could be improved upon!
968 */
969 for (i = 0; i < QH_END; i++) {
970 ep_queue = &priv->qh_list[i];
971 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
972 enqueue_qtds(hcd, qh);
973 }
974}
975
976#define PTD_STATE_QTD_DONE 1
977#define PTD_STATE_QTD_RELOAD 2
978#define PTD_STATE_URB_RETIRE 3
979
980static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
981 struct urb *urb)
982{
983 __dw dw4;
984 int i;
985
986 dw4 = ptd->dw4;
987 dw4 >>= 8;
988
989 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
990 need to handle these errors? Is it done in hardware? */
991
992 if (ptd->dw3 & DW3_HALT_BIT) {
993
994 urb->status = -EPROTO; /* Default unknown error */
995
996 for (i = 0; i < 8; i++) {
997 switch (dw4 & 0x7) {
998 case INT_UNDERRUN:
999 dev_dbg(hcd->self.controller, "%s: underrun "
1000 "during uFrame %d\n",
1001 __func__, i);
1002 urb->status = -ECOMM; /* Could not write data */
1003 break;
1004 case INT_EXACT:
1005 dev_dbg(hcd->self.controller, "%s: transaction "
1006 "error during uFrame %d\n",
1007 __func__, i);
1008 urb->status = -EPROTO; /* timeout, bad CRC, PID
1009 error etc. */
1010 break;
1011 case INT_BABBLE:
1012 dev_dbg(hcd->self.controller, "%s: babble "
1013 "error during uFrame %d\n",
1014 __func__, i);
1015 urb->status = -EOVERFLOW;
1016 break;
1017 }
1018 dw4 >>= 3;
1019 }
1020
1021 return PTD_STATE_URB_RETIRE;
1022 }
1023
1024 return PTD_STATE_QTD_DONE;
1025}
1026
1027static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1028 struct urb *urb)
1029{
1030 WARN_ON(!ptd);
1031 if (ptd->dw3 & DW3_HALT_BIT) {
1032 if (ptd->dw3 & DW3_BABBLE_BIT)
1033 urb->status = -EOVERFLOW;
1034 else if (FROM_DW3_CERR(ptd->dw3))
1035 urb->status = -EPIPE; /* Stall */
1036 else if (ptd->dw3 & DW3_ERROR_BIT)
1037 urb->status = -EPROTO; /* XactErr */
1038 else
1039 urb->status = -EPROTO; /* Unknown */
1040/*
1041 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1042 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1043 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1044 __func__,
1045 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1046 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1047*/
1048 return PTD_STATE_URB_RETIRE;
1049 }
1050
1051 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1052 /* Transfer Error, *but* active and no HALT -> reload */
1053 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1054 return PTD_STATE_QTD_RELOAD;
1055 }
1056
1057 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1058 /*
1059 * NAKs are handled in HW by the chip. Usually if the
1060 * device is not able to send data fast enough.
1061 * This happens mostly on slower hardware.
1062 */
1063 return PTD_STATE_QTD_RELOAD;
1064 }
1065
1066 return PTD_STATE_QTD_DONE;
1067}
1068
1069static void handle_done_ptds(struct usb_hcd *hcd)
1070{
1071 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1072 struct ptd ptd;
1073 struct isp1760_qh *qh;
1074 int slot;
1075 int state;
1076 struct isp1760_slotinfo *slots;
1077 u32 ptd_offset;
1078 struct isp1760_qtd *qtd;
1079 int modified;
1080 int skip_map;
1081
1082 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1083 priv->int_done_map &= ~skip_map;
1084 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1085 priv->atl_done_map &= ~skip_map;
1086
1087 modified = priv->int_done_map || priv->atl_done_map;
1088
1089 while (priv->int_done_map || priv->atl_done_map) {
1090 if (priv->int_done_map) {
1091 /* INT ptd */
1092 slot = __ffs(priv->int_done_map);
1093 priv->int_done_map &= ~(1 << slot);
1094 slots = priv->int_slots;
1095 /* This should not trigger, and could be removed if
1096 noone have any problems with it triggering: */
1097 if (!slots[slot].qh) {
1098 WARN_ON(1);
1099 continue;
1100 }
1101 ptd_offset = INT_PTD_OFFSET;
1102 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1103 state = check_int_transfer(hcd, &ptd,
1104 slots[slot].qtd->urb);
1105 } else {
1106 /* ATL ptd */
1107 slot = __ffs(priv->atl_done_map);
1108 priv->atl_done_map &= ~(1 << slot);
1109 slots = priv->atl_slots;
1110 /* This should not trigger, and could be removed if
1111 noone have any problems with it triggering: */
1112 if (!slots[slot].qh) {
1113 WARN_ON(1);
1114 continue;
1115 }
1116 ptd_offset = ATL_PTD_OFFSET;
1117 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1118 state = check_atl_transfer(hcd, &ptd,
1119 slots[slot].qtd->urb);
1120 }
1121
1122 qtd = slots[slot].qtd;
1123 slots[slot].qtd = NULL;
1124 qh = slots[slot].qh;
1125 slots[slot].qh = NULL;
1126 qh->slot = -1;
1127
1128 WARN_ON(qtd->status != QTD_XFER_STARTED);
1129
1130 switch (state) {
1131 case PTD_STATE_QTD_DONE:
1132 if ((usb_pipeint(qtd->urb->pipe)) &&
1133 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1134 qtd->actual_length =
1135 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1136 else
1137 qtd->actual_length =
1138 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1139
1140 qtd->status = QTD_XFER_COMPLETE;
1141 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1142 is_short_bulk(qtd))
1143 qtd = NULL;
1144 else
1145 qtd = list_entry(qtd->qtd_list.next,
1146 typeof(*qtd), qtd_list);
1147
1148 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1149 qh->ping = FROM_DW3_PING(ptd.dw3);
1150 break;
1151
1152 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1153 qtd->status = QTD_PAYLOAD_ALLOC;
1154 ptd.dw0 |= DW0_VALID_BIT;
1155 /* RL counter = ERR counter */
1156 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1157 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1158 ptd.dw3 &= ~TO_DW3_CERR(3);
1159 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1160 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1161 qh->ping = FROM_DW3_PING(ptd.dw3);
1162 break;
1163
1164 case PTD_STATE_URB_RETIRE:
1165 qtd->status = QTD_RETIRE;
1166 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1167 (qtd->urb->status != -EPIPE) &&
1168 (qtd->urb->status != -EREMOTEIO)) {
1169 qh->tt_buffer_dirty = 1;
1170 if (usb_hub_clear_tt_buffer(qtd->urb))
1171 /* Clear failed; let's hope things work
1172 anyway */
1173 qh->tt_buffer_dirty = 0;
1174 }
1175 qtd = NULL;
1176 qh->toggle = 0;
1177 qh->ping = 0;
1178 break;
1179
1180 default:
1181 WARN_ON(1);
1182 continue;
1183 }
1184
1185 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1186 if (slots == priv->int_slots) {
1187 if (state == PTD_STATE_QTD_RELOAD)
1188 dev_err(hcd->self.controller,
1189 "%s: PTD_STATE_QTD_RELOAD on "
1190 "interrupt packet\n", __func__);
1191 if (state != PTD_STATE_QTD_RELOAD)
1192 create_ptd_int(qh, qtd, &ptd);
1193 } else {
1194 if (state != PTD_STATE_QTD_RELOAD)
1195 create_ptd_atl(qh, qtd, &ptd);
1196 }
1197
1198 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1199 qh, &ptd);
1200 }
1201 }
1202
1203 if (modified)
1204 schedule_ptds(hcd);
1205}
1206
1207static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1208{
1209 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1210 u32 imask;
1211 irqreturn_t irqret = IRQ_NONE;
1212
1213 spin_lock(&priv->lock);
1214
1215 if (!(hcd->state & HC_STATE_RUNNING))
1216 goto leave;
1217
1218 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1219 if (unlikely(!imask))
1220 goto leave;
1221 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1222
1223 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1224 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1225
1226 handle_done_ptds(hcd);
1227
1228 irqret = IRQ_HANDLED;
1229leave:
1230 spin_unlock(&priv->lock);
1231
1232 return irqret;
1233}
1234
1235/*
1236 * Workaround for problem described in chip errata 2:
1237 *
1238 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1239 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1240 * ATL done interrupts (the "instead of" might be important since it seems
1241 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1242 * to set the PTD's done bit in addition to not generating an interrupt!).
1243 *
1244 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1245 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1246 *
1247 * If we use SOF interrupts only, we get latency between ptd completion and the
1248 * actual handling. This is very noticeable in testusb runs which takes several
1249 * minutes longer without ATL interrupts.
1250 *
1251 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1252 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1253 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1254 * completed and its done map bit is set.
1255 *
1256 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1257 * not to cause too much lag when this HW bug occurs, while still hopefully
1258 * ensuring that the check does not falsely trigger.
1259 */
1260#define SLOT_TIMEOUT 300
1261#define SLOT_CHECK_PERIOD 200
1262static struct timer_list errata2_timer;
1263
1264static void errata2_function(unsigned long data)
1265{
1266 struct usb_hcd *hcd = (struct usb_hcd *) data;
1267 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1268 int slot;
1269 struct ptd ptd;
1270 unsigned long spinflags;
1271
1272 spin_lock_irqsave(&priv->lock, spinflags);
1273
1274 for (slot = 0; slot < 32; slot++)
1275 if (priv->atl_slots[slot].qh && time_after(jiffies,
1276 priv->atl_slots[slot].timestamp +
1277 SLOT_TIMEOUT * HZ / 1000)) {
1278 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1279 if (!FROM_DW0_VALID(ptd.dw0) &&
1280 !FROM_DW3_ACTIVE(ptd.dw3))
1281 priv->atl_done_map |= 1 << slot;
1282 }
1283
1284 if (priv->atl_done_map)
1285 handle_done_ptds(hcd);
1286
1287 spin_unlock_irqrestore(&priv->lock, spinflags);
1288
1289 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1290 add_timer(&errata2_timer);
1291}
1292
1293static int isp1760_run(struct usb_hcd *hcd)
1294{
1295 int retval;
1296 u32 temp;
1297 u32 command;
1298 u32 chipid;
1299
1300 hcd->uses_new_polling = 1;
1301
1302 hcd->state = HC_STATE_RUNNING;
1303
1304 /* Set PTD interrupt AND & OR maps */
1305 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1306 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1307 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1308 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1309 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1310 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1311 /* step 23 passed */
1312
1313 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1314 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1315
1316 command = reg_read32(hcd->regs, HC_USBCMD);
1317 command &= ~(CMD_LRESET|CMD_RESET);
1318 command |= CMD_RUN;
1319 reg_write32(hcd->regs, HC_USBCMD, command);
1320
1321 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1322 if (retval)
1323 return retval;
1324
1325 /*
1326 * XXX
1327 * Spec says to write FLAG_CF as last config action, priv code grabs
1328 * the semaphore while doing so.
1329 */
1330 down_write(&ehci_cf_port_reset_rwsem);
1331 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1332
1333 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1334 up_write(&ehci_cf_port_reset_rwsem);
1335 if (retval)
1336 return retval;
1337
1338 init_timer(&errata2_timer);
1339 errata2_timer.function = errata2_function;
1340 errata2_timer.data = (unsigned long) hcd;
1341 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1342 add_timer(&errata2_timer);
1343
1344 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1345 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1346 chipid & 0xffff, chipid >> 16);
1347
1348 /* PTD Register Init Part 2, Step 28 */
1349
1350 /* Setup registers controlling PTD checking */
1351 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1352 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1353 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1354 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1355 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1356 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1357 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1358 ATL_BUF_FILL | INT_BUF_FILL);
1359
1360 /* GRR this is run-once init(), being done every time the HC starts.
1361 * So long as they're part of class devices, we can't do it init()
1362 * since the class device isn't created that early.
1363 */
1364 return 0;
1365}
1366
1367static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1368{
1369 qtd->data_buffer = databuffer;
1370
1371 if (len > MAX_PAYLOAD_SIZE)
1372 len = MAX_PAYLOAD_SIZE;
1373 qtd->length = len;
1374
1375 return qtd->length;
1376}
1377
1378static void qtd_list_free(struct list_head *qtd_list)
1379{
1380 struct isp1760_qtd *qtd, *qtd_next;
1381
1382 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1383 list_del(&qtd->qtd_list);
1384 qtd_free(qtd);
1385 }
1386}
1387
1388/*
1389 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1390 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1391 */
1392#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1393static void packetize_urb(struct usb_hcd *hcd,
1394 struct urb *urb, struct list_head *head, gfp_t flags)
1395{
1396 struct isp1760_qtd *qtd;
1397 void *buf;
1398 int len, maxpacketsize;
1399 u8 packet_type;
1400
1401 /*
1402 * URBs map to sequences of QTDs: one logical transaction
1403 */
1404
1405 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1406 /* XXX This looks like usb storage / SCSI bug */
1407 dev_err(hcd->self.controller,
1408 "buf is null, dma is %08lx len is %d\n",
1409 (long unsigned)urb->transfer_dma,
1410 urb->transfer_buffer_length);
1411 WARN_ON(1);
1412 }
1413
1414 if (usb_pipein(urb->pipe))
1415 packet_type = IN_PID;
1416 else
1417 packet_type = OUT_PID;
1418
1419 if (usb_pipecontrol(urb->pipe)) {
1420 qtd = qtd_alloc(flags, urb, SETUP_PID);
1421 if (!qtd)
1422 goto cleanup;
1423 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1424 list_add_tail(&qtd->qtd_list, head);
1425
1426 /* for zero length DATA stages, STATUS is always IN */
1427 if (urb->transfer_buffer_length == 0)
1428 packet_type = IN_PID;
1429 }
1430
1431 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1432 usb_pipeout(urb->pipe)));
1433
1434 /*
1435 * buffer gets wrapped in one or more qtds;
1436 * last one may be "short" (including zero len)
1437 * and may serve as a control status ack
1438 */
1439 buf = urb->transfer_buffer;
1440 len = urb->transfer_buffer_length;
1441
1442 for (;;) {
1443 int this_qtd_len;
1444
1445 qtd = qtd_alloc(flags, urb, packet_type);
1446 if (!qtd)
1447 goto cleanup;
1448 this_qtd_len = qtd_fill(qtd, buf, len);
1449 list_add_tail(&qtd->qtd_list, head);
1450
1451 len -= this_qtd_len;
1452 buf += this_qtd_len;
1453
1454 if (len <= 0)
1455 break;
1456 }
1457
1458 /*
1459 * control requests may need a terminating data "status" ack;
1460 * bulk ones may need a terminating short packet (zero length).
1461 */
1462 if (urb->transfer_buffer_length != 0) {
1463 int one_more = 0;
1464
1465 if (usb_pipecontrol(urb->pipe)) {
1466 one_more = 1;
1467 if (packet_type == IN_PID)
1468 packet_type = OUT_PID;
1469 else
1470 packet_type = IN_PID;
1471 } else if (usb_pipebulk(urb->pipe)
1472 && (urb->transfer_flags & URB_ZERO_PACKET)
1473 && !(urb->transfer_buffer_length %
1474 maxpacketsize)) {
1475 one_more = 1;
1476 }
1477 if (one_more) {
1478 qtd = qtd_alloc(flags, urb, packet_type);
1479 if (!qtd)
1480 goto cleanup;
1481
1482 /* never any data in such packets */
1483 qtd_fill(qtd, NULL, 0);
1484 list_add_tail(&qtd->qtd_list, head);
1485 }
1486 }
1487
1488 return;
1489
1490cleanup:
1491 qtd_list_free(head);
1492}
1493
1494static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1495 gfp_t mem_flags)
1496{
1497 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1498 struct list_head *ep_queue;
1499 struct isp1760_qh *qh, *qhit;
1500 unsigned long spinflags;
1501 LIST_HEAD(new_qtds);
1502 int retval;
1503 int qh_in_queue;
1504
1505 switch (usb_pipetype(urb->pipe)) {
1506 case PIPE_CONTROL:
1507 ep_queue = &priv->qh_list[QH_CONTROL];
1508 break;
1509 case PIPE_BULK:
1510 ep_queue = &priv->qh_list[QH_BULK];
1511 break;
1512 case PIPE_INTERRUPT:
1513 if (urb->interval < 0)
1514 return -EINVAL;
1515 /* FIXME: Check bandwidth */
1516 ep_queue = &priv->qh_list[QH_INTERRUPT];
1517 break;
1518 case PIPE_ISOCHRONOUS:
1519 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1520 "not yet supported\n",
1521 __func__);
1522 return -EPIPE;
1523 default:
1524 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1525 __func__);
1526 return -EPIPE;
1527 }
1528
1529 if (usb_pipein(urb->pipe))
1530 urb->actual_length = 0;
1531
1532 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1533 if (list_empty(&new_qtds))
1534 return -ENOMEM;
1535
1536 retval = 0;
1537 spin_lock_irqsave(&priv->lock, spinflags);
1538
1539 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1540 retval = -ESHUTDOWN;
1541 qtd_list_free(&new_qtds);
1542 goto out;
1543 }
1544 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1545 if (retval) {
1546 qtd_list_free(&new_qtds);
1547 goto out;
1548 }
1549
1550 qh = urb->ep->hcpriv;
1551 if (qh) {
1552 qh_in_queue = 0;
1553 list_for_each_entry(qhit, ep_queue, qh_list) {
1554 if (qhit == qh) {
1555 qh_in_queue = 1;
1556 break;
1557 }
1558 }
1559 if (!qh_in_queue)
1560 list_add_tail(&qh->qh_list, ep_queue);
1561 } else {
1562 qh = qh_alloc(GFP_ATOMIC);
1563 if (!qh) {
1564 retval = -ENOMEM;
1565 usb_hcd_unlink_urb_from_ep(hcd, urb);
1566 qtd_list_free(&new_qtds);
1567 goto out;
1568 }
1569 list_add_tail(&qh->qh_list, ep_queue);
1570 urb->ep->hcpriv = qh;
1571 }
1572
1573 list_splice_tail(&new_qtds, &qh->qtd_list);
1574 schedule_ptds(hcd);
1575
1576out:
1577 spin_unlock_irqrestore(&priv->lock, spinflags);
1578 return retval;
1579}
1580
1581static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1582 struct isp1760_qh *qh)
1583{
1584 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1585 int skip_map;
1586
1587 WARN_ON(qh->slot == -1);
1588
1589 /* We need to forcefully reclaim the slot since some transfers never
1590 return, e.g. interrupt transfers and NAKed bulk transfers. */
1591 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1592 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1593 skip_map |= (1 << qh->slot);
1594 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1595 priv->atl_slots[qh->slot].qh = NULL;
1596 priv->atl_slots[qh->slot].qtd = NULL;
1597 } else {
1598 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1599 skip_map |= (1 << qh->slot);
1600 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1601 priv->int_slots[qh->slot].qh = NULL;
1602 priv->int_slots[qh->slot].qtd = NULL;
1603 }
1604
1605 qh->slot = -1;
1606}
1607
1608/*
1609 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1610 * any active transfer belonging to the urb in the process.
1611 */
1612static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1613 struct isp1760_qtd *qtd)
1614{
1615 struct urb *urb;
1616 int urb_was_running;
1617
1618 urb = qtd->urb;
1619 urb_was_running = 0;
1620 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1621 if (qtd->urb != urb)
1622 break;
1623
1624 if (qtd->status >= QTD_XFER_STARTED)
1625 urb_was_running = 1;
1626 if (last_qtd_of_urb(qtd, qh) &&
1627 (qtd->status >= QTD_XFER_COMPLETE))
1628 urb_was_running = 0;
1629
1630 if (qtd->status == QTD_XFER_STARTED)
1631 kill_transfer(hcd, urb, qh);
1632 qtd->status = QTD_RETIRE;
1633 }
1634
1635 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1636 qh->tt_buffer_dirty = 1;
1637 if (usb_hub_clear_tt_buffer(urb))
1638 /* Clear failed; let's hope things work anyway */
1639 qh->tt_buffer_dirty = 0;
1640 }
1641}
1642
1643static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1644 int status)
1645{
1646 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1647 unsigned long spinflags;
1648 struct isp1760_qh *qh;
1649 struct isp1760_qtd *qtd;
1650 int retval = 0;
1651
1652 spin_lock_irqsave(&priv->lock, spinflags);
1653 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1654 if (retval)
1655 goto out;
1656
1657 qh = urb->ep->hcpriv;
1658 if (!qh) {
1659 retval = -EINVAL;
1660 goto out;
1661 }
1662
1663 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1664 if (qtd->urb == urb) {
1665 dequeue_urb_from_qtd(hcd, qh, qtd);
1666 list_move(&qtd->qtd_list, &qh->qtd_list);
1667 break;
1668 }
1669
1670 urb->status = status;
1671 schedule_ptds(hcd);
1672
1673out:
1674 spin_unlock_irqrestore(&priv->lock, spinflags);
1675 return retval;
1676}
1677
1678static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1679 struct usb_host_endpoint *ep)
1680{
1681 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1682 unsigned long spinflags;
1683 struct isp1760_qh *qh, *qh_iter;
1684 int i;
1685
1686 spin_lock_irqsave(&priv->lock, spinflags);
1687
1688 qh = ep->hcpriv;
1689 if (!qh)
1690 goto out;
1691
1692 WARN_ON(!list_empty(&qh->qtd_list));
1693
1694 for (i = 0; i < QH_END; i++)
1695 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1696 if (qh_iter == qh) {
1697 list_del(&qh_iter->qh_list);
1698 i = QH_END;
1699 break;
1700 }
1701 qh_free(qh);
1702 ep->hcpriv = NULL;
1703
1704 schedule_ptds(hcd);
1705
1706out:
1707 spin_unlock_irqrestore(&priv->lock, spinflags);
1708}
1709
1710static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1711{
1712 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1713 u32 temp, status = 0;
1714 u32 mask;
1715 int retval = 1;
1716 unsigned long flags;
1717
1718 /* if !PM, root hub timers won't get shut down ... */
1719 if (!HC_IS_RUNNING(hcd->state))
1720 return 0;
1721
1722 /* init status to no-changes */
1723 buf[0] = 0;
1724 mask = PORT_CSC;
1725
1726 spin_lock_irqsave(&priv->lock, flags);
1727 temp = reg_read32(hcd->regs, HC_PORTSC1);
1728
1729 if (temp & PORT_OWNER) {
1730 if (temp & PORT_CSC) {
1731 temp &= ~PORT_CSC;
1732 reg_write32(hcd->regs, HC_PORTSC1, temp);
1733 goto done;
1734 }
1735 }
1736
1737 /*
1738 * Return status information even for ports with OWNER set.
1739 * Otherwise hub_wq wouldn't see the disconnect event when a
1740 * high-speed device is switched over to the companion
1741 * controller by the user.
1742 */
1743
1744 if ((temp & mask) != 0
1745 || ((temp & PORT_RESUME) != 0
1746 && time_after_eq(jiffies,
1747 priv->reset_done))) {
1748 buf [0] |= 1 << (0 + 1);
1749 status = STS_PCD;
1750 }
1751 /* FIXME autosuspend idle root hubs */
1752done:
1753 spin_unlock_irqrestore(&priv->lock, flags);
1754 return status ? retval : 0;
1755}
1756
1757static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1758 struct usb_hub_descriptor *desc)
1759{
1760 int ports = HCS_N_PORTS(priv->hcs_params);
1761 u16 temp;
1762
1763 desc->bDescriptorType = 0x29;
1764 /* priv 1.0, 2.3.9 says 20ms max */
1765 desc->bPwrOn2PwrGood = 10;
1766 desc->bHubContrCurrent = 0;
1767
1768 desc->bNbrPorts = ports;
1769 temp = 1 + (ports / 8);
1770 desc->bDescLength = 7 + 2 * temp;
1771
1772 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1773 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1774 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1775
1776 /* per-port overcurrent reporting */
1777 temp = 0x0008;
1778 if (HCS_PPC(priv->hcs_params))
1779 /* per-port power control */
1780 temp |= 0x0001;
1781 else
1782 /* no power switching */
1783 temp |= 0x0002;
1784 desc->wHubCharacteristics = cpu_to_le16(temp);
1785}
1786
1787#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1788
1789static int check_reset_complete(struct usb_hcd *hcd, int index,
1790 int port_status)
1791{
1792 if (!(port_status & PORT_CONNECT))
1793 return port_status;
1794
1795 /* if reset finished and it's still not enabled -- handoff */
1796 if (!(port_status & PORT_PE)) {
1797
1798 dev_info(hcd->self.controller,
1799 "port %d full speed --> companion\n",
1800 index + 1);
1801
1802 port_status |= PORT_OWNER;
1803 port_status &= ~PORT_RWC_BITS;
1804 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1805
1806 } else
1807 dev_info(hcd->self.controller, "port %d high speed\n",
1808 index + 1);
1809
1810 return port_status;
1811}
1812
1813static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1814 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1815{
1816 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1817 int ports = HCS_N_PORTS(priv->hcs_params);
1818 u32 temp, status;
1819 unsigned long flags;
1820 int retval = 0;
1821 unsigned selector;
1822
1823 /*
1824 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1825 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1826 * (track current state ourselves) ... blink for diagnostics,
1827 * power, "this is the one", etc. EHCI spec supports this.
1828 */
1829
1830 spin_lock_irqsave(&priv->lock, flags);
1831 switch (typeReq) {
1832 case ClearHubFeature:
1833 switch (wValue) {
1834 case C_HUB_LOCAL_POWER:
1835 case C_HUB_OVER_CURRENT:
1836 /* no hub-wide feature/status flags */
1837 break;
1838 default:
1839 goto error;
1840 }
1841 break;
1842 case ClearPortFeature:
1843 if (!wIndex || wIndex > ports)
1844 goto error;
1845 wIndex--;
1846 temp = reg_read32(hcd->regs, HC_PORTSC1);
1847
1848 /*
1849 * Even if OWNER is set, so the port is owned by the
1850 * companion controller, hub_wq needs to be able to clear
1851 * the port-change status bits (especially
1852 * USB_PORT_STAT_C_CONNECTION).
1853 */
1854
1855 switch (wValue) {
1856 case USB_PORT_FEAT_ENABLE:
1857 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1858 break;
1859 case USB_PORT_FEAT_C_ENABLE:
1860 /* XXX error? */
1861 break;
1862 case USB_PORT_FEAT_SUSPEND:
1863 if (temp & PORT_RESET)
1864 goto error;
1865
1866 if (temp & PORT_SUSPEND) {
1867 if ((temp & PORT_PE) == 0)
1868 goto error;
1869 /* resume signaling for 20 msec */
1870 temp &= ~(PORT_RWC_BITS);
1871 reg_write32(hcd->regs, HC_PORTSC1,
1872 temp | PORT_RESUME);
1873 priv->reset_done = jiffies +
1874 msecs_to_jiffies(20);
1875 }
1876 break;
1877 case USB_PORT_FEAT_C_SUSPEND:
1878 /* we auto-clear this feature */
1879 break;
1880 case USB_PORT_FEAT_POWER:
1881 if (HCS_PPC(priv->hcs_params))
1882 reg_write32(hcd->regs, HC_PORTSC1,
1883 temp & ~PORT_POWER);
1884 break;
1885 case USB_PORT_FEAT_C_CONNECTION:
1886 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1887 break;
1888 case USB_PORT_FEAT_C_OVER_CURRENT:
1889 /* XXX error ?*/
1890 break;
1891 case USB_PORT_FEAT_C_RESET:
1892 /* GetPortStatus clears reset */
1893 break;
1894 default:
1895 goto error;
1896 }
1897 reg_read32(hcd->regs, HC_USBCMD);
1898 break;
1899 case GetHubDescriptor:
1900 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1901 buf);
1902 break;
1903 case GetHubStatus:
1904 /* no hub-wide feature/status flags */
1905 memset(buf, 0, 4);
1906 break;
1907 case GetPortStatus:
1908 if (!wIndex || wIndex > ports)
1909 goto error;
1910 wIndex--;
1911 status = 0;
1912 temp = reg_read32(hcd->regs, HC_PORTSC1);
1913
1914 /* wPortChange bits */
1915 if (temp & PORT_CSC)
1916 status |= USB_PORT_STAT_C_CONNECTION << 16;
1917
1918
1919 /* whoever resumes must GetPortStatus to complete it!! */
1920 if (temp & PORT_RESUME) {
1921 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1922
1923 /* Remote Wakeup received? */
1924 if (!priv->reset_done) {
1925 /* resume signaling for 20 msec */
1926 priv->reset_done = jiffies
1927 + msecs_to_jiffies(20);
1928 /* check the port again */
1929 mod_timer(&hcd->rh_timer, priv->reset_done);
1930 }
1931
1932 /* resume completed? */
1933 else if (time_after_eq(jiffies,
1934 priv->reset_done)) {
1935 status |= USB_PORT_STAT_C_SUSPEND << 16;
1936 priv->reset_done = 0;
1937
1938 /* stop resume signaling */
1939 temp = reg_read32(hcd->regs, HC_PORTSC1);
1940 reg_write32(hcd->regs, HC_PORTSC1,
1941 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1942 retval = handshake(hcd, HC_PORTSC1,
1943 PORT_RESUME, 0, 2000 /* 2msec */);
1944 if (retval != 0) {
1945 dev_err(hcd->self.controller,
1946 "port %d resume error %d\n",
1947 wIndex + 1, retval);
1948 goto error;
1949 }
1950 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1951 }
1952 }
1953
1954 /* whoever resets must GetPortStatus to complete it!! */
1955 if ((temp & PORT_RESET)
1956 && time_after_eq(jiffies,
1957 priv->reset_done)) {
1958 status |= USB_PORT_STAT_C_RESET << 16;
1959 priv->reset_done = 0;
1960
1961 /* force reset to complete */
1962 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1963 /* REVISIT: some hardware needs 550+ usec to clear
1964 * this bit; seems too long to spin routinely...
1965 */
1966 retval = handshake(hcd, HC_PORTSC1,
1967 PORT_RESET, 0, 750);
1968 if (retval != 0) {
1969 dev_err(hcd->self.controller, "port %d reset error %d\n",
1970 wIndex + 1, retval);
1971 goto error;
1972 }
1973
1974 /* see what we found out */
1975 temp = check_reset_complete(hcd, wIndex,
1976 reg_read32(hcd->regs, HC_PORTSC1));
1977 }
1978 /*
1979 * Even if OWNER is set, there's no harm letting hub_wq
1980 * see the wPortStatus values (they should all be 0 except
1981 * for PORT_POWER anyway).
1982 */
1983
1984 if (temp & PORT_OWNER)
1985 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1986
1987 if (temp & PORT_CONNECT) {
1988 status |= USB_PORT_STAT_CONNECTION;
1989 /* status may be from integrated TT */
1990 status |= USB_PORT_STAT_HIGH_SPEED;
1991 }
1992 if (temp & PORT_PE)
1993 status |= USB_PORT_STAT_ENABLE;
1994 if (temp & (PORT_SUSPEND|PORT_RESUME))
1995 status |= USB_PORT_STAT_SUSPEND;
1996 if (temp & PORT_RESET)
1997 status |= USB_PORT_STAT_RESET;
1998 if (temp & PORT_POWER)
1999 status |= USB_PORT_STAT_POWER;
2000
2001 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2002 break;
2003 case SetHubFeature:
2004 switch (wValue) {
2005 case C_HUB_LOCAL_POWER:
2006 case C_HUB_OVER_CURRENT:
2007 /* no hub-wide feature/status flags */
2008 break;
2009 default:
2010 goto error;
2011 }
2012 break;
2013 case SetPortFeature:
2014 selector = wIndex >> 8;
2015 wIndex &= 0xff;
2016 if (!wIndex || wIndex > ports)
2017 goto error;
2018 wIndex--;
2019 temp = reg_read32(hcd->regs, HC_PORTSC1);
2020 if (temp & PORT_OWNER)
2021 break;
2022
2023/* temp &= ~PORT_RWC_BITS; */
2024 switch (wValue) {
2025 case USB_PORT_FEAT_ENABLE:
2026 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2027 break;
2028
2029 case USB_PORT_FEAT_SUSPEND:
2030 if ((temp & PORT_PE) == 0
2031 || (temp & PORT_RESET) != 0)
2032 goto error;
2033
2034 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2035 break;
2036 case USB_PORT_FEAT_POWER:
2037 if (HCS_PPC(priv->hcs_params))
2038 reg_write32(hcd->regs, HC_PORTSC1,
2039 temp | PORT_POWER);
2040 break;
2041 case USB_PORT_FEAT_RESET:
2042 if (temp & PORT_RESUME)
2043 goto error;
2044 /* line status bits may report this as low speed,
2045 * which can be fine if this root hub has a
2046 * transaction translator built in.
2047 */
2048 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2049 && PORT_USB11(temp)) {
2050 temp |= PORT_OWNER;
2051 } else {
2052 temp |= PORT_RESET;
2053 temp &= ~PORT_PE;
2054
2055 /*
2056 * caller must wait, then call GetPortStatus
2057 * usb 2.0 spec says 50 ms resets on root
2058 */
2059 priv->reset_done = jiffies +
2060 msecs_to_jiffies(50);
2061 }
2062 reg_write32(hcd->regs, HC_PORTSC1, temp);
2063 break;
2064 default:
2065 goto error;
2066 }
2067 reg_read32(hcd->regs, HC_USBCMD);
2068 break;
2069
2070 default:
2071error:
2072 /* "stall" on error */
2073 retval = -EPIPE;
2074 }
2075 spin_unlock_irqrestore(&priv->lock, flags);
2076 return retval;
2077}
2078
2079static int isp1760_get_frame(struct usb_hcd *hcd)
2080{
2081 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2082 u32 fr;
2083
2084 fr = reg_read32(hcd->regs, HC_FRINDEX);
2085 return (fr >> 3) % priv->periodic_size;
2086}
2087
2088static void isp1760_stop(struct usb_hcd *hcd)
2089{
2090 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2091 u32 temp;
2092
2093 del_timer(&errata2_timer);
2094
2095 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2096 NULL, 0);
2097 mdelay(20);
2098
2099 spin_lock_irq(&priv->lock);
2100 ehci_reset(hcd);
2101 /* Disable IRQ */
2102 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2103 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2104 spin_unlock_irq(&priv->lock);
2105
2106 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2107}
2108
2109static void isp1760_shutdown(struct usb_hcd *hcd)
2110{
2111 u32 command, temp;
2112
2113 isp1760_stop(hcd);
2114 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2115 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2116
2117 command = reg_read32(hcd->regs, HC_USBCMD);
2118 command &= ~CMD_RUN;
2119 reg_write32(hcd->regs, HC_USBCMD, command);
2120}
2121
2122static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2123 struct usb_host_endpoint *ep)
2124{
2125 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2126 struct isp1760_qh *qh = ep->hcpriv;
2127 unsigned long spinflags;
2128
2129 if (!qh)
2130 return;
2131
2132 spin_lock_irqsave(&priv->lock, spinflags);
2133 qh->tt_buffer_dirty = 0;
2134 schedule_ptds(hcd);
2135 spin_unlock_irqrestore(&priv->lock, spinflags);
2136}
2137
2138
2139static const struct hc_driver isp1760_hc_driver = {
2140 .description = "isp1760-hcd",
2141 .product_desc = "NXP ISP1760 USB Host Controller",
2142 .hcd_priv_size = sizeof(struct isp1760_hcd *),
2143 .irq = isp1760_irq,
2144 .flags = HCD_MEMORY | HCD_USB2,
2145 .reset = isp1760_hc_setup,
2146 .start = isp1760_run,
2147 .stop = isp1760_stop,
2148 .shutdown = isp1760_shutdown,
2149 .urb_enqueue = isp1760_urb_enqueue,
2150 .urb_dequeue = isp1760_urb_dequeue,
2151 .endpoint_disable = isp1760_endpoint_disable,
2152 .get_frame_number = isp1760_get_frame,
2153 .hub_status_data = isp1760_hub_status_data,
2154 .hub_control = isp1760_hub_control,
2155 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
2156};
2157
2158int __init isp1760_init_kmem_once(void)
2159{
2160 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2161 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2162 SLAB_MEM_SPREAD, NULL);
2163
2164 if (!urb_listitem_cachep)
2165 return -ENOMEM;
2166
2167 qtd_cachep = kmem_cache_create("isp1760_qtd",
2168 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2169 SLAB_MEM_SPREAD, NULL);
2170
2171 if (!qtd_cachep)
2172 return -ENOMEM;
2173
2174 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2175 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2176
2177 if (!qh_cachep) {
2178 kmem_cache_destroy(qtd_cachep);
2179 return -ENOMEM;
2180 }
2181
2182 return 0;
2183}
2184
2185void isp1760_deinit_kmem_cache(void)
2186{
2187 kmem_cache_destroy(qtd_cachep);
2188 kmem_cache_destroy(qh_cachep);
2189 kmem_cache_destroy(urb_listitem_cachep);
2190}
2191
2192int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs,
2193 struct resource *mem, int irq, unsigned long irqflags,
2194 struct device *dev)
2195{
2196 struct usb_hcd *hcd;
2197 int ret;
2198
2199 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2200 if (!hcd)
2201 return -ENOMEM;
2202
2203 *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2204
2205 priv->hcd = hcd;
2206
2207 init_memory(priv);
2208
2209 hcd->irq = irq;
2210 hcd->regs = regs;
2211 hcd->rsrc_start = mem->start;
2212 hcd->rsrc_len = resource_size(mem);
2213
2214 ret = usb_add_hcd(hcd, irq, irqflags);
2215 if (ret)
2216 goto error;
2217
2218 device_wakeup_enable(hcd->self.controller);
2219
2220 return 0;
2221
2222error:
2223 usb_put_hcd(hcd);
2224 return ret;
2225}
2226
2227void isp1760_hcd_unregister(struct isp1760_hcd *priv)
2228{
2229 usb_remove_hcd(priv->hcd);
2230 usb_put_hcd(priv->hcd);
2231}
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h
deleted file mode 100644
index df7ea3684b77..000000000000
--- a/drivers/usb/host/isp1760-hcd.h
+++ /dev/null
@@ -1,77 +0,0 @@
1#ifndef _ISP1760_HCD_H_
2#define _ISP1760_HCD_H_
3
4#include <linux/spinlock.h>
5
6struct isp1760_qh;
7struct isp1760_qtd;
8struct resource;
9struct usb_hcd;
10
11/*
12 * 60kb divided in:
13 * - 32 blocks @ 256 bytes
14 * - 20 blocks @ 1024 bytes
15 * - 4 blocks @ 8192 bytes
16 */
17
18#define BLOCK_1_NUM 32
19#define BLOCK_2_NUM 20
20#define BLOCK_3_NUM 4
21
22#define BLOCK_1_SIZE 256
23#define BLOCK_2_SIZE 1024
24#define BLOCK_3_SIZE 8192
25#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
26#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
27#define PAYLOAD_AREA_SIZE 0xf000
28
29struct isp1760_slotinfo {
30 struct isp1760_qh *qh;
31 struct isp1760_qtd *qtd;
32 unsigned long timestamp;
33};
34
35/* chip memory management */
36struct isp1760_memory_chunk {
37 unsigned int start;
38 unsigned int size;
39 unsigned int free;
40};
41
42enum isp1760_queue_head_types {
43 QH_CONTROL,
44 QH_BULK,
45 QH_INTERRUPT,
46 QH_END
47};
48
49struct isp1760_hcd {
50 struct usb_hcd *hcd;
51
52 u32 hcs_params;
53 spinlock_t lock;
54 struct isp1760_slotinfo atl_slots[32];
55 int atl_done_map;
56 struct isp1760_slotinfo int_slots[32];
57 int int_done_map;
58 struct isp1760_memory_chunk memory_pool[BLOCKS];
59 struct list_head qh_list[QH_END];
60
61 /* periodic schedule support */
62#define DEFAULT_I_TDPS 1024
63 unsigned periodic_size;
64 unsigned i_thresh;
65 unsigned long reset_done;
66 unsigned long next_statechange;
67};
68
69int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs,
70 struct resource *mem, int irq, unsigned long irqflags,
71 struct device *dev);
72void isp1760_hcd_unregister(struct isp1760_hcd *priv);
73
74int isp1760_init_kmem_once(void);
75void isp1760_deinit_kmem_cache(void);
76
77#endif /* _ISP1760_HCD_H_ */
diff --git a/drivers/usb/host/isp1760-if.c b/drivers/usb/host/isp1760-if.c
deleted file mode 100644
index c2a94c966350..000000000000
--- a/drivers/usb/host/isp1760-if.c
+++ /dev/null
@@ -1,312 +0,0 @@
1/*
2 * Glue code for the ISP1760 driver and bus
3 * Currently there is support for
4 * - OpenFirmware
5 * - PCI
6 * - PDEV (generic platform device centralized driver model)
7 *
8 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
9 *
10 */
11
12#include <linux/usb.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18#include <linux/usb/isp1760.h>
19#include <linux/usb/hcd.h>
20
21#include "isp1760-core.h"
22#include "isp1760-regs.h"
23
24#ifdef CONFIG_PCI
25#include <linux/pci.h>
26#endif
27
28#ifdef CONFIG_PCI
29static int isp1761_pci_init(struct pci_dev *dev)
30{
31 resource_size_t mem_start;
32 resource_size_t mem_length;
33 u8 __iomem *iobase;
34 u8 latency, limit;
35 int retry_count;
36 u32 reg_data;
37
38 /* Grab the PLX PCI shared memory of the ISP 1761 we need */
39 mem_start = pci_resource_start(dev, 3);
40 mem_length = pci_resource_len(dev, 3);
41 if (mem_length < 0xffff) {
42 printk(KERN_ERR "memory length for this resource is wrong\n");
43 return -ENOMEM;
44 }
45
46 if (!request_mem_region(mem_start, mem_length, "ISP-PCI")) {
47 printk(KERN_ERR "host controller already in use\n");
48 return -EBUSY;
49 }
50
51 /* map available memory */
52 iobase = ioremap_nocache(mem_start, mem_length);
53 if (!iobase) {
54 printk(KERN_ERR "Error ioremap failed\n");
55 release_mem_region(mem_start, mem_length);
56 return -ENOMEM;
57 }
58
59 /* bad pci latencies can contribute to overruns */
60 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &latency);
61 if (latency) {
62 pci_read_config_byte(dev, PCI_MAX_LAT, &limit);
63 if (limit && limit < latency)
64 pci_write_config_byte(dev, PCI_LATENCY_TIMER, limit);
65 }
66
67 /* Try to check whether we can access Scratch Register of
68 * Host Controller or not. The initial PCI access is retried until
69 * local init for the PCI bridge is completed
70 */
71 retry_count = 20;
72 reg_data = 0;
73 while ((reg_data != 0xFACE) && retry_count) {
74 /*by default host is in 16bit mode, so
75 * io operations at this stage must be 16 bit
76 * */
77 writel(0xface, iobase + HC_SCRATCH_REG);
78 udelay(100);
79 reg_data = readl(iobase + HC_SCRATCH_REG) & 0x0000ffff;
80 retry_count--;
81 }
82
83 iounmap(iobase);
84 release_mem_region(mem_start, mem_length);
85
86 /* Host Controller presence is detected by writing to scratch register
87 * and reading back and checking the contents are same or not
88 */
89 if (reg_data != 0xFACE) {
90 dev_err(&dev->dev, "scratch register mismatch %x\n", reg_data);
91 return -ENOMEM;
92 }
93
94 /* Grab the PLX PCI mem maped port start address we need */
95 mem_start = pci_resource_start(dev, 0);
96 mem_length = pci_resource_len(dev, 0);
97
98 if (!request_mem_region(mem_start, mem_length, "ISP1761 IO MEM")) {
99 printk(KERN_ERR "request region #1\n");
100 return -EBUSY;
101 }
102
103 iobase = ioremap_nocache(mem_start, mem_length);
104 if (!iobase) {
105 printk(KERN_ERR "ioremap #1\n");
106 release_mem_region(mem_start, mem_length);
107 return -ENOMEM;
108 }
109
110 /* configure PLX PCI chip to pass interrupts */
111#define PLX_INT_CSR_REG 0x68
112 reg_data = readl(iobase + PLX_INT_CSR_REG);
113 reg_data |= 0x900;
114 writel(reg_data, iobase + PLX_INT_CSR_REG);
115
116 /* done with PLX IO access */
117 iounmap(iobase);
118 release_mem_region(mem_start, mem_length);
119
120 return 0;
121}
122
123static int isp1761_pci_probe(struct pci_dev *dev,
124 const struct pci_device_id *id)
125{
126 unsigned int devflags = 0;
127 int ret;
128
129 if (usb_disabled())
130 return -ENODEV;
131
132 if (!dev->irq)
133 return -ENODEV;
134
135 if (pci_enable_device(dev) < 0)
136 return -ENODEV;
137
138 ret = isp1761_pci_init(dev);
139 if (ret < 0)
140 goto error;
141
142 pci_set_master(dev);
143
144 dev->dev.dma_mask = NULL;
145 ret = isp1760_register(&dev->resource[3], dev->irq, 0, &dev->dev,
146 devflags);
147 if (ret < 0)
148 goto error;
149
150 return 0;
151
152error:
153 pci_disable_device(dev);
154 return ret;
155}
156
157static void isp1761_pci_remove(struct pci_dev *dev)
158{
159 isp1760_unregister(&dev->dev);
160
161 pci_disable_device(dev);
162}
163
164static void isp1761_pci_shutdown(struct pci_dev *dev)
165{
166 printk(KERN_ERR "ips1761_pci_shutdown\n");
167}
168
169static const struct pci_device_id isp1760_plx [] = {
170 {
171 .class = PCI_CLASS_BRIDGE_OTHER << 8,
172 .class_mask = ~0,
173 .vendor = PCI_VENDOR_ID_PLX,
174 .device = 0x5406,
175 .subvendor = PCI_VENDOR_ID_PLX,
176 .subdevice = 0x9054,
177 },
178 { }
179};
180MODULE_DEVICE_TABLE(pci, isp1760_plx);
181
182static struct pci_driver isp1761_pci_driver = {
183 .name = "isp1760",
184 .id_table = isp1760_plx,
185 .probe = isp1761_pci_probe,
186 .remove = isp1761_pci_remove,
187 .shutdown = isp1761_pci_shutdown,
188};
189#endif
190
191static int isp1760_plat_probe(struct platform_device *pdev)
192{
193 unsigned long irqflags;
194 unsigned int devflags = 0;
195 struct resource *mem_res;
196 struct resource *irq_res;
197 int ret;
198
199 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
200
201 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
202 if (!irq_res) {
203 pr_warning("isp1760: IRQ resource not available\n");
204 return -ENODEV;
205 }
206 irqflags = irq_res->flags & IRQF_TRIGGER_MASK;
207
208 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
209 struct device_node *dp = pdev->dev.of_node;
210 u32 bus_width = 0;
211
212 if (of_device_is_compatible(dp, "nxp,usb-isp1761"))
213 devflags |= ISP1760_FLAG_ISP1761;
214
215 /* Some systems wire up only 16 of the 32 data lines */
216 of_property_read_u32(dp, "bus-width", &bus_width);
217 if (bus_width == 16)
218 devflags |= ISP1760_FLAG_BUS_WIDTH_16;
219
220 if (of_property_read_bool(dp, "port1-otg"))
221 devflags |= ISP1760_FLAG_OTG_EN;
222
223 if (of_property_read_bool(dp, "analog-oc"))
224 devflags |= ISP1760_FLAG_ANALOG_OC;
225
226 if (of_property_read_bool(dp, "dack-polarity"))
227 devflags |= ISP1760_FLAG_DACK_POL_HIGH;
228
229 if (of_property_read_bool(dp, "dreq-polarity"))
230 devflags |= ISP1760_FLAG_DREQ_POL_HIGH;
231 } else if (dev_get_platdata(&pdev->dev)) {
232 struct isp1760_platform_data *pdata =
233 dev_get_platdata(&pdev->dev);
234
235 if (pdata->is_isp1761)
236 devflags |= ISP1760_FLAG_ISP1761;
237 if (pdata->bus_width_16)
238 devflags |= ISP1760_FLAG_BUS_WIDTH_16;
239 if (pdata->port1_otg)
240 devflags |= ISP1760_FLAG_OTG_EN;
241 if (pdata->analog_oc)
242 devflags |= ISP1760_FLAG_ANALOG_OC;
243 if (pdata->dack_polarity_high)
244 devflags |= ISP1760_FLAG_DACK_POL_HIGH;
245 if (pdata->dreq_polarity_high)
246 devflags |= ISP1760_FLAG_DREQ_POL_HIGH;
247 }
248
249 ret = isp1760_register(mem_res, irq_res->start, irqflags, &pdev->dev,
250 devflags);
251 if (ret < 0)
252 return ret;
253
254 pr_info("ISP1760 USB device initialised\n");
255 return 0;
256}
257
258static int isp1760_plat_remove(struct platform_device *pdev)
259{
260 isp1760_unregister(&pdev->dev);
261
262 return 0;
263}
264
265#ifdef CONFIG_OF
266static const struct of_device_id isp1760_of_match[] = {
267 { .compatible = "nxp,usb-isp1760", },
268 { .compatible = "nxp,usb-isp1761", },
269 { },
270};
271MODULE_DEVICE_TABLE(of, isp1760_of_match);
272#endif
273
274static struct platform_driver isp1760_plat_driver = {
275 .probe = isp1760_plat_probe,
276 .remove = isp1760_plat_remove,
277 .driver = {
278 .name = "isp1760",
279 .of_match_table = of_match_ptr(isp1760_of_match),
280 },
281};
282
283static int __init isp1760_init(void)
284{
285 int ret, any_ret = -ENODEV;
286
287 isp1760_init_kmem_once();
288
289 ret = platform_driver_register(&isp1760_plat_driver);
290 if (!ret)
291 any_ret = 0;
292#ifdef CONFIG_PCI
293 ret = pci_register_driver(&isp1761_pci_driver);
294 if (!ret)
295 any_ret = 0;
296#endif
297
298 if (any_ret)
299 isp1760_deinit_kmem_cache();
300 return any_ret;
301}
302module_init(isp1760_init);
303
304static void __exit isp1760_exit(void)
305{
306 platform_driver_unregister(&isp1760_plat_driver);
307#ifdef CONFIG_PCI
308 pci_unregister_driver(&isp1761_pci_driver);
309#endif
310 isp1760_deinit_kmem_cache();
311}
312module_exit(isp1760_exit);
diff --git a/drivers/usb/host/isp1760-regs.h b/drivers/usb/host/isp1760-regs.h
deleted file mode 100644
index b67095c9a9d4..000000000000
--- a/drivers/usb/host/isp1760-regs.h
+++ /dev/null
@@ -1,230 +0,0 @@
1/*
2 * Driver for the NXP ISP1760 chip
3 *
4 * Copyright 2014 Laurent Pinchart
5 * Copyright 2007 Sebastian Siewior
6 *
7 * Contacts:
8 * Sebastian Siewior <bigeasy@linutronix.de>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 */
15
16#ifndef _ISP1760_REGS_H_
17#define _ISP1760_REGS_H_
18
19/* -----------------------------------------------------------------------------
20 * Host Controller
21 */
22
23/* EHCI capability registers */
24#define HC_CAPLENGTH 0x000
25#define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */
26#define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */
27
28#define HC_HCSPARAMS 0x004
29#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */
30#define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */
31#define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
32
33#define HC_HCCPARAMS 0x008
34#define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */
35#define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
36
37/* EHCI operational registers */
38#define HC_USBCMD 0x020
39#define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */
40#define CMD_RESET (1 << 1) /* reset HC not bus */
41#define CMD_RUN (1 << 0) /* start/stop HC */
42
43#define HC_USBSTS 0x024
44#define STS_PCD (1 << 2) /* port change detect */
45
46#define HC_FRINDEX 0x02c
47
48#define HC_CONFIGFLAG 0x060
49#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
50
51#define HC_PORTSC1 0x064
52#define PORT_OWNER (1 << 13) /* true: companion hc owns this port */
53#define PORT_POWER (1 << 12) /* true: has power (see PPC) */
54#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
55#define PORT_RESET (1 << 8) /* reset port */
56#define PORT_SUSPEND (1 << 7) /* suspend port */
57#define PORT_RESUME (1 << 6) /* resume it */
58#define PORT_PE (1 << 2) /* port enable */
59#define PORT_CSC (1 << 1) /* connect status change */
60#define PORT_CONNECT (1 << 0) /* device connected */
61#define PORT_RWC_BITS (PORT_CSC)
62
63#define HC_ISO_PTD_DONEMAP_REG 0x130
64#define HC_ISO_PTD_SKIPMAP_REG 0x134
65#define HC_ISO_PTD_LASTPTD_REG 0x138
66#define HC_INT_PTD_DONEMAP_REG 0x140
67#define HC_INT_PTD_SKIPMAP_REG 0x144
68#define HC_INT_PTD_LASTPTD_REG 0x148
69#define HC_ATL_PTD_DONEMAP_REG 0x150
70#define HC_ATL_PTD_SKIPMAP_REG 0x154
71#define HC_ATL_PTD_LASTPTD_REG 0x158
72
73/* Configuration Register */
74#define HC_HW_MODE_CTRL 0x300
75#define ALL_ATX_RESET (1 << 31)
76#define HW_ANA_DIGI_OC (1 << 15)
77#define HW_DEV_DMA (1 << 11)
78#define HW_COMN_IRQ (1 << 10)
79#define HW_COMN_DMA (1 << 9)
80#define HW_DATA_BUS_32BIT (1 << 8)
81#define HW_DACK_POL_HIGH (1 << 6)
82#define HW_DREQ_POL_HIGH (1 << 5)
83#define HW_INTR_HIGH_ACT (1 << 2)
84#define HW_INTR_EDGE_TRIG (1 << 1)
85#define HW_GLOBAL_INTR_EN (1 << 0)
86
87#define HC_CHIP_ID_REG 0x304
88#define HC_SCRATCH_REG 0x308
89
90#define HC_RESET_REG 0x30c
91#define SW_RESET_RESET_HC (1 << 1)
92#define SW_RESET_RESET_ALL (1 << 0)
93
94#define HC_BUFFER_STATUS_REG 0x334
95#define ISO_BUF_FILL (1 << 2)
96#define INT_BUF_FILL (1 << 1)
97#define ATL_BUF_FILL (1 << 0)
98
99#define HC_MEMORY_REG 0x33c
100#define ISP_BANK(x) ((x) << 16)
101
102#define HC_PORT1_CTRL 0x374
103#define PORT1_POWER (3 << 3)
104#define PORT1_INIT1 (1 << 7)
105#define PORT1_INIT2 (1 << 23)
106#define HW_OTG_CTRL_SET 0x374
107#define HW_OTG_CTRL_CLR 0x376
108#define HW_OTG_DISABLE (1 << 10)
109#define HW_OTG_SE0_EN (1 << 9)
110#define HW_BDIS_ACON_EN (1 << 8)
111#define HW_SW_SEL_HC_DC (1 << 7)
112#define HW_VBUS_CHRG (1 << 6)
113#define HW_VBUS_DISCHRG (1 << 5)
114#define HW_VBUS_DRV (1 << 4)
115#define HW_SEL_CP_EXT (1 << 3)
116#define HW_DM_PULLDOWN (1 << 2)
117#define HW_DP_PULLDOWN (1 << 1)
118#define HW_DP_PULLUP (1 << 0)
119
120/* Interrupt Register */
121#define HC_INTERRUPT_REG 0x310
122
123#define HC_INTERRUPT_ENABLE 0x314
124#define HC_ISO_INT (1 << 9)
125#define HC_ATL_INT (1 << 8)
126#define HC_INTL_INT (1 << 7)
127#define HC_EOT_INT (1 << 3)
128#define HC_SOT_INT (1 << 1)
129#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
130
131#define HC_ISO_IRQ_MASK_OR_REG 0x318
132#define HC_INT_IRQ_MASK_OR_REG 0x31c
133#define HC_ATL_IRQ_MASK_OR_REG 0x320
134#define HC_ISO_IRQ_MASK_AND_REG 0x324
135#define HC_INT_IRQ_MASK_AND_REG 0x328
136#define HC_ATL_IRQ_MASK_AND_REG 0x32c
137
138/* -----------------------------------------------------------------------------
139 * Peripheral Controller
140 */
141
142/* Initialization Registers */
143#define DC_ADDRESS 0x0200
144#define DC_DEVEN (1 << 7)
145
146#define DC_MODE 0x020c
147#define DC_DMACLKON (1 << 9)
148#define DC_VBUSSTAT (1 << 8)
149#define DC_CLKAON (1 << 7)
150#define DC_SNDRSU (1 << 6)
151#define DC_GOSUSP (1 << 5)
152#define DC_SFRESET (1 << 4)
153#define DC_GLINTENA (1 << 3)
154#define DC_WKUPCS (1 << 2)
155
156#define DC_INTCONF 0x0210
157#define DC_CDBGMOD_ACK_NAK (0 << 6)
158#define DC_CDBGMOD_ACK (1 << 6)
159#define DC_CDBGMOD_ACK_1NAK (2 << 6)
160#define DC_DDBGMODIN_ACK_NAK (0 << 4)
161#define DC_DDBGMODIN_ACK (1 << 4)
162#define DC_DDBGMODIN_ACK_1NAK (2 << 4)
163#define DC_DDBGMODOUT_ACK_NYET_NAK (0 << 2)
164#define DC_DDBGMODOUT_ACK_NYET (1 << 2)
165#define DC_DDBGMODOUT_ACK_NYET_1NAK (2 << 2)
166#define DC_INTLVL (1 << 1)
167#define DC_INTPOL (1 << 0)
168
169#define DC_DEBUG 0x0212
170#define DC_INTENABLE 0x0214
171#define DC_IEPTX(n) (1 << (11 + 2 * (n)))
172#define DC_IEPRX(n) (1 << (10 + 2 * (n)))
173#define DC_IEPRXTX(n) (3 << (10 + 2 * (n)))
174#define DC_IEP0SETUP (1 << 8)
175#define DC_IEVBUS (1 << 7)
176#define DC_IEDMA (1 << 6)
177#define DC_IEHS_STA (1 << 5)
178#define DC_IERESM (1 << 4)
179#define DC_IESUSP (1 << 3)
180#define DC_IEPSOF (1 << 2)
181#define DC_IESOF (1 << 1)
182#define DC_IEBRST (1 << 0)
183
184/* Data Flow Registers */
185#define DC_EPINDEX 0x022c
186#define DC_EP0SETUP (1 << 5)
187#define DC_ENDPIDX(n) ((n) << 1)
188#define DC_EPDIR (1 << 0)
189
190#define DC_CTRLFUNC 0x0228
191#define DC_CLBUF (1 << 4)
192#define DC_VENDP (1 << 3)
193#define DC_DSEN (1 << 2)
194#define DC_STATUS (1 << 1)
195#define DC_STALL (1 << 0)
196
197#define DC_DATAPORT 0x0220
198#define DC_BUFLEN 0x021c
199#define DC_DATACOUNT_MASK 0xffff
200#define DC_BUFSTAT 0x021e
201#define DC_EPMAXPKTSZ 0x0204
202
203#define DC_EPTYPE 0x0208
204#define DC_NOEMPKT (1 << 4)
205#define DC_EPENABLE (1 << 3)
206#define DC_DBLBUF (1 << 2)
207#define DC_ENDPTYP_ISOC (1 << 0)
208#define DC_ENDPTYP_BULK (2 << 0)
209#define DC_ENDPTYP_INTERRUPT (3 << 0)
210
211/* DMA Registers */
212#define DC_DMACMD 0x0230
213#define DC_DMATXCOUNT 0x0234
214#define DC_DMACONF 0x0238
215#define DC_DMAHW 0x023c
216#define DC_DMAINTREASON 0x0250
217#define DC_DMAINTEN 0x0254
218#define DC_DMAEP 0x0258
219#define DC_DMABURSTCOUNT 0x0264
220
221/* General Registers */
222#define DC_INTERRUPT 0x0218
223#define DC_CHIPID 0x0270
224#define DC_FRAMENUM 0x0274
225#define DC_SCRATCH 0x0278
226#define DC_UNLOCKDEV 0x027c
227#define DC_INTPULSEWIDTH 0x0280
228#define DC_TESTMODE 0x0284
229
230#endif
diff --git a/drivers/usb/host/isp1760-udc.c b/drivers/usb/host/isp1760-udc.c
deleted file mode 100644
index 6bfda3082807..000000000000
--- a/drivers/usb/host/isp1760-udc.c
+++ /dev/null
@@ -1,1495 +0,0 @@
1/*
2 * Driver for the NXP ISP1761 device controller
3 *
4 * Copyright 2014 Ideas on Board Oy
5 *
6 * Contacts:
7 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 */
13
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/list.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/timer.h>
21#include <linux/usb.h>
22
23#include "isp1760-core.h"
24#include "isp1760-regs.h"
25#include "isp1760-udc.h"
26
27#define ISP1760_VBUS_POLL_INTERVAL msecs_to_jiffies(500)
28
29struct isp1760_request {
30 struct usb_request req;
31 struct list_head queue;
32 struct isp1760_ep *ep;
33 unsigned int packet_size;
34};
35
36static inline struct isp1760_udc *gadget_to_udc(struct usb_gadget *gadget)
37{
38 return container_of(gadget, struct isp1760_udc, gadget);
39}
40
41static inline struct isp1760_ep *ep_to_udc_ep(struct usb_ep *ep)
42{
43 return container_of(ep, struct isp1760_ep, ep);
44}
45
46static inline struct isp1760_request *req_to_udc_req(struct usb_request *req)
47{
48 return container_of(req, struct isp1760_request, req);
49}
50
51static inline u32 isp1760_udc_read(struct isp1760_udc *udc, u16 reg)
52{
53 return isp1760_read32(udc->regs, reg);
54}
55
56static inline void isp1760_udc_write(struct isp1760_udc *udc, u16 reg, u32 val)
57{
58 isp1760_write32(udc->regs, reg, val);
59}
60
61/* -----------------------------------------------------------------------------
62 * Endpoint Management
63 */
64
65static struct isp1760_ep *isp1760_udc_find_ep(struct isp1760_udc *udc,
66 u16 index)
67{
68 unsigned int i;
69
70 if (index == 0)
71 return &udc->ep[0];
72
73 for (i = 1; i < ARRAY_SIZE(udc->ep); ++i) {
74 if (udc->ep[i].addr == index)
75 return udc->ep[i].desc ? &udc->ep[i] : NULL;
76 }
77
78 return NULL;
79}
80
81static void __isp1760_udc_select_ep(struct isp1760_ep *ep, int dir)
82{
83 isp1760_udc_write(ep->udc, DC_EPINDEX,
84 DC_ENDPIDX(ep->addr & USB_ENDPOINT_NUMBER_MASK) |
85 (dir == USB_DIR_IN ? DC_EPDIR : 0));
86}
87
88/**
89 * isp1760_udc_select_ep - Select an endpoint for register access
90 * @ep: The endpoint
91 *
92 * The ISP1761 endpoint registers are banked. This function selects the target
93 * endpoint for banked register access. The selection remains valid until the
94 * next call to this function, the next direct access to the EPINDEX register
95 * or the next reset, whichever comes first.
96 *
97 * Called with the UDC spinlock held.
98 */
99static void isp1760_udc_select_ep(struct isp1760_ep *ep)
100{
101 __isp1760_udc_select_ep(ep, ep->addr & USB_ENDPOINT_DIR_MASK);
102}
103
104/* Called with the UDC spinlock held. */
105static void isp1760_udc_ctrl_send_status(struct isp1760_ep *ep, int dir)
106{
107 struct isp1760_udc *udc = ep->udc;
108
109 /*
110 * Proceed to the status stage. The status stage data packet flows in
111 * the direction opposite to the data stage data packets, we thus need
112 * to select the OUT/IN endpoint for IN/OUT transfers.
113 */
114 isp1760_udc_write(udc, DC_EPINDEX, DC_ENDPIDX(0) |
115 (dir == USB_DIR_IN ? 0 : DC_EPDIR));
116 isp1760_udc_write(udc, DC_CTRLFUNC, DC_STATUS);
117
118 /*
119 * The hardware will terminate the request automatically and go back to
120 * the setup stage without notifying us.
121 */
122 udc->ep0_state = ISP1760_CTRL_SETUP;
123}
124
125/* Called without the UDC spinlock held. */
126static void isp1760_udc_request_complete(struct isp1760_ep *ep,
127 struct isp1760_request *req,
128 int status)
129{
130 struct isp1760_udc *udc = ep->udc;
131 unsigned long flags;
132
133 dev_dbg(ep->udc->isp->dev, "completing request %p with status %d\n",
134 req, status);
135
136 req->ep = NULL;
137 req->req.status = status;
138 req->req.complete(&ep->ep, &req->req);
139
140 spin_lock_irqsave(&udc->lock, flags);
141
142 /*
143 * When completing control OUT requests, move to the status stage after
144 * calling the request complete callback. This gives the gadget an
145 * opportunity to stall the control transfer if needed.
146 */
147 if (status == 0 && ep->addr == 0 && udc->ep0_dir == USB_DIR_OUT)
148 isp1760_udc_ctrl_send_status(ep, USB_DIR_OUT);
149
150 spin_unlock_irqrestore(&udc->lock, flags);
151}
152
153static void isp1760_udc_ctrl_send_stall(struct isp1760_ep *ep)
154{
155 struct isp1760_udc *udc = ep->udc;
156 unsigned long flags;
157
158 dev_dbg(ep->udc->isp->dev, "%s(ep%02x)\n", __func__, ep->addr);
159
160 spin_lock_irqsave(&udc->lock, flags);
161
162 /* Stall both the IN and OUT endpoints. */
163 __isp1760_udc_select_ep(ep, USB_DIR_OUT);
164 isp1760_udc_write(udc, DC_CTRLFUNC, DC_STALL);
165 __isp1760_udc_select_ep(ep, USB_DIR_IN);
166 isp1760_udc_write(udc, DC_CTRLFUNC, DC_STALL);
167
168 /* A protocol stall completes the control transaction. */
169 udc->ep0_state = ISP1760_CTRL_SETUP;
170
171 spin_unlock_irqrestore(&udc->lock, flags);
172}
173
174/* -----------------------------------------------------------------------------
175 * Data Endpoints
176 */
177
178/* Called with the UDC spinlock held. */
179static bool isp1760_udc_receive(struct isp1760_ep *ep,
180 struct isp1760_request *req)
181{
182 struct isp1760_udc *udc = ep->udc;
183 unsigned int len;
184 u32 *buf;
185 int i;
186
187 isp1760_udc_select_ep(ep);
188 len = isp1760_udc_read(udc, DC_BUFLEN) & DC_DATACOUNT_MASK;
189
190 dev_dbg(udc->isp->dev, "%s: received %u bytes (%u/%u done)\n",
191 __func__, len, req->req.actual, req->req.length);
192
193 len = min(len, req->req.length - req->req.actual);
194
195 if (!len) {
196 /*
197 * There's no data to be read from the FIFO, acknowledge the RX
198 * interrupt by clearing the buffer.
199 *
200 * TODO: What if another packet arrives in the meantime ? The
201 * datasheet doesn't clearly document how this should be
202 * handled.
203 */
204 isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF);
205 return false;
206 }
207
208 buf = req->req.buf + req->req.actual;
209
210 /*
211 * Make sure not to read more than one extra byte, otherwise data from
212 * the next packet might be removed from the FIFO.
213 */
214 for (i = len; i > 2; i -= 4, ++buf)
215 *buf = le32_to_cpu(isp1760_udc_read(udc, DC_DATAPORT));
216 if (i > 0)
217 *(u16 *)buf = le16_to_cpu(readw(udc->regs + DC_DATAPORT));
218
219 req->req.actual += len;
220
221 /*
222 * TODO: The short_not_ok flag isn't supported yet, but isn't used by
223 * any gadget driver either.
224 */
225
226 dev_dbg(udc->isp->dev,
227 "%s: req %p actual/length %u/%u maxpacket %u packet size %u\n",
228 __func__, req, req->req.actual, req->req.length, ep->maxpacket,
229 len);
230
231 ep->rx_pending = false;
232
233 /*
234 * Complete the request if all data has been received or if a short
235 * packet has been received.
236 */
237 if (req->req.actual == req->req.length || len < ep->maxpacket) {
238 list_del(&req->queue);
239 return true;
240 }
241
242 return false;
243}
244
245static void isp1760_udc_transmit(struct isp1760_ep *ep,
246 struct isp1760_request *req)
247{
248 struct isp1760_udc *udc = ep->udc;
249 u32 *buf = req->req.buf + req->req.actual;
250 int i;
251
252 req->packet_size = min(req->req.length - req->req.actual,
253 ep->maxpacket);
254
255 dev_dbg(udc->isp->dev, "%s: transferring %u bytes (%u/%u done)\n",
256 __func__, req->packet_size, req->req.actual,
257 req->req.length);
258
259 __isp1760_udc_select_ep(ep, USB_DIR_IN);
260
261 if (req->packet_size)
262 isp1760_udc_write(udc, DC_BUFLEN, req->packet_size);
263
264 /*
265 * Make sure not to write more than one extra byte, otherwise extra data
266 * will stay in the FIFO and will be transmitted during the next control
267 * request. The endpoint control CLBUF bit is supposed to allow flushing
268 * the FIFO for this kind of conditions, but doesn't seem to work.
269 */
270 for (i = req->packet_size; i > 2; i -= 4, ++buf)
271 isp1760_udc_write(udc, DC_DATAPORT, cpu_to_le32(*buf));
272 if (i > 0)
273 writew(cpu_to_le16(*(u16 *)buf), udc->regs + DC_DATAPORT);
274
275 if (ep->addr == 0)
276 isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN);
277 if (!req->packet_size)
278 isp1760_udc_write(udc, DC_CTRLFUNC, DC_VENDP);
279}
280
281static void isp1760_ep_rx_ready(struct isp1760_ep *ep)
282{
283 struct isp1760_udc *udc = ep->udc;
284 struct isp1760_request *req;
285 bool complete;
286
287 spin_lock(&udc->lock);
288
289 if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_OUT) {
290 spin_unlock(&udc->lock);
291 dev_dbg(udc->isp->dev, "%s: invalid ep0 state %u\n", __func__,
292 udc->ep0_state);
293 return;
294 }
295
296 if (ep->addr != 0 && !ep->desc) {
297 spin_unlock(&udc->lock);
298 dev_dbg(udc->isp->dev, "%s: ep%02x is disabled\n", __func__,
299 ep->addr);
300 return;
301 }
302
303 if (list_empty(&ep->queue)) {
304 ep->rx_pending = true;
305 spin_unlock(&udc->lock);
306 dev_dbg(udc->isp->dev, "%s: ep%02x (%p) has no request queued\n",
307 __func__, ep->addr, ep);
308 return;
309 }
310
311 req = list_first_entry(&ep->queue, struct isp1760_request,
312 queue);
313 complete = isp1760_udc_receive(ep, req);
314
315 spin_unlock(&udc->lock);
316
317 if (complete)
318 isp1760_udc_request_complete(ep, req, 0);
319}
320
321static void isp1760_ep_tx_complete(struct isp1760_ep *ep)
322{
323 struct isp1760_udc *udc = ep->udc;
324 struct isp1760_request *complete = NULL;
325 struct isp1760_request *req;
326 bool need_zlp;
327
328 spin_lock(&udc->lock);
329
330 if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_IN) {
331 spin_unlock(&udc->lock);
332 dev_dbg(udc->isp->dev, "TX IRQ: invalid endpoint state %u\n",
333 udc->ep0_state);
334 return;
335 }
336
337 if (list_empty(&ep->queue)) {
338 /*
339 * This can happen for the control endpoint when the reply to
340 * the GET_STATUS IN control request is sent directly by the
341 * setup IRQ handler. Just proceed to the status stage.
342 */
343 if (ep->addr == 0) {
344 isp1760_udc_ctrl_send_status(ep, USB_DIR_IN);
345 spin_unlock(&udc->lock);
346 return;
347 }
348
349 spin_unlock(&udc->lock);
350 dev_dbg(udc->isp->dev, "%s: ep%02x has no request queued\n",
351 __func__, ep->addr);
352 return;
353 }
354
355 req = list_first_entry(&ep->queue, struct isp1760_request,
356 queue);
357 req->req.actual += req->packet_size;
358
359 need_zlp = req->req.actual == req->req.length &&
360 !(req->req.length % ep->maxpacket) &&
361 req->packet_size && req->req.zero;
362
363 dev_dbg(udc->isp->dev,
364 "TX IRQ: req %p actual/length %u/%u maxpacket %u packet size %u zero %u need zlp %u\n",
365 req, req->req.actual, req->req.length, ep->maxpacket,
366 req->packet_size, req->req.zero, need_zlp);
367
368 /*
369 * Complete the request if all data has been sent and we don't need to
370 * transmit a zero length packet.
371 */
372 if (req->req.actual == req->req.length && !need_zlp) {
373 complete = req;
374 list_del(&req->queue);
375
376 if (ep->addr == 0)
377 isp1760_udc_ctrl_send_status(ep, USB_DIR_IN);
378
379 if (!list_empty(&ep->queue))
380 req = list_first_entry(&ep->queue,
381 struct isp1760_request, queue);
382 else
383 req = NULL;
384 }
385
386 /*
387 * Transmit the next packet or start the next request, if any.
388 *
389 * TODO: If the endpoint is stalled the next request shouldn't be
390 * started, but what about the next packet ?
391 */
392 if (req)
393 isp1760_udc_transmit(ep, req);
394
395 spin_unlock(&udc->lock);
396
397 if (complete)
398 isp1760_udc_request_complete(ep, complete, 0);
399}
400
401static int __isp1760_udc_set_halt(struct isp1760_ep *ep, bool halt)
402{
403 struct isp1760_udc *udc = ep->udc;
404
405 dev_dbg(udc->isp->dev, "%s: %s halt on ep%02x\n", __func__,
406 halt ? "set" : "clear", ep->addr);
407
408 if (ep->desc && usb_endpoint_xfer_isoc(ep->desc)) {
409 dev_dbg(udc->isp->dev, "%s: ep%02x is isochronous\n", __func__,
410 ep->addr);
411 return -EINVAL;
412 }
413
414 isp1760_udc_select_ep(ep);
415 isp1760_udc_write(udc, DC_CTRLFUNC, halt ? DC_STALL : 0);
416
417 if (ep->addr == 0) {
418 /* When halting the control endpoint, stall both IN and OUT. */
419 __isp1760_udc_select_ep(ep, USB_DIR_IN);
420 isp1760_udc_write(udc, DC_CTRLFUNC, halt ? DC_STALL : 0);
421 } else if (!halt) {
422 /* Reset the data PID by cycling the endpoint enable bit. */
423 u16 eptype = isp1760_udc_read(udc, DC_EPTYPE);
424
425 isp1760_udc_write(udc, DC_EPTYPE, eptype & ~DC_EPENABLE);
426 isp1760_udc_write(udc, DC_EPTYPE, eptype);
427
428 /*
429 * Disabling the endpoint emptied the transmit FIFO, fill it
430 * again if a request is pending.
431 *
432 * TODO: Does the gadget framework require synchronizatino with
433 * the TX IRQ handler ?
434 */
435 if ((ep->addr & USB_DIR_IN) && !list_empty(&ep->queue)) {
436 struct isp1760_request *req;
437
438 req = list_first_entry(&ep->queue,
439 struct isp1760_request, queue);
440 isp1760_udc_transmit(ep, req);
441 }
442 }
443
444 ep->halted = halt;
445
446 return 0;
447}
448
449/* -----------------------------------------------------------------------------
450 * Control Endpoint
451 */
452
453static int isp1760_udc_get_status(struct isp1760_udc *udc,
454 const struct usb_ctrlrequest *req)
455{
456 struct isp1760_ep *ep;
457 u16 status;
458
459 if (req->wLength != cpu_to_le16(2) || req->wValue != cpu_to_le16(0))
460 return -EINVAL;
461
462 switch (req->bRequestType) {
463 case USB_DIR_IN | USB_RECIP_DEVICE:
464 status = udc->devstatus;
465 break;
466
467 case USB_DIR_IN | USB_RECIP_INTERFACE:
468 status = 0;
469 break;
470
471 case USB_DIR_IN | USB_RECIP_ENDPOINT:
472 ep = isp1760_udc_find_ep(udc, le16_to_cpu(req->wIndex));
473 if (!ep)
474 return -EINVAL;
475
476 status = 0;
477 if (ep->halted)
478 status |= 1 << USB_ENDPOINT_HALT;
479 break;
480
481 default:
482 return -EINVAL;
483 }
484
485 isp1760_udc_write(udc, DC_EPINDEX, DC_ENDPIDX(0) | DC_EPDIR);
486 isp1760_udc_write(udc, DC_BUFLEN, 2);
487
488 writew(cpu_to_le16(status), udc->regs + DC_DATAPORT);
489
490 isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN);
491
492 dev_dbg(udc->isp->dev, "%s: status 0x%04x\n", __func__, status);
493
494 return 0;
495}
496
497static int isp1760_udc_set_address(struct isp1760_udc *udc, u16 addr)
498{
499 if (addr > 127) {
500 dev_dbg(udc->isp->dev, "invalid device address %u\n", addr);
501 return -EINVAL;
502 }
503
504 if (udc->gadget.state != USB_STATE_DEFAULT &&
505 udc->gadget.state != USB_STATE_ADDRESS) {
506 dev_dbg(udc->isp->dev, "can't set address in state %u\n",
507 udc->gadget.state);
508 return -EINVAL;
509 }
510
511 usb_gadget_set_state(&udc->gadget, addr ? USB_STATE_ADDRESS :
512 USB_STATE_DEFAULT);
513
514 isp1760_udc_write(udc, DC_ADDRESS, DC_DEVEN | addr);
515
516 spin_lock(&udc->lock);
517 isp1760_udc_ctrl_send_status(&udc->ep[0], USB_DIR_OUT);
518 spin_unlock(&udc->lock);
519
520 return 0;
521}
522
523static bool isp1760_ep0_setup_standard(struct isp1760_udc *udc,
524 struct usb_ctrlrequest *req)
525{
526 bool stall;
527
528 switch (req->bRequest) {
529 case USB_REQ_GET_STATUS:
530 return isp1760_udc_get_status(udc, req);
531
532 case USB_REQ_CLEAR_FEATURE:
533 switch (req->bRequestType) {
534 case USB_DIR_OUT | USB_RECIP_DEVICE: {
535 /* TODO: Handle remote wakeup feature. */
536 return true;
537 }
538
539 case USB_DIR_OUT | USB_RECIP_ENDPOINT: {
540 u16 index = le16_to_cpu(req->wIndex);
541 struct isp1760_ep *ep;
542
543 if (req->wLength != cpu_to_le16(0) ||
544 req->wValue != cpu_to_le16(USB_ENDPOINT_HALT))
545 return true;
546
547 ep = isp1760_udc_find_ep(udc, index);
548 if (!ep)
549 return true;
550
551 spin_lock(&udc->lock);
552
553 /*
554 * If the endpoint is wedged only the gadget can clear
555 * the halt feature. Pretend success in that case, but
556 * keep the endpoint halted.
557 */
558 if (!ep->wedged)
559 stall = __isp1760_udc_set_halt(ep, false);
560 else
561 stall = false;
562
563 if (!stall)
564 isp1760_udc_ctrl_send_status(&udc->ep[0],
565 USB_DIR_OUT);
566
567 spin_unlock(&udc->lock);
568 return stall;
569 }
570
571 default:
572 return true;
573 }
574 break;
575
576 case USB_REQ_SET_FEATURE:
577 switch (req->bRequestType) {
578 case USB_DIR_OUT | USB_RECIP_DEVICE: {
579 /* TODO: Handle remote wakeup and test mode features */
580 return true;
581 }
582
583 case USB_DIR_OUT | USB_RECIP_ENDPOINT: {
584 u16 index = le16_to_cpu(req->wIndex);
585 struct isp1760_ep *ep;
586
587 if (req->wLength != cpu_to_le16(0) ||
588 req->wValue != cpu_to_le16(USB_ENDPOINT_HALT))
589 return true;
590
591 ep = isp1760_udc_find_ep(udc, index);
592 if (!ep)
593 return true;
594
595 spin_lock(&udc->lock);
596
597 stall = __isp1760_udc_set_halt(ep, true);
598 if (!stall)
599 isp1760_udc_ctrl_send_status(&udc->ep[0],
600 USB_DIR_OUT);
601
602 spin_unlock(&udc->lock);
603 return stall;
604 }
605
606 default:
607 return true;
608 }
609 break;
610
611 case USB_REQ_SET_ADDRESS:
612 if (req->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
613 return true;
614
615 return isp1760_udc_set_address(udc, le16_to_cpu(req->wValue));
616
617 case USB_REQ_SET_CONFIGURATION:
618 if (req->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
619 return true;
620
621 if (udc->gadget.state != USB_STATE_ADDRESS &&
622 udc->gadget.state != USB_STATE_CONFIGURED)
623 return true;
624
625 stall = udc->driver->setup(&udc->gadget, req) < 0;
626 if (stall)
627 return true;
628
629 usb_gadget_set_state(&udc->gadget, req->wValue ?
630 USB_STATE_CONFIGURED : USB_STATE_ADDRESS);
631
632 /*
633 * SET_CONFIGURATION (and SET_INTERFACE) must reset the halt
634 * feature on all endpoints. There is however no need to do so
635 * explicitly here as the gadget driver will disable and
636 * reenable endpoints, clearing the halt feature.
637 */
638 return false;
639
640 default:
641 return udc->driver->setup(&udc->gadget, req) < 0;
642 }
643}
644
645static void isp1760_ep0_setup(struct isp1760_udc *udc)
646{
647 union {
648 struct usb_ctrlrequest r;
649 u32 data[2];
650 } req;
651 unsigned int count;
652 bool stall = false;
653
654 spin_lock(&udc->lock);
655
656 isp1760_udc_write(udc, DC_EPINDEX, DC_EP0SETUP);
657
658 count = isp1760_udc_read(udc, DC_BUFLEN) & DC_DATACOUNT_MASK;
659 if (count != sizeof(req)) {
660 spin_unlock(&udc->lock);
661
662 dev_err(udc->isp->dev, "invalid length %u for setup packet\n",
663 count);
664
665 isp1760_udc_ctrl_send_stall(&udc->ep[0]);
666 return;
667 }
668
669 req.data[0] = isp1760_udc_read(udc, DC_DATAPORT);
670 req.data[1] = isp1760_udc_read(udc, DC_DATAPORT);
671
672 if (udc->ep0_state != ISP1760_CTRL_SETUP) {
673 spin_unlock(&udc->lock);
674 dev_dbg(udc->isp->dev, "unexpected SETUP packet\n");
675 return;
676 }
677
678 /* Move to the data stage. */
679 if (!req.r.wLength)
680 udc->ep0_state = ISP1760_CTRL_STATUS;
681 else if (req.r.bRequestType & USB_DIR_IN)
682 udc->ep0_state = ISP1760_CTRL_DATA_IN;
683 else
684 udc->ep0_state = ISP1760_CTRL_DATA_OUT;
685
686 udc->ep0_dir = req.r.bRequestType & USB_DIR_IN;
687 udc->ep0_length = le16_to_cpu(req.r.wLength);
688
689 spin_unlock(&udc->lock);
690
691 dev_dbg(udc->isp->dev,
692 "%s: bRequestType 0x%02x bRequest 0x%02x wValue 0x%04x wIndex 0x%04x wLength 0x%04x\n",
693 __func__, req.r.bRequestType, req.r.bRequest,
694 le16_to_cpu(req.r.wValue), le16_to_cpu(req.r.wIndex),
695 le16_to_cpu(req.r.wLength));
696
697 if ((req.r.bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
698 stall = isp1760_ep0_setup_standard(udc, &req.r);
699 else
700 stall = udc->driver->setup(&udc->gadget, &req.r) < 0;
701
702 if (stall)
703 isp1760_udc_ctrl_send_stall(&udc->ep[0]);
704}
705
706/* -----------------------------------------------------------------------------
707 * Gadget Endpoint Operations
708 */
709
710static int isp1760_ep_enable(struct usb_ep *ep,
711 const struct usb_endpoint_descriptor *desc)
712{
713 struct isp1760_ep *uep = ep_to_udc_ep(ep);
714 struct isp1760_udc *udc = uep->udc;
715 unsigned long flags;
716 unsigned int type;
717
718 dev_dbg(uep->udc->isp->dev, "%s\n", __func__);
719
720 /*
721 * Validate the descriptor. The control endpoint can't be enabled
722 * manually.
723 */
724 if (desc->bDescriptorType != USB_DT_ENDPOINT ||
725 desc->bEndpointAddress == 0 ||
726 desc->bEndpointAddress != uep->addr ||
727 le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket) {
728 dev_dbg(udc->isp->dev,
729 "%s: invalid descriptor type %u addr %02x ep addr %02x max packet size %u/%u\n",
730 __func__, desc->bDescriptorType,
731 desc->bEndpointAddress, uep->addr,
732 le16_to_cpu(desc->wMaxPacketSize), ep->maxpacket);
733 return -EINVAL;
734 }
735
736 switch (usb_endpoint_type(desc)) {
737 case USB_ENDPOINT_XFER_ISOC:
738 type = DC_ENDPTYP_ISOC;
739 break;
740 case USB_ENDPOINT_XFER_BULK:
741 type = DC_ENDPTYP_BULK;
742 break;
743 case USB_ENDPOINT_XFER_INT:
744 type = DC_ENDPTYP_INTERRUPT;
745 break;
746 case USB_ENDPOINT_XFER_CONTROL:
747 default:
748 dev_dbg(udc->isp->dev, "%s: control endpoints unsupported\n",
749 __func__);
750 return -EINVAL;
751 }
752
753 spin_lock_irqsave(&udc->lock, flags);
754
755 uep->desc = desc;
756 uep->maxpacket = le16_to_cpu(desc->wMaxPacketSize);
757 uep->rx_pending = false;
758 uep->halted = false;
759 uep->wedged = false;
760
761 isp1760_udc_select_ep(uep);
762 isp1760_udc_write(udc, DC_EPMAXPKTSZ, uep->maxpacket);
763 isp1760_udc_write(udc, DC_BUFLEN, uep->maxpacket);
764 isp1760_udc_write(udc, DC_EPTYPE, DC_EPENABLE | type);
765
766 spin_unlock_irqrestore(&udc->lock, flags);
767
768 return 0;
769}
770
771static int isp1760_ep_disable(struct usb_ep *ep)
772{
773 struct isp1760_ep *uep = ep_to_udc_ep(ep);
774 struct isp1760_udc *udc = uep->udc;
775 struct isp1760_request *req, *nreq;
776 LIST_HEAD(req_list);
777 unsigned long flags;
778
779 dev_dbg(udc->isp->dev, "%s\n", __func__);
780
781 spin_lock_irqsave(&udc->lock, flags);
782
783 if (!uep->desc) {
784 dev_dbg(udc->isp->dev, "%s: endpoint not enabled\n", __func__);
785 spin_unlock_irqrestore(&udc->lock, flags);
786 return -EINVAL;
787 }
788
789 uep->desc = NULL;
790 uep->maxpacket = 0;
791
792 isp1760_udc_select_ep(uep);
793 isp1760_udc_write(udc, DC_EPTYPE, 0);
794
795 /* TODO Synchronize with the IRQ handler */
796
797 list_splice_init(&uep->queue, &req_list);
798
799 spin_unlock_irqrestore(&udc->lock, flags);
800
801 list_for_each_entry_safe(req, nreq, &req_list, queue) {
802 list_del(&req->queue);
803 isp1760_udc_request_complete(uep, req, -ESHUTDOWN);
804 }
805
806 return 0;
807}
808
809static struct usb_request *isp1760_ep_alloc_request(struct usb_ep *ep,
810 gfp_t gfp_flags)
811{
812 struct isp1760_request *req;
813
814 req = kzalloc(sizeof(*req), gfp_flags);
815
816 return &req->req;
817}
818
819static void isp1760_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
820{
821 struct isp1760_request *req = req_to_udc_req(_req);
822
823 kfree(req);
824}
825
826static int isp1760_ep_queue(struct usb_ep *ep, struct usb_request *_req,
827 gfp_t gfp_flags)
828{
829 struct isp1760_request *req = req_to_udc_req(_req);
830 struct isp1760_ep *uep = ep_to_udc_ep(ep);
831 struct isp1760_udc *udc = uep->udc;
832 bool complete = false;
833 unsigned long flags;
834 int ret = 0;
835
836 _req->status = -EINPROGRESS;
837 _req->actual = 0;
838
839 spin_lock_irqsave(&udc->lock, flags);
840
841 dev_dbg(udc->isp->dev,
842 "%s: req %p (%u bytes%s) ep %p(0x%02x)\n", __func__, _req,
843 _req->length, _req->zero ? " (zlp)" : "", uep, uep->addr);
844
845 req->ep = uep;
846
847 if (uep->addr == 0) {
848 if (_req->length != udc->ep0_length &&
849 udc->ep0_state != ISP1760_CTRL_DATA_IN) {
850 dev_dbg(udc->isp->dev,
851 "%s: invalid length %u for req %p\n",
852 __func__, _req->length, req);
853 ret = -EINVAL;
854 goto done;
855 }
856
857 switch (udc->ep0_state) {
858 case ISP1760_CTRL_DATA_IN:
859 dev_dbg(udc->isp->dev, "%s: transmitting req %p\n",
860 __func__, req);
861
862 list_add_tail(&req->queue, &uep->queue);
863 isp1760_udc_transmit(uep, req);
864 break;
865
866 case ISP1760_CTRL_DATA_OUT:
867 list_add_tail(&req->queue, &uep->queue);
868 __isp1760_udc_select_ep(uep, USB_DIR_OUT);
869 isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN);
870 break;
871
872 case ISP1760_CTRL_STATUS:
873 complete = true;
874 break;
875
876 default:
877 dev_dbg(udc->isp->dev, "%s: invalid ep0 state\n",
878 __func__);
879 ret = -EINVAL;
880 break;
881 }
882 } else if (uep->desc) {
883 bool empty = list_empty(&uep->queue);
884
885 list_add_tail(&req->queue, &uep->queue);
886 if ((uep->addr & USB_DIR_IN) && !uep->halted && empty)
887 isp1760_udc_transmit(uep, req);
888 else if (!(uep->addr & USB_DIR_IN) && uep->rx_pending)
889 complete = isp1760_udc_receive(uep, req);
890 } else {
891 dev_dbg(udc->isp->dev,
892 "%s: can't queue request to disabled ep%02x\n",
893 __func__, uep->addr);
894 ret = -ESHUTDOWN;
895 }
896
897done:
898 if (ret < 0)
899 req->ep = NULL;
900
901 spin_unlock_irqrestore(&udc->lock, flags);
902
903 if (complete)
904 isp1760_udc_request_complete(uep, req, 0);
905
906 return ret;
907}
908
909static int isp1760_ep_dequeue(struct usb_ep *ep, struct usb_request *_req)
910{
911 struct isp1760_request *req = req_to_udc_req(_req);
912 struct isp1760_ep *uep = ep_to_udc_ep(ep);
913 struct isp1760_udc *udc = uep->udc;
914 unsigned long flags;
915
916 dev_dbg(uep->udc->isp->dev, "%s(ep%02x)\n", __func__, uep->addr);
917
918 spin_lock_irqsave(&udc->lock, flags);
919
920 if (req->ep != uep)
921 req = NULL;
922 else
923 list_del(&req->queue);
924
925 spin_unlock_irqrestore(&udc->lock, flags);
926
927 if (!req)
928 return -EINVAL;
929
930 isp1760_udc_request_complete(uep, req, -ECONNRESET);
931 return 0;
932}
933
934static int __isp1760_ep_set_halt(struct isp1760_ep *uep, bool stall, bool wedge)
935{
936 struct isp1760_udc *udc = uep->udc;
937 int ret;
938
939 if (!uep->addr) {
940 /*
941 * Halting the control endpoint is only valid as a delayed error
942 * response to a SETUP packet. Make sure EP0 is in the right
943 * stage and that the gadget isn't trying to clear the halt
944 * condition.
945 */
946 if (WARN_ON(udc->ep0_state == ISP1760_CTRL_SETUP || !stall ||
947 wedge)) {
948 return -EINVAL;
949 }
950 }
951
952 if (uep->addr && !uep->desc) {
953 dev_dbg(udc->isp->dev, "%s: ep%02x is disabled\n", __func__,
954 uep->addr);
955 return -EINVAL;
956 }
957
958 if (uep->addr & USB_DIR_IN) {
959 /* Refuse to halt IN endpoints with active transfers. */
960 if (!list_empty(&uep->queue)) {
961 dev_dbg(udc->isp->dev,
962 "%s: ep%02x has request pending\n", __func__,
963 uep->addr);
964 return -EAGAIN;
965 }
966 }
967
968 ret = __isp1760_udc_set_halt(uep, stall);
969 if (ret < 0)
970 return ret;
971
972 if (!uep->addr) {
973 /*
974 * Stalling EP0 completes the control transaction, move back to
975 * the SETUP state.
976 */
977 udc->ep0_state = ISP1760_CTRL_SETUP;
978 return 0;
979 }
980
981 if (wedge)
982 uep->wedged = true;
983 else if (!stall)
984 uep->wedged = false;
985
986 return 0;
987}
988
989static int isp1760_ep_set_halt(struct usb_ep *ep, int value)
990{
991 struct isp1760_ep *uep = ep_to_udc_ep(ep);
992 unsigned long flags;
993 int ret;
994
995 dev_dbg(uep->udc->isp->dev, "%s: %s halt on ep%02x\n", __func__,
996 value ? "set" : "clear", uep->addr);
997
998 spin_lock_irqsave(&uep->udc->lock, flags);
999 ret = __isp1760_ep_set_halt(uep, value, false);
1000 spin_unlock_irqrestore(&uep->udc->lock, flags);
1001
1002 return ret;
1003}
1004
1005static int isp1760_ep_set_wedge(struct usb_ep *ep)
1006{
1007 struct isp1760_ep *uep = ep_to_udc_ep(ep);
1008 unsigned long flags;
1009 int ret;
1010
1011 dev_dbg(uep->udc->isp->dev, "%s: set wedge on ep%02x)\n", __func__,
1012 uep->addr);
1013
1014 spin_lock_irqsave(&uep->udc->lock, flags);
1015 ret = __isp1760_ep_set_halt(uep, true, true);
1016 spin_unlock_irqrestore(&uep->udc->lock, flags);
1017
1018 return ret;
1019}
1020
1021static void isp1760_ep_fifo_flush(struct usb_ep *ep)
1022{
1023 struct isp1760_ep *uep = ep_to_udc_ep(ep);
1024 struct isp1760_udc *udc = uep->udc;
1025 unsigned long flags;
1026
1027 spin_lock_irqsave(&udc->lock, flags);
1028
1029 isp1760_udc_select_ep(uep);
1030
1031 /*
1032 * Set the CLBUF bit twice to flush both buffers in case double
1033 * buffering is enabled.
1034 */
1035 isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF);
1036 isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF);
1037
1038 spin_unlock_irqrestore(&udc->lock, flags);
1039}
1040
1041static const struct usb_ep_ops isp1760_ep_ops = {
1042 .enable = isp1760_ep_enable,
1043 .disable = isp1760_ep_disable,
1044 .alloc_request = isp1760_ep_alloc_request,
1045 .free_request = isp1760_ep_free_request,
1046 .queue = isp1760_ep_queue,
1047 .dequeue = isp1760_ep_dequeue,
1048 .set_halt = isp1760_ep_set_halt,
1049 .set_wedge = isp1760_ep_set_wedge,
1050 .fifo_flush = isp1760_ep_fifo_flush,
1051};
1052
1053/* -----------------------------------------------------------------------------
1054 * Device States
1055 */
1056
1057/* Called with the UDC spinlock held. */
1058static void isp1760_udc_connect(struct isp1760_udc *udc)
1059{
1060 usb_gadget_set_state(&udc->gadget, USB_STATE_POWERED);
1061 mod_timer(&udc->vbus_timer, jiffies + ISP1760_VBUS_POLL_INTERVAL);
1062}
1063
1064/* Called with the UDC spinlock held. */
1065static void isp1760_udc_disconnect(struct isp1760_udc *udc)
1066{
1067 if (udc->gadget.state < USB_STATE_POWERED)
1068 return;
1069
1070 dev_dbg(udc->isp->dev, "Device disconnected in state %u\n",
1071 udc->gadget.state);
1072
1073 udc->gadget.speed = USB_SPEED_UNKNOWN;
1074 usb_gadget_set_state(&udc->gadget, USB_STATE_ATTACHED);
1075
1076 if (udc->driver->disconnect)
1077 udc->driver->disconnect(&udc->gadget);
1078
1079 del_timer(&udc->vbus_timer);
1080
1081 /* TODO Reset all endpoints ? */
1082}
1083
1084static void isp1760_udc_init_hw(struct isp1760_udc *udc)
1085{
1086 /*
1087 * The device controller currently shares its interrupt with the host
1088 * controller, the DC_IRQ polarity and signaling mode are ignored. Set
1089 * the to active-low level-triggered.
1090 *
1091 * Configure the control, in and out pipes to generate interrupts on
1092 * ACK tokens only (and NYET for the out pipe). The default
1093 * configuration also generates an interrupt on the first NACK token.
1094 */
1095 isp1760_udc_write(udc, DC_INTCONF, DC_CDBGMOD_ACK | DC_DDBGMODIN_ACK |
1096 DC_DDBGMODOUT_ACK_NYET);
1097
1098 isp1760_udc_write(udc, DC_INTENABLE, DC_IEPRXTX(7) | DC_IEPRXTX(6) |
1099 DC_IEPRXTX(5) | DC_IEPRXTX(4) | DC_IEPRXTX(3) |
1100 DC_IEPRXTX(2) | DC_IEPRXTX(1) | DC_IEPRXTX(0) |
1101 DC_IEP0SETUP | DC_IEVBUS | DC_IERESM | DC_IESUSP |
1102 DC_IEHS_STA | DC_IEBRST);
1103
1104 if (udc->connected)
1105 isp1760_set_pullup(udc->isp, true);
1106
1107 isp1760_udc_write(udc, DC_ADDRESS, DC_DEVEN);
1108}
1109
1110static void isp1760_udc_reset(struct isp1760_udc *udc)
1111{
1112 unsigned long flags;
1113
1114 spin_lock_irqsave(&udc->lock, flags);
1115
1116 /*
1117 * The bus reset has reset most registers to their default value,
1118 * reinitialize the UDC hardware.
1119 */
1120 isp1760_udc_init_hw(udc);
1121
1122 udc->ep0_state = ISP1760_CTRL_SETUP;
1123 udc->gadget.speed = USB_SPEED_FULL;
1124
1125 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1126
1127 spin_unlock_irqrestore(&udc->lock, flags);
1128}
1129
1130static void isp1760_udc_suspend(struct isp1760_udc *udc)
1131{
1132 if (udc->gadget.state < USB_STATE_DEFAULT)
1133 return;
1134
1135 if (udc->driver->suspend)
1136 udc->driver->suspend(&udc->gadget);
1137}
1138
1139static void isp1760_udc_resume(struct isp1760_udc *udc)
1140{
1141 if (udc->gadget.state < USB_STATE_DEFAULT)
1142 return;
1143
1144 if (udc->driver->resume)
1145 udc->driver->resume(&udc->gadget);
1146}
1147
1148/* -----------------------------------------------------------------------------
1149 * Gadget Operations
1150 */
1151
1152static int isp1760_udc_get_frame(struct usb_gadget *gadget)
1153{
1154 struct isp1760_udc *udc = gadget_to_udc(gadget);
1155
1156 return isp1760_udc_read(udc, DC_FRAMENUM) & ((1 << 11) - 1);
1157}
1158
1159static int isp1760_udc_wakeup(struct usb_gadget *gadget)
1160{
1161 struct isp1760_udc *udc = gadget_to_udc(gadget);
1162
1163 dev_dbg(udc->isp->dev, "%s\n", __func__);
1164 return -ENOTSUPP;
1165}
1166
1167static int isp1760_udc_set_selfpowered(struct usb_gadget *gadget,
1168 int is_selfpowered)
1169{
1170 struct isp1760_udc *udc = gadget_to_udc(gadget);
1171
1172 if (is_selfpowered)
1173 udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
1174 else
1175 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
1176
1177 return 0;
1178}
1179
1180static int isp1760_udc_pullup(struct usb_gadget *gadget, int is_on)
1181{
1182 struct isp1760_udc *udc = gadget_to_udc(gadget);
1183
1184 isp1760_set_pullup(udc->isp, is_on);
1185 udc->connected = is_on;
1186
1187 return 0;
1188}
1189
1190static int isp1760_udc_start(struct usb_gadget *gadget,
1191 struct usb_gadget_driver *driver)
1192{
1193 struct isp1760_udc *udc = gadget_to_udc(gadget);
1194
1195 /* The hardware doesn't support low speed. */
1196 if (driver->max_speed < USB_SPEED_FULL) {
1197 dev_err(udc->isp->dev, "Invalid gadget driver\n");
1198 return -EINVAL;
1199 }
1200
1201 spin_lock(&udc->lock);
1202
1203 if (udc->driver) {
1204 dev_err(udc->isp->dev, "UDC already has a gadget driver\n");
1205 spin_unlock(&udc->lock);
1206 return -EBUSY;
1207 }
1208
1209 udc->driver = driver;
1210
1211 spin_unlock(&udc->lock);
1212
1213 dev_dbg(udc->isp->dev, "starting UDC with driver %s\n",
1214 driver->function);
1215
1216 udc->devstatus = 0;
1217 udc->connected = true;
1218
1219 usb_gadget_set_state(&udc->gadget, USB_STATE_ATTACHED);
1220
1221 /* DMA isn't supported yet, don't enable the DMA clock. */
1222 isp1760_udc_write(udc, DC_MODE, DC_GLINTENA);
1223
1224 isp1760_udc_init_hw(udc);
1225
1226 dev_dbg(udc->isp->dev, "UDC started with driver %s\n",
1227 driver->function);
1228
1229 return 0;
1230}
1231
1232static int isp1760_udc_stop(struct usb_gadget *gadget)
1233{
1234 struct isp1760_udc *udc = gadget_to_udc(gadget);
1235
1236 dev_dbg(udc->isp->dev, "%s\n", __func__);
1237
1238 del_timer_sync(&udc->vbus_timer);
1239
1240 isp1760_udc_write(udc, DC_MODE, 0);
1241
1242 spin_lock(&udc->lock);
1243 udc->driver = NULL;
1244 spin_unlock(&udc->lock);
1245
1246 return 0;
1247}
1248
1249static struct usb_gadget_ops isp1760_udc_ops = {
1250 .get_frame = isp1760_udc_get_frame,
1251 .wakeup = isp1760_udc_wakeup,
1252 .set_selfpowered = isp1760_udc_set_selfpowered,
1253 .pullup = isp1760_udc_pullup,
1254 .udc_start = isp1760_udc_start,
1255 .udc_stop = isp1760_udc_stop,
1256};
1257
1258/* -----------------------------------------------------------------------------
1259 * Interrupt Handling
1260 */
1261
1262static irqreturn_t isp1760_udc_irq(int irq, void *dev)
1263{
1264 struct isp1760_udc *udc = dev;
1265 unsigned int i;
1266 u32 status;
1267
1268 status = isp1760_udc_read(udc, DC_INTERRUPT)
1269 & isp1760_udc_read(udc, DC_INTENABLE);
1270 isp1760_udc_write(udc, DC_INTERRUPT, status);
1271
1272 if (status & DC_IEVBUS) {
1273 dev_dbg(udc->isp->dev, "%s(VBUS)\n", __func__);
1274 /* The VBUS interrupt is only triggered when VBUS appears. */
1275 spin_lock(&udc->lock);
1276 isp1760_udc_connect(udc);
1277 spin_unlock(&udc->lock);
1278 }
1279
1280 if (status & DC_IEBRST) {
1281 dev_dbg(udc->isp->dev, "%s(BRST)\n", __func__);
1282
1283 isp1760_udc_reset(udc);
1284 }
1285
1286 for (i = 0; i <= 7; ++i) {
1287 struct isp1760_ep *ep = &udc->ep[i*2];
1288
1289 if (status & DC_IEPTX(i)) {
1290 dev_dbg(udc->isp->dev, "%s(EPTX%u)\n", __func__, i);
1291 isp1760_ep_tx_complete(ep);
1292 }
1293
1294 if (status & DC_IEPRX(i)) {
1295 dev_dbg(udc->isp->dev, "%s(EPRX%u)\n", __func__, i);
1296 isp1760_ep_rx_ready(i ? ep - 1 : ep);
1297 }
1298 }
1299
1300 if (status & DC_IEP0SETUP) {
1301 dev_dbg(udc->isp->dev, "%s(EP0SETUP)\n", __func__);
1302
1303 isp1760_ep0_setup(udc);
1304 }
1305
1306 if (status & DC_IERESM) {
1307 dev_dbg(udc->isp->dev, "%s(RESM)\n", __func__);
1308 isp1760_udc_resume(udc);
1309 }
1310
1311 if (status & DC_IESUSP) {
1312 dev_dbg(udc->isp->dev, "%s(SUSP)\n", __func__);
1313
1314 spin_lock(&udc->lock);
1315 if (!(isp1760_udc_read(udc, DC_MODE) & DC_VBUSSTAT))
1316 isp1760_udc_disconnect(udc);
1317 else
1318 isp1760_udc_suspend(udc);
1319 spin_unlock(&udc->lock);
1320 }
1321
1322 if (status & DC_IEHS_STA) {
1323 dev_dbg(udc->isp->dev, "%s(HS_STA)\n", __func__);
1324 udc->gadget.speed = USB_SPEED_HIGH;
1325 }
1326
1327 return status ? IRQ_HANDLED : IRQ_NONE;
1328}
1329
1330static void isp1760_udc_vbus_poll(unsigned long data)
1331{
1332 struct isp1760_udc *udc = (struct isp1760_udc *)data;
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&udc->lock, flags);
1336
1337 if (!(isp1760_udc_read(udc, DC_MODE) & DC_VBUSSTAT))
1338 isp1760_udc_disconnect(udc);
1339 else if (udc->gadget.state >= USB_STATE_POWERED)
1340 mod_timer(&udc->vbus_timer,
1341 jiffies + ISP1760_VBUS_POLL_INTERVAL);
1342
1343 spin_unlock_irqrestore(&udc->lock, flags);
1344}
1345
1346/* -----------------------------------------------------------------------------
1347 * Registration
1348 */
1349
1350static void isp1760_udc_init_eps(struct isp1760_udc *udc)
1351{
1352 unsigned int i;
1353
1354 INIT_LIST_HEAD(&udc->gadget.ep_list);
1355
1356 for (i = 0; i < ARRAY_SIZE(udc->ep); ++i) {
1357 struct isp1760_ep *ep = &udc->ep[i];
1358 unsigned int ep_num = (i + 1) / 2;
1359 bool is_in = !(i & 1);
1360
1361 ep->udc = udc;
1362
1363 INIT_LIST_HEAD(&ep->queue);
1364
1365 ep->addr = (ep_num && is_in ? USB_DIR_IN : USB_DIR_OUT)
1366 | ep_num;
1367 ep->desc = NULL;
1368
1369 sprintf(ep->name, "ep%u%s", ep_num,
1370 ep_num ? (is_in ? "in" : "out") : "");
1371
1372 ep->ep.ops = &isp1760_ep_ops;
1373 ep->ep.name = ep->name;
1374
1375 /*
1376 * Hardcode the maximum packet sizes for now, to 64 bytes for
1377 * the control endpoint and 512 bytes for all other endpoints.
1378 * This fits in the 8kB FIFO without double-buffering.
1379 */
1380 if (ep_num == 0) {
1381 ep->ep.maxpacket = 64;
1382 ep->maxpacket = 64;
1383 udc->gadget.ep0 = &ep->ep;
1384 } else {
1385 ep->ep.maxpacket = 512;
1386 ep->maxpacket = 0;
1387 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1388 }
1389 }
1390}
1391
1392static int isp1760_udc_init(struct isp1760_udc *udc)
1393{
1394 u16 scratch;
1395 u32 chipid;
1396
1397 /*
1398 * Check that the controller is present by writing to the scratch
1399 * register, modifying the bus pattern by reading from the chip ID
1400 * register, and reading the scratch register value back. The chip ID
1401 * and scratch register contents must match the expected values.
1402 */
1403 isp1760_udc_write(udc, DC_SCRATCH, 0xbabe);
1404 chipid = isp1760_udc_read(udc, DC_CHIPID);
1405 scratch = isp1760_udc_read(udc, DC_SCRATCH);
1406
1407 if (scratch != 0xbabe) {
1408 dev_err(udc->isp->dev,
1409 "udc: scratch test failed (0x%04x/0x%08x)\n",
1410 scratch, chipid);
1411 return -ENODEV;
1412 }
1413
1414 if (chipid != 0x00011582) {
1415 dev_err(udc->isp->dev, "udc: invalid chip ID 0x%08x\n", chipid);
1416 return -ENODEV;
1417 }
1418
1419 /* Reset the device controller. */
1420 isp1760_udc_write(udc, DC_MODE, DC_SFRESET);
1421 usleep_range(10000, 11000);
1422 isp1760_udc_write(udc, DC_MODE, 0);
1423 usleep_range(10000, 11000);
1424
1425 return 0;
1426}
1427
1428int isp1760_udc_register(struct isp1760_device *isp, int irq,
1429 unsigned long irqflags)
1430{
1431 struct isp1760_udc *udc = &isp->udc;
1432 const char *devname;
1433 int ret;
1434
1435 udc->irq = -1;
1436 udc->isp = isp;
1437 udc->regs = isp->regs;
1438
1439 spin_lock_init(&udc->lock);
1440 setup_timer(&udc->vbus_timer, isp1760_udc_vbus_poll,
1441 (unsigned long)udc);
1442
1443 ret = isp1760_udc_init(udc);
1444 if (ret < 0)
1445 return ret;
1446
1447 devname = dev_name(isp->dev);
1448 udc->irqname = kmalloc(strlen(devname) + 7, GFP_KERNEL);
1449 if (!udc->irqname)
1450 return -ENOMEM;
1451
1452 sprintf(udc->irqname, "%s (udc)", devname);
1453
1454 ret = request_irq(irq, isp1760_udc_irq, IRQF_SHARED | IRQF_DISABLED |
1455 irqflags, udc->irqname, udc);
1456 if (ret < 0)
1457 goto error;
1458
1459 udc->irq = irq;
1460
1461 /*
1462 * Initialize the gadget static fields and register its device. Gadget
1463 * fields that vary during the life time of the gadget are initialized
1464 * by the UDC core.
1465 */
1466 udc->gadget.ops = &isp1760_udc_ops;
1467 udc->gadget.speed = USB_SPEED_UNKNOWN;
1468 udc->gadget.max_speed = USB_SPEED_HIGH;
1469 udc->gadget.name = "isp1761_udc";
1470
1471 isp1760_udc_init_eps(udc);
1472
1473 ret = usb_add_gadget_udc(isp->dev, &udc->gadget);
1474 if (ret < 0)
1475 goto error;
1476
1477 return 0;
1478
1479error:
1480 if (udc->irq >= 0)
1481 free_irq(udc->irq, udc);
1482 kfree(udc->irqname);
1483
1484 return ret;
1485}
1486
1487void isp1760_udc_unregister(struct isp1760_device *isp)
1488{
1489 struct isp1760_udc *udc = &isp->udc;
1490
1491 usb_del_gadget_udc(&udc->gadget);
1492
1493 free_irq(udc->irq, udc);
1494 kfree(udc->irqname);
1495}
diff --git a/drivers/usb/host/isp1760-udc.h b/drivers/usb/host/isp1760-udc.h
deleted file mode 100644
index 4af6ba6eda86..000000000000
--- a/drivers/usb/host/isp1760-udc.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * Driver for the NXP ISP1761 device controller
3 *
4 * Copyright 2014 Ideas on Board Oy
5 *
6 * Contacts:
7 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 */
13
14#ifndef _ISP1760_UDC_H_
15#define _ISP1760_UDC_H_
16
17#include <linux/ioport.h>
18#include <linux/list.h>
19#include <linux/spinlock.h>
20#include <linux/timer.h>
21#include <linux/usb/gadget.h>
22
23struct isp1760_device;
24struct isp1760_udc;
25
26enum isp1760_ctrl_state {
27 ISP1760_CTRL_SETUP, /* Waiting for a SETUP transaction */
28 ISP1760_CTRL_DATA_IN, /* Setup received, data IN stage */
29 ISP1760_CTRL_DATA_OUT, /* Setup received, data OUT stage */
30 ISP1760_CTRL_STATUS, /* 0-length request in status stage */
31};
32
33struct isp1760_ep {
34 struct isp1760_udc *udc;
35 struct usb_ep ep;
36
37 struct list_head queue;
38
39 unsigned int addr;
40 unsigned int maxpacket;
41 char name[7];
42
43 const struct usb_endpoint_descriptor *desc;
44
45 bool rx_pending;
46 bool halted;
47 bool wedged;
48};
49
50/**
51 * struct isp1760_udc - UDC state information
52 * irq: IRQ number
53 * irqname: IRQ name (as passed to request_irq)
54 * regs: Base address of the UDC registers
55 * driver: Gadget driver
56 * gadget: Gadget device
57 * lock: Protects driver, vbus_timer, ep, ep0_*, DC_EPINDEX register
58 * ep: Array of endpoints
59 * ep0_state: Control request state for endpoint 0
60 * ep0_dir: Direction of the current control request
61 * ep0_length: Length of the current control request
62 * connected: Tracks gadget driver bus connection state
63 */
64struct isp1760_udc {
65#if CONFIG_USB_ISP1761_UDC
66 struct isp1760_device *isp;
67
68 int irq;
69 char *irqname;
70 void __iomem *regs;
71
72 struct usb_gadget_driver *driver;
73 struct usb_gadget gadget;
74
75 spinlock_t lock;
76 struct timer_list vbus_timer;
77
78 struct isp1760_ep ep[15];
79
80 enum isp1760_ctrl_state ep0_state;
81 u8 ep0_dir;
82 u16 ep0_length;
83
84 bool connected;
85
86 unsigned int devstatus;
87#endif
88};
89
90#if CONFIG_USB_ISP1761_UDC
91int isp1760_udc_register(struct isp1760_device *isp, int irq,
92 unsigned long irqflags);
93void isp1760_udc_unregister(struct isp1760_device *isp);
94#else
95static inline int isp1760_udc_register(struct isp1760_device *isp, int irq,
96 unsigned long irqflags)
97{
98 return 0;
99}
100
101static inline void isp1760_udc_unregister(struct isp1760_device *isp)
102{
103}
104#endif
105
106#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-12 11:07:11 -0400