USB: xhci: Ring allocation and initialization.

Allocate basic xHCI host controller data structures.  For every xHC, there
is a command ring, an event ring, and a doorbell array.

The doorbell array is used to notify the host controller that work has
been enqueued onto one of the rings.  The host controller driver enqueues
commands on the command ring.  The HW enqueues command completion events
on the event ring and interrupts the system (currently using PCI
interrupts, although the xHCI HW will use MSI interrupts eventually).

All rings and the doorbell array must be allocated by the xHCI host
controller driver.

Each ring is comprised of one or more segments, which consists of 16-byte
Transfer Request Blocks (TRBs) that can be chained to form a Transfer
Descriptor (TD) that represents a multiple-buffer request.  Segments are
linked into a ring using Link TRBs, which means they are dynamically
growable.

The producer of the ring enqueues a TD by writing one or more TRBs in the
ring and toggling the TRB cycle bit for each TRB.  The consumer knows it
can process the TRB when the cycle bit matches its internal consumer cycle
state for the ring.  The consumer cycle state is toggled an odd amount of
times in the ring.

An example ring (a ring must have a minimum of 16 TRBs on it, but that's
too big to draw in ASCII art):

              chain  cycle
               bit    bit
 ------------------------
| TD A TRB 1 |  1  |  1  |<-------------  <-- consumer dequeue ptr
 ------------------------               |     consumer cycle state = 1
| TD A TRB 2 |  1  |  1  |              |
 ------------------------               |
| TD A TRB 3 |  0  |  1  |  segment 1   |
 ------------------------               |
| TD B TRB 1 |  1  |  1  |              |
 ------------------------               |
| TD B TRB 2 |  0  |  1  |              |
 ------------------------               |
| Link TRB   |  0  |  1  |-----         |
 ------------------------     |         |
                              |         |
              chain  cycle    |         |
               bit    bit     |         |
 ------------------------     |         |
| TD C TRB 1 |  0  |  1  |<----         |
 ------------------------               |
| TD D TRB 1 |  1  |  1  |              |
 ------------------------               |
| TD D TRB 2 |  1  |  1  |   segment 2  |
 ------------------------               |
| TD D TRB 3 |  1  |  1  |              |
 ------------------------               |
| TD D TRB 4 |  1  |  1  |              |
 ------------------------               |
| Link TRB   |  1  |  1  |-----         |
 ------------------------     |         |
                              |         |
              chain  cycle    |         |
               bit    bit     |         |
 ------------------------     |         |
| TD D TRB 5 |  1  |  1  |<----         |
 ------------------------               |
| TD D TRB 6 |  0  |  1  |              |
 ------------------------               |
| TD E TRB 1 |  0  |  1  |   segment 3  |
 ------------------------               |
|            |  0  |  0  |              | <-- producer enqueue ptr
 ------------------------               |
|            |  0  |  0  |              |
 ------------------------               |
| Link TRB   |  0  |  0  |---------------
 ------------------------

Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 304 insertions, 1 deletions

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 0e383f9c380c..7cf15ca854be 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -21,18 +21,215 @@
  */
 
 #include <linux/usb.h>
+#include <linux/pci.h>
 
 #include "xhci.h"
 
+/*
+ * Allocates a generic ring segment from the ring pool, sets the dma address,
+ * initializes the segment to zero, and sets the private next pointer to NULL.
+ *
+ * Section 4.11.1.1:
+ * "All components of all Command and Transfer TRBs shall be initialized to '0'"
+ */
+static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
+{
+        struct xhci_segment *seg;
+        dma_addr_t      dma;
+
+        seg = kzalloc(sizeof *seg, flags);
+        if (!seg)
+                return 0;
+        xhci_dbg(xhci, "Allocating priv segment structure at 0x%x\n",
+                        (unsigned int) seg);
+
+        seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
+        if (!seg->trbs) {
+                kfree(seg);
+                return 0;
+        }
+        xhci_dbg(xhci, "// Allocating segment at 0x%x (virtual) 0x%x (DMA)\n",
+                        (unsigned int) seg->trbs, (u32) dma);
+
+        memset(seg->trbs, 0, SEGMENT_SIZE);
+        seg->dma = dma;
+        seg->next = NULL;
+
+        return seg;
+}
+
+static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
+{
+        if (!seg)
+                return;
+        if (seg->trbs) {
+                xhci_dbg(xhci, "Freeing DMA segment at 0x%x"
+                                " (virtual) 0x%x (DMA)\n",
+                                (unsigned int) seg->trbs, (u32) seg->dma);
+                dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
+                seg->trbs = NULL;
+        }
+        xhci_dbg(xhci, "Freeing priv segment structure at 0x%x\n",
+                        (unsigned int) seg);
+        kfree(seg);
+}
+
+/*
+ * Make the prev segment point to the next segment.
+ *
+ * Change the last TRB in the prev segment to be a Link TRB which points to the
+ * DMA address of the next segment.  The caller needs to set any Link TRB
+ * related flags, such as End TRB, Toggle Cycle, and no snoop.
+ */
+static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
+                struct xhci_segment *next, bool link_trbs)
+{
+        u32 val;
+
+        if (!prev || !next)
+                return;
+        prev->next = next;
+        if (link_trbs) {
+                prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr[0] = next->dma;
+
+                /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
+                val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
+                val &= ~TRB_TYPE_BITMASK;
+                val |= TRB_TYPE(TRB_LINK);
+                prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
+        }
+        xhci_dbg(xhci, "Linking segment 0x%x to segment 0x%x (DMA)\n",
+                        prev->dma, next->dma);
+}
+
+/* XXX: Do we need the hcd structure in all these functions? */
+static void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
+{
+        struct xhci_segment *seg;
+        struct xhci_segment *first_seg;
+
+        if (!ring || !ring->first_seg)
+                return;
+        first_seg = ring->first_seg;
+        seg = first_seg->next;
+        xhci_dbg(xhci, "Freeing ring at 0x%x\n", (unsigned int) ring);
+        while (seg != first_seg) {
+                struct xhci_segment *next = seg->next;
+                xhci_segment_free(xhci, seg);
+                seg = next;
+        }
+        xhci_segment_free(xhci, first_seg);
+        ring->first_seg = NULL;
+        kfree(ring);
+}
+
+/**
+ * Create a new ring with zero or more segments.
+ *
+ * Link each segment together into a ring.
+ * Set the end flag and the cycle toggle bit on the last segment.
+ * See section 4.9.1 and figures 15 and 16.
+ */
+static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
+                unsigned int num_segs, bool link_trbs, gfp_t flags)
+{
+        struct xhci_ring        *ring;
+        struct xhci_segment     *prev;
+
+        ring = kzalloc(sizeof *(ring), flags);
+        xhci_dbg(xhci, "Allocating ring at 0x%x\n", (unsigned int) ring);
+        if (!ring)
+                return 0;
+
+        if (num_segs == 0)
+                return ring;
+
+        ring->first_seg = xhci_segment_alloc(xhci, flags);
+        if (!ring->first_seg)
+                goto fail;
+        num_segs--;
+
+        prev = ring->first_seg;
+        while (num_segs > 0) {
+                struct xhci_segment     *next;
+
+                next = xhci_segment_alloc(xhci, flags);
+                if (!next)
+                        goto fail;
+                xhci_link_segments(xhci, prev, next, link_trbs);
+
+                prev = next;
+                num_segs--;
+        }
+        xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
+
+        if (link_trbs) {
+                /* See section 4.9.2.1 and 6.4.4.1 */
+                prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
+                xhci_dbg(xhci, "Wrote link toggle flag to"
+                                " segment 0x%x (virtual), 0x%x (DMA)\n",
+                                (unsigned int) prev, (u32) prev->dma);
+        }
+        /* The ring is empty, so the enqueue pointer == dequeue pointer */
+        ring->enqueue = ring->first_seg->trbs;
+        ring->dequeue = ring->enqueue;
+        /* The ring is initialized to 0. The producer must write 1 to the cycle
+         * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
+         * compare CCS to the cycle bit to check ownership, so CCS = 1.
+         */
+        ring->cycle_state = 1;
+
+        return ring;
+
+fail:
+        xhci_ring_free(xhci, ring);
+        return 0;
+}
+
 void xhci_mem_cleanup(struct xhci_hcd *xhci)
 {
+        struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
+        int size;
+
+        /* XXX: Free all the segments in the various rings */
+
+        /* Free the Event Ring Segment Table and the actual Event Ring */
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_base[1]);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_base[0]);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[1]);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[0]);
+        size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
+        if (xhci->erst.entries)
+                pci_free_consistent(pdev, size,
+                                xhci->erst.entries, xhci->erst.erst_dma_addr);
+        xhci->erst.entries = NULL;
+        xhci_dbg(xhci, "Freed ERST\n");
+        if (xhci->event_ring)
+                xhci_ring_free(xhci, xhci->event_ring);
+        xhci->event_ring = NULL;
+        xhci_dbg(xhci, "Freed event ring\n");
+
+        xhci_writel(xhci, 0, &xhci->op_regs->cmd_ring[1]);
+        xhci_writel(xhci, 0, &xhci->op_regs->cmd_ring[0]);
+        if (xhci->cmd_ring)
+                xhci_ring_free(xhci, xhci->cmd_ring);
+        xhci->cmd_ring = NULL;
+        xhci_dbg(xhci, "Freed command ring\n");
+        if (xhci->segment_pool)
+                dma_pool_destroy(xhci->segment_pool);
+        xhci->segment_pool = NULL;
+        xhci_dbg(xhci, "Freed segment pool\n");
         xhci->page_size = 0;
         xhci->page_shift = 0;
 }
 
 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
 {
+        dma_addr_t      dma;
+        struct device   *dev = xhci_to_hcd(xhci)->self.controller;
         unsigned int    val, val2;
+        struct xhci_segment     *seg;
         u32 page_size;
         int i;
 
@@ -65,7 +262,113 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
                         (unsigned int) val);
         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
 
-        xhci->ir_set = &xhci->run_regs->ir_set[0];
+        /*
+         * Initialize the ring segment pool.  The ring must be a contiguous
+         * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
+         * however, the command ring segment needs 64-byte aligned segments,
+         * so we pick the greater alignment need.
+         */
+        xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
+                        SEGMENT_SIZE, 64, xhci->page_size);
+        if (!xhci->segment_pool)
+                goto fail;
+
+        /* Set up the command ring to have one segments for now. */
+        xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
+        if (!xhci->cmd_ring)
+                goto fail;
+        xhci_dbg(xhci, "Allocated command ring at 0x%x\n", (unsigned int) xhci->cmd_ring);
+        xhci_dbg(xhci, "First segment DMA is 0x%x\n", (unsigned int) xhci->cmd_ring->first_seg->dma);
+
+        /* Set the address in the Command Ring Control register */
+        val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]);
+        val = (val & ~CMD_RING_ADDR_MASK) |
+                (xhci->cmd_ring->first_seg->dma & CMD_RING_ADDR_MASK) |
+                xhci->cmd_ring->cycle_state;
+        xhci_dbg(xhci, "// Setting command ring address high bits to 0x0\n");
+        xhci_writel(xhci, (u32) 0, &xhci->op_regs->cmd_ring[1]);
+        xhci_dbg(xhci, "// Setting command ring address low bits to 0x%x\n", val);
+        xhci_writel(xhci, val, &xhci->op_regs->cmd_ring[0]);
+        xhci_dbg_cmd_ptrs(xhci);
+
+        val = xhci_readl(xhci, &xhci->cap_regs->db_off);
+        val &= DBOFF_MASK;
+        xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
+                        " from cap regs base addr\n", val);
+        xhci->dba = (void *) xhci->cap_regs + val;
+        xhci_dbg_regs(xhci);
+        xhci_print_run_regs(xhci);
+        /* Set ir_set to interrupt register set 0 */
+        xhci->ir_set = (void *) xhci->run_regs->ir_set;
+
+        /*
+         * Event ring setup: Allocate a normal ring, but also setup
+         * the event ring segment table (ERST).  Section 4.9.3.
+         */
+        xhci_dbg(xhci, "// Allocating event ring\n");
+        xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
+        if (!xhci->event_ring)
+                goto fail;
+
+        xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
+                        sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
+        if (!xhci->erst.entries)
+                goto fail;
+        xhci_dbg(xhci, "// Allocated event ring segment table at 0x%x\n", dma);
+
+        memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
+        xhci->erst.num_entries = ERST_NUM_SEGS;
+        xhci->erst.erst_dma_addr = dma;
+        xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = 0x%x, dma addr = 0x%x\n",
+                        xhci->erst.num_entries,
+                        (unsigned int) xhci->erst.entries,
+                        xhci->erst.erst_dma_addr);
+
+        /* set ring base address and size for each segment table entry */
+        for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
+                struct xhci_erst_entry *entry = &xhci->erst.entries[val];
+                entry->seg_addr[1] = 0;
+                entry->seg_addr[0] = seg->dma;
+                entry->seg_size = TRBS_PER_SEGMENT;
+                entry->rsvd = 0;
+                seg = seg->next;
+        }
+
+        /* set ERST count with the number of entries in the segment table */
+        val = xhci_readl(xhci, &xhci->ir_set->erst_size);
+        val &= ERST_SIZE_MASK;
+        val |= ERST_NUM_SEGS;
+        xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
+                        val);
+        xhci_writel(xhci, val, &xhci->ir_set->erst_size);
+
+        xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
+        /* set the segment table base address */
+        xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%x\n",
+                        xhci->erst.erst_dma_addr);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_base[1]);
+        val = xhci_readl(xhci, &xhci->ir_set->erst_base[0]);
+        val &= ERST_PTR_MASK;
+        val |= (xhci->erst.erst_dma_addr & ~ERST_PTR_MASK);
+        xhci_writel(xhci, val, &xhci->ir_set->erst_base[0]);
+
+        /* Set the event ring dequeue address */
+        xhci_dbg(xhci, "// Set ERST dequeue address for ir_set 0 = 0x%x%x\n",
+                        xhci->erst.entries[0].seg_addr[1], xhci->erst.entries[0].seg_addr[0]);
+        val = xhci_readl(xhci, &xhci->run_regs->ir_set[0].erst_dequeue[0]);
+        val &= ERST_PTR_MASK;
+        val |= (xhci->erst.entries[0].seg_addr[0] & ~ERST_PTR_MASK);
+        xhci_writel(xhci, val, &xhci->run_regs->ir_set[0].erst_dequeue[0]);
+        xhci_writel(xhci, xhci->erst.entries[0].seg_addr[1],
+                        &xhci->run_regs->ir_set[0].erst_dequeue[1]);
+        xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
+        xhci_print_ir_set(xhci, xhci->ir_set, 0);
+
+        /*
+         * XXX: Might need to set the Interrupter Moderation Register to
+         * something other than the default (~1ms minimum between interrupts).
+         * See section 5.5.1.2.
+         */
 
         return 0;
 fail: