diff options
author | Jan Andersson <jan@gaisler.com> | 2011-05-06 06:00:16 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-05-06 21:24:01 -0400 |
commit | 9faa091a409851ac6b3812164d53644074bc89b1 (patch) | |
tree | c7d95c20e9b476261a1ccd7a5f02286be5b7502d /drivers/usb/host/uhci-hub.c | |
parent | c31a65f869f7b8a7039007411c76d7b6f9a63323 (diff) |
USB: UHCI: Wrap I/O register accesses
This patch is part of a series that extend the UHCI HCD to support
non-PCI controllers.
This patch replaces in{b,w,l} and out{b,wl} with calls to local inline
functions. This is done so that the register access functions can be
extended to support register areas not mapped in PCI I/O space.
Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/uhci-hub.c')
-rw-r--r-- | drivers/usb/host/uhci-hub.c | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/drivers/usb/host/uhci-hub.c b/drivers/usb/host/uhci-hub.c index 75418265488d..045cde4cbc3d 100644 --- a/drivers/usb/host/uhci-hub.c +++ b/drivers/usb/host/uhci-hub.c | |||
@@ -44,7 +44,7 @@ static int any_ports_active(struct uhci_hcd *uhci) | |||
44 | int port; | 44 | int port; |
45 | 45 | ||
46 | for (port = 0; port < uhci->rh_numports; ++port) { | 46 | for (port = 0; port < uhci->rh_numports; ++port) { |
47 | if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) & | 47 | if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & |
48 | (USBPORTSC_CCS | RWC_BITS)) || | 48 | (USBPORTSC_CCS | RWC_BITS)) || |
49 | test_bit(port, &uhci->port_c_suspend)) | 49 | test_bit(port, &uhci->port_c_suspend)) |
50 | return 1; | 50 | return 1; |
@@ -68,7 +68,7 @@ static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf) | |||
68 | 68 | ||
69 | *buf = 0; | 69 | *buf = 0; |
70 | for (port = 0; port < uhci->rh_numports; ++port) { | 70 | for (port = 0; port < uhci->rh_numports; ++port) { |
71 | if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) & mask) || | 71 | if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) || |
72 | test_bit(port, &uhci->port_c_suspend)) | 72 | test_bit(port, &uhci->port_c_suspend)) |
73 | *buf |= (1 << (port + 1)); | 73 | *buf |= (1 << (port + 1)); |
74 | } | 74 | } |
@@ -78,17 +78,17 @@ static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf) | |||
78 | #define OK(x) len = (x); break | 78 | #define OK(x) len = (x); break |
79 | 79 | ||
80 | #define CLR_RH_PORTSTAT(x) \ | 80 | #define CLR_RH_PORTSTAT(x) \ |
81 | status = inw(port_addr); \ | 81 | status = uhci_readw(uhci, port_addr); \ |
82 | status &= ~(RWC_BITS|WZ_BITS); \ | 82 | status &= ~(RWC_BITS|WZ_BITS); \ |
83 | status &= ~(x); \ | 83 | status &= ~(x); \ |
84 | status |= RWC_BITS & (x); \ | 84 | status |= RWC_BITS & (x); \ |
85 | outw(status, port_addr) | 85 | uhci_writew(uhci, status, port_addr) |
86 | 86 | ||
87 | #define SET_RH_PORTSTAT(x) \ | 87 | #define SET_RH_PORTSTAT(x) \ |
88 | status = inw(port_addr); \ | 88 | status = uhci_readw(uhci, port_addr); \ |
89 | status |= (x); \ | 89 | status |= (x); \ |
90 | status &= ~(RWC_BITS|WZ_BITS); \ | 90 | status &= ~(RWC_BITS|WZ_BITS); \ |
91 | outw(status, port_addr) | 91 | uhci_writew(uhci, status, port_addr) |
92 | 92 | ||
93 | /* UHCI controllers don't automatically stop resume signalling after 20 msec, | 93 | /* UHCI controllers don't automatically stop resume signalling after 20 msec, |
94 | * so we have to poll and check timeouts in order to take care of it. | 94 | * so we have to poll and check timeouts in order to take care of it. |
@@ -99,7 +99,7 @@ static void uhci_finish_suspend(struct uhci_hcd *uhci, int port, | |||
99 | int status; | 99 | int status; |
100 | int i; | 100 | int i; |
101 | 101 | ||
102 | if (inw(port_addr) & SUSPEND_BITS) { | 102 | if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) { |
103 | CLR_RH_PORTSTAT(SUSPEND_BITS); | 103 | CLR_RH_PORTSTAT(SUSPEND_BITS); |
104 | if (test_bit(port, &uhci->resuming_ports)) | 104 | if (test_bit(port, &uhci->resuming_ports)) |
105 | set_bit(port, &uhci->port_c_suspend); | 105 | set_bit(port, &uhci->port_c_suspend); |
@@ -110,7 +110,7 @@ static void uhci_finish_suspend(struct uhci_hcd *uhci, int port, | |||
110 | * Experiments show that some controllers take longer, so | 110 | * Experiments show that some controllers take longer, so |
111 | * we'll poll for completion. */ | 111 | * we'll poll for completion. */ |
112 | for (i = 0; i < 10; ++i) { | 112 | for (i = 0; i < 10; ++i) { |
113 | if (!(inw(port_addr) & SUSPEND_BITS)) | 113 | if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS)) |
114 | break; | 114 | break; |
115 | udelay(1); | 115 | udelay(1); |
116 | } | 116 | } |
@@ -121,12 +121,12 @@ static void uhci_finish_suspend(struct uhci_hcd *uhci, int port, | |||
121 | /* Wait for the UHCI controller in HP's iLO2 server management chip. | 121 | /* Wait for the UHCI controller in HP's iLO2 server management chip. |
122 | * It can take up to 250 us to finish a reset and set the CSC bit. | 122 | * It can take up to 250 us to finish a reset and set the CSC bit. |
123 | */ | 123 | */ |
124 | static void wait_for_HP(unsigned long port_addr) | 124 | static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr) |
125 | { | 125 | { |
126 | int i; | 126 | int i; |
127 | 127 | ||
128 | for (i = 10; i < 250; i += 10) { | 128 | for (i = 10; i < 250; i += 10) { |
129 | if (inw(port_addr) & USBPORTSC_CSC) | 129 | if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC) |
130 | return; | 130 | return; |
131 | udelay(10); | 131 | udelay(10); |
132 | } | 132 | } |
@@ -140,8 +140,8 @@ static void uhci_check_ports(struct uhci_hcd *uhci) | |||
140 | int status; | 140 | int status; |
141 | 141 | ||
142 | for (port = 0; port < uhci->rh_numports; ++port) { | 142 | for (port = 0; port < uhci->rh_numports; ++port) { |
143 | port_addr = uhci->io_addr + USBPORTSC1 + 2 * port; | 143 | port_addr = USBPORTSC1 + 2 * port; |
144 | status = inw(port_addr); | 144 | status = uhci_readw(uhci, port_addr); |
145 | if (unlikely(status & USBPORTSC_PR)) { | 145 | if (unlikely(status & USBPORTSC_PR)) { |
146 | if (time_after_eq(jiffies, uhci->ports_timeout)) { | 146 | if (time_after_eq(jiffies, uhci->ports_timeout)) { |
147 | CLR_RH_PORTSTAT(USBPORTSC_PR); | 147 | CLR_RH_PORTSTAT(USBPORTSC_PR); |
@@ -150,7 +150,7 @@ static void uhci_check_ports(struct uhci_hcd *uhci) | |||
150 | /* HP's server management chip requires | 150 | /* HP's server management chip requires |
151 | * a longer delay. */ | 151 | * a longer delay. */ |
152 | if (uhci->wait_for_hp) | 152 | if (uhci->wait_for_hp) |
153 | wait_for_HP(port_addr); | 153 | wait_for_HP(uhci, port_addr); |
154 | 154 | ||
155 | /* If the port was enabled before, turning | 155 | /* If the port was enabled before, turning |
156 | * reset on caused a port enable change. | 156 | * reset on caused a port enable change. |
@@ -241,7 +241,7 @@ static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
241 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | 241 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); |
242 | int status, lstatus, retval = 0, len = 0; | 242 | int status, lstatus, retval = 0, len = 0; |
243 | unsigned int port = wIndex - 1; | 243 | unsigned int port = wIndex - 1; |
244 | unsigned long port_addr = uhci->io_addr + USBPORTSC1 + 2 * port; | 244 | unsigned long port_addr = USBPORTSC1 + 2 * port; |
245 | u16 wPortChange, wPortStatus; | 245 | u16 wPortChange, wPortStatus; |
246 | unsigned long flags; | 246 | unsigned long flags; |
247 | 247 | ||
@@ -259,7 +259,7 @@ static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
259 | goto err; | 259 | goto err; |
260 | 260 | ||
261 | uhci_check_ports(uhci); | 261 | uhci_check_ports(uhci); |
262 | status = inw(port_addr); | 262 | status = uhci_readw(uhci, port_addr); |
263 | 263 | ||
264 | /* Intel controllers report the OverCurrent bit active on. | 264 | /* Intel controllers report the OverCurrent bit active on. |
265 | * VIA controllers report it active off, so we'll adjust the | 265 | * VIA controllers report it active off, so we'll adjust the |
@@ -356,7 +356,7 @@ static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
356 | CLR_RH_PORTSTAT(USBPORTSC_PEC); | 356 | CLR_RH_PORTSTAT(USBPORTSC_PEC); |
357 | OK(0); | 357 | OK(0); |
358 | case USB_PORT_FEAT_SUSPEND: | 358 | case USB_PORT_FEAT_SUSPEND: |
359 | if (!(inw(port_addr) & USBPORTSC_SUSP)) { | 359 | if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) { |
360 | 360 | ||
361 | /* Make certain the port isn't suspended */ | 361 | /* Make certain the port isn't suspended */ |
362 | uhci_finish_suspend(uhci, port, port_addr); | 362 | uhci_finish_suspend(uhci, port, port_addr); |
@@ -368,7 +368,8 @@ static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
368 | * if the port is disabled. When this happens | 368 | * if the port is disabled. When this happens |
369 | * just skip the Resume signalling. | 369 | * just skip the Resume signalling. |
370 | */ | 370 | */ |
371 | if (!(inw(port_addr) & USBPORTSC_RD)) | 371 | if (!(uhci_readw(uhci, port_addr) & |
372 | USBPORTSC_RD)) | ||
372 | uhci_finish_suspend(uhci, port, | 373 | uhci_finish_suspend(uhci, port, |
373 | port_addr); | 374 | port_addr); |
374 | else | 375 | else |